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| author | Tim Gore <tim.gore@intel.com> | 2016-03-16 16:13:46 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-03-18 11:12:29 +0000 |
| commit | 950b2aaeea6960561425fc80adfb5b2fc0ac020f (patch) | |
| tree | 021c9a0fa6dfad8e3ca7855207bb0a1bc51f60f9 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 26720ab97feac7153a7b5c3c79cf5d53a8531126 (diff) | |
drm/i915/gen9: add WaClearFlowControlGpgpuContextSave
This allows writes to EU flow control registers. Together
with SIP code from the user-mode driver this resolves a
hang seen in some pre-emption scenarios. Note that this
patch is just the kernel mode part of this workaround.
v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.
Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458144826-17269-1-git-send-email-tim.gore@intel.com
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions