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| author | Stephen Boyd <sboyd@kernel.org> | 2022-08-30 14:36:24 -0700 | 
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-08-30 14:36:24 -0700 | 
| commit | 37eceb69205b2a98e67c48710c1e9ad5e78f21e9 (patch) | |
| tree | 3cbead10a8ca0b61a576d302fc9f2be965911de5 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff) | |
| parent | ef96c458888fa2a329b14efc7991530f645fbddb (diff) | |
Merge tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driverd updates from Krzysztof Kozlowski:
 - Exynos7885: add FSYS, TREX and MFC clock controllers.
 - Exynos850: add IS and AUD (audio) clock controllers with bindings.
 - ExynosAutov9: add FSYS clock controllers with bindings.
 - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
   controllers, due to duplicated entries.  This is an acceptable ABI
   break: recently developed/added platform so without legacies, acked
   by known users/developers.
 - ExynosAutov9: add few missing Peric 0/1 gates.
 - ExynosAutov9: correct register offsets of few Peric 0/1 clocks.
 - Minor code improvements (use of_device_get_match_data() helper, code
   style).
 - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
   already maintainers that architecture/platform.
* tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
  clk: samsung: exynos850: Implement CMU_MFCMSCL domain
  clk: samsung: exynos850: Implement CMU_IS domain
  clk: samsung: exynos850: Implement CMU_AUD domain
  clk: samsung: exynos850: Style fixes
  clk: samsung: exynosautov9: add fsys1 clock support
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: correct register offsets of peric0/c1
  clk: samsung: exynosautov9: add missing gate clks for peric0/c1
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  clk: samsung: exynos7885: Add TREX clocks
  clk: samsung: exynos7885: Implement CMU_FSYS domain
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
  clk: samsung: exynos-clkout: Use of_device_get_match_data()
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
