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-rw-r--r--drivers/pci/controller/dwc/pcie-qcom.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 9791af8b09f3..ecd6d1e46666 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -193,7 +193,7 @@ struct qcom_pcie_resources_2_4_0 {
int num_resets;
};
-#define QCOM_PCIE_2_7_0_MAX_CLOCKS 12
+#define QCOM_PCIE_2_7_0_MAX_CLOCKS 13
#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
struct qcom_pcie_resources_2_7_0 {
struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
@@ -879,6 +879,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[idx++].id = "noc_aggr_4";
res->clks[idx++].id = "noc_aggr_south_sf";
res->clks[idx++].id = "cnoc_qx";
+ res->clks[idx++].id = "sleep";
num_opt_clks = idx - num_clks;
res->num_clks = idx;
@@ -1611,6 +1612,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
+ { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },