diff options
20 files changed, 2021 insertions, 288 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index db99bd95d423..3bb76487669f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,7 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl" or "mscc,serval-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl" or + "microchip,lan966x-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 8952b4cc1262..9400b665a46f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -17,6 +17,7 @@ properties: compatible: items: - enum: + - qcom,pm2250-gpio - qcom,pm660-gpio - qcom,pm660l-gpio - qcom,pm6150-gpio @@ -26,10 +27,12 @@ properties: - qcom,pm8005-gpio - qcom,pm8008-gpio - qcom,pm8018-gpio + - qcom,pm8019-gpio - qcom,pm8038-gpio - qcom,pm8058-gpio - qcom,pm8150-gpio - qcom,pm8150b-gpio + - qcom,pm8226-gpio - qcom,pm8350-gpio - qcom,pm8350b-gpio - qcom,pm8350c-gpio diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml new file mode 100644 index 000000000000..58dd34f4fcb5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX65 TLMM block + +maintainers: + - Vamsi krishna Lanka <quic_vamslank@quicinc.com> + +description: + This binding describes the Top Level Mode Multiplexer block found in the + SDX65 platform. + +properties: + compatible: + const: qcom,sdx65-tlmm + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '$-state': + oneOf: + - $ref: "#/$defs/qcom-sdx65-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sdx65-tlmm-state" +'$defs': + qcom-sdx65-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$" + - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ] + minItems: 1 + maxItems: 150 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0x03000000 0xdc2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <2>; + bias-disable; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "blsp_uart1"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "blsp_uart1"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml index a804d9bc1602..27c5762b9cf8 100644 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -26,11 +26,45 @@ properties: - socionext,uniphier-pxs3-pinctrl - socionext,uniphier-nx1-pinctrl +additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + phandle: true + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + phandle: true + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + unevaluatedProperties: false + required: - compatible -additionalProperties: false - examples: - | // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c index d26bff29157b..8943cea92764 100644 --- a/drivers/gpio/gpio-mockup.c +++ b/drivers/gpio/gpio-mockup.c @@ -491,27 +491,6 @@ static void gpio_mockup_unregister_pdevs(void) } } -static __init char **gpio_mockup_make_line_names(const char *label, - unsigned int num_lines) -{ - unsigned int i; - char **names; - - names = kcalloc(num_lines + 1, sizeof(char *), GFP_KERNEL); - if (!names) - return NULL; - - for (i = 0; i < num_lines; i++) { - names[i] = kasprintf(GFP_KERNEL, "%s-%u", label, i); - if (!names[i]) { - kfree_strarray(names, i); - return NULL; - } - } - - return names; -} - static int __init gpio_mockup_register_chip(int idx) { struct property_entry properties[GPIO_MOCKUP_MAX_PROP]; @@ -538,7 +517,7 @@ static int __init gpio_mockup_register_chip(int idx) properties[prop++] = PROPERTY_ENTRY_U16("nr-gpios", ngpio); if (gpio_mockup_named_lines) { - line_names = gpio_mockup_make_line_names(chip_label, ngpio); + line_names = kasprintf_strarray(GFP_KERNEL, chip_label, ngpio); if (!line_names) return -ENOMEM; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5cb018f98800..08cad14042e2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -23,6 +23,7 @@ #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> +#include <linux/string_helpers.h> #include "../pinctrl-utils.h" @@ -341,12 +342,12 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, struct armada_37xx_pin_group *grp) { struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = info->dev; unsigned int reg = SELECTION; unsigned int mask = grp->reg_mask; int func, val; - dev_dbg(info->dev, "enable function %s group %s\n", - name, grp->name); + dev_dbg(dev, "enable function %s group %s\n", name, grp->name); func = match_string(grp->funcs, NB_FUNCS, name); if (func < 0) @@ -722,25 +723,22 @@ static unsigned int armada_37xx_irq_startup(struct irq_data *d) static int armada_37xx_irqchip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { - struct device_node *np = info->dev->of_node; struct gpio_chip *gc = &info->gpio_chip; struct irq_chip *irqchip = &info->irq_chip; struct gpio_irq_chip *girq = &gc->irq; struct device *dev = &pdev->dev; - struct resource res; + struct device_node *np; int ret = -ENODEV, i, nr_irq_parent; /* Check if we have at least one gpio-controller child node */ - for_each_child_of_node(info->dev->of_node, np) { + for_each_child_of_node(dev->of_node, np) { if (of_property_read_bool(np, "gpio-controller")) { ret = 0; break; } } - if (ret) { - dev_err(dev, "no gpio-controller child node\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "no gpio-controller child node\n"); nr_irq_parent = of_irq_count(np); spin_lock_init(&info->irq_lock); @@ -750,12 +748,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, return 0; } - if (of_address_to_resource(info->dev->of_node, 1, &res)) { - dev_err(dev, "cannot find IO resource\n"); - return -ENOENT; - } - - info->base = devm_ioremap_resource(info->dev, &res); + info->base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(info->base)) return PTR_ERR(info->base); @@ -774,8 +767,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, * the chained irq with all of them. */ girq->num_parents = nr_irq_parent; - girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, - sizeof(*girq->parents), GFP_KERNEL); + girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; for (i = 0; i < nr_irq_parent; i++) { @@ -794,11 +786,12 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, static int armada_37xx_gpiochip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { + struct device *dev = &pdev->dev; struct device_node *np; struct gpio_chip *gc; int ret = -ENODEV; - for_each_child_of_node(info->dev->of_node, np) { + for_each_child_of_node(dev->of_node, np) { if (of_find_property(np, "gpio-controller", NULL)) { ret = 0; break; @@ -811,7 +804,7 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, gc = &info->gpio_chip; gc->ngpio = info->data->nr_pins; - gc->parent = &pdev->dev; + gc->parent = dev; gc->base = -1; gc->of_node = np; gc->label = info->data->name; @@ -819,11 +812,8 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, ret = armada_37xx_irqchip_register(pdev, info); if (ret) return ret; - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); - if (ret) - return ret; - return 0; + return devm_gpiochip_add_data(dev, gc, info); } /** @@ -874,13 +864,13 @@ static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) { int n, num = 0, funcsize = info->data->nr_pins; + struct device *dev = info->dev; for (n = 0; n < info->ngroups; n++) { struct armada_37xx_pin_group *grp = &info->groups[n]; int i, j, f; - grp->pins = devm_kcalloc(info->dev, - grp->npins + grp->extra_npins, + grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, sizeof(*grp->pins), GFP_KERNEL); if (!grp->pins) @@ -898,8 +888,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) ret = armada_37xx_add_function(info->funcs, &funcsize, grp->funcs[f]); if (ret == -EOVERFLOW) - dev_err(info->dev, - "More functions than pins(%d)\n", + dev_err(dev, "More functions than pins(%d)\n", info->data->nr_pins); if (ret < 0) continue; @@ -913,7 +902,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) } /** - * armada_37xx_fill_funcs() - complete the funcs array + * armada_37xx_fill_func() - complete the funcs array * @info: info driver instance * * Based on the data available from the armada_37xx_pin_group array @@ -925,6 +914,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) { struct armada_37xx_pmx_func *funcs = info->funcs; + struct device *dev = info->dev; int n; for (n = 0; n < info->nfuncs; n++) { @@ -932,8 +922,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) const char **groups; int g; - funcs[n].groups = devm_kcalloc(info->dev, - funcs[n].ngroups, + funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, sizeof(*(funcs[n].groups)), GFP_KERNEL); if (!funcs[n].groups) @@ -962,6 +951,8 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, const struct armada_37xx_pin_data *pin_data = info->data; struct pinctrl_desc *ctrldesc = &info->pctl; struct pinctrl_pin_desc *pindesc, *pdesc; + struct device *dev = &pdev->dev; + char **pin_names; int pin, ret; info->groups = pin_data->groups; @@ -973,20 +964,21 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, ctrldesc->pmxops = &armada_37xx_pmx_ops; ctrldesc->confops = &armada_37xx_pinconf_ops; - pindesc = devm_kcalloc(&pdev->dev, - pin_data->nr_pins, sizeof(*pindesc), - GFP_KERNEL); + pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); if (!pindesc) return -ENOMEM; ctrldesc->pins = pindesc; ctrldesc->npins = pin_data->nr_pins; + pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + pdesc = pindesc; for (pin = 0; pin < pin_data->nr_pins; pin++) { pdesc->number = pin; - pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", - pin_data->name, pin); + pdesc->name = pin_names[pin]; pdesc++; } @@ -994,14 +986,10 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, * we allocate functions for number of pins and hope there are * fewer unique functions than pins available */ - info->funcs = devm_kcalloc(&pdev->dev, - pin_data->nr_pins, - sizeof(struct armada_37xx_pmx_func), - GFP_KERNEL); + info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); if (!info->funcs) return -ENOMEM; - ret = armada_37xx_fill_group(info); if (ret) return ret; @@ -1010,11 +998,9 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev, if (ret) return ret; - info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); - if (IS_ERR(info->pctl_dev)) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return PTR_ERR(info->pctl_dev); - } + info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); return 0; } @@ -1143,18 +1129,15 @@ static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) struct regmap *regmap; int ret; - info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl), - GFP_KERNEL); + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; info->dev = dev; regmap = syscon_node_to_regmap(np); - if (IS_ERR(regmap)) { - dev_err(&pdev->dev, "cannot get regmap\n"); - return PTR_ERR(regmap); - } + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n"); info->regmap = regmap; info->data = of_device_get_match_data(dev); diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 78765faa245a..8e081c90bdb2 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -17,6 +17,7 @@ #include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/regmap.h> #include <linux/reset.h> #include "core.h" @@ -113,7 +114,7 @@ struct sgpio_priv { u32 bitcount; u32 ports; u32 clock; - u32 __iomem *regs; + struct regmap *regs; const struct sgpio_properties *properties; }; @@ -134,31 +135,42 @@ static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) return bit + port * priv->bitcount; } -static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) +static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) +{ + return priv->properties->regoff[rno] + off; +} + +static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + u32 addr = sgpio_get_addr(priv, rno, off); + u32 val = 0; + int ret; - return readl(reg); + ret = regmap_read(priv->regs, addr, &val); + WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); + + return val; } -static inline void sgpio_writel(struct sgpio_priv *priv, +static void sgpio_writel(struct sgpio_priv *priv, u32 val, u32 rno, u32 off) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; + u32 addr = sgpio_get_addr(priv, rno, off); + int ret; - writel(val, reg); + ret = regmap_write(priv->regs, addr, val); + WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); } static inline void sgpio_clrsetbits(struct sgpio_priv *priv, u32 rno, u32 off, u32 clear, u32 set) { - u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; - u32 val = readl(reg); + u32 val = sgpio_readl(priv, rno, off); val &= ~clear; val |= set; - writel(val, reg); + sgpio_writel(priv, val, rno, off); } static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) @@ -807,7 +819,13 @@ static int microchip_sgpio_probe(struct platform_device *pdev) struct reset_control *reset; struct sgpio_priv *priv; struct clk *clk; + u32 __iomem *regs; u32 val; + struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -832,9 +850,14 @@ static int microchip_sgpio_probe(struct platform_device *pdev) return -EINVAL; } - priv->regs = devm_platform_ioremap_resource(pdev, 0); + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); + priv->properties = device_get_match_data(dev); priv->in.is_input = true; diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 0a36ec8775a3..42aab9ba049a 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -57,16 +57,71 @@ enum { #define OCELOT_FUNC_PER_PIN 4 enum { + FUNC_CAN0_a, + FUNC_CAN0_b, + FUNC_CAN1, FUNC_NONE, + FUNC_FC0_a, + FUNC_FC0_b, + FUNC_FC0_c, + FUNC_FC1_a, + FUNC_FC1_b, + FUNC_FC1_c, + FUNC_FC2_a, + FUNC_FC2_b, + FUNC_FC3_a, + FUNC_FC3_b, + FUNC_FC3_c, + FUNC_FC4_a, + FUNC_FC4_b, + FUNC_FC4_c, + FUNC_FC_SHRD0, + FUNC_FC_SHRD1, + FUNC_FC_SHRD2, + FUNC_FC_SHRD3, + FUNC_FC_SHRD4, + FUNC_FC_SHRD5, + FUNC_FC_SHRD6, + FUNC_FC_SHRD7, + FUNC_FC_SHRD8, + FUNC_FC_SHRD9, + FUNC_FC_SHRD10, + FUNC_FC_SHRD11, + FUNC_FC_SHRD12, + FUNC_FC_SHRD13, + FUNC_FC_SHRD14, + FUNC_FC_SHRD15, + FUNC_FC_SHRD16, + FUNC_FC_SHRD17, + FUNC_FC_SHRD18, + FUNC_FC_SHRD19, + FUNC_FC_SHRD20, FUNC_GPIO, + FUNC_IB_TRG_a, + FUNC_IB_TRG_b, + FUNC_IB_TRG_c, FUNC_IRQ0, + FUNC_IRQ_IN_a, + FUNC_IRQ_IN_b, + FUNC_IRQ_IN_c, FUNC_IRQ0_IN, + FUNC_IRQ_OUT_a, + FUNC_IRQ_OUT_b, + FUNC_IRQ_OUT_c, FUNC_IRQ0_OUT, FUNC_IRQ1, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, FUNC_EXT_IRQ, FUNC_MIIM, + FUNC_MIIM_a, + FUNC_MIIM_b, + FUNC_MIIM_c, + FUNC_MIIM_Sa, + FUNC_MIIM_Sb, + FUNC_OB_TRG, + FUNC_OB_TRG_a, + FUNC_OB_TRG_b, FUNC_PHY_LED, FUNC_PCI_WAKE, FUNC_MD, @@ -74,65 +129,174 @@ enum { FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, + FUNC_PTPSYNC_1, + FUNC_PTPSYNC_2, + FUNC_PTPSYNC_3, + FUNC_PTPSYNC_4, + FUNC_PTPSYNC_5, + FUNC_PTPSYNC_6, + FUNC_PTPSYNC_7, FUNC_PWM, + FUNC_QSPI1, + FUNC_QSPI2, + FUNC_R, + FUNC_RECO_a, + FUNC_RECO_b, FUNC_RECO_CLK, + FUNC_SD, FUNC_SFP, + FUNC_SFP_SD, FUNC_SG0, FUNC_SG1, FUNC_SG2, + FUNC_SGPIO_a, + FUNC_SGPIO_b, FUNC_SI, FUNC_SI2, FUNC_TACHO, + FUNC_TACHO_a, + FUNC_TACHO_b, FUNC_TWI, FUNC_TWI2, FUNC_TWI3, FUNC_TWI_SCL_M, + FUNC_TWI_SLC_GATE, + FUNC_TWI_SLC_GATE_AD, FUNC_UART, FUNC_UART2, FUNC_UART3, + FUNC_USB_H_a, + FUNC_USB_H_b, + FUNC_USB_H_c, + FUNC_USB_S_a, + FUNC_USB_S_b, + FUNC_USB_S_c, FUNC_PLL_STAT, FUNC_EMMC, + FUNC_EMMC_SD, FUNC_REF_CLK, FUNC_RCVRD_CLK, FUNC_MAX }; static const char *const ocelot_function_names[] = { + [FUNC_CAN0_a] = "can0_a", + [FUNC_CAN0_b] = "can0_b", + [FUNC_CAN1] = "can1", [FUNC_NONE] = "none", + [FUNC_FC0_a] = "fc0_a", + [FUNC_FC0_b] = "fc0_b", + [FUNC_FC0_c] = "fc0_c", + [FUNC_FC1_a] = "fc1_a", + [FUNC_FC1_b] = "fc1_b", + [FUNC_FC1_c] = "fc1_c", + [FUNC_FC2_a] = "fc2_a", + [FUNC_FC2_b] = "fc2_b", + [FUNC_FC3_a] = "fc3_a", + [FUNC_FC3_b] = "fc3_b", + [FUNC_FC3_c] = "fc3_c", + [FUNC_FC4_a] = "fc4_a", + [FUNC_FC4_b] = "fc4_b", + [FUNC_FC4_c] = "fc4_c", + [FUNC_FC_SHRD0] = "fc_shrd0", + [FUNC_FC_SHRD1] = "fc_shrd1", + [FUNC_FC_SHRD2] = "fc_shrd2", + [FUNC_FC_SHRD3] = "fc_shrd3", + [FUNC_FC_SHRD4] = "fc_shrd4", + [FUNC_FC_SHRD5] = "fc_shrd5", + [FUNC_FC_SHRD6] = "fc_shrd6", + [FUNC_FC_SHRD7] = "fc_shrd7", + [FUNC_FC_SHRD8] = "fc_shrd8", + [FUNC_FC_SHRD9] = "fc_shrd9", + [FUNC_FC_SHRD10] = "fc_shrd10", + [FUNC_FC_SHRD11] = "fc_shrd11", + [FUNC_FC_SHRD12] = "fc_shrd12", + [FUNC_FC_SHRD13] = "fc_shrd13", + [FUNC_FC_SHRD14] = "fc_shrd14", + [FUNC_FC_SHRD15] = "fc_shrd15", + [FUNC_FC_SHRD16] = "fc_shrd16", + [FUNC_FC_SHRD17] = "fc_shrd17", + [FUNC_FC_SHRD18] = "fc_shrd18", + [FUNC_FC_SHRD19] = "fc_shrd19", + [FUNC_FC_SHRD20] = "fc_shrd20", [FUNC_GPIO] = "gpio", + [FUNC_IB_TRG_a] = "ib_trig_a", + [FUNC_IB_TRG_b] = "ib_trig_b", + [FUNC_IB_TRG_c] = "ib_trig_c", [FUNC_IRQ0] = "irq0", + [FUNC_IRQ_IN_a] = "irq_in_a", + [FUNC_IRQ_IN_b] = "irq_in_b", + [FUNC_IRQ_IN_c] = "irq_in_c", [FUNC_IRQ0_IN] = "irq0_in", + [FUNC_IRQ_OUT_a] = "irq_out_a", + [FUNC_IRQ_OUT_b] = "irq_out_b", + [FUNC_IRQ_OUT_c] = "irq_out_c", [FUNC_IRQ0_OUT] = "irq0_out", [FUNC_IRQ1] = "irq1", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", [FUNC_EXT_IRQ] = "ext_irq", [FUNC_MIIM] = "miim", + [FUNC_MIIM_a] = "miim_a", + [FUNC_MIIM_b] = "miim_b", + [FUNC_MIIM_c] = "miim_c", + [FUNC_MIIM_Sa] = "miim_slave_a", + [FUNC_MIIM_Sb] = "miim_slave_b", [FUNC_PHY_LED] = "phy_led", [FUNC_PCI_WAKE] = "pci_wake", [FUNC_MD] = "md", + [FUNC_OB_TRG] = "ob_trig", + [FUNC_OB_TRG_a] = "ob_trig_a", + [FUNC_OB_TRG_b] = "ob_trig_b", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", + [FUNC_PTPSYNC_1] = "ptpsync_1", + [FUNC_PTPSYNC_2] = "ptpsync_2", + [FUNC_PTPSYNC_3] = "ptpsync_3", + [FUNC_PTPSYNC_4] = "ptpsync_4", + [FUNC_PTPSYNC_5] = "ptpsync_5", + [FUNC_PTPSYNC_6] = "ptpsync_6", + [FUNC_PTPSYNC_7] = "ptpsync_7", [FUNC_PWM] = "pwm", + [FUNC_QSPI1] = "qspi1", + [FUNC_QSPI2] = "qspi2", + [FUNC_R] = "reserved", + [FUNC_RECO_a] = "reco_a", + [FUNC_RECO_b] = "reco_b", [FUNC_RECO_CLK] = "reco_clk", + [FUNC_SD] = "sd", [FUNC_SFP] = "sfp", + [FUNC_SFP_SD] = "sfp_sd", [FUNC_SG0] = "sg0", [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", + [FUNC_SGPIO_a] = "sgpio_a", + [FUNC_SGPIO_b] = "sgpio_b", [FUNC_SI] = "si", [FUNC_SI2] = "si2", [FUNC_TACHO] = "tacho", + [FUNC_TACHO_a] = "tacho_a", + [FUNC_TACHO_b] = "tacho_b", [FUNC_TWI] = "twi", [FUNC_TWI2] = "twi2", [FUNC_TWI3] = "twi3", [FUNC_TWI_SCL_M] = "twi_scl_m", + [FUNC_TWI_SLC_GATE] = "twi_slc_gate", + [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad", + [FUNC_USB_H_a] = "usb_host_a", + [FUNC_USB_H_b] = "usb_host_b", + [FUNC_USB_H_c] = "usb_host_c", + [FUNC_USB_S_a] = "usb_slave_a", + [FUNC_USB_S_b] = "usb_slave_b", + [FUNC_USB_S_c] = "usb_slave_c", [FUNC_UART] = "uart", [FUNC_UART2] = "uart2", [FUNC_UART3] = "uart3", [FUNC_PLL_STAT] = "pll_stat", [FUNC_EMMC] = "emmc", + [FUNC_EMMC_SD] = "emmc_sd", [FUNC_REF_CLK] = "ref_clk", [FUNC_RCVRD_CLK] = "rcvrd_clk", }; @@ -145,6 +309,7 @@ struct ocelot_pmx_func { struct ocelot_pin_caps { unsigned int pin; unsigned char functions[OCELOT_FUNC_PER_PIN]; + unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ }; struct ocelot_pinctrl { @@ -152,7 +317,7 @@ struct ocelot_pinctrl { struct pinctrl_dev *pctl; struct gpio_chip gpio_chip; struct regmap *map; - void __iomem *pincfg; + struct regmap *pincfg; struct pinctrl_desc *desc; struct ocelot_pmx_func func[FUNC_MAX]; u8 stride; @@ -676,6 +841,187 @@ static const struct pinctrl_pin_desc sparx5_pins[] = { SPARX5_PIN(63), }; +#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ +static struct ocelot_pin_caps lan966x_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3 \ + }, \ + .a_functions = { \ + FUNC_##f4, FUNC_##f5, FUNC_##f6, \ + FUNC_##f7 \ + }, \ +} + +/* Pinmuxing table taken from data sheet */ +/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ +LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R); +LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R); +LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R); +LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R); +LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R); +LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R); +LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); +LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R); +LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, NONE, R); +LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R); +LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R); +LAN966X_P(30, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); +LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NONE, R); +LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); +LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); +LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); +LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); +LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); +LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R); +LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R); +LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R); +LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); +LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); +LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R); +LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R); +LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R); +LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R); +LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R); +LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R); +LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R); +LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); +LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R); +LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R); +LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); +LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R); +LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R); +LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R); +LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R); +LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); +LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R); +LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R); +LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R); +LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R); +LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R); +LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R); +LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R); +LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R); +LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R); + +#define LAN966X_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &lan966x_pin_##n \ +} + +static const struct pinctrl_pin_desc lan966x_pins[] = { + LAN966X_PIN(0), + LAN966X_PIN(1), + LAN966X_PIN(2), + LAN966X_PIN(3), + LAN966X_PIN(4), + LAN966X_PIN(5), + LAN966X_PIN(6), + LAN966X_PIN(7), + LAN966X_PIN(8), + LAN966X_PIN(9), + LAN966X_PIN(10), + LAN966X_PIN(11), + LAN966X_PIN(12), + LAN966X_PIN(13), + LAN966X_PIN(14), + LAN966X_PIN(15), + LAN966X_PIN(16), + LAN966X_PIN(17), + LAN966X_PIN(18), + LAN966X_PIN(19), + LAN966X_PIN(20), + LAN966X_PIN(21), + LAN966X_PIN(22), + LAN966X_PIN(23), + LAN966X_PIN(24), + LAN966X_PIN(25), + LAN966X_PIN(26), + LAN966X_PIN(27), + LAN966X_PIN(28), + LAN966X_PIN(29), + LAN966X_PIN(30), + LAN966X_PIN(31), + LAN966X_PIN(32), + LAN966X_PIN(33), + LAN966X_PIN(34), + LAN966X_PIN(35), + LAN966X_PIN(36), + LAN966X_PIN(37), + LAN966X_PIN(38), + LAN966X_PIN(39), + LAN966X_PIN(40), + LAN966X_PIN(41), + LAN966X_PIN(42), + LAN966X_PIN(43), + LAN966X_PIN(44), + LAN966X_PIN(45), + LAN966X_PIN(46), + LAN966X_PIN(47), + LAN966X_PIN(48), + LAN966X_PIN(49), + LAN966X_PIN(50), + LAN966X_PIN(51), + LAN966X_PIN(52), + LAN966X_PIN(53), + LAN966X_PIN(54), + LAN966X_PIN(55), + LAN966X_PIN(56), + LAN966X_PIN(57), + LAN966X_PIN(58), + LAN966X_PIN(59), + LAN966X_PIN(60), + LAN966X_PIN(61), + LAN966X_PIN(62), + LAN966X_PIN(63), + LAN966X_PIN(64), + LAN966X_PIN(65), + LAN966X_PIN(66), + LAN966X_PIN(67), + LAN966X_PIN(68), + LAN966X_PIN(69), + LAN966X_PIN(70), + LAN966X_PIN(71), + LAN966X_PIN(72), + LAN966X_PIN(73), + LAN966X_PIN(74), + LAN966X_PIN(75), + LAN966X_PIN(76), + LAN966X_PIN(77), +}; + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(ocelot_function_names); @@ -709,6 +1055,9 @@ static int ocelot_pin_function_idx(struct ocelot_pinctrl *info, for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) { if (function == p->functions[i]) return i; + + if (function == p->a_functions[i]) + return i + OCELOT_FUNC_PER_PIN; } return -1; @@ -744,6 +1093,36 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data; + unsigned int p = pin->pin % 32; + int f; + + f = ocelot_pin_function_idx(info, group, selector); + if (f < 0) + return -EINVAL; + + /* + * f is encoded on three bits. + * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of + * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] + * This is racy because three registers can't be updated at the same time + * but it doesn't matter much for now. + * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets + */ + regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), + BIT(p), f << p); + regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), + BIT(p), (f >> 1) << p); + regmap_update_bits(info->map, REG_ALT(2, info, pin->pin), + BIT(p), (f >> 2) << p); + + return 0; +} + #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -774,6 +1153,23 @@ static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } +static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); + unsigned int p = offset % 32; + + regmap_update_bits(info->map, REG_ALT(0, info, offset), + BIT(p), 0); + regmap_update_bits(info->map, REG_ALT(1, info, offset), + BIT(p), 0); + regmap_update_bits(info->map, REG_ALT(2, info, offset), + BIT(p), 0); + + return 0; +} + static const struct pinmux_ops ocelot_pmx_ops = { .get_functions_count = ocelot_get_functions_count, .get_function_name = ocelot_get_function_name, @@ -783,6 +1179,15 @@ static const struct pinmux_ops ocelot_pmx_ops = { .gpio_request_enable = ocelot_gpio_request_enable, }; +static const struct pinmux_ops lan966x_pmx_ops = { + .get_functions_count = ocelot_get_functions_count, + .get_function_name = ocelot_get_function_name, + .get_function_groups = ocelot_get_function_groups, + .set_mux = lan966x_pinmux_set_mux, + .gpio_set_direction = ocelot_gpio_set_direction, + .gpio_request_enable = lan966x_gpio_request_enable, +}; + static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) { struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); @@ -819,7 +1224,11 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info, int ret = -EOPNOTSUPP; if (info->pincfg) { - u32 regcfg = readl(info->pincfg + (pin * sizeof(u32))); + u32 regcfg; + + ret = regmap_read(info->pincfg, pin, ®cfg); + if (ret) + return ret; ret = 0; switch (reg) { @@ -843,6 +1252,24 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info, return ret; } +static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr, + u32 clrbits, u32 setbits) +{ + u32 val; + int ret; + + ret = regmap_read(info->pincfg, regaddr, &val); + if (ret) + return ret; + + val &= ~clrbits; + val |= setbits; + + ret = regmap_write(info->pincfg, regaddr, val); + + return ret; +} + static int ocelot_hw_set_value(struct ocelot_pinctrl *info, unsigned int pin, unsigned int reg, @@ -851,21 +1278,23 @@ static int ocelot_hw_set_value(struct ocelot_pinctrl *info, int ret = -EOPNOTSUPP; if (info->pincfg) { - void __iomem *regaddr = info->pincfg + (pin * sizeof(u32)); ret = 0; switch (reg) { case PINCONF_BIAS: - ocelot_clrsetbits(regaddr, BIAS_BITS, val); + ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, + val); break; case PINCONF_SCHMITT: - ocelot_clrsetbits(regaddr, SCHMITT_BIT, val); + ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, + val); break; case PINCONF_DRIVE_STRENGTH: if (val <= 3) - ocelot_clrsetbits(regaddr, DRIVE_BITS, val); + ret = ocelot_pincfg_clrsetbits(info, pin, + DRIVE_BITS, val); else ret = -EINVAL; break; @@ -1078,6 +1507,16 @@ static struct pinctrl_desc sparx5_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc lan966x_desc = { + .name = "lan966x-pinctrl", + .pins = lan966x_pins, + .npins = ARRAY_SIZE(lan966x_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &lan966x_pmx_ops, + .confops = &ocelot_confops, + .owner = THIS_MODULE, +}; + static int ocelot_create_group_func_map(struct device *dev, struct ocelot_pinctrl *info) { @@ -1308,7 +1747,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc = &info->gpio_chip; gc->ngpio = info->desc->npins; gc->parent = &pdev->dev; - gc->base = 0; + gc->base = -1; gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; @@ -1337,15 +1776,36 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, + { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, }; +static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) +{ + void __iomem *base; + + const struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 32, + }; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); + return NULL; + } + + return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); +} + static int ocelot_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; + struct regmap *pincfg; void __iomem *base; - struct resource *res; int ret; struct regmap_config regmap_config = { .reg_bits = 32, @@ -1378,12 +1838,11 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) /* Pinconf registers */ if (info->desc->confops) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n"); + pincfg = ocelot_pinctrl_create_pincfg(pdev); + if (IS_ERR(pincfg)) + dev_dbg(dev, "Failed to create pincfg regmap\n"); else - info->pincfg = base; + info->pincfg = pincfg; } ret = ocelot_pinctrl_register(pdev, info); diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5ce260f152ce..438808a867cf 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -33,13 +33,15 @@ #include <linux/clk.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> +#include <linux/string_helpers.h> + #include <dt-bindings/pinctrl/rockchip.h> #include "core.h" #include "pinconf.h" #include "pinctrl-rockchip.h" -/** +/* * Generate a bitmask for setting a value (v) with a write mask bit in hiword * register 31:16 area. */ @@ -285,6 +287,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, { struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct rockchip_pin_group *grp; + struct device *dev = info->dev; struct pinctrl_map *new_map; struct device_node *parent; int map_num = 1; @@ -296,8 +299,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, */ grp = pinctrl_name_to_group(info, np->name); if (!grp) { - dev_err(info->dev, "unable to find group for node %pOFn\n", - np); + dev_err(dev, "unable to find group for node %pOFn\n", np); return -EINVAL; } @@ -331,7 +333,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, new_map[i].data.configs.num_configs = grp->data[i].nconfigs; } - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", + dev_dbg(dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group, map_num); return 0; @@ -872,20 +874,20 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + struct device *dev = info->dev; int iomux_num = (pin / 8); if (iomux_num > 3) return -EINVAL; if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { - dev_err(info->dev, "pin %d is unrouted\n", pin); + dev_err(dev, "pin %d is unrouted\n", pin); return -EINVAL; } if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { if (mux != RK_FUNC_GPIO) { - dev_err(info->dev, - "pin %d only supports a gpio mux\n", pin); + dev_err(dev, "pin %d only supports a gpio mux\n", pin); return -ENOTSUPP; } } @@ -909,6 +911,7 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; + struct device *dev = info->dev; int iomux_num = (pin / 8); struct regmap *regmap; int reg, ret, mask, mux_type; @@ -922,8 +925,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) return 0; - dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", - bank->bank_num, pin, mux); + dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? info->regmap_pmu : info->regmap_base; @@ -1575,6 +1577,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret; u32 data, temp, rmask_bits; @@ -1620,7 +1623,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, bit -= 16; break; default: - dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", + dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type); return -EINVAL; } @@ -1632,8 +1635,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3288_DRV_BITS_PER_PIN; break; default: - dev_err(info->dev, "unsupported pinctrl drive type: %d\n", - drv_type); + dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } @@ -1652,13 +1654,14 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, i; u32 data, rmask, rmask_bits, temp; u8 bit; int drv_type = bank->drv[pin_num / 8].drv_type; - dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", + dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength); ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); @@ -1680,8 +1683,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, } if (ret < 0) { - dev_err(info->dev, "unsupported driver strength %d\n", - strength); + dev_err(dev, "unsupported driver strength %d\n", strength); return ret; } @@ -1720,7 +1722,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, bit -= 16; break; default: - dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", + dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type); return -EINVAL; } @@ -1731,8 +1733,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, rmask_bits = RK3288_DRV_BITS_PER_PIN; break; default: - dev_err(info->dev, "unsupported pinctrl drive type: %d\n", - drv_type); + dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } @@ -1766,6 +1767,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, pull_type; u8 bit; @@ -1800,7 +1802,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) return rockchip_pull_list[pull_type][data]; default: - dev_err(info->dev, "unsupported pinctrl type\n"); + dev_err(dev, "unsupported pinctrl type\n"); return -EINVAL; }; } @@ -1810,13 +1812,13 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret, i, pull_type; u8 bit; u32 data, rmask; - dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", - bank->bank_num, pin_num, pull); + dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); /* rk3066b does support any pulls */ if (ctrl->type == RK3066B) @@ -1859,8 +1861,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, } if (ret < 0) { - dev_err(info->dev, "unsupported pull setting %d\n", - pull); + dev_err(dev, "unsupported pull setting %d\n", pull); return ret; } @@ -1872,7 +1873,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, ret = regmap_update_bits(regmap, reg, rmask, data); break; default: - dev_err(info->dev, "unsupported pinctrl type\n"); + dev_err(dev, "unsupported pinctrl type\n"); return -EINVAL; } @@ -1963,12 +1964,13 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl *info = bank->drvdata; struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct device *dev = info->dev; struct regmap *regmap; int reg, ret; u8 bit; u32 data, rmask; - dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", + dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, pin_num, enable); ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); @@ -2028,10 +2030,11 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins = info->groups[group].pins; const struct rockchip_pin_config *data = info->groups[group].data; + struct device *dev = info->dev; struct rockchip_pin_bank *bank; int cnt, ret = 0; - dev_dbg(info->dev, "enable function %s group %s\n", + dev_dbg(dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name); /* @@ -2310,6 +2313,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, struct rockchip_pinctrl *info, u32 index) { + struct device *dev = info->dev; struct rockchip_pin_bank *bank; int size; const __be32 *list; @@ -2317,7 +2321,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, int i, j; int ret; - dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); + dev_dbg(dev, "group(%d): %pOFn\n", index, np); /* Initialise group */ grp->name = np->name; @@ -2329,19 +2333,13 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, list = of_get_property(np, "rockchip,pins", &size); /* we do not check return since it's safe node passed down */ size /= sizeof(*list); - if (!size || size % 4) { - dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); - return -EINVAL; - } + if (!size || size % 4) + return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n"); grp->npins = size / 4; - grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), - GFP_KERNEL); - grp->data = devm_kcalloc(info->dev, - grp->npins, - sizeof(struct rockchip_pin_config), - GFP_KERNEL); + grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); + grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); if (!grp->pins || !grp->data) return -ENOMEM; @@ -2375,6 +2373,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, struct rockchip_pinctrl *info, u32 index) { + struct device *dev = info->dev; struct device_node *child; struct rockchip_pmx_func *func; struct rockchip_pin_group *grp; @@ -2382,7 +2381,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, static u32 grp_index; u32 i = 0; - dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); + dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); func = &info->functions[index]; @@ -2392,8 +2391,7 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, if (func->ngroups <= 0) return 0; - func->groups = devm_kcalloc(info->dev, - func->ngroups, sizeof(char *), GFP_KERNEL); + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); if (!func->groups) return -ENOMEM; @@ -2421,20 +2419,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, rockchip_pinctrl_child_count(info, np); - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); + dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); + dev_dbg(dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kcalloc(dev, - info->nfunctions, - sizeof(struct rockchip_pmx_func), - GFP_KERNEL); + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); if (!info->functions) return -ENOMEM; - info->groups = devm_kcalloc(dev, - info->ngroups, - sizeof(struct rockchip_pin_group), - GFP_KERNEL); + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); if (!info->groups) return -ENOMEM; @@ -2446,7 +2438,7 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, ret = rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); + dev_err(dev, "failed to parse function\n"); of_node_put(child); return ret; } @@ -2461,6 +2453,8 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, struct pinctrl_desc *ctrldesc = &info->pctl; struct pinctrl_pin_desc *pindesc, *pdesc; struct rockchip_pin_bank *pin_bank; + struct device *dev = &pdev->dev; + char **pin_names; int pin, bank, ret; int k; @@ -2470,9 +2464,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, ctrldesc->pmxops = &rockchip_pmx_ops; ctrldesc->confops = &rockchip_pinconf_ops; - pindesc = devm_kcalloc(&pdev->dev, - info->ctrl->nr_pins, sizeof(*pindesc), - GFP_KERNEL); + pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); if (!pindesc) return -ENOMEM; @@ -2482,10 +2474,14 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, pdesc = pindesc; for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { pin_bank = &info->ctrl->pin_banks[bank]; + + pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", - pin_bank->name, pin); + pdesc->name = pin_names[pin]; pdesc++; } @@ -2497,11 +2493,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, if (ret) return ret; - info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); - if (IS_ERR(info->pctl_dev)) { - dev_err(&pdev->dev, "could not register pinctrl driver\n"); - return PTR_ERR(info->pctl_dev); - } + info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); return 0; } @@ -2513,8 +2507,9 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pinctrl *d, struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; const struct of_device_id *match; - struct device_node *node = pdev->dev.of_node; struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; @@ -2566,7 +2561,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( drv_pmu_offs : drv_grf_offs; } - dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", + dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", i, j, iom->offset, drv->offset); /* @@ -2675,16 +2670,14 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node, *node; struct rockchip_pin_ctrl *ctrl; - struct device_node *np = pdev->dev.of_node, *node; struct resource *res; void __iomem *base; int ret; - if (!dev->of_node) { - dev_err(dev, "device tree node not found\n"); - return -ENODEV; - } + if (!dev->of_node) + return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -2693,10 +2686,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) info->dev = dev; ctrl = rockchip_pinctrl_get_soc_data(info, pdev); - if (!ctrl) { - dev_err(dev, "driver data not available\n"); - return -EINVAL; - } + if (!ctrl) + return dev_err_probe(dev, -EINVAL, "driver data not available\n"); info->ctrl = ctrl; node = of_parse_phandle(np, "rockchip,grf", 0); @@ -2705,32 +2696,28 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(info->regmap_base)) return PTR_ERR(info->regmap_base); } else { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); rockchip_regmap_config.max_register = resource_size(res) - 4; rockchip_regmap_config.name = "rockchip,pinctrl"; - info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, - &rockchip_regmap_config); + info->regmap_base = + devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); /* to check for the old dt-bindings */ info->reg_size = resource_size(res); /* Honor the old binding, with pull registers as 2nd resource */ if (ctrl->type == RK3188 && info->reg_size < 0x200) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); if (IS_ERR(base)) return PTR_ERR(base); - rockchip_regmap_config.max_register = - resource_size(res) - 4; + rockchip_regmap_config.max_register = resource_size(res) - 4; rockchip_regmap_config.name = "rockchip,pinctrl-pull"; - info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, - base, - &rockchip_regmap_config); + info->regmap_pull = + devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); } } @@ -2749,10 +2736,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, info); ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL); - if (ret) { - dev_err(&pdev->dev, "failed to register gpio device\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to register gpio device\n"); return 0; } diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1482a01dfec7..0fea71fd9a00 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -55,7 +55,7 @@ #define ST_GPIO_DIRECTION_OUT 0x2 #define ST_GPIO_DIRECTION_IN 0x4 -/** +/* * Packed style retime configuration. * There are two registers cfg0 and cfg1 in this style for each bank. * Each field in this register is 8 bit corresponding to 8 pins in the bank. @@ -69,7 +69,7 @@ #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) -/** +/* * Dedicated style retime Configuration register * each register is dedicated per pin. */ @@ -814,26 +814,25 @@ static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, { struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); const struct st_pctl_group *grp; + struct device *dev = info->dev; struct pinctrl_map *new_map; struct device_node *parent; int map_num, i; grp = st_pctl_find_group_by_name(info, np->name); if (!grp) { - dev_err(info->dev, "unable to find group for node %pOFn\n", - np); + dev_err(dev, "unable to find group for node %pOFn\n", np); return -EINVAL; } map_num = grp->npins + 1; - new_map = devm_kcalloc(pctldev->dev, - map_num, sizeof(*new_map), GFP_KERNEL); + new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; parent = of_get_parent(np); if (!parent) { - devm_kfree(pctldev->dev, new_map); + devm_kfree(dev, new_map); return -EINVAL; } @@ -853,7 +852,7 @@ static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, new_map[i].data.configs.configs = &grp->pin_conf[i].config; new_map[i].data.configs.num_configs = 1; } - dev_info(pctldev->dev, "maps: function %s group %s num %d\n", + dev_info(dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, grp->name, map_num); return 0; @@ -1173,6 +1172,7 @@ static int st_pctl_dt_parse_groups(struct device_node *np, /* bank pad direction val altfunction */ const __be32 *list; struct property *pp; + struct device *dev = info->dev; struct st_pinconf *conf; struct device_node *pins; int i = 0, npins = 0, nr_props, ret = 0; @@ -1197,9 +1197,8 @@ static int st_pctl_dt_parse_groups(struct device_node *np, grp->npins = npins; grp->name = np->name; - grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL); - grp->pin_conf = devm_kcalloc(info->dev, - npins, sizeof(*conf), GFP_KERNEL); + grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); + grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); if (!grp->pins || !grp->pin_conf) { ret = -ENOMEM; @@ -1247,6 +1246,7 @@ out_put_node: static int st_pctl_parse_functions(struct device_node *np, struct st_pinctrl *info, u32 index, int *grp_index) { + struct device *dev = info->dev; struct device_node *child; struct st_pmx_func *func; struct st_pctl_group *grp; @@ -1255,12 +1255,9 @@ static int st_pctl_parse_functions(struct device_node *np, func = &info->functions[index]; func->name = np->name; func->ngroups = of_get_child_count(np); - if (func->ngroups == 0) { - dev_err(info->dev, "No groups defined\n"); - return -EINVAL; - } - func->groups = devm_kcalloc(info->dev, - func->ngroups, sizeof(char *), GFP_KERNEL); + if (func->ngroups == 0) + return dev_err_probe(dev, -EINVAL, "No groups defined\n"); + func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); if (!func->groups) return -ENOMEM; @@ -1275,8 +1272,7 @@ static int st_pctl_parse_functions(struct device_node *np, return ret; } } - dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", - index, func->name, func->ngroups); + dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); return 0; } @@ -1557,10 +1553,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, skip_irq: err = gpiochip_add_data(&bank->gpio_chip, bank); - if (err) { - dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); dev_info(dev, "%s bank added.\n", range->name); return 0; @@ -1577,63 +1571,50 @@ static const struct of_device_id st_pctl_of_match[] = { static int st_pctl_probe_dt(struct platform_device *pdev, struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) { + struct device *dev = &pdev->dev; int ret = 0; int i = 0, j = 0, k = 0, bank; struct pinctrl_pin_desc *pdesc; - struct device_node *np = pdev->dev.of_node; + struct device_node *np = dev->of_node; struct device_node *child; int grp_index = 0; int irq = 0; - struct resource *res; st_pctl_dt_child_count(info, np); - if (!info->nbanks) { - dev_err(&pdev->dev, "you need at least one gpio bank\n"); - return -EINVAL; - } + if (!info->nbanks) + return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); - dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks); - dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups); + dev_info(dev, "nbanks = %d\n", info->nbanks); + dev_info(dev, "nfunctions = %d\n", info->nfunctions); + dev_info(dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kcalloc(&pdev->dev, - info->nfunctions, sizeof(*info->functions), GFP_KERNEL); + info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); - info->groups = devm_kcalloc(&pdev->dev, - info->ngroups, sizeof(*info->groups), - GFP_KERNEL); + info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); - info->banks = devm_kcalloc(&pdev->dev, - info->nbanks, sizeof(*info->banks), GFP_KERNEL); + info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); if (!info->functions || !info->groups || !info->banks) return -ENOMEM; info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); - if (IS_ERR(info->regmap)) { - dev_err(info->dev, "No syscfg phandle specified\n"); - return PTR_ERR(info->regmap); - } + if (IS_ERR(info->regmap)) + return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); info->data = of_match_node(st_pctl_of_match, np)->data; irq = platform_get_irq(pdev, 0); if (irq > 0) { - res = platform_get_resource_byname(pdev, - IORESOURCE_MEM, "irqmux"); - info->irqmux_base = devm_ioremap_resource(&pdev->dev, res); - + info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); if (IS_ERR(info->irqmux_base)) return PTR_ERR(info->irqmux_base); irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, info); - } pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; - pdesc = devm_kcalloc(&pdev->dev, - pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); + pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); if (!pdesc) return -ENOMEM; @@ -1643,6 +1624,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev, for_each_child_of_node(np, child) { if (of_property_read_bool(child, "gpio-controller")) { const char *bank_name = NULL; + char **pin_names; + ret = st_gpiolib_register_bank(info, bank, child); if (ret) { of_node_put(child); @@ -1651,10 +1634,16 @@ static int st_pctl_probe_dt(struct platform_device *pdev, k = info->banks[bank].range.pin_base; bank_name = info->banks[bank].range.name; + + pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); + if (IS_ERR(pin_names)) { + of_node_put(child); + return PTR_ERR(pin_names); + } + for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]", - bank_name, j); + pdesc->name = pin_names[j]; pdesc++; } st_parse_syscfgs(info, bank, child); @@ -1663,7 +1652,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev, ret = st_pctl_parse_functions(child, info, i++, &grp_index); if (ret) { - dev_err(&pdev->dev, "No functions found.\n"); + dev_err(dev, "No functions found.\n"); of_node_put(child); return ret; } @@ -1675,24 +1664,25 @@ static int st_pctl_probe_dt(struct platform_device *pdev, static int st_pctl_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct st_pinctrl *info; struct pinctrl_desc *pctl_desc; int ret, i; - if (!pdev->dev.of_node) { - dev_err(&pdev->dev, "device node not found.\n"); + if (!dev->of_node) { + dev_err(dev, "device node not found.\n"); return -EINVAL; } - pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); + pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); if (!pctl_desc) return -ENOMEM; - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); if (!info) return -ENOMEM; - info->dev = &pdev->dev; + info->dev = dev; platform_set_drvdata(pdev, info); ret = st_pctl_probe_dt(pdev, pctl_desc, info); if (ret) @@ -1702,13 +1692,11 @@ static int st_pctl_probe(struct platform_device *pdev) pctl_desc->pctlops = &st_pctlops; pctl_desc->pmxops = &st_pmxops; pctl_desc->confops = &st_confops; - pctl_desc->name = dev_name(&pdev->dev); + pctl_desc->name = dev_name(dev); - info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info); - if (IS_ERR(info->pctl)) { - dev_err(&pdev->dev, "Failed pinctrl registration\n"); - return PTR_ERR(info->pctl); - } + info->pctl = devm_pinctrl_register(dev, pctl_desc, info); + if (IS_ERR(info->pctl)) + return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); for (i = 0; i < info->nbanks; i++) pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index e14012209992..42da6bd399ee 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -809,6 +809,7 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, unsigned int *npins) { struct pinctrl_pin_desc *pins, *pin; + char **pin_names; int ret; int i; @@ -820,13 +821,14 @@ static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev, if (!pins) return -ENOMEM; + pin_names = devm_kasprintf_strarray(dev, ZYNQMP_PIN_PREFIX, *npins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (i = 0; i < *npins; i++) { pin = &pins[i]; pin->number = i; - pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", - ZYNQMP_PIN_PREFIX, i); - if (!pin->name) - return -ENOMEM; + pin->name = pin_names[i]; } *zynqmp_pins = pins; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 3e0c00766f59..d77637054a15 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -302,6 +302,15 @@ config PINCTRL_SM6350 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM6350 platform. +config PINCTRL_SDX65 + tristate "Qualcomm Technologies Inc SDX65 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDX65 platform. + config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 49b509080745..ecf20b5e615e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 8476a8ac4451..ae09e2dd8a50 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -185,6 +185,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int irq = irq_find_mapping(gc->irq.domain, group); struct irq_data *d = irq_get_irq_data(irq); unsigned int gpio_func = pctrl->soc->gpio_func; + unsigned int egpio_func = pctrl->soc->egpio_func; const struct msm_pingroup *g; unsigned long flags; u32 val, mask; @@ -218,8 +219,18 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_ctl(pctrl, g); - val &= ~mask; - val |= i << g->mux_bit; + + if (egpio_func && i == egpio_func) { + if (val & BIT(g->egpio_present)) + val &= ~BIT(g->egpio_enable); + } else { + val &= ~mask; + val |= i << g->mux_bit; + /* Claim ownership of pin if egpio capable */ + if (egpio_func && val & BIT(g->egpio_present)) + val |= BIT(g->egpio_enable); + } + msm_writel_ctl(val, pctrl, g); raw_spin_unlock_irqrestore(&pctrl->lock, flags); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index e31a5167c91e..dd0d949f7a9e 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -77,6 +77,8 @@ struct msm_pingroup { unsigned drv_bit:5; unsigned od_bit:5; + unsigned egpio_enable:5; + unsigned egpio_present:5; unsigned oe_bit:5; unsigned in_bit:5; unsigned out_bit:5; @@ -119,6 +121,13 @@ struct msm_gpio_wakeirq_map { * to be aware that their parent can't handle dual * edge interrupts. * @gpio_func: Which function number is GPIO (usually 0). + * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in + * hardware this is a mux 1-level above the TLMM, we'll treat + * it as if this is just another mux state of the TLMM. Since + * it doesn't really map to hardware, we'll allocate a virtual + * function number for eGPIO and any time we see that function + * number used we'll treat it as a request to mux away from + * our TLMM towards another owner. */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -136,6 +145,7 @@ struct msm_pinctrl_soc_data { unsigned int nwakeirq_map; bool wakeirq_dual_edge_errata; unsigned int gpio_func; + unsigned int egpio_func; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 9017ede409c9..31df55c79cb3 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -43,6 +43,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -520,6 +522,7 @@ enum sc7280_functions { msm_mux_dp_lcd, msm_mux_edp_hot, msm_mux_edp_lcd, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -658,6 +661,14 @@ static const char * const gpio_groups[] = { "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", }; +static const char * const egpio_groups[] = { + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", +}; static const char * const atest_char_groups[] = { "gpio81", }; @@ -1150,6 +1161,7 @@ static const struct msm_function sc7280_functions[] = { FUNCTION(dp_lcd), FUNCTION(edp_hot), FUNCTION(edp_lcd), + FUNCTION(egpio), FUNCTION(gcc_gp1), FUNCTION(gcc_gp2), FUNCTION(gcc_gp3), @@ -1408,37 +1420,37 @@ static const struct msm_pingroup sc7280_groups[] = { [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _), [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _), [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _), - [144] = PINGROUP(144, _, _, _, _, _, _, _, _, _), - [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _), - [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), - [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), - [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), - [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), - [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, _), - [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, _), - [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, _), - [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, _), - [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _), - [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _), - [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, _), - [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, _), - [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _), - [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _), - [160] = PINGROUP(160, _, _, _, _, _, _, _, _, _), - [161] = PINGROUP(161, _, _, _, _, _, _, _, _, _), - [162] = PINGROUP(162, _, _, _, _, _, _, _, _, _), - [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _), - [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, _, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, qdss, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, qdss, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, qdss, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, qdss, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, qdss_cti, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, qdss_cti, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, _, _, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, _, _, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, _, _, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, qdss_cti, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, qdss_cti, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, qdss, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, egpio), [175] = UFS_RESET(ufs_reset, 0xbe000), [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6), [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6), @@ -1481,6 +1493,7 @@ static const struct msm_pinctrl_soc_data sc7280_pinctrl = { .ngpios = 176, .wakeirq_map = sc7280_pdc_map, .nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map), + .egpio_func = 9, }; static int sc7280_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c new file mode 100644 index 000000000000..e793ea713965 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -0,0 +1,967 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_BASE 0x0 +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_BASE + REG_SIZE * id, \ + .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ + .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdx65_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "UFS_RESET"), + PINCTRL_PIN(109, "SDC1_RCLK"), + PINCTRL_PIN(110, "SDC1_CLK"), + PINCTRL_PIN(111, "SDC1_CMD"), + PINCTRL_PIN(112, "SDC1_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); + +static const unsigned int ufs_reset_pins[] = { 108 }; +static const unsigned int sdc1_rclk_pins[] = { 109 }; +static const unsigned int sdc1_clk_pins[] = { 110 }; +static const unsigned int sdc1_cmd_pins[] = { 111 }; +static const unsigned int sdc1_data_pins[] = { 112 }; + +enum sdx65_functions { + msm_mux_qlink0_wmss, + msm_mux_adsp_ext, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_ref, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_char_exec, + msm_mux_coex_uart, + msm_mux_coex_uart2, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ebi0_wrcdc, + msm_mux_ebi2_a, + msm_mux_ebi2_lcd, + msm_mux_ext_dbg, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_plltest, + msm_mux_gpio, + msm_mux_i2s_mclk, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_m_voc, + msm_mux_mgpi_clk, + msm_mux_native_char, + msm_mux_native_tsens, + msm_mux_native_tsense, + msm_mux_nav_gpio, + msm_mux_pa_indicator, + msm_mux_pci_e, + msm_mux_pcie_clkreq, + msm_mux_pll_bist, + msm_mux_pll_ref, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_en, + msm_mux_qlink0_req, + msm_mux_qlink1_en, + msm_mux_qlink1_req, + msm_mux_qlink1_wmss, + msm_mux_qlink2_en, + msm_mux_qlink2_req, + msm_mux_qlink2_wmss, + msm_mux_sdc1_tb, + msm_mux_sec_mi2s, + msm_mux_spmi_coex, + msm_mux_spmi_vgi, + msm_mux_tgu_ch0, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", +}; +static const char * const uim2_data_groups[] = { + "gpio0", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80", + "gpio81", +}; +static const char * const ebi0_wrcdc_groups[] = { + "gpio0", "gpio2", +}; +static const char * const uim2_present_groups[] = { + "gpio1", +}; +static const char * const uim2_reset_groups[] = { + "gpio2", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", "gpio82", "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65", + "gpio66", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", "gpio65", "gpio66", +}; +static const char * const char_exec_groups[] = { + "gpio6", "gpio7", +}; +static const char * const qdss_gpio_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ext_dbg_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const ldo_en_groups[] = { + "gpio8", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const gcc_gp3_groups[] = { + "gpio11", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio12", +}; +static const char * const pri_mi2s_groups[] = { + "gpio13", "gpio14", "gpio15", +}; +static const char * const vsense_trigger_groups[] = { + "gpio13", +}; +static const char * const native_tsens_groups[] = { + "gpio14", +}; +static const char * const bimc_dte0_groups[] = { + "gpio14", "gpio59", +}; +static const char * const bimc_dte1_groups[] = { + "gpio15", "gpio61", +}; +static const char * const sec_mi2s_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62", +}; +static const char * const blsp_uart4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48", + "gpio49", +}; +static const char * const qdss_cti_groups[] = { + "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55", + "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66", + "gpio94", "gpio94", "gpio95", "gpio95", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio18", "gpio19", "gpio84", "gpio85", +}; +static const char * const gcc_gp1_groups[] = { + "gpio18", +}; +static const char * const jitter_bist_groups[] = { + "gpio19", +}; +static const char * const gcc_gp2_groups[] = { + "gpio19", +}; +static const char * const pll_bist_groups[] = { + "gpio22", +}; +static const char * const blsp_spi1_groups[] = { + "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const adsp_ext_groups[] = { + "gpio24", "gpio25", +}; +static const char * const qlink0_wmss_groups[] = { + "gpio28", +}; +static const char * const native_tsense_groups[] = { + "gpio29", "gpio72", +}; +static const char * const nav_gpio_groups[] = { + "gpio31", "gpio32", +}; +static const char * const pll_ref_groups[] = { + "gpio32", +}; +static const char * const pa_indicator_groups[] = { + "gpio33", +}; +static const char * const qlink0_en_groups[] = { + "gpio34", +}; +static const char * const qlink0_req_groups[] = { + "gpio35", +}; +static const char * const dbg_out_groups[] = { + "gpio35", +}; +static const char * const cri_trng_groups[] = { + "gpio36", +}; +static const char * const prng_rosc_groups[] = { + "gpio38", +}; +static const char * const cri_trng0_groups[] = { + "gpio40", +}; +static const char * const cri_trng1_groups[] = { + "gpio41", +}; +static const char * const coex_uart_groups[] = { + "gpio44", "gpio45", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio45", "gpio46", +}; +static const char * const m_voc_groups[] = { + "gpio46", "gpio48", "gpio49", "gpio59", "gpio60", +}; +static const char * const ddr_bist_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; +static const char * const pci_e_groups[] = { + "gpio53", +}; +static const char * const tgu_ch0_groups[] = { + "gpio55", +}; +static const char * const pcie_clkreq_groups[] = { + "gpio56", +}; +static const char * const native_char_groups[] = { + "gpio26", "gpio29", "gpio33", "gpio42", "gpio57", +}; +static const char * const mgpi_clk_groups[] = { + "gpio61", "gpio71", +}; +static const char * const qlink2_wmss_groups[] = { + "gpio61", +}; +static const char * const i2s_mclk_groups[] = { + "gpio62", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const ldo_update_groups[] = { + "gpio62", +}; +static const char * const atest_char_groups[] = { + "gpio63", +}; +static const char * const atest_char3_groups[] = { + "gpio64", +}; +static const char * const atest_char2_groups[] = { + "gpio65", +}; +static const char * const atest_char1_groups[] = { + "gpio66", +}; +static const char * const uim1_data_groups[] = { + "gpio67", +}; +static const char * const atest_char0_groups[] = { + "gpio67", +}; +static const char * const uim1_present_groups[] = { + "gpio68", +}; +static const char * const uim1_reset_groups[] = { + "gpio69", +}; +static const char * const uim1_clk_groups[] = { + "gpio70", +}; +static const char * const qlink2_en_groups[] = { + "gpio71", +}; +static const char * const qlink1_en_groups[] = { + "gpio72", +}; +static const char * const qlink1_req_groups[] = { + "gpio73", +}; +static const char * const qlink1_wmss_groups[] = { + "gpio74", +}; +static const char * const coex_uart2_groups[] = { + "gpio75", "gpio76", "gpio102", "gpio103", +}; +static const char * const spmi_coex_groups[] = { + "gpio75", "gpio76", +}; +static const char * const qlink2_req_groups[] = { + "gpio77", +}; +static const char * const spmi_vgi_groups[] = { + "gpio78", "gpio79", +}; +static const char * const gcc_plltest_groups[] = { + "gpio81", "gpio82", +}; +static const char * const ebi2_lcd_groups[] = { + "gpio84", "gpio85", "gpio90", +}; +static const char * const ebi2_a_groups[] = { + "gpio89", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio93", +}; +static const char * const sdc1_tb_groups[] = { + "gpio106", +}; + +static const struct msm_function sdx65_functions[] = { + FUNCTION(qlink0_wmss), + FUNCTION(adsp_ext), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(audio_ref), + FUNCTION(bimc_dte0), + FUNCTION(bimc_dte1), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(char_exec), + FUNCTION(coex_uart), + FUNCTION(coex_uart2), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ebi0_wrcdc), + FUNCTION(ebi2_a), + FUNCTION(ebi2_lcd), + FUNCTION(ext_dbg), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_plltest), + FUNCTION(gpio), + FUNCTION(i2s_mclk), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(m_voc), + FUNCTION(mgpi_clk), + FUNCTION(native_char), + FUNCTION(native_tsens), + FUNCTION(native_tsense), + FUNCTION(nav_gpio), + FUNCTION(pa_indicator), + FUNCTION(pci_e), + FUNCTION(pcie_clkreq), + FUNCTION(pll_bist), + FUNCTION(pll_ref), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qlink0_en), + FUNCTION(qlink0_req), + FUNCTION(qlink1_en), + FUNCTION(qlink1_req), + FUNCTION(qlink1_wmss), + FUNCTION(qlink2_en), + FUNCTION(qlink2_req), + FUNCTION(qlink2_wmss), + FUNCTION(sdc1_tb), + FUNCTION(sec_mi2s), + FUNCTION(spmi_coex), + FUNCTION(spmi_vgi), + FUNCTION(tgu_ch0), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdx65_groups[] = { + [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _), + [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _), + [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _), + [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _), + [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _), + [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _), + [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _), + [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _), + [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _), + [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _), + [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _), + [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _), + [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _), + [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _), + [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _), + [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _), + [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _), + [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _), + [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _), + [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _), + [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _), + [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _), + [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _), + [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _), + [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _), + [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _), + [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _), + [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _), + [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _), + [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _), + [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _), + [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _), + [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _), + [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _), + [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _), + [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _), + [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _), + [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _), + [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _), + [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _), + [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _), + [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _), + [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _), + [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _), + [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _), + [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _), + [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _), + [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _), + [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _), + [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _), + [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _), + [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _), + [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _), + [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _), + [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _), + [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _), + [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _), + [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), + [108] = UFS_RESET(ufs_reset, 0x0), + [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), + [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6), + [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3), + [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = { + {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25}, + {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31}, + {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70}, + {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45}, + {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53}, + {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59}, + {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67}, + {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74}, + {99, 75}, {103, 78}, {104, 79} +}; + +static const struct msm_pinctrl_soc_data sdx65_pinctrl = { + .pins = sdx65_pins, + .npins = ARRAY_SIZE(sdx65_pins), + .functions = sdx65_functions, + .nfunctions = ARRAY_SIZE(sdx65_functions), + .groups = sdx65_groups, + .ngroups = ARRAY_SIZE(sdx65_groups), + .ngpios = 109, + .wakeirq_map = sdx65_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map), +}; + +static int sdx65_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdx65_pinctrl); +} + +static const struct of_device_id sdx65_pinctrl_of_match[] = { + { .compatible = "qcom,sdx65-tlmm", }, + { }, +}; + +static struct platform_driver sdx65_pinctrl_driver = { + .driver = { + .name = "sdx65-tlmm", + .of_match_table = sdx65_pinctrl_of_match, + }, + .probe = sdx65_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdx65_pinctrl_init(void) +{ + return platform_driver_register(&sdx65_pinctrl_driver); +} +arch_initcall(sdx65_pinctrl_init); + +static void __exit sdx65_pinctrl_exit(void) +{ + platform_driver_unregister(&sdx65_pinctrl_driver); +} +module_exit(sdx65_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdx65 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 5283d5e9e8bc..f2eac3b05d67 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1141,6 +1141,7 @@ static int pmic_gpio_remove(struct platform_device *pdev) } static const struct of_device_id pmic_gpio_of_match[] = { + { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 }, /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ @@ -1151,6 +1152,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 }, + { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 }, diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h index 4ba39e1403b2..7a22921c9db7 100644 --- a/include/linux/string_helpers.h +++ b/include/linux/string_helpers.h @@ -7,6 +7,7 @@ #include <linux/string.h> #include <linux/types.h> +struct device; struct file; struct task_struct; @@ -100,6 +101,9 @@ char *kstrdup_quotable(const char *src, gfp_t gfp); char *kstrdup_quotable_cmdline(struct task_struct *task, gfp_t gfp); char *kstrdup_quotable_file(struct file *file, gfp_t gfp); +char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n); void kfree_strarray(char **array, size_t n); +char **devm_kasprintf_strarray(struct device *dev, const char *prefix, size_t n); + #endif diff --git a/lib/string_helpers.c b/lib/string_helpers.c index d5d008f5b1d9..90f9f1b7afec 100644 --- a/lib/string_helpers.c +++ b/lib/string_helpers.c @@ -10,6 +10,7 @@ #include <linux/math64.h> #include <linux/export.h> #include <linux/ctype.h> +#include <linux/device.h> #include <linux/errno.h> #include <linux/fs.h> #include <linux/limits.h> @@ -675,6 +676,39 @@ char *kstrdup_quotable_file(struct file *file, gfp_t gfp) EXPORT_SYMBOL_GPL(kstrdup_quotable_file); /** + * kasprintf_strarray - allocate and fill array of sequential strings + * @gfp: flags for the slab allocator + * @prefix: prefix to be used + * @n: amount of lines to be allocated and filled + * + * Allocates and fills @n strings using pattern "%s-%zu", where prefix + * is provided by caller. The caller is responsible to free them with + * kfree_strarray() after use. + * + * Returns array of strings or NULL when memory can't be allocated. + */ +char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n) +{ + char **names; + size_t i; + + names = kcalloc(n + 1, sizeof(char *), gfp); + if (!names) + return NULL; + + for (i = 0; i < n; i++) { + names[i] = kasprintf(gfp, "%s-%zu", prefix, i); + if (!names[i]) { + kfree_strarray(names, i); + return NULL; + } + } + + return names; +} +EXPORT_SYMBOL_GPL(kasprintf_strarray); + +/** * kfree_strarray - free a number of dynamically allocated strings contained * in an array and the array itself * @@ -697,6 +731,36 @@ void kfree_strarray(char **array, size_t n) } EXPORT_SYMBOL_GPL(kfree_strarray); +struct strarray { + char **array; + size_t n; +}; + +static void devm_kfree_strarray(struct device *dev, void *res) +{ + struct strarray *array = res; + + kfree_strarray(array->array, array->n); +} + +char **devm_kasprintf_strarray(struct device *dev, const char *prefix, size_t n) +{ + struct strarray *ptr; + + ptr = devres_alloc(devm_kfree_strarray, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + ptr->array = kasprintf_strarray(GFP_KERNEL, prefix, n); + if (!ptr->array) { + devres_free(ptr); + return ERR_PTR(-ENOMEM); + } + + return ptr->array; +} +EXPORT_SYMBOL_GPL(devm_kasprintf_strarray); + /** * strscpy_pad() - Copy a C-string into a sized buffer * @dest: Where to copy the string to |