diff options
Diffstat (limited to 'Documentation')
238 files changed, 7787 insertions, 4583 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-pwm b/Documentation/ABI/testing/sysfs-class-pwm index c479d77b67c5..c20e61354561 100644 --- a/Documentation/ABI/testing/sysfs-class-pwm +++ b/Documentation/ABI/testing/sysfs-class-pwm @@ -77,3 +77,12 @@ Description: Enable/disable the PWM signal. 0 is disabled 1 is enabled + +What: /sys/class/pwm/pwmchipN/pwmX/capture +Date: June 2016 +KernelVersion: 4.8 +Contact: Lee Jones <lee.jones@linaro.org> +Description: + Capture information about a PWM signal. The output format is a + pair unsigned integers (period and duty cycle), separated by a + single space. diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt index 45ef3f279c3b..1d26eeb6b5f6 100644 --- a/Documentation/DMA-API.txt +++ b/Documentation/DMA-API.txt @@ -369,35 +369,32 @@ See also dma_map_single(). dma_addr_t dma_map_single_attrs(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) + unsigned long attrs) void dma_unmap_single_attrs(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) + unsigned long attrs) int dma_map_sg_attrs(struct device *dev, struct scatterlist *sgl, int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) + unsigned long attrs) void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sgl, int nents, enum dma_data_direction dir, - struct dma_attrs *attrs) + unsigned long attrs) The four functions above are just like the counterpart functions without the _attrs suffixes, except that they pass an optional -struct dma_attrs*. - -struct dma_attrs encapsulates a set of "DMA attributes". For the -definition of struct dma_attrs see linux/dma-attrs.h. +dma_attrs. The interpretation of DMA attributes is architecture-specific, and each attribute should be documented in Documentation/DMA-attributes.txt. -If struct dma_attrs* is NULL, the semantics of each of these -functions is identical to those of the corresponding function +If dma_attrs are 0, the semantics of each of these functions +is identical to those of the corresponding function without the _attrs suffix. As a result dma_map_single_attrs() can generally replace dma_map_single(), etc. @@ -405,15 +402,15 @@ As an example of the use of the *_attrs functions, here's how you could pass an attribute DMA_ATTR_FOO when mapping memory for DMA: -#include <linux/dma-attrs.h> -/* DMA_ATTR_FOO should be defined in linux/dma-attrs.h and +#include <linux/dma-mapping.h> +/* DMA_ATTR_FOO should be defined in linux/dma-mapping.h and * documented in Documentation/DMA-attributes.txt */ ... - DEFINE_DMA_ATTRS(attrs); - dma_set_attr(DMA_ATTR_FOO, &attrs); + unsigned long attr; + attr |= DMA_ATTR_FOO; .... - n = dma_map_sg_attrs(dev, sg, nents, DMA_TO_DEVICE, &attr); + n = dma_map_sg_attrs(dev, sg, nents, DMA_TO_DEVICE, attr); .... Architectures that care about DMA_ATTR_FOO would check for its @@ -422,12 +419,10 @@ routines, e.g.: void whizco_dma_map_sg_attrs(struct device *dev, dma_addr_t dma_addr, size_t size, enum dma_data_direction dir, - struct dma_attrs *attrs) + unsigned long attrs) { .... - int foo = dma_get_attr(DMA_ATTR_FOO, attrs); - .... - if (foo) + if (attrs & DMA_ATTR_FOO) /* twizzle the frobnozzle */ .... diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index e8cf9cf873b3..2d455a5cf671 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -2,7 +2,7 @@ ============== This document describes the semantics of the DMA attributes that are -defined in linux/dma-attrs.h. +defined in linux/dma-mapping.h. DMA_ATTR_WRITE_BARRIER ---------------------- diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile index 2bfd664b5e35..c481df33ef21 100644 --- a/Documentation/DocBook/Makefile +++ b/Documentation/DocBook/Makefile @@ -16,7 +16,7 @@ DOCBOOKS := z8530book.xml device-drivers.xml \ genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \ 80211.xml debugobjects.xml sh.xml regulator.xml \ alsa-driver-api.xml writing-an-alsa-driver.xml \ - tracepoint.xml gpu.xml w1.xml \ + tracepoint.xml w1.xml \ writing_musb_glue_layer.xml crypto-API.xml iio.xml ### diff --git a/Documentation/DocBook/device-drivers.tmpl b/Documentation/DocBook/device-drivers.tmpl index 7febdeb08159..9c10030eb2be 100644 --- a/Documentation/DocBook/device-drivers.tmpl +++ b/Documentation/DocBook/device-drivers.tmpl @@ -161,6 +161,10 @@ X!Edrivers/base/interface.c !Iinclude/linux/fence.h !Edrivers/dma-buf/seqno-fence.c !Iinclude/linux/seqno-fence.h +!Edrivers/dma-buf/fence-array.c +!Iinclude/linux/fence-array.h +!Edrivers/dma-buf/reservation.c +!Iinclude/linux/reservation.h !Edrivers/dma-buf/sync_file.c !Iinclude/linux/sync_file.h </sect2> @@ -484,7 +488,7 @@ X!Ilib/fonts/fonts.c </para> !Iinclude/linux/hsi/hsi.h -!Edrivers/hsi/hsi.c +!Edrivers/hsi/hsi_core.c </chapter> <chapter id="pwm"> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl deleted file mode 100644 index 7586bf75f62e..000000000000 --- a/Documentation/DocBook/gpu.tmpl +++ /dev/null @@ -1,3540 +0,0 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN" - "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []> - -<book id="gpuDevelopersGuide"> - <bookinfo> - <title>Linux GPU Driver Developer's Guide</title> - - <authorgroup> - <author> - <firstname>Jesse</firstname> - <surname>Barnes</surname> - <contrib>Initial version</contrib> - <affiliation> - <orgname>Intel Corporation</orgname> - <address> - <email>jesse.barnes@intel.com</email> - </address> - </affiliation> - </author> - <author> - <firstname>Laurent</firstname> - <surname>Pinchart</surname> - <contrib>Driver internals</contrib> - <affiliation> - <orgname>Ideas on board SPRL</orgname> - <address> - <email>laurent.pinchart@ideasonboard.com</email> - </address> - </affiliation> - </author> - <author> - <firstname>Daniel</firstname> - <surname>Vetter</surname> - <contrib>Contributions all over the place</contrib> - <affiliation> - <orgname>Intel Corporation</orgname> - <address> - <email>daniel.vetter@ffwll.ch</email> - </address> - </affiliation> - </author> - <author> - <firstname>Lukas</firstname> - <surname>Wunner</surname> - <contrib>vga_switcheroo documentation</contrib> - <affiliation> - <address> - <email>lukas@wunner.de</email> - </address> - </affiliation> - </author> - </authorgroup> - - <copyright> - <year>2008-2009</year> - <year>2013-2014</year> - <holder>Intel Corporation</holder> - </copyright> - <copyright> - <year>2012</year> - <holder>Laurent Pinchart</holder> - </copyright> - <copyright> - <year>2015</year> - <holder>Lukas Wunner</holder> - </copyright> - - <legalnotice> - <para> - The contents of this file may be used under the terms of the GNU - General Public License version 2 (the "GPL") as distributed in - the kernel source COPYING file. - </para> - </legalnotice> - - <revhistory> - <!-- Put document revisions here, newest first. --> - <revision> - <revnumber>1.0</revnumber> - <date>2012-07-13</date> - <authorinitials>LP</authorinitials> - <revremark>Added extensive documentation about driver internals. - </revremark> - </revision> - <revision> - <revnumber>1.1</revnumber> - <date>2015-10-11</date> - <authorinitials>LW</authorinitials> - <revremark>Added vga_switcheroo documentation. - </revremark> - </revision> - </revhistory> - </bookinfo> - -<toc></toc> - -<part id="drmCore"> - <title>DRM Core</title> - <partintro> - <para> - This first part of the GPU Driver Developer's Guide documents core DRM - code, helper libraries for writing drivers and generic userspace - interfaces exposed by DRM drivers. - </para> - </partintro> - - <chapter id="drmIntroduction"> - <title>Introduction</title> - <para> - The Linux DRM layer contains code intended to support the needs - of complex graphics devices, usually containing programmable - pipelines well suited to 3D graphics acceleration. Graphics - drivers in the kernel may make use of DRM functions to make - tasks like memory management, interrupt handling and DMA easier, - and provide a uniform interface to applications. - </para> - <para> - A note on versions: this guide covers features found in the DRM - tree, including the TTM memory manager, output configuration and - mode setting, and the new vblank internals, in addition to all - the regular features found in current kernels. - </para> - <para> - [Insert diagram of typical DRM stack here] - </para> - <sect1> - <title>Style Guidelines</title> - <para> - For consistency this documentation uses American English. Abbreviations - are written as all-uppercase, for example: DRM, KMS, IOCTL, CRTC, and so - on. To aid in reading, documentations make full use of the markup - characters kerneldoc provides: @parameter for function parameters, @member - for structure members, &structure to reference structures and - function() for functions. These all get automatically hyperlinked if - kerneldoc for the referenced objects exists. When referencing entries in - function vtables please use ->vfunc(). Note that kerneldoc does - not support referencing struct members directly, so please add a reference - to the vtable struct somewhere in the same paragraph or at least section. - </para> - <para> - Except in special situations (to separate locked from unlocked variants) - locking requirements for functions aren't documented in the kerneldoc. - Instead locking should be check at runtime using e.g. - <code>WARN_ON(!mutex_is_locked(...));</code>. Since it's much easier to - ignore documentation than runtime noise this provides more value. And on - top of that runtime checks do need to be updated when the locking rules - change, increasing the chances that they're correct. Within the - documentation the locking rules should be explained in the relevant - structures: Either in the comment for the lock explaining what it - protects, or data fields need a note about which lock protects them, or - both. - </para> - <para> - Functions which have a non-<code>void</code> return value should have a - section called "Returns" explaining the expected return values in - different cases and their meanings. Currently there's no consensus whether - that section name should be all upper-case or not, and whether it should - end in a colon or not. Go with the file-local style. Other common section - names are "Notes" with information for dangerous or tricky corner cases, - and "FIXME" where the interface could be cleaned up. - </para> - </sect1> - </chapter> - - <!-- Internals --> - - <chapter id="drmInternals"> - <title>DRM Internals</title> - <para> - This chapter documents DRM internals relevant to driver authors - and developers working to add support for the latest features to - existing drivers. - </para> - <para> - First, we go over some typical driver initialization - requirements, like setting up command buffers, creating an - initial output configuration, and initializing core services. - Subsequent sections cover core internals in more detail, - providing implementation notes and examples. - </para> - <para> - The DRM layer provides several services to graphics drivers, - many of them driven by the application interfaces it provides - through libdrm, the library that wraps most of the DRM ioctls. - These include vblank event handling, memory - management, output management, framebuffer management, command - submission & fencing, suspend/resume support, and DMA - services. - </para> - - <!-- Internals: driver init --> - - <sect1> - <title>Driver Initialization</title> - <para> - At the core of every DRM driver is a <structname>drm_driver</structname> - structure. Drivers typically statically initialize a drm_driver structure, - and then pass it to <function>drm_dev_alloc()</function> to allocate a - device instance. After the device instance is fully initialized it can be - registered (which makes it accessible from userspace) using - <function>drm_dev_register()</function>. - </para> - <para> - The <structname>drm_driver</structname> structure contains static - information that describes the driver and features it supports, and - pointers to methods that the DRM core will call to implement the DRM API. - We will first go through the <structname>drm_driver</structname> static - information fields, and will then describe individual operations in - details as they get used in later sections. - </para> - <sect2> - <title>Driver Information</title> - <sect3> - <title>Driver Features</title> - <para> - Drivers inform the DRM core about their requirements and supported - features by setting appropriate flags in the - <structfield>driver_features</structfield> field. Since those flags - influence the DRM core behaviour since registration time, most of them - must be set to registering the <structname>drm_driver</structname> - instance. - </para> - <synopsis>u32 driver_features;</synopsis> - <variablelist> - <title>Driver Feature Flags</title> - <varlistentry> - <term>DRIVER_USE_AGP</term> - <listitem><para> - Driver uses AGP interface, the DRM core will manage AGP resources. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_REQUIRE_AGP</term> - <listitem><para> - Driver needs AGP interface to function. AGP initialization failure - will become a fatal error. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_PCI_DMA</term> - <listitem><para> - Driver is capable of PCI DMA, mapping of PCI DMA buffers to - userspace will be enabled. Deprecated. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_SG</term> - <listitem><para> - Driver can perform scatter/gather DMA, allocation and mapping of - scatter/gather buffers will be enabled. Deprecated. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_HAVE_DMA</term> - <listitem><para> - Driver supports DMA, the userspace DMA API will be supported. - Deprecated. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_HAVE_IRQ</term><term>DRIVER_IRQ_SHARED</term> - <listitem><para> - DRIVER_HAVE_IRQ indicates whether the driver has an IRQ handler - managed by the DRM Core. The core will support simple IRQ handler - installation when the flag is set. The installation process is - described in <xref linkend="drm-irq-registration"/>.</para> - <para>DRIVER_IRQ_SHARED indicates whether the device & handler - support shared IRQs (note that this is required of PCI drivers). - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_GEM</term> - <listitem><para> - Driver use the GEM memory manager. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_MODESET</term> - <listitem><para> - Driver supports mode setting interfaces (KMS). - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_PRIME</term> - <listitem><para> - Driver implements DRM PRIME buffer sharing. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_RENDER</term> - <listitem><para> - Driver supports dedicated render nodes. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRIVER_ATOMIC</term> - <listitem><para> - Driver supports atomic properties. In this case the driver - must implement appropriate obj->atomic_get_property() vfuncs - for any modeset objects with driver specific properties. - </para></listitem> - </varlistentry> - </variablelist> - </sect3> - <sect3> - <title>Major, Minor and Patchlevel</title> - <synopsis>int major; -int minor; -int patchlevel;</synopsis> - <para> - The DRM core identifies driver versions by a major, minor and patch - level triplet. The information is printed to the kernel log at - initialization time and passed to userspace through the - DRM_IOCTL_VERSION ioctl. - </para> - <para> - The major and minor numbers are also used to verify the requested driver - API version passed to DRM_IOCTL_SET_VERSION. When the driver API changes - between minor versions, applications can call DRM_IOCTL_SET_VERSION to - select a specific version of the API. If the requested major isn't equal - to the driver major, or the requested minor is larger than the driver - minor, the DRM_IOCTL_SET_VERSION call will return an error. Otherwise - the driver's set_version() method will be called with the requested - version. - </para> - </sect3> - <sect3> - <title>Name, Description and Date</title> - <synopsis>char *name; -char *desc; -char *date;</synopsis> - <para> - The driver name is printed to the kernel log at initialization time, - used for IRQ registration and passed to userspace through - DRM_IOCTL_VERSION. - </para> - <para> - The driver description is a purely informative string passed to - userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by - the kernel. - </para> - <para> - The driver date, formatted as YYYYMMDD, is meant to identify the date of - the latest modification to the driver. However, as most drivers fail to - update it, its value is mostly useless. The DRM core prints it to the - kernel log at initialization time and passes it to userspace through the - DRM_IOCTL_VERSION ioctl. - </para> - </sect3> - </sect2> - <sect2> - <title>Device Instance and Driver Handling</title> -!Pdrivers/gpu/drm/drm_drv.c driver instance overview -!Edrivers/gpu/drm/drm_drv.c - </sect2> - <sect2> - <title>Driver Load</title> - <sect3 id="drm-irq-registration"> - <title>IRQ Registration</title> - <para> - The DRM core tries to facilitate IRQ handler registration and - unregistration by providing <function>drm_irq_install</function> and - <function>drm_irq_uninstall</function> functions. Those functions only - support a single interrupt per device, devices that use more than one - IRQs need to be handled manually. - </para> - <sect4> - <title>Managed IRQ Registration</title> - <para> - <function>drm_irq_install</function> starts by calling the - <methodname>irq_preinstall</methodname> driver operation. The operation - is optional and must make sure that the interrupt will not get fired by - clearing all pending interrupt flags or disabling the interrupt. - </para> - <para> - The passed-in IRQ will then be requested by a call to - <function>request_irq</function>. If the DRIVER_IRQ_SHARED driver - feature flag is set, a shared (IRQF_SHARED) IRQ handler will be - requested. - </para> - <para> - The IRQ handler function must be provided as the mandatory irq_handler - driver operation. It will get passed directly to - <function>request_irq</function> and thus has the same prototype as all - IRQ handlers. It will get called with a pointer to the DRM device as the - second argument. - </para> - <para> - Finally the function calls the optional - <methodname>irq_postinstall</methodname> driver operation. The operation - usually enables interrupts (excluding the vblank interrupt, which is - enabled separately), but drivers may choose to enable/disable interrupts - at a different time. - </para> - <para> - <function>drm_irq_uninstall</function> is similarly used to uninstall an - IRQ handler. It starts by waking up all processes waiting on a vblank - interrupt to make sure they don't hang, and then calls the optional - <methodname>irq_uninstall</methodname> driver operation. The operation - must disable all hardware interrupts. Finally the function frees the IRQ - by calling <function>free_irq</function>. - </para> - </sect4> - <sect4> - <title>Manual IRQ Registration</title> - <para> - Drivers that require multiple interrupt handlers can't use the managed - IRQ registration functions. In that case IRQs must be registered and - unregistered manually (usually with the <function>request_irq</function> - and <function>free_irq</function> functions, or their devm_* equivalent). - </para> - <para> - When manually registering IRQs, drivers must not set the DRIVER_HAVE_IRQ - driver feature flag, and must not provide the - <methodname>irq_handler</methodname> driver operation. They must set the - <structname>drm_device</structname> <structfield>irq_enabled</structfield> - field to 1 upon registration of the IRQs, and clear it to 0 after - unregistering the IRQs. - </para> - </sect4> - </sect3> - <sect3> - <title>Memory Manager Initialization</title> - <para> - Every DRM driver requires a memory manager which must be initialized at - load time. DRM currently contains two memory managers, the Translation - Table Manager (TTM) and the Graphics Execution Manager (GEM). - This document describes the use of the GEM memory manager only. See - <xref linkend="drm-memory-management"/> for details. - </para> - </sect3> - <sect3> - <title>Miscellaneous Device Configuration</title> - <para> - Another task that may be necessary for PCI devices during configuration - is mapping the video BIOS. On many devices, the VBIOS describes device - configuration, LCD panel timings (if any), and contains flags indicating - device state. Mapping the BIOS can be done using the pci_map_rom() call, - a convenience function that takes care of mapping the actual ROM, - whether it has been shadowed into memory (typically at address 0xc0000) - or exists on the PCI device in the ROM BAR. Note that after the ROM has - been mapped and any necessary information has been extracted, it should - be unmapped; on many devices, the ROM address decoder is shared with - other BARs, so leaving it mapped could cause undesired behaviour like - hangs or memory corruption. - <!--!Fdrivers/pci/rom.c pci_map_rom--> - </para> - </sect3> - </sect2> - <sect2> - <title>Bus-specific Device Registration and PCI Support</title> - <para> - A number of functions are provided to help with device registration. - The functions deal with PCI and platform devices respectively and are - only provided for historical reasons. These are all deprecated and - shouldn't be used in new drivers. Besides that there's a few - helpers for pci drivers. - </para> -!Edrivers/gpu/drm/drm_pci.c -!Edrivers/gpu/drm/drm_platform.c - </sect2> - </sect1> - - <!-- Internals: memory management --> - - <sect1 id="drm-memory-management"> - <title>Memory management</title> - <para> - Modern Linux systems require large amount of graphics memory to store - frame buffers, textures, vertices and other graphics-related data. Given - the very dynamic nature of many of that data, managing graphics memory - efficiently is thus crucial for the graphics stack and plays a central - role in the DRM infrastructure. - </para> - <para> - The DRM core includes two memory managers, namely Translation Table Maps - (TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory - manager to be developed and tried to be a one-size-fits-them all - solution. It provides a single userspace API to accommodate the need of - all hardware, supporting both Unified Memory Architecture (UMA) devices - and devices with dedicated video RAM (i.e. most discrete video cards). - This resulted in a large, complex piece of code that turned out to be - hard to use for driver development. - </para> - <para> - GEM started as an Intel-sponsored project in reaction to TTM's - complexity. Its design philosophy is completely different: instead of - providing a solution to every graphics memory-related problems, GEM - identified common code between drivers and created a support library to - share it. GEM has simpler initialization and execution requirements than - TTM, but has no video RAM management capabilities and is thus limited to - UMA devices. - </para> - <sect2> - <title>The Translation Table Manager (TTM)</title> - <para> - TTM design background and information belongs here. - </para> - <sect3> - <title>TTM initialization</title> - <warning><para>This section is outdated.</para></warning> - <para> - Drivers wishing to support TTM must fill out a drm_bo_driver - structure. The structure contains several fields with function - pointers for initializing the TTM, allocating and freeing memory, - waiting for command completion and fence synchronization, and memory - migration. See the radeon_ttm.c file for an example of usage. - </para> - <para> - The ttm_global_reference structure is made up of several fields: - </para> - <programlisting> - struct ttm_global_reference { - enum ttm_global_types global_type; - size_t size; - void *object; - int (*init) (struct ttm_global_reference *); - void (*release) (struct ttm_global_reference *); - }; - </programlisting> - <para> - There should be one global reference structure for your memory - manager as a whole, and there will be others for each object - created by the memory manager at runtime. Your global TTM should - have a type of TTM_GLOBAL_TTM_MEM. The size field for the global - object should be sizeof(struct ttm_mem_global), and the init and - release hooks should point at your driver-specific init and - release routines, which probably eventually call - ttm_mem_global_init and ttm_mem_global_release, respectively. - </para> - <para> - Once your global TTM accounting structure is set up and initialized - by calling ttm_global_item_ref() on it, - you need to create a buffer object TTM to - provide a pool for buffer object allocation by clients and the - kernel itself. The type of this object should be TTM_GLOBAL_TTM_BO, - and its size should be sizeof(struct ttm_bo_global). Again, - driver-specific init and release functions may be provided, - likely eventually calling ttm_bo_global_init() and - ttm_bo_global_release(), respectively. Also, like the previous - object, ttm_global_item_ref() is used to create an initial reference - count for the TTM, which will call your initialization function. - </para> - </sect3> - </sect2> - <sect2 id="drm-gem"> - <title>The Graphics Execution Manager (GEM)</title> - <para> - The GEM design approach has resulted in a memory manager that doesn't - provide full coverage of all (or even all common) use cases in its - userspace or kernel API. GEM exposes a set of standard memory-related - operations to userspace and a set of helper functions to drivers, and let - drivers implement hardware-specific operations with their own private API. - </para> - <para> - The GEM userspace API is described in the - <ulink url="http://lwn.net/Articles/283798/"><citetitle>GEM - the Graphics - Execution Manager</citetitle></ulink> article on LWN. While slightly - outdated, the document provides a good overview of the GEM API principles. - Buffer allocation and read and write operations, described as part of the - common GEM API, are currently implemented using driver-specific ioctls. - </para> - <para> - GEM is data-agnostic. It manages abstract buffer objects without knowing - what individual buffers contain. APIs that require knowledge of buffer - contents or purpose, such as buffer allocation or synchronization - primitives, are thus outside of the scope of GEM and must be implemented - using driver-specific ioctls. - </para> - <para> - On a fundamental level, GEM involves several operations: - <itemizedlist> - <listitem>Memory allocation and freeing</listitem> - <listitem>Command execution</listitem> - <listitem>Aperture management at command execution time</listitem> - </itemizedlist> - Buffer object allocation is relatively straightforward and largely - provided by Linux's shmem layer, which provides memory to back each - object. - </para> - <para> - Device-specific operations, such as command execution, pinning, buffer - read & write, mapping, and domain ownership transfers are left to - driver-specific ioctls. - </para> - <sect3> - <title>GEM Initialization</title> - <para> - Drivers that use GEM must set the DRIVER_GEM bit in the struct - <structname>drm_driver</structname> - <structfield>driver_features</structfield> field. The DRM core will - then automatically initialize the GEM core before calling the - <methodname>load</methodname> operation. Behind the scene, this will - create a DRM Memory Manager object which provides an address space - pool for object allocation. - </para> - <para> - In a KMS configuration, drivers need to allocate and initialize a - command ring buffer following core GEM initialization if required by - the hardware. UMA devices usually have what is called a "stolen" - memory region, which provides space for the initial framebuffer and - large, contiguous memory regions required by the device. This space is - typically not managed by GEM, and must be initialized separately into - its own DRM MM object. - </para> - </sect3> - <sect3> - <title>GEM Objects Creation</title> - <para> - GEM splits creation of GEM objects and allocation of the memory that - backs them in two distinct operations. - </para> - <para> - GEM objects are represented by an instance of struct - <structname>drm_gem_object</structname>. Drivers usually need to extend - GEM objects with private information and thus create a driver-specific - GEM object structure type that embeds an instance of struct - <structname>drm_gem_object</structname>. - </para> - <para> - To create a GEM object, a driver allocates memory for an instance of its - specific GEM object type and initializes the embedded struct - <structname>drm_gem_object</structname> with a call to - <function>drm_gem_object_init</function>. The function takes a pointer to - the DRM device, a pointer to the GEM object and the buffer object size - in bytes. - </para> - <para> - GEM uses shmem to allocate anonymous pageable memory. - <function>drm_gem_object_init</function> will create an shmfs file of - the requested size and store it into the struct - <structname>drm_gem_object</structname> <structfield>filp</structfield> - field. The memory is used as either main storage for the object when the - graphics hardware uses system memory directly or as a backing store - otherwise. - </para> - <para> - Drivers are responsible for the actual physical pages allocation by - calling <function>shmem_read_mapping_page_gfp</function> for each page. - Note that they can decide to allocate pages when initializing the GEM - object, or to delay allocation until the memory is needed (for instance - when a page fault occurs as a result of a userspace memory access or - when the driver needs to start a DMA transfer involving the memory). - </para> - <para> - Anonymous pageable memory allocation is not always desired, for instance - when the hardware requires physically contiguous system memory as is - often the case in embedded devices. Drivers can create GEM objects with - no shmfs backing (called private GEM objects) by initializing them with - a call to <function>drm_gem_private_object_init</function> instead of - <function>drm_gem_object_init</function>. Storage for private GEM - objects must be managed by drivers. - </para> - </sect3> - <sect3> - <title>GEM Objects Lifetime</title> - <para> - All GEM objects are reference-counted by the GEM core. References can be - acquired and release by <function>calling drm_gem_object_reference</function> - and <function>drm_gem_object_unreference</function> respectively. The - caller must hold the <structname>drm_device</structname> - <structfield>struct_mutex</structfield> lock when calling - <function>drm_gem_object_reference</function>. As a convenience, GEM - provides <function>drm_gem_object_unreference_unlocked</function> - functions that can be called without holding the lock. - </para> - <para> - When the last reference to a GEM object is released the GEM core calls - the <structname>drm_driver</structname> - <methodname>gem_free_object</methodname> operation. That operation is - mandatory for GEM-enabled drivers and must free the GEM object and all - associated resources. - </para> - <para> - <synopsis>void (*gem_free_object) (struct drm_gem_object *obj);</synopsis> - Drivers are responsible for freeing all GEM object resources. This includes - the resources created by the GEM core, which need to be released with - <function>drm_gem_object_release</function>. - </para> - </sect3> - <sect3> - <title>GEM Objects Naming</title> - <para> - Communication between userspace and the kernel refers to GEM objects - using local handles, global names or, more recently, file descriptors. - All of those are 32-bit integer values; the usual Linux kernel limits - apply to the file descriptors. - </para> - <para> - GEM handles are local to a DRM file. Applications get a handle to a GEM - object through a driver-specific ioctl, and can use that handle to refer - to the GEM object in other standard or driver-specific ioctls. Closing a - DRM file handle frees all its GEM handles and dereferences the - associated GEM objects. - </para> - <para> - To create a handle for a GEM object drivers call - <function>drm_gem_handle_create</function>. The function takes a pointer - to the DRM file and the GEM object and returns a locally unique handle. - When the handle is no longer needed drivers delete it with a call to - <function>drm_gem_handle_delete</function>. Finally the GEM object - associated with a handle can be retrieved by a call to - <function>drm_gem_object_lookup</function>. - </para> - <para> - Handles don't take ownership of GEM objects, they only take a reference - to the object that will be dropped when the handle is destroyed. To - avoid leaking GEM objects, drivers must make sure they drop the - reference(s) they own (such as the initial reference taken at object - creation time) as appropriate, without any special consideration for the - handle. For example, in the particular case of combined GEM object and - handle creation in the implementation of the - <methodname>dumb_create</methodname> operation, drivers must drop the - initial reference to the GEM object before returning the handle. - </para> - <para> - GEM names are similar in purpose to handles but are not local to DRM - files. They can be passed between processes to reference a GEM object - globally. Names can't be used directly to refer to objects in the DRM - API, applications must convert handles to names and names to handles - using the DRM_IOCTL_GEM_FLINK and DRM_IOCTL_GEM_OPEN ioctls - respectively. The conversion is handled by the DRM core without any - driver-specific support. - </para> - <para> - GEM also supports buffer sharing with dma-buf file descriptors through - PRIME. GEM-based drivers must use the provided helpers functions to - implement the exporting and importing correctly. See <xref linkend="drm-prime-support" />. - Since sharing file descriptors is inherently more secure than the - easily guessable and global GEM names it is the preferred buffer - sharing mechanism. Sharing buffers through GEM names is only supported - for legacy userspace. Furthermore PRIME also allows cross-device - buffer sharing since it is based on dma-bufs. - </para> - </sect3> - <sect3 id="drm-gem-objects-mapping"> - <title>GEM Objects Mapping</title> - <para> - Because mapping operations are fairly heavyweight GEM favours - read/write-like access to buffers, implemented through driver-specific - ioctls, over mapping buffers to userspace. However, when random access - to the buffer is needed (to perform software rendering for instance), - direct access to the object can be more efficient. - </para> - <para> - The mmap system call can't be used directly to map GEM objects, as they - don't have their own file handle. Two alternative methods currently - co-exist to map GEM objects to userspace. The first method uses a - driver-specific ioctl to perform the mapping operation, calling - <function>do_mmap</function> under the hood. This is often considered - dubious, seems to be discouraged for new GEM-enabled drivers, and will - thus not be described here. - </para> - <para> - The second method uses the mmap system call on the DRM file handle. - <synopsis>void *mmap(void *addr, size_t length, int prot, int flags, int fd, - off_t offset);</synopsis> - DRM identifies the GEM object to be mapped by a fake offset passed - through the mmap offset argument. Prior to being mapped, a GEM object - must thus be associated with a fake offset. To do so, drivers must call - <function>drm_gem_create_mmap_offset</function> on the object. - </para> - <para> - Once allocated, the fake offset value - must be passed to the application in a driver-specific way and can then - be used as the mmap offset argument. - </para> - <para> - The GEM core provides a helper method <function>drm_gem_mmap</function> - to handle object mapping. The method can be set directly as the mmap - file operation handler. It will look up the GEM object based on the - offset value and set the VMA operations to the - <structname>drm_driver</structname> <structfield>gem_vm_ops</structfield> - field. Note that <function>drm_gem_mmap</function> doesn't map memory to - userspace, but relies on the driver-provided fault handler to map pages - individually. - </para> - <para> - To use <function>drm_gem_mmap</function>, drivers must fill the struct - <structname>drm_driver</structname> <structfield>gem_vm_ops</structfield> - field with a pointer to VM operations. - </para> - <para> - <synopsis>struct vm_operations_struct *gem_vm_ops - - struct vm_operations_struct { - void (*open)(struct vm_area_struct * area); - void (*close)(struct vm_area_struct * area); - int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf); - };</synopsis> - </para> - <para> - The <methodname>open</methodname> and <methodname>close</methodname> - operations must update the GEM object reference count. Drivers can use - the <function>drm_gem_vm_open</function> and - <function>drm_gem_vm_close</function> helper functions directly as open - and close handlers. - </para> - <para> - The fault operation handler is responsible for mapping individual pages - to userspace when a page fault occurs. Depending on the memory - allocation scheme, drivers can allocate pages at fault time, or can - decide to allocate memory for the GEM object at the time the object is - created. - </para> - <para> - Drivers that want to map the GEM object upfront instead of handling page - faults can implement their own mmap file operation handler. - </para> - </sect3> - <sect3> - <title>Memory Coherency</title> - <para> - When mapped to the device or used in a command buffer, backing pages - for an object are flushed to memory and marked write combined so as to - be coherent with the GPU. Likewise, if the CPU accesses an object - after the GPU has finished rendering to the object, then the object - must be made coherent with the CPU's view of memory, usually involving - GPU cache flushing of various kinds. This core CPU<->GPU - coherency management is provided by a device-specific ioctl, which - evaluates an object's current domain and performs any necessary - flushing or synchronization to put the object into the desired - coherency domain (note that the object may be busy, i.e. an active - render target; in that case, setting the domain blocks the client and - waits for rendering to complete before performing any necessary - flushing operations). - </para> - </sect3> - <sect3> - <title>Command Execution</title> - <para> - Perhaps the most important GEM function for GPU devices is providing a - command execution interface to clients. Client programs construct - command buffers containing references to previously allocated memory - objects, and then submit them to GEM. At that point, GEM takes care to - bind all the objects into the GTT, execute the buffer, and provide - necessary synchronization between clients accessing the same buffers. - This often involves evicting some objects from the GTT and re-binding - others (a fairly expensive operation), and providing relocation - support which hides fixed GTT offsets from clients. Clients must take - care not to submit command buffers that reference more objects than - can fit in the GTT; otherwise, GEM will reject them and no rendering - will occur. Similarly, if several objects in the buffer require fence - registers to be allocated for correct rendering (e.g. 2D blits on - pre-965 chips), care must be taken not to require more fence registers - than are available to the client. Such resource management should be - abstracted from the client in libdrm. - </para> - </sect3> - </sect2> - <sect2> - <title>GEM Function Reference</title> -!Edrivers/gpu/drm/drm_gem.c -!Iinclude/drm/drm_gem.h - </sect2> - <sect2> - <title>VMA Offset Manager</title> -!Pdrivers/gpu/drm/drm_vma_manager.c vma offset manager -!Edrivers/gpu/drm/drm_vma_manager.c -!Iinclude/drm/drm_vma_manager.h - </sect2> - <sect2 id="drm-prime-support"> - <title>PRIME Buffer Sharing</title> - <para> - PRIME is the cross device buffer sharing framework in drm, originally - created for the OPTIMUS range of multi-gpu platforms. To userspace - PRIME buffers are dma-buf based file descriptors. - </para> - <sect3> - <title>Overview and Driver Interface</title> - <para> - Similar to GEM global names, PRIME file descriptors are - also used to share buffer objects across processes. They offer - additional security: as file descriptors must be explicitly sent over - UNIX domain sockets to be shared between applications, they can't be - guessed like the globally unique GEM names. - </para> - <para> - Drivers that support the PRIME - API must set the DRIVER_PRIME bit in the struct - <structname>drm_driver</structname> - <structfield>driver_features</structfield> field, and implement the - <methodname>prime_handle_to_fd</methodname> and - <methodname>prime_fd_to_handle</methodname> operations. - </para> - <para> - <synopsis>int (*prime_handle_to_fd)(struct drm_device *dev, - struct drm_file *file_priv, uint32_t handle, - uint32_t flags, int *prime_fd); -int (*prime_fd_to_handle)(struct drm_device *dev, - struct drm_file *file_priv, int prime_fd, - uint32_t *handle);</synopsis> - Those two operations convert a handle to a PRIME file descriptor and - vice versa. Drivers must use the kernel dma-buf buffer sharing framework - to manage the PRIME file descriptors. Similar to the mode setting - API PRIME is agnostic to the underlying buffer object manager, as - long as handles are 32bit unsigned integers. - </para> - <para> - While non-GEM drivers must implement the operations themselves, GEM - drivers must use the <function>drm_gem_prime_handle_to_fd</function> - and <function>drm_gem_prime_fd_to_handle</function> helper functions. - Those helpers rely on the driver - <methodname>gem_prime_export</methodname> and - <methodname>gem_prime_import</methodname> operations to create a dma-buf - instance from a GEM object (dma-buf exporter role) and to create a GEM - object from a dma-buf instance (dma-buf importer role). - </para> - <para> - <synopsis>struct dma_buf * (*gem_prime_export)(struct drm_device *dev, - struct drm_gem_object *obj, - int flags); -struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev, - struct dma_buf *dma_buf);</synopsis> - These two operations are mandatory for GEM drivers that support - PRIME. - </para> - </sect3> - <sect3> - <title>PRIME Helper Functions</title> -!Pdrivers/gpu/drm/drm_prime.c PRIME Helpers - </sect3> - </sect2> - <sect2> - <title>PRIME Function References</title> -!Edrivers/gpu/drm/drm_prime.c - </sect2> - <sect2> - <title>DRM MM Range Allocator</title> - <sect3> - <title>Overview</title> -!Pdrivers/gpu/drm/drm_mm.c Overview - </sect3> - <sect3> - <title>LRU Scan/Eviction Support</title> -!Pdrivers/gpu/drm/drm_mm.c lru scan roaster - </sect3> - </sect2> - <sect2> - <title>DRM MM Range Allocator Function References</title> -!Edrivers/gpu/drm/drm_mm.c -!Iinclude/drm/drm_mm.h - </sect2> - <sect2> - <title>CMA Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_gem_cma_helper.c cma helpers -!Edrivers/gpu/drm/drm_gem_cma_helper.c -!Iinclude/drm/drm_gem_cma_helper.h - </sect2> - </sect1> - - <!-- Internals: mode setting --> - - <sect1 id="drm-mode-setting"> - <title>Mode Setting</title> - <para> - Drivers must initialize the mode setting core by calling - <function>drm_mode_config_init</function> on the DRM device. The function - initializes the <structname>drm_device</structname> - <structfield>mode_config</structfield> field and never fails. Once done, - mode configuration must be setup by initializing the following fields. - </para> - <itemizedlist> - <listitem> - <synopsis>int min_width, min_height; -int max_width, max_height;</synopsis> - <para> - Minimum and maximum width and height of the frame buffers in pixel - units. - </para> - </listitem> - <listitem> - <synopsis>struct drm_mode_config_funcs *funcs;</synopsis> - <para>Mode setting functions.</para> - </listitem> - </itemizedlist> - <sect2> - <title>Display Modes Function Reference</title> -!Iinclude/drm/drm_modes.h -!Edrivers/gpu/drm/drm_modes.c - </sect2> - <sect2> - <title>Atomic Mode Setting Function Reference</title> -!Edrivers/gpu/drm/drm_atomic.c -!Idrivers/gpu/drm/drm_atomic.c - </sect2> - <sect2> - <title>Frame Buffer Abstraction</title> - <para> - Frame buffers are abstract memory objects that provide a source of - pixels to scanout to a CRTC. Applications explicitly request the - creation of frame buffers through the DRM_IOCTL_MODE_ADDFB(2) ioctls and - receive an opaque handle that can be passed to the KMS CRTC control, - plane configuration and page flip functions. - </para> - <para> - Frame buffers rely on the underneath memory manager for low-level memory - operations. When creating a frame buffer applications pass a memory - handle (or a list of memory handles for multi-planar formats) through - the <parameter>drm_mode_fb_cmd2</parameter> argument. For drivers using - GEM as their userspace buffer management interface this would be a GEM - handle. Drivers are however free to use their own backing storage object - handles, e.g. vmwgfx directly exposes special TTM handles to userspace - and so expects TTM handles in the create ioctl and not GEM handles. - </para> - <para> - The lifetime of a drm framebuffer is controlled with a reference count, - drivers can grab additional references with - <function>drm_framebuffer_reference</function>and drop them - again with <function>drm_framebuffer_unreference</function>. For - driver-private framebuffers for which the last reference is never - dropped (e.g. for the fbdev framebuffer when the struct - <structname>drm_framebuffer</structname> is embedded into the fbdev - helper struct) drivers can manually clean up a framebuffer at module - unload time with - <function>drm_framebuffer_unregister_private</function>. - </para> - </sect2> - <sect2> - <title>Dumb Buffer Objects</title> - <para> - The KMS API doesn't standardize backing storage object creation and - leaves it to driver-specific ioctls. Furthermore actually creating a - buffer object even for GEM-based drivers is done through a - driver-specific ioctl - GEM only has a common userspace interface for - sharing and destroying objects. While not an issue for full-fledged - graphics stacks that include device-specific userspace components (in - libdrm for instance), this limit makes DRM-based early boot graphics - unnecessarily complex. - </para> - <para> - Dumb objects partly alleviate the problem by providing a standard - API to create dumb buffers suitable for scanout, which can then be used - to create KMS frame buffers. - </para> - <para> - To support dumb objects drivers must implement the - <methodname>dumb_create</methodname>, - <methodname>dumb_destroy</methodname> and - <methodname>dumb_map_offset</methodname> operations. - </para> - <itemizedlist> - <listitem> - <synopsis>int (*dumb_create)(struct drm_file *file_priv, struct drm_device *dev, - struct drm_mode_create_dumb *args);</synopsis> - <para> - The <methodname>dumb_create</methodname> operation creates a driver - object (GEM or TTM handle) suitable for scanout based on the - width, height and depth from the struct - <structname>drm_mode_create_dumb</structname> argument. It fills the - argument's <structfield>handle</structfield>, - <structfield>pitch</structfield> and <structfield>size</structfield> - fields with a handle for the newly created object and its line - pitch and size in bytes. - </para> - </listitem> - <listitem> - <synopsis>int (*dumb_destroy)(struct drm_file *file_priv, struct drm_device *dev, - uint32_t handle);</synopsis> - <para> - The <methodname>dumb_destroy</methodname> operation destroys a dumb - object created by <methodname>dumb_create</methodname>. - </para> - </listitem> - <listitem> - <synopsis>int (*dumb_map_offset)(struct drm_file *file_priv, struct drm_device *dev, - uint32_t handle, uint64_t *offset);</synopsis> - <para> - The <methodname>dumb_map_offset</methodname> operation associates an - mmap fake offset with the object given by the handle and returns - it. Drivers must use the - <function>drm_gem_create_mmap_offset</function> function to - associate the fake offset as described in - <xref linkend="drm-gem-objects-mapping"/>. - </para> - </listitem> - </itemizedlist> - <para> - Note that dumb objects may not be used for gpu acceleration, as has been - attempted on some ARM embedded platforms. Such drivers really must have - a hardware-specific ioctl to allocate suitable buffer objects. - </para> - </sect2> - <sect2> - <title>Output Polling</title> - <synopsis>void (*output_poll_changed)(struct drm_device *dev);</synopsis> - <para> - This operation notifies the driver that the status of one or more - connectors has changed. Drivers that use the fb helper can just call the - <function>drm_fb_helper_hotplug_event</function> function to handle this - operation. - </para> - </sect2> - <sect2> - <title>Locking</title> - <para> - Beside some lookup structures with their own locking (which is hidden - behind the interface functions) most of the modeset state is protected - by the <code>dev-<mode_config.lock</code> mutex and additionally - per-crtc locks to allow cursor updates, pageflips and similar operations - to occur concurrently with background tasks like output detection. - Operations which cross domains like a full modeset always grab all - locks. Drivers there need to protect resources shared between crtcs with - additional locking. They also need to be careful to always grab the - relevant crtc locks if a modset functions touches crtc state, e.g. for - load detection (which does only grab the <code>mode_config.lock</code> - to allow concurrent screen updates on live crtcs). - </para> - </sect2> - </sect1> - - <!-- Internals: kms initialization and cleanup --> - - <sect1 id="drm-kms-init"> - <title>KMS Initialization and Cleanup</title> - <para> - A KMS device is abstracted and exposed as a set of planes, CRTCs, encoders - and connectors. KMS drivers must thus create and initialize all those - objects at load time after initializing mode setting. - </para> - <sect2> - <title>CRTCs (struct <structname>drm_crtc</structname>)</title> - <para> - A CRTC is an abstraction representing a part of the chip that contains a - pointer to a scanout buffer. Therefore, the number of CRTCs available - determines how many independent scanout buffers can be active at any - given time. The CRTC structure contains several fields to support this: - a pointer to some video memory (abstracted as a frame buffer object), a - display mode, and an (x, y) offset into the video memory to support - panning or configurations where one piece of video memory spans multiple - CRTCs. - </para> - <sect3> - <title>CRTC Initialization</title> - <para> - A KMS device must create and register at least one struct - <structname>drm_crtc</structname> instance. The instance is allocated - and zeroed by the driver, possibly as part of a larger structure, and - registered with a call to <function>drm_crtc_init</function> with a - pointer to CRTC functions. - </para> - </sect3> - </sect2> - <sect2> - <title>Planes (struct <structname>drm_plane</structname>)</title> - <para> - A plane represents an image source that can be blended with or overlayed - on top of a CRTC during the scanout process. Planes are associated with - a frame buffer to crop a portion of the image memory (source) and - optionally scale it to a destination size. The result is then blended - with or overlayed on top of a CRTC. - </para> - <para> - The DRM core recognizes three types of planes: - <itemizedlist> - <listitem> - DRM_PLANE_TYPE_PRIMARY represents a "main" plane for a CRTC. Primary - planes are the planes operated upon by CRTC modesetting and flipping - operations described in the page_flip hook in <structname>drm_crtc_funcs</structname>. - </listitem> - <listitem> - DRM_PLANE_TYPE_CURSOR represents a "cursor" plane for a CRTC. Cursor - planes are the planes operated upon by the DRM_IOCTL_MODE_CURSOR and - DRM_IOCTL_MODE_CURSOR2 ioctls. - </listitem> - <listitem> - DRM_PLANE_TYPE_OVERLAY represents all non-primary, non-cursor planes. - Some drivers refer to these types of planes as "sprites" internally. - </listitem> - </itemizedlist> - For compatibility with legacy userspace, only overlay planes are made - available to userspace by default. Userspace clients may set the - DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate that - they wish to receive a universal plane list containing all plane types. - </para> - <sect3> - <title>Plane Initialization</title> - <para> - To create a plane, a KMS drivers allocates and - zeroes an instances of struct <structname>drm_plane</structname> - (possibly as part of a larger structure) and registers it with a call - to <function>drm_universal_plane_init</function>. The function takes a bitmask - of the CRTCs that can be associated with the plane, a pointer to the - plane functions, a list of format supported formats, and the type of - plane (primary, cursor, or overlay) being initialized. - </para> - <para> - Cursor and overlay planes are optional. All drivers should provide - one primary plane per CRTC (although this requirement may change in - the future); drivers that do not wish to provide special handling for - primary planes may make use of the helper functions described in - <xref linkend="drm-kms-planehelpers"/> to create and register a - primary plane with standard capabilities. - </para> - </sect3> - </sect2> - <sect2> - <title>Encoders (struct <structname>drm_encoder</structname>)</title> - <para> - An encoder takes pixel data from a CRTC and converts it to a format - suitable for any attached connectors. On some devices, it may be - possible to have a CRTC send data to more than one encoder. In that - case, both encoders would receive data from the same scanout buffer, - resulting in a "cloned" display configuration across the connectors - attached to each encoder. - </para> - <sect3> - <title>Encoder Initialization</title> - <para> - As for CRTCs, a KMS driver must create, initialize and register at - least one struct <structname>drm_encoder</structname> instance. The - instance is allocated and zeroed by the driver, possibly as part of a - larger structure. - </para> - <para> - Drivers must initialize the struct <structname>drm_encoder</structname> - <structfield>possible_crtcs</structfield> and - <structfield>possible_clones</structfield> fields before registering the - encoder. Both fields are bitmasks of respectively the CRTCs that the - encoder can be connected to, and sibling encoders candidate for cloning. - </para> - <para> - After being initialized, the encoder must be registered with a call to - <function>drm_encoder_init</function>. The function takes a pointer to - the encoder functions and an encoder type. Supported types are - <itemizedlist> - <listitem> - DRM_MODE_ENCODER_DAC for VGA and analog on DVI-I/DVI-A - </listitem> - <listitem> - DRM_MODE_ENCODER_TMDS for DVI, HDMI and (embedded) DisplayPort - </listitem> - <listitem> - DRM_MODE_ENCODER_LVDS for display panels - </listitem> - <listitem> - DRM_MODE_ENCODER_TVDAC for TV output (Composite, S-Video, Component, - SCART) - </listitem> - <listitem> - DRM_MODE_ENCODER_VIRTUAL for virtual machine displays - </listitem> - </itemizedlist> - </para> - <para> - Encoders must be attached to a CRTC to be used. DRM drivers leave - encoders unattached at initialization time. Applications (or the fbdev - compatibility layer when implemented) are responsible for attaching the - encoders they want to use to a CRTC. - </para> - </sect3> - </sect2> - <sect2> - <title>Connectors (struct <structname>drm_connector</structname>)</title> - <para> - A connector is the final destination for pixel data on a device, and - usually connects directly to an external display device like a monitor - or laptop panel. A connector can only be attached to one encoder at a - time. The connector is also the structure where information about the - attached display is kept, so it contains fields for display data, EDID - data, DPMS & connection status, and information about modes - supported on the attached displays. - </para> - <sect3> - <title>Connector Initialization</title> - <para> - Finally a KMS driver must create, initialize, register and attach at - least one struct <structname>drm_connector</structname> instance. The - instance is created as other KMS objects and initialized by setting the - following fields. - </para> - <variablelist> - <varlistentry> - <term><structfield>interlace_allowed</structfield></term> - <listitem><para> - Whether the connector can handle interlaced modes. - </para></listitem> - </varlistentry> - <varlistentry> - <term><structfield>doublescan_allowed</structfield></term> - <listitem><para> - Whether the connector can handle doublescan. - </para></listitem> - </varlistentry> - <varlistentry> - <term><structfield>display_info - </structfield></term> - <listitem><para> - Display information is filled from EDID information when a display - is detected. For non hot-pluggable displays such as flat panels in - embedded systems, the driver should initialize the - <structfield>display_info</structfield>.<structfield>width_mm</structfield> - and - <structfield>display_info</structfield>.<structfield>height_mm</structfield> - fields with the physical size of the display. - </para></listitem> - </varlistentry> - <varlistentry> - <term id="drm-kms-connector-polled"><structfield>polled</structfield></term> - <listitem><para> - Connector polling mode, a combination of - <variablelist> - <varlistentry> - <term>DRM_CONNECTOR_POLL_HPD</term> - <listitem><para> - The connector generates hotplug events and doesn't need to be - periodically polled. The CONNECT and DISCONNECT flags must not - be set together with the HPD flag. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRM_CONNECTOR_POLL_CONNECT</term> - <listitem><para> - Periodically poll the connector for connection. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRM_CONNECTOR_POLL_DISCONNECT</term> - <listitem><para> - Periodically poll the connector for disconnection. - </para></listitem> - </varlistentry> - </variablelist> - Set to 0 for connectors that don't support connection status - discovery. - </para></listitem> - </varlistentry> - </variablelist> - <para> - The connector is then registered with a call to - <function>drm_connector_init</function> with a pointer to the connector - functions and a connector type, and exposed through sysfs with a call to - <function>drm_connector_register</function>. - </para> - <para> - Supported connector types are - <itemizedlist> - <listitem>DRM_MODE_CONNECTOR_VGA</listitem> - <listitem>DRM_MODE_CONNECTOR_DVII</listitem> - <listitem>DRM_MODE_CONNECTOR_DVID</listitem> - <listitem>DRM_MODE_CONNECTOR_DVIA</listitem> - <listitem>DRM_MODE_CONNECTOR_Composite</listitem> - <listitem>DRM_MODE_CONNECTOR_SVIDEO</listitem> - <listitem>DRM_MODE_CONNECTOR_LVDS</listitem> - <listitem>DRM_MODE_CONNECTOR_Component</listitem> - <listitem>DRM_MODE_CONNECTOR_9PinDIN</listitem> - <listitem>DRM_MODE_CONNECTOR_DisplayPort</listitem> - <listitem>DRM_MODE_CONNECTOR_HDMIA</listitem> - <listitem>DRM_MODE_CONNECTOR_HDMIB</listitem> - <listitem>DRM_MODE_CONNECTOR_TV</listitem> - <listitem>DRM_MODE_CONNECTOR_eDP</listitem> - <listitem>DRM_MODE_CONNECTOR_VIRTUAL</listitem> - </itemizedlist> - </para> - <para> - Connectors must be attached to an encoder to be used. For devices that - map connectors to encoders 1:1, the connector should be attached at - initialization time with a call to - <function>drm_mode_connector_attach_encoder</function>. The driver must - also set the <structname>drm_connector</structname> - <structfield>encoder</structfield> field to point to the attached - encoder. - </para> - <para> - Finally, drivers must initialize the connectors state change detection - with a call to <function>drm_kms_helper_poll_init</function>. If at - least one connector is pollable but can't generate hotplug interrupts - (indicated by the DRM_CONNECTOR_POLL_CONNECT and - DRM_CONNECTOR_POLL_DISCONNECT connector flags), a delayed work will - automatically be queued to periodically poll for changes. Connectors - that can generate hotplug interrupts must be marked with the - DRM_CONNECTOR_POLL_HPD flag instead, and their interrupt handler must - call <function>drm_helper_hpd_irq_event</function>. The function will - queue a delayed work to check the state of all connectors, but no - periodic polling will be done. - </para> - </sect3> - <sect3> - <title>Connector Operations</title> - <note><para> - Unless otherwise state, all operations are mandatory. - </para></note> - <sect4> - <title>DPMS</title> - <synopsis>void (*dpms)(struct drm_connector *connector, int mode);</synopsis> - <para> - The DPMS operation sets the power state of a connector. The mode - argument is one of - <itemizedlist> - <listitem><para>DRM_MODE_DPMS_ON</para></listitem> - <listitem><para>DRM_MODE_DPMS_STANDBY</para></listitem> - <listitem><para>DRM_MODE_DPMS_SUSPEND</para></listitem> - <listitem><para>DRM_MODE_DPMS_OFF</para></listitem> - </itemizedlist> - </para> - <para> - In all but DPMS_ON mode the encoder to which the connector is attached - should put the display in low-power mode by driving its signals - appropriately. If more than one connector is attached to the encoder - care should be taken not to change the power state of other displays as - a side effect. Low-power mode should be propagated to the encoders and - CRTCs when all related connectors are put in low-power mode. - </para> - </sect4> - <sect4> - <title>Modes</title> - <synopsis>int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, - uint32_t max_height);</synopsis> - <para> - Fill the mode list with all supported modes for the connector. If the - <parameter>max_width</parameter> and <parameter>max_height</parameter> - arguments are non-zero, the implementation must ignore all modes wider - than <parameter>max_width</parameter> or higher than - <parameter>max_height</parameter>. - </para> - <para> - The connector must also fill in this operation its - <structfield>display_info</structfield> - <structfield>width_mm</structfield> and - <structfield>height_mm</structfield> fields with the connected display - physical size in millimeters. The fields should be set to 0 if the value - isn't known or is not applicable (for instance for projector devices). - </para> - </sect4> - <sect4> - <title>Connection Status</title> - <para> - The connection status is updated through polling or hotplug events when - supported (see <xref linkend="drm-kms-connector-polled"/>). The status - value is reported to userspace through ioctls and must not be used - inside the driver, as it only gets initialized by a call to - <function>drm_mode_getconnector</function> from userspace. - </para> - <synopsis>enum drm_connector_status (*detect)(struct drm_connector *connector, - bool force);</synopsis> - <para> - Check to see if anything is attached to the connector. The - <parameter>force</parameter> parameter is set to false whilst polling or - to true when checking the connector due to user request. - <parameter>force</parameter> can be used by the driver to avoid - expensive, destructive operations during automated probing. - </para> - <para> - Return connector_status_connected if something is connected to the - connector, connector_status_disconnected if nothing is connected and - connector_status_unknown if the connection state isn't known. - </para> - <para> - Drivers should only return connector_status_connected if the connection - status has really been probed as connected. Connectors that can't detect - the connection status, or failed connection status probes, should return - connector_status_unknown. - </para> - </sect4> - </sect3> - </sect2> - <sect2> - <title>Cleanup</title> - <para> - The DRM core manages its objects' lifetime. When an object is not needed - anymore the core calls its destroy function, which must clean up and - free every resource allocated for the object. Every - <function>drm_*_init</function> call must be matched with a - corresponding <function>drm_*_cleanup</function> call to cleanup CRTCs - (<function>drm_crtc_cleanup</function>), planes - (<function>drm_plane_cleanup</function>), encoders - (<function>drm_encoder_cleanup</function>) and connectors - (<function>drm_connector_cleanup</function>). Furthermore, connectors - that have been added to sysfs must be removed by a call to - <function>drm_connector_unregister</function> before calling - <function>drm_connector_cleanup</function>. - </para> - <para> - Connectors state change detection must be cleanup up with a call to - <function>drm_kms_helper_poll_fini</function>. - </para> - </sect2> - <sect2> - <title>Output discovery and initialization example</title> - <programlisting><![CDATA[ -void intel_crt_init(struct drm_device *dev) -{ - struct drm_connector *connector; - struct intel_output *intel_output; - - intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); - if (!intel_output) - return; - - connector = &intel_output->base; - drm_connector_init(dev, &intel_output->base, - &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); - - drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs, - DRM_MODE_ENCODER_DAC); - - drm_mode_connector_attach_encoder(&intel_output->base, - &intel_output->enc); - - /* Set up the DDC bus. */ - intel_output->ddc_bus = intel_i2c_create(dev, GPIOA, "CRTDDC_A"); - if (!intel_output->ddc_bus) { - dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " - "failed.\n"); - return; - } - - intel_output->type = INTEL_OUTPUT_ANALOG; - connector->interlace_allowed = 0; - connector->doublescan_allowed = 0; - - drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs); - drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); - - drm_connector_register(connector); -}]]></programlisting> - <para> - In the example above (taken from the i915 driver), a CRTC, connector and - encoder combination is created. A device-specific i2c bus is also - created for fetching EDID data and performing monitor detection. Once - the process is complete, the new connector is registered with sysfs to - make its properties available to applications. - </para> - </sect2> - <sect2> - <title>KMS API Functions</title> -!Edrivers/gpu/drm/drm_crtc.c - </sect2> - <sect2> - <title>KMS Data Structures</title> -!Iinclude/drm/drm_crtc.h - </sect2> - <sect2> - <title>KMS Locking</title> -!Pdrivers/gpu/drm/drm_modeset_lock.c kms locking -!Iinclude/drm/drm_modeset_lock.h -!Edrivers/gpu/drm/drm_modeset_lock.c - </sect2> - </sect1> - - <!-- Internals: kms helper functions --> - - <sect1> - <title>Mode Setting Helper Functions</title> - <para> - The plane, CRTC, encoder and connector functions provided by the drivers - implement the DRM API. They're called by the DRM core and ioctl handlers - to handle device state changes and configuration request. As implementing - those functions often requires logic not specific to drivers, mid-layer - helper functions are available to avoid duplicating boilerplate code. - </para> - <para> - The DRM core contains one mid-layer implementation. The mid-layer provides - implementations of several plane, CRTC, encoder and connector functions - (called from the top of the mid-layer) that pre-process requests and call - lower-level functions provided by the driver (at the bottom of the - mid-layer). For instance, the - <function>drm_crtc_helper_set_config</function> function can be used to - fill the struct <structname>drm_crtc_funcs</structname> - <structfield>set_config</structfield> field. When called, it will split - the <methodname>set_config</methodname> operation in smaller, simpler - operations and call the driver to handle them. - </para> - <para> - To use the mid-layer, drivers call <function>drm_crtc_helper_add</function>, - <function>drm_encoder_helper_add</function> and - <function>drm_connector_helper_add</function> functions to install their - mid-layer bottom operations handlers, and fill the - <structname>drm_crtc_funcs</structname>, - <structname>drm_encoder_funcs</structname> and - <structname>drm_connector_funcs</structname> structures with pointers to - the mid-layer top API functions. Installing the mid-layer bottom operation - handlers is best done right after registering the corresponding KMS object. - </para> - <para> - The mid-layer is not split between CRTC, encoder and connector operations. - To use it, a driver must provide bottom functions for all of the three KMS - entities. - </para> - <sect2> - <title>Atomic Modeset Helper Functions Reference</title> - <sect3> - <title>Overview</title> -!Pdrivers/gpu/drm/drm_atomic_helper.c overview - </sect3> - <sect3> - <title>Implementing Asynchronous Atomic Commit</title> -!Pdrivers/gpu/drm/drm_atomic_helper.c implementing async commit - </sect3> - <sect3> - <title>Atomic State Reset and Initialization</title> -!Pdrivers/gpu/drm/drm_atomic_helper.c atomic state reset and initialization - </sect3> -!Iinclude/drm/drm_atomic_helper.h -!Edrivers/gpu/drm/drm_atomic_helper.c - </sect2> - <sect2> - <title>Modeset Helper Reference for Common Vtables</title> -!Iinclude/drm/drm_modeset_helper_vtables.h -!Pinclude/drm/drm_modeset_helper_vtables.h overview - </sect2> - <sect2> - <title>Legacy CRTC/Modeset Helper Functions Reference</title> -!Edrivers/gpu/drm/drm_crtc_helper.c -!Pdrivers/gpu/drm/drm_crtc_helper.c overview - </sect2> - <sect2> - <title>Output Probing Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_probe_helper.c output probing helper overview -!Edrivers/gpu/drm/drm_probe_helper.c - </sect2> - <sect2> - <title>fbdev Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_fb_helper.c fbdev helpers -!Edrivers/gpu/drm/drm_fb_helper.c -!Iinclude/drm/drm_fb_helper.h - </sect2> - <sect2> - <title>Framebuffer CMA Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_fb_cma_helper.c framebuffer cma helper functions -!Edrivers/gpu/drm/drm_fb_cma_helper.c - </sect2> - <sect2> - <title>Display Port Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_dp_helper.c dp helpers -!Iinclude/drm/drm_dp_helper.h -!Edrivers/gpu/drm/drm_dp_helper.c - </sect2> - <sect2> - <title>Display Port Dual Mode Adaptor Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_dp_dual_mode_helper.c dp dual mode helpers -!Iinclude/drm/drm_dp_dual_mode_helper.h -!Edrivers/gpu/drm/drm_dp_dual_mode_helper.c - </sect2> - <sect2> - <title>Display Port MST Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_dp_mst_topology.c dp mst helper -!Iinclude/drm/drm_dp_mst_helper.h -!Edrivers/gpu/drm/drm_dp_mst_topology.c - </sect2> - <sect2> - <title>MIPI DSI Helper Functions Reference</title> -!Pdrivers/gpu/drm/drm_mipi_dsi.c dsi helpers -!Iinclude/drm/drm_mipi_dsi.h -!Edrivers/gpu/drm/drm_mipi_dsi.c - </sect2> - <sect2> - <title>EDID Helper Functions Reference</title> -!Edrivers/gpu/drm/drm_edid.c - </sect2> - <sect2> - <title>Rectangle Utilities Reference</title> -!Pinclude/drm/drm_rect.h rect utils -!Iinclude/drm/drm_rect.h -!Edrivers/gpu/drm/drm_rect.c - </sect2> - <sect2> - <title>Flip-work Helper Reference</title> -!Pinclude/drm/drm_flip_work.h flip utils -!Iinclude/drm/drm_flip_work.h -!Edrivers/gpu/drm/drm_flip_work.c - </sect2> - <sect2> - <title>HDMI Infoframes Helper Reference</title> - <para> - Strictly speaking this is not a DRM helper library but generally useable - by any driver interfacing with HDMI outputs like v4l or alsa drivers. - But it nicely fits into the overall topic of mode setting helper - libraries and hence is also included here. - </para> -!Iinclude/linux/hdmi.h -!Edrivers/video/hdmi.c - </sect2> - <sect2> - <title id="drm-kms-planehelpers">Plane Helper Reference</title> -!Edrivers/gpu/drm/drm_plane_helper.c -!Pdrivers/gpu/drm/drm_plane_helper.c overview - </sect2> - <sect2> - <title>Tile group</title> -!Pdrivers/gpu/drm/drm_crtc.c Tile group - </sect2> - <sect2> - <title>Bridges</title> - <sect3> - <title>Overview</title> -!Pdrivers/gpu/drm/drm_bridge.c overview - </sect3> - <sect3> - <title>Default bridge callback sequence</title> -!Pdrivers/gpu/drm/drm_bridge.c bridge callbacks - </sect3> -!Edrivers/gpu/drm/drm_bridge.c - </sect2> - <sect2> - <title>Panel Helper Reference</title> -!Iinclude/drm/drm_panel.h -!Edrivers/gpu/drm/drm_panel.c -!Pdrivers/gpu/drm/drm_panel.c drm panel - </sect2> - </sect1> - - <!-- Internals: kms properties --> - - <sect1 id="drm-kms-properties"> - <title>KMS Properties</title> - <para> - Drivers may need to expose additional parameters to applications than - those described in the previous sections. KMS supports attaching - properties to CRTCs, connectors and planes and offers a userspace API to - list, get and set the property values. - </para> - <para> - Properties are identified by a name that uniquely defines the property - purpose, and store an associated value. For all property types except blob - properties the value is a 64-bit unsigned integer. - </para> - <para> - KMS differentiates between properties and property instances. Drivers - first create properties and then create and associate individual instances - of those properties to objects. A property can be instantiated multiple - times and associated with different objects. Values are stored in property - instances, and all other property information are stored in the property - and shared between all instances of the property. - </para> - <para> - Every property is created with a type that influences how the KMS core - handles the property. Supported property types are - <variablelist> - <varlistentry> - <term>DRM_MODE_PROP_RANGE</term> - <listitem><para>Range properties report their minimum and maximum - admissible values. The KMS core verifies that values set by - application fit in that range.</para></listitem> - </varlistentry> - <varlistentry> - <term>DRM_MODE_PROP_ENUM</term> - <listitem><para>Enumerated properties take a numerical value that - ranges from 0 to the number of enumerated values defined by the - property minus one, and associate a free-formed string name to each - value. Applications can retrieve the list of defined value-name pairs - and use the numerical value to get and set property instance values. - </para></listitem> - </varlistentry> - <varlistentry> - <term>DRM_MODE_PROP_BITMASK</term> - <listitem><para>Bitmask properties are enumeration properties that - additionally restrict all enumerated values to the 0..63 range. - Bitmask property instance values combine one or more of the - enumerated bits defined by the property.</para></listitem> - </varlistentry> - <varlistentry> - <term>DRM_MODE_PROP_BLOB</term> - <listitem><para>Blob properties store a binary blob without any format - restriction. The binary blobs are created as KMS standalone objects, - and blob property instance values store the ID of their associated - blob object.</para> - <para>Blob properties are only used for the connector EDID property - and cannot be created by drivers.</para></listitem> - </varlistentry> - </variablelist> - </para> - <para> - To create a property drivers call one of the following functions depending - on the property type. All property creation functions take property flags - and name, as well as type-specific arguments. - <itemizedlist> - <listitem> - <synopsis>struct drm_property *drm_property_create_range(struct drm_device *dev, int flags, - const char *name, - uint64_t min, uint64_t max);</synopsis> - <para>Create a range property with the given minimum and maximum - values.</para> - </listitem> - <listitem> - <synopsis>struct drm_property *drm_property_create_enum(struct drm_device *dev, int flags, - const char *name, - const struct drm_prop_enum_list *props, - int num_values);</synopsis> - <para>Create an enumerated property. The <parameter>props</parameter> - argument points to an array of <parameter>num_values</parameter> - value-name pairs.</para> - </listitem> - <listitem> - <synopsis>struct drm_property *drm_property_create_bitmask(struct drm_device *dev, - int flags, const char *name, - const struct drm_prop_enum_list *props, - int num_values);</synopsis> - <para>Create a bitmask property. The <parameter>props</parameter> - argument points to an array of <parameter>num_values</parameter> - value-name pairs.</para> - </listitem> - </itemizedlist> - </para> - <para> - Properties can additionally be created as immutable, in which case they - will be read-only for applications but can be modified by the driver. To - create an immutable property drivers must set the DRM_MODE_PROP_IMMUTABLE - flag at property creation time. - </para> - <para> - When no array of value-name pairs is readily available at property - creation time for enumerated or range properties, drivers can create - the property using the <function>drm_property_create</function> function - and manually add enumeration value-name pairs by calling the - <function>drm_property_add_enum</function> function. Care must be taken to - properly specify the property type through the <parameter>flags</parameter> - argument. - </para> - <para> - After creating properties drivers can attach property instances to CRTC, - connector and plane objects by calling the - <function>drm_object_attach_property</function>. The function takes a - pointer to the target object, a pointer to the previously created property - and an initial instance value. - </para> - <sect2> - <title>Existing KMS Properties</title> - <para> - The following table gives description of drm properties exposed by various - modules/drivers. - </para> - <table border="1" cellpadding="0" cellspacing="0"> - <tbody> - <tr style="font-weight: bold;"> - <td valign="top" >Owner Module/Drivers</td> - <td valign="top" >Group</td> - <td valign="top" >Property Name</td> - <td valign="top" >Type</td> - <td valign="top" >Property Values</td> - <td valign="top" >Object attached</td> - <td valign="top" >Description/Restrictions</td> - </tr> - <tr> - <td rowspan="42" valign="top" >DRM</td> - <td rowspan="2" valign="top" >Generic</td> - <td valign="top" >“rotation”</td> - <td valign="top" >BITMASK</td> - <td valign="top" >{ 0, "rotate-0" }, - { 1, "rotate-90" }, - { 2, "rotate-180" }, - { 3, "rotate-270" }, - { 4, "reflect-x" }, - { 5, "reflect-y" }</td> - <td valign="top" >CRTC, Plane</td> - <td valign="top" >rotate-(degrees) rotates the image by the specified amount in degrees - in counter clockwise direction. reflect-x and reflect-y reflects the - image along the specified axis prior to rotation</td> - </tr> - <tr> - <td valign="top" >“scaling mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "None", "Full", "Center", "Full aspect" }</td> - <td valign="top" >Connector</td> - <td valign="top" >Supported by: amdgpu, gma500, i915, nouveau and radeon.</td> - </tr> - <tr> - <td rowspan="5" valign="top" >Connector</td> - <td valign="top" >“EDID”</td> - <td valign="top" >BLOB | IMMUTABLE</td> - <td valign="top" >0</td> - <td valign="top" >Connector</td> - <td valign="top" >Contains id of edid blob ptr object.</td> - </tr> - <tr> - <td valign="top" >“DPMS”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ “On”, “Standby”, “Suspend”, “Off” }</td> - <td valign="top" >Connector</td> - <td valign="top" >Contains DPMS operation mode value.</td> - </tr> - <tr> - <td valign="top" >“PATH”</td> - <td valign="top" >BLOB | IMMUTABLE</td> - <td valign="top" >0</td> - <td valign="top" >Connector</td> - <td valign="top" >Contains topology path to a connector.</td> - </tr> - <tr> - <td valign="top" >“TILE”</td> - <td valign="top" >BLOB | IMMUTABLE</td> - <td valign="top" >0</td> - <td valign="top" >Connector</td> - <td valign="top" >Contains tiling information for a connector.</td> - </tr> - <tr> - <td valign="top" >“CRTC_ID”</td> - <td valign="top" >OBJECT</td> - <td valign="top" >DRM_MODE_OBJECT_CRTC</td> - <td valign="top" >Connector</td> - <td valign="top" >CRTC that connector is attached to (atomic)</td> - </tr> - <tr> - <td rowspan="11" valign="top" >Plane</td> - <td valign="top" >“type”</td> - <td valign="top" >ENUM | IMMUTABLE</td> - <td valign="top" >{ "Overlay", "Primary", "Cursor" }</td> - <td valign="top" >Plane</td> - <td valign="top" >Plane type</td> - </tr> - <tr> - <td valign="top" >“SRC_X”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout source x coordinate in 16.16 fixed point (atomic)</td> - </tr> - <tr> - <td valign="top" >“SRC_Y”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout source y coordinate in 16.16 fixed point (atomic)</td> - </tr> - <tr> - <td valign="top" >“SRC_W”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout source width in 16.16 fixed point (atomic)</td> - </tr> - <tr> - <td valign="top" >“SRC_H”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout source height in 16.16 fixed point (atomic)</td> - </tr> - <tr> - <td valign="top" >“CRTC_X”</td> - <td valign="top" >SIGNED_RANGE</td> - <td valign="top" >Min=INT_MIN, Max=INT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout CRTC (destination) x coordinate (atomic)</td> - </tr> - <tr> - <td valign="top" >“CRTC_Y”</td> - <td valign="top" >SIGNED_RANGE</td> - <td valign="top" >Min=INT_MIN, Max=INT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout CRTC (destination) y coordinate (atomic)</td> - </tr> - <tr> - <td valign="top" >“CRTC_W”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout CRTC (destination) width (atomic)</td> - </tr> - <tr> - <td valign="top" >“CRTC_H”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout CRTC (destination) height (atomic)</td> - </tr> - <tr> - <td valign="top" >“FB_ID”</td> - <td valign="top" >OBJECT</td> - <td valign="top" >DRM_MODE_OBJECT_FB</td> - <td valign="top" >Plane</td> - <td valign="top" >Scanout framebuffer (atomic)</td> - </tr> - <tr> - <td valign="top" >“CRTC_ID”</td> - <td valign="top" >OBJECT</td> - <td valign="top" >DRM_MODE_OBJECT_CRTC</td> - <td valign="top" >Plane</td> - <td valign="top" >CRTC that plane is attached to (atomic)</td> - </tr> - <tr> - <td rowspan="2" valign="top" >DVI-I</td> - <td valign="top" >“subconnector”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ “Unknown”, “DVI-D”, “DVI-A” }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“select subconnector”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ “Automatic”, “DVI-D”, “DVI-A” }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="13" valign="top" >TV</td> - <td valign="top" >“subconnector”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "Unknown", "Composite", "SVIDEO", "Component", "SCART" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“select subconnector”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "Automatic", "Composite", "SVIDEO", "Component", "SCART" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc.</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“left margin”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“right margin”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“top margin”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“bottom margin”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“brightness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“contrast”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker reduction”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“overscan”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“saturation”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hue”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="2" valign="top" >Virtual GPU</td> - <td valign="top" >“suggested X”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffffff</td> - <td valign="top" >Connector</td> - <td valign="top" >property to suggest an X offset for a connector</td> - </tr> - <tr> - <td valign="top" >“suggested Y”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffffff</td> - <td valign="top" >Connector</td> - <td valign="top" >property to suggest an Y offset for a connector</td> - </tr> - <tr> - <td rowspan="7" valign="top" >Optional</td> - <td valign="top" >"aspect ratio"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "None", "4:3", "16:9" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TDB</td> - </tr> - <tr> - <td valign="top" >“dirty”</td> - <td valign="top" >ENUM | IMMUTABLE</td> - <td valign="top" >{ "Off", "On", "Annotate" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“DEGAMMA_LUT”</td> - <td valign="top" >BLOB</td> - <td valign="top" >0</td> - <td valign="top" >CRTC</td> - <td valign="top" >DRM property to set the degamma lookup table - (LUT) mapping pixel data from the framebuffer before it is - given to the transformation matrix. The data is an interpreted - as an array of struct drm_color_lut elements. Hardware might - choose not to use the full precision of the LUT elements nor - use all the elements of the LUT (for example the hardware - might choose to interpolate between LUT[0] and LUT[4]). </td> - </tr> - <tr> - <td valign="top" >“DEGAMMA_LUT_SIZE”</td> - <td valign="top" >RANGE | IMMUTABLE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >CRTC</td> - <td valign="top" >DRM property to gives the size of the lookup - table to be set on the DEGAMMA_LUT property (the size depends - on the underlying hardware).</td> - </tr> - <tr> - <td valign="top" >“CTM”</td> - <td valign="top" >BLOB</td> - <td valign="top" >0</td> - <td valign="top" >CRTC</td> - <td valign="top" >DRM property to set the current - transformation matrix (CTM) apply to pixel data after the - lookup through the degamma LUT and before the lookup through - the gamma LUT. The data is an interpreted as a struct - drm_color_ctm.</td> - </tr> - <tr> - <td valign="top" >“GAMMA_LUT”</td> - <td valign="top" >BLOB</td> - <td valign="top" >0</td> - <td valign="top" >CRTC</td> - <td valign="top" >DRM property to set the gamma lookup table - (LUT) mapping pixel data after to the transformation matrix to - data sent to the connector. The data is an interpreted as an - array of struct drm_color_lut elements. Hardware might choose - not to use the full precision of the LUT elements nor use all - the elements of the LUT (for example the hardware might choose - to interpolate between LUT[0] and LUT[4]).</td> - </tr> - <tr> - <td valign="top" >“GAMMA_LUT_SIZE”</td> - <td valign="top" >RANGE | IMMUTABLE</td> - <td valign="top" >Min=0, Max=UINT_MAX</td> - <td valign="top" >CRTC</td> - <td valign="top" >DRM property to gives the size of the lookup - table to be set on the GAMMA_LUT property (the size depends on - the underlying hardware).</td> - </tr> - <tr> - <td rowspan="20" valign="top" >i915</td> - <td rowspan="2" valign="top" >Generic</td> - <td valign="top" >"Broadcast RGB"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "Automatic", "Full", "Limited 16:235" }</td> - <td valign="top" >Connector</td> - <td valign="top" >When this property is set to Limited 16:235 - and CTM is set, the hardware will be programmed with the - result of the multiplication of CTM by the limited range - matrix to ensure the pixels normaly in the range 0..1.0 are - remapped to the range 16/255..235/255.</td> - </tr> - <tr> - <td valign="top" >“audio”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "force-dvi", "off", "auto", "on" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="17" valign="top" >SDVO-TV</td> - <td valign="top" >“mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc.</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"left_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"right_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"top_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"bottom_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hpos”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“vpos”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“contrast”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“saturation”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hue”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“sharpness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter_adaptive”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter_2d”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“tv_chroma_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“tv_luma_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“dot_crawl”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >SDVO-TV/LVDS</td> - <td valign="top" >“brightness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="2" valign="top" >CDV gma-500</td> - <td rowspan="2" valign="top" >Generic</td> - <td valign="top" >"Broadcast RGB"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ “Full”, “Limited 16:235” }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"Broadcast RGB"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ “off”, “auto”, “on” }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="19" valign="top" >Poulsbo</td> - <td rowspan="1" valign="top" >Generic</td> - <td valign="top" >“backlight”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=100</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="17" valign="top" >SDVO-TV</td> - <td valign="top" >“mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B" } etc.</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"left_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"right_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"top_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"bottom_margin"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hpos”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“vpos”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“contrast”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“saturation”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hue”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“sharpness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter_adaptive”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“flicker_filter_2d”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“tv_chroma_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“tv_luma_filter”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“dot_crawl”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >SDVO-TV/LVDS</td> - <td valign="top" >“brightness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max= SDVO dependent</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="11" valign="top" >armada</td> - <td rowspan="2" valign="top" >CRTC</td> - <td valign="top" >"CSC_YUV"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "Auto" , "CCIR601", "CCIR709" }</td> - <td valign="top" >CRTC</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"CSC_RGB"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "Auto", "Computer system", "Studio" }</td> - <td valign="top" >CRTC</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="9" valign="top" >Overlay</td> - <td valign="top" >"colorkey"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey_min"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey_max"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey_val"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey_alpha"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0xffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey_mode"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "disabled", "Y component", "U component" - , "V component", "RGB", “R component", "G component", "B component" }</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"brightness"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=256 + 255</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"contrast"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0x7fff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"saturation"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0x7fff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="2" valign="top" >exynos</td> - <td valign="top" >CRTC</td> - <td valign="top" >“mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "normal", "blank" }</td> - <td valign="top" >CRTC</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >Overlay</td> - <td valign="top" >“zpos”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=MAX_PLANE-1</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="2" valign="top" >i2c/ch7006_drv</td> - <td valign="top" >Generic</td> - <td valign="top" >“scale”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=2</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="1" valign="top" >TV</td> - <td valign="top" >“mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "PAL", "PAL-M","PAL-N"}, ”PAL-Nc" - , "PAL-60", "NTSC-M", "NTSC-J" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="15" valign="top" >nouveau</td> - <td rowspan="6" valign="top" >NV10 Overlay</td> - <td valign="top" >"colorkey"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0x01ffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“contrast”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=8192-1</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“brightness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1024</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“hue”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=359</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“saturation”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=8192-1</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“iturbt_709”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="2" valign="top" >Nv04 Overlay</td> - <td valign="top" >“colorkey”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0x01ffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“brightness”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1024</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="7" valign="top" >Display</td> - <td valign="top" >“dithering mode”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "auto", "off", "on" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“dithering depth”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "auto", "off", "on", "static 2x2", "dynamic 2x2", "temporal" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“underscan”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "auto", "6 bpc", "8 bpc" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“underscan hborder”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=128</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“underscan vborder”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=128</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“vibrant hue”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=180</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >“color vibrance”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=200</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >omap</td> - <td valign="top" >Generic</td> - <td valign="top" >“zorder”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=3</td> - <td valign="top" >CRTC, Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >qxl</td> - <td valign="top" >Generic</td> - <td valign="top" >“hotplug_mode_update"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="9" valign="top" >radeon</td> - <td valign="top" >DVI-I</td> - <td valign="top" >“coherent”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >DAC enable load detect</td> - <td valign="top" >“load detection”</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=1</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >TV Standard</td> - <td valign="top" >"tv standard"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "ntsc", "pal", "pal-m", "pal-60", "ntsc-j" - , "scart-pal", "pal-cn", "secam" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >legacy TMDS PLL detect</td> - <td valign="top" >"tmds_pll"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "driver", "bios" }</td> - <td valign="top" >-</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="3" valign="top" >Underscan</td> - <td valign="top" >"underscan"</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "off", "on", "auto" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"underscan hborder"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=128</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"underscan vborder"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=128</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >Audio</td> - <td valign="top" >“audio”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "off", "on", "auto" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >FMT Dithering</td> - <td valign="top" >“dither”</td> - <td valign="top" >ENUM</td> - <td valign="top" >{ "off", "on" }</td> - <td valign="top" >Connector</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td rowspan="3" valign="top" >rcar-du</td> - <td rowspan="3" valign="top" >Generic</td> - <td valign="top" >"alpha"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=255</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"colorkey"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=0, Max=0x01ffffff</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - <tr> - <td valign="top" >"zpos"</td> - <td valign="top" >RANGE</td> - <td valign="top" >Min=1, Max=7</td> - <td valign="top" >Plane</td> - <td valign="top" >TBD</td> - </tr> - </tbody> - </table> - </sect2> - </sect1> - - <!-- Internals: vertical blanking --> - - <sect1 id="drm-vertical-blank"> - <title>Vertical Blanking</title> - <para> - Vertical blanking plays a major role in graphics rendering. To achieve - tear-free display, users must synchronize page flips and/or rendering to - vertical blanking. The DRM API offers ioctls to perform page flips - synchronized to vertical blanking and wait for vertical blanking. - </para> - <para> - The DRM core handles most of the vertical blanking management logic, which - involves filtering out spurious interrupts, keeping race-free blanking - counters, coping with counter wrap-around and resets and keeping use - counts. It relies on the driver to generate vertical blanking interrupts - and optionally provide a hardware vertical blanking counter. Drivers must - implement the following operations. - </para> - <itemizedlist> - <listitem> - <synopsis>int (*enable_vblank) (struct drm_device *dev, int crtc); -void (*disable_vblank) (struct drm_device *dev, int crtc);</synopsis> - <para> - Enable or disable vertical blanking interrupts for the given CRTC. - </para> - </listitem> - <listitem> - <synopsis>u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);</synopsis> - <para> - Retrieve the value of the vertical blanking counter for the given - CRTC. If the hardware maintains a vertical blanking counter its value - should be returned. Otherwise drivers can use the - <function>drm_vblank_count</function> helper function to handle this - operation. - </para> - </listitem> - </itemizedlist> - <para> - Drivers must initialize the vertical blanking handling core with a call to - <function>drm_vblank_init</function> in their - <methodname>load</methodname> operation. The function will set the struct - <structname>drm_device</structname> - <structfield>vblank_disable_allowed</structfield> field to 0. This will - keep vertical blanking interrupts enabled permanently until the first mode - set operation, where <structfield>vblank_disable_allowed</structfield> is - set to 1. The reason behind this is not clear. Drivers can set the field - to 1 after <function>calling drm_vblank_init</function> to make vertical - blanking interrupts dynamically managed from the beginning. - </para> - <para> - Vertical blanking interrupts can be enabled by the DRM core or by drivers - themselves (for instance to handle page flipping operations). The DRM core - maintains a vertical blanking use count to ensure that the interrupts are - not disabled while a user still needs them. To increment the use count, - drivers call <function>drm_vblank_get</function>. Upon return vertical - blanking interrupts are guaranteed to be enabled. - </para> - <para> - To decrement the use count drivers call - <function>drm_vblank_put</function>. Only when the use count drops to zero - will the DRM core disable the vertical blanking interrupts after a delay - by scheduling a timer. The delay is accessible through the vblankoffdelay - module parameter or the <varname>drm_vblank_offdelay</varname> global - variable and expressed in milliseconds. Its default value is 5000 ms. - Zero means never disable, and a negative value means disable immediately. - Drivers may override the behaviour by setting the - <structname>drm_device</structname> - <structfield>vblank_disable_immediate</structfield> flag, which when set - causes vblank interrupts to be disabled immediately regardless of the - drm_vblank_offdelay value. The flag should only be set if there's a - properly working hardware vblank counter present. - </para> - <para> - When a vertical blanking interrupt occurs drivers only need to call the - <function>drm_handle_vblank</function> function to account for the - interrupt. - </para> - <para> - Resources allocated by <function>drm_vblank_init</function> must be freed - with a call to <function>drm_vblank_cleanup</function> in the driver - <methodname>unload</methodname> operation handler. - </para> - <sect2> - <title>Vertical Blanking and Interrupt Handling Functions Reference</title> -!Edrivers/gpu/drm/drm_irq.c -!Finclude/drm/drmP.h drm_crtc_vblank_waitqueue - </sect2> - </sect1> - - <!-- Internals: open/close, file operations and ioctls --> - - <sect1> - <title>Open/Close, File Operations and IOCTLs</title> - <sect2> - <title>Open and Close</title> - <synopsis>int (*firstopen) (struct drm_device *); -void (*lastclose) (struct drm_device *); -int (*open) (struct drm_device *, struct drm_file *); -void (*preclose) (struct drm_device *, struct drm_file *); -void (*postclose) (struct drm_device *, struct drm_file *);</synopsis> - <abstract>Open and close handlers. None of those methods are mandatory. - </abstract> - <para> - The <methodname>firstopen</methodname> method is called by the DRM core - for legacy UMS (User Mode Setting) drivers only when an application - opens a device that has no other opened file handle. UMS drivers can - implement it to acquire device resources. KMS drivers can't use the - method and must acquire resources in the <methodname>load</methodname> - method instead. - </para> - <para> - Similarly the <methodname>lastclose</methodname> method is called when - the last application holding a file handle opened on the device closes - it, for both UMS and KMS drivers. Additionally, the method is also - called at module unload time or, for hot-pluggable devices, when the - device is unplugged. The <methodname>firstopen</methodname> and - <methodname>lastclose</methodname> calls can thus be unbalanced. - </para> - <para> - The <methodname>open</methodname> method is called every time the device - is opened by an application. Drivers can allocate per-file private data - in this method and store them in the struct - <structname>drm_file</structname> <structfield>driver_priv</structfield> - field. Note that the <methodname>open</methodname> method is called - before <methodname>firstopen</methodname>. - </para> - <para> - The close operation is split into <methodname>preclose</methodname> and - <methodname>postclose</methodname> methods. Drivers must stop and - cleanup all per-file operations in the <methodname>preclose</methodname> - method. For instance pending vertical blanking and page flip events must - be cancelled. No per-file operation is allowed on the file handle after - returning from the <methodname>preclose</methodname> method. - </para> - <para> - Finally the <methodname>postclose</methodname> method is called as the - last step of the close operation, right before calling the - <methodname>lastclose</methodname> method if no other open file handle - exists for the device. Drivers that have allocated per-file private data - in the <methodname>open</methodname> method should free it here. - </para> - <para> - The <methodname>lastclose</methodname> method should restore CRTC and - plane properties to default value, so that a subsequent open of the - device will not inherit state from the previous user. It can also be - used to execute delayed power switching state changes, e.g. in - conjunction with the vga_switcheroo infrastructure (see - <xref linkend="vga_switcheroo"/>). Beyond that KMS drivers should not - do any further cleanup. Only legacy UMS drivers might need to clean up - device state so that the vga console or an independent fbdev driver - could take over. - </para> - </sect2> - <sect2> - <title>File Operations</title> -!Pdrivers/gpu/drm/drm_fops.c file operations -!Edrivers/gpu/drm/drm_fops.c - </sect2> - <sect2> - <title>IOCTLs</title> - <synopsis>struct drm_ioctl_desc *ioctls; -int num_ioctls;</synopsis> - <abstract>Driver-specific ioctls descriptors table.</abstract> - <para> - Driver-specific ioctls numbers start at DRM_COMMAND_BASE. The ioctls - descriptors table is indexed by the ioctl number offset from the base - value. Drivers can use the DRM_IOCTL_DEF_DRV() macro to initialize the - table entries. - </para> - <para> - <programlisting>DRM_IOCTL_DEF_DRV(ioctl, func, flags)</programlisting> - <para> - <parameter>ioctl</parameter> is the ioctl name. Drivers must define - the DRM_##ioctl and DRM_IOCTL_##ioctl macros to the ioctl number - offset from DRM_COMMAND_BASE and the ioctl number respectively. The - first macro is private to the device while the second must be exposed - to userspace in a public header. - </para> - <para> - <parameter>func</parameter> is a pointer to the ioctl handler function - compatible with the <type>drm_ioctl_t</type> type. - <programlisting>typedef int drm_ioctl_t(struct drm_device *dev, void *data, - struct drm_file *file_priv);</programlisting> - </para> - <para> - <parameter>flags</parameter> is a bitmask combination of the following - values. It restricts how the ioctl is allowed to be called. - <itemizedlist> - <listitem><para> - DRM_AUTH - Only authenticated callers allowed - </para></listitem> - <listitem><para> - DRM_MASTER - The ioctl can only be called on the master file - handle - </para></listitem> - <listitem><para> - DRM_ROOT_ONLY - Only callers with the SYSADMIN capability allowed - </para></listitem> - <listitem><para> - DRM_CONTROL_ALLOW - The ioctl can only be called on a control - device - </para></listitem> - <listitem><para> - DRM_UNLOCKED - The ioctl handler will be called without locking - the DRM global mutex. This is the enforced default for kms drivers - (i.e. using the DRIVER_MODESET flag) and hence shouldn't be used - any more for new drivers. - </para></listitem> - </itemizedlist> - </para> - </para> -!Edrivers/gpu/drm/drm_ioctl.c - </sect2> - </sect1> - <sect1> - <title>Legacy Support Code</title> - <para> - The section very briefly covers some of the old legacy support code which - is only used by old DRM drivers which have done a so-called shadow-attach - to the underlying device instead of registering as a real driver. This - also includes some of the old generic buffer management and command - submission code. Do not use any of this in new and modern drivers. - </para> - - <sect2> - <title>Legacy Suspend/Resume</title> - <para> - The DRM core provides some suspend/resume code, but drivers wanting full - suspend/resume support should provide save() and restore() functions. - These are called at suspend, hibernate, or resume time, and should perform - any state save or restore required by your device across suspend or - hibernate states. - </para> - <synopsis>int (*suspend) (struct drm_device *, pm_message_t state); - int (*resume) (struct drm_device *);</synopsis> - <para> - Those are legacy suspend and resume methods which - <emphasis>only</emphasis> work with the legacy shadow-attach driver - registration functions. New driver should use the power management - interface provided by their bus type (usually through - the struct <structname>device_driver</structname> dev_pm_ops) and set - these methods to NULL. - </para> - </sect2> - - <sect2> - <title>Legacy DMA Services</title> - <para> - This should cover how DMA mapping etc. is supported by the core. - These functions are deprecated and should not be used. - </para> - </sect2> - </sect1> - </chapter> - -<!-- TODO - -- Add a glossary -- Document the struct_mutex catch-all lock -- Document connector properties - -- Why is the load method optional? -- What are drivers supposed to set the initial display state to, and how? - Connector's DPMS states are not initialized and are thus equal to - DRM_MODE_DPMS_ON. The fbcon compatibility layer calls - drm_helper_disable_unused_functions(), which disables unused encoders and - CRTCs, but doesn't touch the connectors' DPMS state, and - drm_helper_connector_dpms() in reaction to fbdev blanking events. Do drivers - that don't implement (or just don't use) fbcon compatibility need to call - those functions themselves? -- KMS drivers must call drm_vblank_pre_modeset() and drm_vblank_post_modeset() - around mode setting. Should this be done in the DRM core? -- vblank_disable_allowed is set to 1 in the first drm_vblank_post_modeset() - call and never set back to 0. It seems to be safe to permanently set it to 1 - in drm_vblank_init() for KMS driver, and it might be safe for UMS drivers as - well. This should be investigated. -- crtc and connector .save and .restore operations are only used internally in - drivers, should they be removed from the core? -- encoder mid-layer .save and .restore operations are only used internally in - drivers, should they be removed from the core? -- encoder mid-layer .detect operation is only used internally in drivers, - should it be removed from the core? ---> - - <!-- External interfaces --> - - <chapter id="drmExternals"> - <title>Userland interfaces</title> - <para> - The DRM core exports several interfaces to applications, - generally intended to be used through corresponding libdrm - wrapper functions. In addition, drivers export device-specific - interfaces for use by userspace drivers & device-aware - applications through ioctls and sysfs files. - </para> - <para> - External interfaces include: memory mapping, context management, - DMA operations, AGP management, vblank control, fence - management, memory management, and output management. - </para> - <para> - Cover generic ioctls and sysfs layout here. We only need high-level - info, since man pages should cover the rest. - </para> - - <!-- External: render nodes --> - - <sect1> - <title>Render nodes</title> - <para> - DRM core provides multiple character-devices for user-space to use. - Depending on which device is opened, user-space can perform a different - set of operations (mainly ioctls). The primary node is always created - and called card<num>. Additionally, a currently - unused control node, called controlD<num> is also - created. The primary node provides all legacy operations and - historically was the only interface used by userspace. With KMS, the - control node was introduced. However, the planned KMS control interface - has never been written and so the control node stays unused to date. - </para> - <para> - With the increased use of offscreen renderers and GPGPU applications, - clients no longer require running compositors or graphics servers to - make use of a GPU. But the DRM API required unprivileged clients to - authenticate to a DRM-Master prior to getting GPU access. To avoid this - step and to grant clients GPU access without authenticating, render - nodes were introduced. Render nodes solely serve render clients, that - is, no modesetting or privileged ioctls can be issued on render nodes. - Only non-global rendering commands are allowed. If a driver supports - render nodes, it must advertise it via the DRIVER_RENDER - DRM driver capability. If not supported, the primary node must be used - for render clients together with the legacy drmAuth authentication - procedure. - </para> - <para> - If a driver advertises render node support, DRM core will create a - separate render node called renderD<num>. There will - be one render node per device. No ioctls except PRIME-related ioctls - will be allowed on this node. Especially GEM_OPEN will be - explicitly prohibited. Render nodes are designed to avoid the - buffer-leaks, which occur if clients guess the flink names or mmap - offsets on the legacy interface. Additionally to this basic interface, - drivers must mark their driver-dependent render-only ioctls as - DRM_RENDER_ALLOW so render clients can use them. Driver - authors must be careful not to allow any privileged ioctls on render - nodes. - </para> - <para> - With render nodes, user-space can now control access to the render node - via basic file-system access-modes. A running graphics server which - authenticates clients on the privileged primary/legacy node is no longer - required. Instead, a client can open the render node and is immediately - granted GPU access. Communication between clients (or servers) is done - via PRIME. FLINK from render node to legacy node is not supported. New - clients must not use the insecure FLINK interface. - </para> - <para> - Besides dropping all modeset/global ioctls, render nodes also drop the - DRM-Master concept. There is no reason to associate render clients with - a DRM-Master as they are independent of any graphics server. Besides, - they must work without any running master, anyway. - Drivers must be able to run without a master object if they support - render nodes. If, on the other hand, a driver requires shared state - between clients which is visible to user-space and accessible beyond - open-file boundaries, they cannot support render nodes. - </para> - </sect1> - - <!-- External: vblank handling --> - - <sect1> - <title>VBlank event handling</title> - <para> - The DRM core exposes two vertical blank related ioctls: - <variablelist> - <varlistentry> - <term>DRM_IOCTL_WAIT_VBLANK</term> - <listitem> - <para> - This takes a struct drm_wait_vblank structure as its argument, - and it is used to block or request a signal when a specified - vblank event occurs. - </para> - </listitem> - </varlistentry> - <varlistentry> - <term>DRM_IOCTL_MODESET_CTL</term> - <listitem> - <para> - This was only used for user-mode-settind drivers around - modesetting changes to allow the kernel to update the vblank - interrupt after mode setting, since on many devices the vertical - blank counter is reset to 0 at some point during modeset. Modern - drivers should not call this any more since with kernel mode - setting it is a no-op. - </para> - </listitem> - </varlistentry> - </variablelist> - </para> - </sect1> - - </chapter> -</part> -<part id="drmDrivers"> - <title>DRM Drivers</title> - - <partintro> - <para> - This second part of the GPU Driver Developer's Guide documents driver - code, implementation details and also all the driver-specific userspace - interfaces. Especially since all hardware-acceleration interfaces to - userspace are driver specific for efficiency and other reasons these - interfaces can be rather substantial. Hence every driver has its own - chapter. - </para> - </partintro> - - <chapter id="drmI915"> - <title>drm/i915 Intel GFX Driver</title> - <para> - The drm/i915 driver supports all (with the exception of some very early - models) integrated GFX chipsets with both Intel display and rendering - blocks. This excludes a set of SoC platforms with an SGX rendering unit, - those have basic support through the gma500 drm driver. - </para> - <sect1> - <title>Core Driver Infrastructure</title> - <para> - This section covers core driver infrastructure used by both the display - and the GEM parts of the driver. - </para> - <sect2> - <title>Runtime Power Management</title> -!Pdrivers/gpu/drm/i915/intel_runtime_pm.c runtime pm -!Idrivers/gpu/drm/i915/intel_runtime_pm.c -!Idrivers/gpu/drm/i915/intel_uncore.c - </sect2> - <sect2> - <title>Interrupt Handling</title> -!Pdrivers/gpu/drm/i915/i915_irq.c interrupt handling -!Fdrivers/gpu/drm/i915/i915_irq.c intel_irq_init intel_irq_init_hw intel_hpd_init -!Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_disable_interrupts -!Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_enable_interrupts - </sect2> - <sect2> - <title>Intel GVT-g Guest Support(vGPU)</title> -!Pdrivers/gpu/drm/i915/i915_vgpu.c Intel GVT-g guest support -!Idrivers/gpu/drm/i915/i915_vgpu.c - </sect2> - </sect1> - <sect1> - <title>Display Hardware Handling</title> - <para> - This section covers everything related to the display hardware including - the mode setting infrastructure, plane, sprite and cursor handling and - display, output probing and related topics. - </para> - <sect2> - <title>Mode Setting Infrastructure</title> - <para> - The i915 driver is thus far the only DRM driver which doesn't use the - common DRM helper code to implement mode setting sequences. Thus it - has its own tailor-made infrastructure for executing a display - configuration change. - </para> - </sect2> - <sect2> - <title>Frontbuffer Tracking</title> -!Pdrivers/gpu/drm/i915/intel_frontbuffer.c frontbuffer tracking -!Idrivers/gpu/drm/i915/intel_frontbuffer.c -!Fdrivers/gpu/drm/i915/i915_gem.c i915_gem_track_fb - </sect2> - <sect2> - <title>Display FIFO Underrun Reporting</title> -!Pdrivers/gpu/drm/i915/intel_fifo_underrun.c fifo underrun handling -!Idrivers/gpu/drm/i915/intel_fifo_underrun.c - </sect2> - <sect2> - <title>Plane Configuration</title> - <para> - This section covers plane configuration and composition with the - primary plane, sprites, cursors and overlays. This includes the - infrastructure to do atomic vsync'ed updates of all this state and - also tightly coupled topics like watermark setup and computation, - framebuffer compression and panel self refresh. - </para> - </sect2> - <sect2> - <title>Atomic Plane Helpers</title> -!Pdrivers/gpu/drm/i915/intel_atomic_plane.c atomic plane helpers -!Idrivers/gpu/drm/i915/intel_atomic_plane.c - </sect2> - <sect2> - <title>Output Probing</title> - <para> - This section covers output probing and related infrastructure like the - hotplug interrupt storm detection and mitigation code. Note that the - i915 driver still uses most of the common DRM helper code for output - probing, so those sections fully apply. - </para> - </sect2> - <sect2> - <title>Hotplug</title> -!Pdrivers/gpu/drm/i915/intel_hotplug.c Hotplug -!Idrivers/gpu/drm/i915/intel_hotplug.c - </sect2> - <sect2> - <title>High Definition Audio</title> -!Pdrivers/gpu/drm/i915/intel_audio.c High Definition Audio over HDMI and Display Port -!Idrivers/gpu/drm/i915/intel_audio.c -!Iinclude/drm/i915_component.h - </sect2> - <sect2> - <title>Panel Self Refresh PSR (PSR/SRD)</title> -!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD) -!Idrivers/gpu/drm/i915/intel_psr.c - </sect2> - <sect2> - <title>Frame Buffer Compression (FBC)</title> -!Pdrivers/gpu/drm/i915/intel_fbc.c Frame Buffer Compression (FBC) -!Idrivers/gpu/drm/i915/intel_fbc.c - </sect2> - <sect2> - <title>Display Refresh Rate Switching (DRRS)</title> -!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS) -!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state -!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable -!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable -!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate -!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush -!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init - - </sect2> - <sect2> - <title>DPIO</title> -!Pdrivers/gpu/drm/i915/i915_reg.h DPIO - </sect2> - - <sect2> - <title>CSR firmware support for DMC</title> -!Pdrivers/gpu/drm/i915/intel_csr.c csr support for dmc -!Idrivers/gpu/drm/i915/intel_csr.c - </sect2> - <sect2> - <title>Video BIOS Table (VBT)</title> -!Pdrivers/gpu/drm/i915/intel_bios.c Video BIOS Table (VBT) -!Idrivers/gpu/drm/i915/intel_bios.c -!Idrivers/gpu/drm/i915/intel_vbt_defs.h - </sect2> - </sect1> - - <sect1> - <title>Memory Management and Command Submission</title> - <para> - This sections covers all things related to the GEM implementation in the - i915 driver. - </para> - <sect2> - <title>Batchbuffer Parsing</title> -!Pdrivers/gpu/drm/i915/i915_cmd_parser.c batch buffer command parser -!Idrivers/gpu/drm/i915/i915_cmd_parser.c - </sect2> - <sect2> - <title>Batchbuffer Pools</title> -!Pdrivers/gpu/drm/i915/i915_gem_batch_pool.c batch pool -!Idrivers/gpu/drm/i915/i915_gem_batch_pool.c - </sect2> - <sect2> - <title>Logical Rings, Logical Ring Contexts and Execlists</title> -!Pdrivers/gpu/drm/i915/intel_lrc.c Logical Rings, Logical Ring Contexts and Execlists -!Idrivers/gpu/drm/i915/intel_lrc.c - </sect2> - <sect2> - <title>Global GTT views</title> -!Pdrivers/gpu/drm/i915/i915_gem_gtt.c Global GTT views -!Idrivers/gpu/drm/i915/i915_gem_gtt.c - </sect2> - <sect2> - <title>GTT Fences and Swizzling</title> -!Idrivers/gpu/drm/i915/i915_gem_fence.c - <sect3> - <title>Global GTT Fence Handling</title> -!Pdrivers/gpu/drm/i915/i915_gem_fence.c fence register handling - </sect3> - <sect3> - <title>Hardware Tiling and Swizzling Details</title> -!Pdrivers/gpu/drm/i915/i915_gem_fence.c tiling swizzling details - </sect3> - </sect2> - <sect2> - <title>Object Tiling IOCTLs</title> -!Idrivers/gpu/drm/i915/i915_gem_tiling.c -!Pdrivers/gpu/drm/i915/i915_gem_tiling.c buffer object tiling - </sect2> - <sect2> - <title>Buffer Object Eviction</title> - <para> - This section documents the interface functions for evicting buffer - objects to make space available in the virtual gpu address spaces. - Note that this is mostly orthogonal to shrinking buffer objects - caches, which has the goal to make main memory (shared with the gpu - through the unified memory architecture) available. - </para> -!Idrivers/gpu/drm/i915/i915_gem_evict.c - </sect2> - <sect2> - <title>Buffer Object Memory Shrinking</title> - <para> - This section documents the interface function for shrinking memory - usage of buffer object caches. Shrinking is used to make main memory - available. Note that this is mostly orthogonal to evicting buffer - objects, which has the goal to make space in gpu virtual address - spaces. - </para> -!Idrivers/gpu/drm/i915/i915_gem_shrinker.c - </sect2> - </sect1> - <sect1> - <title>GuC</title> - <sect2> - <title>GuC-specific firmware loader</title> -!Pdrivers/gpu/drm/i915/intel_guc_loader.c GuC-specific firmware loader -!Idrivers/gpu/drm/i915/intel_guc_loader.c - </sect2> - <sect2> - <title>GuC-based command submission</title> -!Pdrivers/gpu/drm/i915/i915_guc_submission.c GuC-based command submission -!Idrivers/gpu/drm/i915/i915_guc_submission.c - </sect2> - <sect2> - <title>GuC Firmware Layout</title> -!Pdrivers/gpu/drm/i915/intel_guc_fwif.h GuC Firmware Layout - </sect2> - </sect1> - - <sect1> - <title> Tracing </title> - <para> - This sections covers all things related to the tracepoints implemented in - the i915 driver. - </para> - <sect2> - <title> i915_ppgtt_create and i915_ppgtt_release </title> -!Pdrivers/gpu/drm/i915/i915_trace.h i915_ppgtt_create and i915_ppgtt_release tracepoints - </sect2> - <sect2> - <title> i915_context_create and i915_context_free </title> -!Pdrivers/gpu/drm/i915/i915_trace.h i915_context_create and i915_context_free tracepoints - </sect2> - <sect2> - <title> switch_mm </title> -!Pdrivers/gpu/drm/i915/i915_trace.h switch_mm tracepoint - </sect2> - </sect1> - - </chapter> -!Cdrivers/gpu/drm/i915/i915_irq.c -</part> - -<part id="vga_switcheroo"> - <title>vga_switcheroo</title> - <partintro> -!Pdrivers/gpu/vga/vga_switcheroo.c Overview - </partintro> - - <chapter id="modes_of_use"> - <title>Modes of Use</title> - <sect1> - <title>Manual switching and manual power control</title> -!Pdrivers/gpu/vga/vga_switcheroo.c Manual switching and manual power control - </sect1> - <sect1> - <title>Driver power control</title> -!Pdrivers/gpu/vga/vga_switcheroo.c Driver power control - </sect1> - </chapter> - - <chapter id="api"> - <title>API</title> - <sect1> - <title>Public functions</title> -!Edrivers/gpu/vga/vga_switcheroo.c - </sect1> - <sect1> - <title>Public structures</title> -!Finclude/linux/vga_switcheroo.h vga_switcheroo_handler -!Finclude/linux/vga_switcheroo.h vga_switcheroo_client_ops - </sect1> - <sect1> - <title>Public constants</title> -!Finclude/linux/vga_switcheroo.h vga_switcheroo_handler_flags_t -!Finclude/linux/vga_switcheroo.h vga_switcheroo_client_id -!Finclude/linux/vga_switcheroo.h vga_switcheroo_state - </sect1> - <sect1> - <title>Private structures</title> -!Fdrivers/gpu/vga/vga_switcheroo.c vgasr_priv -!Fdrivers/gpu/vga/vga_switcheroo.c vga_switcheroo_client - </sect1> - </chapter> - - <chapter id="handlers"> - <title>Handlers</title> - <sect1> - <title>apple-gmux Handler</title> -!Pdrivers/platform/x86/apple-gmux.c Overview -!Pdrivers/platform/x86/apple-gmux.c Interrupt - <sect2> - <title>Graphics mux</title> -!Pdrivers/platform/x86/apple-gmux.c Graphics mux - </sect2> - <sect2> - <title>Power control</title> -!Pdrivers/platform/x86/apple-gmux.c Power control - </sect2> - <sect2> - <title>Backlight control</title> -!Pdrivers/platform/x86/apple-gmux.c Backlight control - </sect2> - <sect2> - <title>Public functions</title> -!Iinclude/linux/apple-gmux.h - </sect2> - </sect1> - </chapter> - -!Cdrivers/gpu/vga/vga_switcheroo.c -!Cinclude/linux/vga_switcheroo.h -!Cdrivers/platform/x86/apple-gmux.c -</part> - -</book> diff --git a/Documentation/PCI/MSI-HOWTO.txt b/Documentation/PCI/MSI-HOWTO.txt index 1179850f453c..c55df2911136 100644 --- a/Documentation/PCI/MSI-HOWTO.txt +++ b/Documentation/PCI/MSI-HOWTO.txt @@ -78,422 +78,111 @@ CONFIG_PCI_MSI option. 4.2 Using MSI -Most of the hard work is done for the driver in the PCI layer. It simply -has to request that the PCI layer set up the MSI capability for this +Most of the hard work is done for the driver in the PCI layer. The driver +simply has to request that the PCI layer set up the MSI capability for this device. -4.2.1 pci_enable_msi +To automatically use MSI or MSI-X interrupt vectors, use the following +function: -int pci_enable_msi(struct pci_dev *dev) + int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags); -A successful call allocates ONE interrupt to the device, regardless -of how many MSIs the device supports. The device is switched from -pin-based interrupt mode to MSI mode. The dev->irq number is changed -to a new number which represents the message signaled interrupt; -consequently, this function should be called before the driver calls -request_irq(), because an MSI is delivered via a vector that is -different from the vector of a pin-based interrupt. +which allocates up to max_vecs interrupt vectors for a PCI device. It +returns the number of vectors allocated or a negative error. If the device +has a requirements for a minimum number of vectors the driver can pass a +min_vecs argument set to this limit, and the PCI core will return -ENOSPC +if it can't meet the minimum number of vectors. -4.2.2 pci_enable_msi_range +The flags argument should normally be set to 0, but can be used to pass the +PCI_IRQ_NOMSI and PCI_IRQ_NOMSIX flag in case a device claims to support +MSI or MSI-X, but the support is broken, or to pass PCI_IRQ_NOLEGACY in +case the device does not support legacy interrupt lines. -int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) +By default this function will spread the interrupts around the available +CPUs, but this feature can be disabled by passing the PCI_IRQ_NOAFFINITY +flag. -This function allows a device driver to request any number of MSI -interrupts within specified range from 'minvec' to 'maxvec'. +To get the Linux IRQ numbers passed to request_irq() and free_irq() and the +vectors, use the following function: -If this function returns a positive number it indicates the number of -MSI interrupts that have been successfully allocated. In this case -the device is switched from pin-based interrupt mode to MSI mode and -updates dev->irq to be the lowest of the new interrupts assigned to it. -The other interrupts assigned to the device are in the range dev->irq -to dev->irq + returned value - 1. Device driver can use the returned -number of successfully allocated MSI interrupts to further allocate -and initialize device resources. + int pci_irq_vector(struct pci_dev *dev, unsigned int nr); -If this function returns a negative number, it indicates an error and -the driver should not attempt to request any more MSI interrupts for -this device. +Any allocated resources should be freed before removing the device using +the following function: -This function should be called before the driver calls request_irq(), -because MSI interrupts are delivered via vectors that are different -from the vector of a pin-based interrupt. + void pci_free_irq_vectors(struct pci_dev *dev); -It is ideal if drivers can cope with a variable number of MSI interrupts; -there are many reasons why the platform may not be able to provide the -exact number that a driver asks for. +If a device supports both MSI-X and MSI capabilities, this API will use the +MSI-X facilities in preference to the MSI facilities. MSI-X supports any +number of interrupts between 1 and 2048. In contrast, MSI is restricted to +a maximum of 32 interrupts (and must be a power of two). In addition, the +MSI interrupt vectors must be allocated consecutively, so the system might +not be able to allocate as many vectors for MSI as it could for MSI-X. On +some platforms, MSI interrupts must all be targeted at the same set of CPUs +whereas MSI-X interrupts can all be targeted at different CPUs. -There could be devices that can not operate with just any number of MSI -interrupts within a range. See chapter 4.3.1.3 to get the idea how to -handle such devices for MSI-X - the same logic applies to MSI. +If a device supports neither MSI-X or MSI it will fall back to a single +legacy IRQ vector. -4.2.1.1 Maximum possible number of MSI interrupts +The typical usage of MSI or MSI-X interrupts is to allocate as many vectors +as possible, likely up to the limit supported by the device. If nvec is +larger than the number supported by the device it will automatically be +capped to the supported limit, so there is no need to query the number of +vectors supported beforehand: -The typical usage of MSI interrupts is to allocate as many vectors as -possible, likely up to the limit returned by pci_msi_vec_count() function: - -static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec) -{ - return pci_enable_msi_range(pdev, 1, nvec); -} - -Note the value of 'minvec' parameter is 1. As 'minvec' is inclusive, -the value of 0 would be meaningless and could result in error. - -Some devices have a minimal limit on number of MSI interrupts. -In this case the function could look like this: - -static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec) -{ - return pci_enable_msi_range(pdev, FOO_DRIVER_MINIMUM_NVEC, nvec); -} - -4.2.1.2 Exact number of MSI interrupts + nvec = pci_alloc_irq_vectors(pdev, 1, nvec, 0); + if (nvec < 0) + goto out_err; If a driver is unable or unwilling to deal with a variable number of MSI -interrupts it could request a particular number of interrupts by passing -that number to pci_enable_msi_range() function as both 'minvec' and 'maxvec' -parameters: - -static int foo_driver_enable_msi(struct pci_dev *pdev, int nvec) -{ - return pci_enable_msi_range(pdev, nvec, nvec); -} - -Note, unlike pci_enable_msi_exact() function, which could be also used to -enable a particular number of MSI-X interrupts, pci_enable_msi_range() -returns either a negative errno or 'nvec' (not negative errno or 0 - as -pci_enable_msi_exact() does). - -4.2.1.3 Single MSI mode - -The most notorious example of the request type described above is -enabling the single MSI mode for a device. It could be done by passing -two 1s as 'minvec' and 'maxvec': - -static int foo_driver_enable_single_msi(struct pci_dev *pdev) -{ - return pci_enable_msi_range(pdev, 1, 1); -} - -Note, unlike pci_enable_msi() function, which could be also used to -enable the single MSI mode, pci_enable_msi_range() returns either a -negative errno or 1 (not negative errno or 0 - as pci_enable_msi() -does). - -4.2.3 pci_enable_msi_exact - -int pci_enable_msi_exact(struct pci_dev *dev, int nvec) - -This variation on pci_enable_msi_range() call allows a device driver to -request exactly 'nvec' MSIs. - -If this function returns a negative number, it indicates an error and -the driver should not attempt to request any more MSI interrupts for -this device. - -By contrast with pci_enable_msi_range() function, pci_enable_msi_exact() -returns zero in case of success, which indicates MSI interrupts have been -successfully allocated. - -4.2.4 pci_disable_msi - -void pci_disable_msi(struct pci_dev *dev) - -This function should be used to undo the effect of pci_enable_msi_range(). -Calling it restores dev->irq to the pin-based interrupt number and frees -the previously allocated MSIs. The interrupts may subsequently be assigned -to another device, so drivers should not cache the value of dev->irq. - -Before calling this function, a device driver must always call free_irq() -on any interrupt for which it previously called request_irq(). -Failure to do so results in a BUG_ON(), leaving the device with -MSI enabled and thus leaking its vector. - -4.2.4 pci_msi_vec_count - -int pci_msi_vec_count(struct pci_dev *dev) - -This function could be used to retrieve the number of MSI vectors the -device requested (via the Multiple Message Capable register). The MSI -specification only allows the returned value to be a power of two, -up to a maximum of 2^5 (32). - -If this function returns a negative number, it indicates the device is -not capable of sending MSIs. - -If this function returns a positive number, it indicates the maximum -number of MSI interrupt vectors that could be allocated. - -4.3 Using MSI-X - -The MSI-X capability is much more flexible than the MSI capability. -It supports up to 2048 interrupts, each of which can be controlled -independently. To support this flexibility, drivers must use an array of -`struct msix_entry': - -struct msix_entry { - u16 vector; /* kernel uses to write alloc vector */ - u16 entry; /* driver uses to specify entry */ -}; - -This allows for the device to use these interrupts in a sparse fashion; -for example, it could use interrupts 3 and 1027 and yet allocate only a -two-element array. The driver is expected to fill in the 'entry' value -in each element of the array to indicate for which entries the kernel -should assign interrupts; it is invalid to fill in two entries with the -same number. - -4.3.1 pci_enable_msix_range - -int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, - int minvec, int maxvec) - -Calling this function asks the PCI subsystem to allocate any number of -MSI-X interrupts within specified range from 'minvec' to 'maxvec'. -The 'entries' argument is a pointer to an array of msix_entry structs -which should be at least 'maxvec' entries in size. - -On success, the device is switched into MSI-X mode and the function -returns the number of MSI-X interrupts that have been successfully -allocated. In this case the 'vector' member in entries numbered from -0 to the returned value - 1 is populated with the interrupt number; -the driver should then call request_irq() for each 'vector' that it -decides to use. The device driver is responsible for keeping track of the -interrupts assigned to the MSI-X vectors so it can free them again later. -Device driver can use the returned number of successfully allocated MSI-X -interrupts to further allocate and initialize device resources. - -If this function returns a negative number, it indicates an error and -the driver should not attempt to allocate any more MSI-X interrupts for -this device. - -This function, in contrast with pci_enable_msi_range(), does not adjust -dev->irq. The device will not generate interrupts for this interrupt -number once MSI-X is enabled. - -Device drivers should normally call this function once per device -during the initialization phase. - -It is ideal if drivers can cope with a variable number of MSI-X interrupts; -there are many reasons why the platform may not be able to provide the -exact number that a driver asks for. - -There could be devices that can not operate with just any number of MSI-X -interrupts within a range. E.g., an network adapter might need let's say -four vectors per each queue it provides. Therefore, a number of MSI-X -interrupts allocated should be a multiple of four. In this case interface -pci_enable_msix_range() can not be used alone to request MSI-X interrupts -(since it can allocate any number within the range, without any notion of -the multiple of four) and the device driver should master a custom logic -to request the required number of MSI-X interrupts. - -4.3.1.1 Maximum possible number of MSI-X interrupts - -The typical usage of MSI-X interrupts is to allocate as many vectors as -possible, likely up to the limit returned by pci_msix_vec_count() function: - -static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec) -{ - return pci_enable_msix_range(adapter->pdev, adapter->msix_entries, - 1, nvec); -} - -Note the value of 'minvec' parameter is 1. As 'minvec' is inclusive, -the value of 0 would be meaningless and could result in error. - -Some devices have a minimal limit on number of MSI-X interrupts. -In this case the function could look like this: - -static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec) -{ - return pci_enable_msix_range(adapter->pdev, adapter->msix_entries, - FOO_DRIVER_MINIMUM_NVEC, nvec); -} - -4.3.1.2 Exact number of MSI-X interrupts - -If a driver is unable or unwilling to deal with a variable number of MSI-X -interrupts it could request a particular number of interrupts by passing -that number to pci_enable_msix_range() function as both 'minvec' and 'maxvec' -parameters: - -static int foo_driver_enable_msix(struct foo_adapter *adapter, int nvec) -{ - return pci_enable_msix_range(adapter->pdev, adapter->msix_entries, - nvec, nvec); -} - -Note, unlike pci_enable_msix_exact() function, which could be also used to -enable a particular number of MSI-X interrupts, pci_enable_msix_range() -returns either a negative errno or 'nvec' (not negative errno or 0 - as -pci_enable_msix_exact() does). - -4.3.1.3 Specific requirements to the number of MSI-X interrupts - -As noted above, there could be devices that can not operate with just any -number of MSI-X interrupts within a range. E.g., let's assume a device that -is only capable sending the number of MSI-X interrupts which is a power of -two. A routine that enables MSI-X mode for such device might look like this: - -/* - * Assume 'minvec' and 'maxvec' are non-zero - */ -static int foo_driver_enable_msix(struct foo_adapter *adapter, - int minvec, int maxvec) -{ - int rc; - - minvec = roundup_pow_of_two(minvec); - maxvec = rounddown_pow_of_two(maxvec); - - if (minvec > maxvec) - return -ERANGE; - -retry: - rc = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, - maxvec, maxvec); - /* - * -ENOSPC is the only error code allowed to be analyzed - */ - if (rc == -ENOSPC) { - if (maxvec == 1) - return -ENOSPC; - - maxvec /= 2; - - if (minvec > maxvec) - return -ENOSPC; - - goto retry; - } - - return rc; -} - -Note how pci_enable_msix_range() return value is analyzed for a fallback - -any error code other than -ENOSPC indicates a fatal error and should not -be retried. - -4.3.2 pci_enable_msix_exact - -int pci_enable_msix_exact(struct pci_dev *dev, - struct msix_entry *entries, int nvec) - -This variation on pci_enable_msix_range() call allows a device driver to -request exactly 'nvec' MSI-Xs. - -If this function returns a negative number, it indicates an error and -the driver should not attempt to allocate any more MSI-X interrupts for -this device. - -By contrast with pci_enable_msix_range() function, pci_enable_msix_exact() -returns zero in case of success, which indicates MSI-X interrupts have been -successfully allocated. - -Another version of a routine that enables MSI-X mode for a device with -specific requirements described in chapter 4.3.1.3 might look like this: - -/* - * Assume 'minvec' and 'maxvec' are non-zero - */ -static int foo_driver_enable_msix(struct foo_adapter *adapter, - int minvec, int maxvec) -{ - int rc; - - minvec = roundup_pow_of_two(minvec); - maxvec = rounddown_pow_of_two(maxvec); - - if (minvec > maxvec) - return -ERANGE; - -retry: - rc = pci_enable_msix_exact(adapter->pdev, - adapter->msix_entries, maxvec); - - /* - * -ENOSPC is the only error code allowed to be analyzed - */ - if (rc == -ENOSPC) { - if (maxvec == 1) - return -ENOSPC; - - maxvec /= 2; - - if (minvec > maxvec) - return -ENOSPC; - - goto retry; - } else if (rc < 0) { - return rc; - } - - return maxvec; -} - -4.3.3 pci_disable_msix - -void pci_disable_msix(struct pci_dev *dev) - -This function should be used to undo the effect of pci_enable_msix_range(). -It frees the previously allocated MSI-X interrupts. The interrupts may -subsequently be assigned to another device, so drivers should not cache -the value of the 'vector' elements over a call to pci_disable_msix(). - -Before calling this function, a device driver must always call free_irq() -on any interrupt for which it previously called request_irq(). -Failure to do so results in a BUG_ON(), leaving the device with -MSI-X enabled and thus leaking its vector. - -4.3.3 The MSI-X Table - -The MSI-X capability specifies a BAR and offset within that BAR for the -MSI-X Table. This address is mapped by the PCI subsystem, and should not -be accessed directly by the device driver. If the driver wishes to -mask or unmask an interrupt, it should call disable_irq() / enable_irq(). +interrupts it can request a particular number of interrupts by passing that +number to pci_alloc_irq_vectors() function as both 'min_vecs' and +'max_vecs' parameters: -4.3.4 pci_msix_vec_count + ret = pci_alloc_irq_vectors(pdev, nvec, nvec, 0); + if (ret < 0) + goto out_err; -int pci_msix_vec_count(struct pci_dev *dev) +The most notorious example of the request type described above is enabling +the single MSI mode for a device. It could be done by passing two 1s as +'min_vecs' and 'max_vecs': -This function could be used to retrieve number of entries in the device -MSI-X table. + ret = pci_alloc_irq_vectors(pdev, 1, 1, 0); + if (ret < 0) + goto out_err; -If this function returns a negative number, it indicates the device is -not capable of sending MSI-Xs. +Some devices might not support using legacy line interrupts, in which case +the PCI_IRQ_NOLEGACY flag can be used to fail the request if the platform +can't provide MSI or MSI-X interrupts: -If this function returns a positive number, it indicates the maximum -number of MSI-X interrupt vectors that could be allocated. + nvec = pci_alloc_irq_vectors(pdev, 1, nvec, PCI_IRQ_NOLEGACY); + if (nvec < 0) + goto out_err; -4.4 Handling devices implementing both MSI and MSI-X capabilities +4.3 Legacy APIs -If a device implements both MSI and MSI-X capabilities, it can -run in either MSI mode or MSI-X mode, but not both simultaneously. -This is a requirement of the PCI spec, and it is enforced by the -PCI layer. Calling pci_enable_msi_range() when MSI-X is already -enabled or pci_enable_msix_range() when MSI is already enabled -results in an error. If a device driver wishes to switch between MSI -and MSI-X at runtime, it must first quiesce the device, then switch -it back to pin-interrupt mode, before calling pci_enable_msi_range() -or pci_enable_msix_range() and resuming operation. This is not expected -to be a common operation but may be useful for debugging or testing -during development. +The following old APIs to enable and disable MSI or MSI-X interrupts should +not be used in new code: -4.5 Considerations when using MSIs + pci_enable_msi() /* deprecated */ + pci_enable_msi_range() /* deprecated */ + pci_enable_msi_exact() /* deprecated */ + pci_disable_msi() /* deprecated */ + pci_enable_msix_range() /* deprecated */ + pci_enable_msix_exact() /* deprecated */ + pci_disable_msix() /* deprecated */ -4.5.1 Choosing between MSI-X and MSI +Additionally there are APIs to provide the number of supported MSI or MSI-X +vectors: pci_msi_vec_count() and pci_msix_vec_count(). In general these +should be avoided in favor of letting pci_alloc_irq_vectors() cap the +number of vectors. If you have a legitimate special use case for the count +of vectors we might have to revisit that decision and add a +pci_nr_irq_vectors() helper that handles MSI and MSI-X transparently. -If your device supports both MSI-X and MSI capabilities, you should use -the MSI-X facilities in preference to the MSI facilities. As mentioned -above, MSI-X supports any number of interrupts between 1 and 2048. -In contrast, MSI is restricted to a maximum of 32 interrupts (and -must be a power of two). In addition, the MSI interrupt vectors must -be allocated consecutively, so the system might not be able to allocate -as many vectors for MSI as it could for MSI-X. On some platforms, MSI -interrupts must all be targeted at the same set of CPUs whereas MSI-X -interrupts can all be targeted at different CPUs. +4.4 Considerations when using MSIs -4.5.2 Spinlocks +4.4.1 Spinlocks Most device drivers have a per-device spinlock which is taken in the interrupt handler. With pin-based interrupts or a single MSI, it is not @@ -505,7 +194,7 @@ acquire the spinlock. Such deadlocks can be avoided by using spin_lock_irqsave() or spin_lock_irq() which disable local interrupts and acquire the lock (see Documentation/DocBook/kernel-locking). -4.6 How to tell whether MSI/MSI-X is enabled on a device +4.5 How to tell whether MSI/MSI-X is enabled on a device Using 'lspci -v' (as root) may show some devices with "MSI", "Message Signalled Interrupts" or "MSI-X" capabilities. Each of these capabilities diff --git a/Documentation/arm/Atmel/README b/Documentation/arm/Atmel/README index 0931cf7e2e56..6ca78f818dbf 100644 --- a/Documentation/arm/Atmel/README +++ b/Documentation/arm/Atmel/README @@ -91,9 +91,15 @@ the Atmel website: http://www.atmel.com. http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf - sama5d2 family - - sama5d27 + - sama5d21 + - sama5d22 + - sama5d23 + - sama5d24 + - sama5d26 + - sama5d27 (device superset) + - sama5d28 (device superset + environmental monitors) + Datasheet - Coming soon + http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf Linux kernel information diff --git a/Documentation/block/biodoc.txt b/Documentation/block/biodoc.txt index 5be8a7f4cc7f..026d13362aca 100644 --- a/Documentation/block/biodoc.txt +++ b/Documentation/block/biodoc.txt @@ -1024,8 +1024,7 @@ could be on demand. For example wait_on_buffer sets the unplugging going through sync_buffer() running blk_run_address_space(mapping). Or the caller can do it explicity through blk_unplug(bdev). So in the read case, the queue gets explicitly unplugged as part of waiting for completion on that -buffer. For page driven IO, the address space ->sync_page() takes care of -doing the blk_run_address_space(). +buffer. Aside: This is kind of controversial territory, as it's not clear if plugging is diff --git a/Documentation/cgroup-v1/memcg_test.txt b/Documentation/cgroup-v1/memcg_test.txt index 8870b0212150..78a8c2963b38 100644 --- a/Documentation/cgroup-v1/memcg_test.txt +++ b/Documentation/cgroup-v1/memcg_test.txt @@ -107,9 +107,9 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y. 8. LRU Each memcg has its own private LRU. Now, its handling is under global - VM's control (means that it's handled under global zone->lru_lock). + VM's control (means that it's handled under global zone_lru_lock). Almost all routines around memcg's LRU is called by global LRU's - list management functions under zone->lru_lock(). + list management functions under zone_lru_lock(). A special function is mem_cgroup_isolate_pages(). This scans memcg's private LRU and call __isolate_lru_page() to extract a page diff --git a/Documentation/cgroup-v1/memory.txt b/Documentation/cgroup-v1/memory.txt index b14abf217239..946e69103cdd 100644 --- a/Documentation/cgroup-v1/memory.txt +++ b/Documentation/cgroup-v1/memory.txt @@ -267,11 +267,11 @@ When oom event notifier is registered, event will be delivered. Other lock order is following: PG_locked. mm->page_table_lock - zone->lru_lock + zone_lru_lock lock_page_cgroup. In many cases, just lock_page_cgroup() is called. per-zone-per-cgroup LRU (cgroup's private LRU) is just guarded by - zone->lru_lock, it has no lock of its own. + zone_lru_lock, it has no lock of its own. 2.7 Kernel Memory Extension (CONFIG_MEMCG_KMEM) diff --git a/Documentation/coccinelle.txt b/Documentation/coccinelle.txt index 7f773d51fdd9..01fb1dae3163 100644 --- a/Documentation/coccinelle.txt +++ b/Documentation/coccinelle.txt @@ -38,6 +38,15 @@ as a regular user, and install it with sudo make install + Supplemental documentation +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For supplemental documentation refer to the wiki: + +https://bottest.wiki.kernel.org/coccicheck + +The wiki documentation always refers to the linux-next version of the script. + Using Coccinelle on the Linux kernel ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -94,11 +103,26 @@ To enable verbose messages set the V= variable, for example: make coccicheck MODE=report V=1 + Coccinelle parallelization +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + By default, coccicheck tries to run as parallel as possible. To change the parallelism, set the J= variable. For example, to run across 4 CPUs: make coccicheck MODE=report J=4 +As of Coccinelle 1.0.2 Coccinelle uses Ocaml parmap for parallelization, +if support for this is detected you will benefit from parmap parallelization. + +When parmap is enabled coccicheck will enable dynamic load balancing by using +'--chunksize 1' argument, this ensures we keep feeding threads with work +one by one, so that we avoid the situation where most work gets done by only +a few threads. With dynamic load balancing, if a thread finishes early we keep +feeding it more work. + +When parmap is enabled, if an error occurs in Coccinelle, this error +value is propagated back, the return value of the 'make coccicheck' +captures this return value. Using Coccinelle with a single semantic patch ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -142,15 +166,118 @@ semantic patch as shown in the previous section. The "report" mode is the default. You can select another one with the MODE variable explained above. + Debugging Coccinelle SmPL patches +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Using coccicheck is best as it provides in the spatch command line +include options matching the options used when we compile the kernel. +You can learn what these options are by using V=1, you could then +manually run Coccinelle with debug options added. + +Alternatively you can debug running Coccinelle against SmPL patches +by asking for stderr to be redirected to stderr, by default stderr +is redirected to /dev/null, if you'd like to capture stderr you +can specify the DEBUG_FILE="file.txt" option to coccicheck. For +instance: + + rm -f cocci.err + make coccicheck COCCI=scripts/coccinelle/free/kfree.cocci MODE=report DEBUG_FILE=cocci.err + cat cocci.err + +You can use SPFLAGS to add debugging flags, for instance you may want to +add both --profile --show-trying to SPFLAGS when debugging. For instance +you may want to use: + + rm -f err.log + export COCCI=scripts/coccinelle/misc/irqf_oneshot.cocci + make coccicheck DEBUG_FILE="err.log" MODE=report SPFLAGS="--profile --show-trying" M=./drivers/mfd/arizona-irq.c + +err.log will now have the profiling information, while stdout will +provide some progress information as Coccinelle moves forward with +work. + +DEBUG_FILE support is only supported when using coccinelle >= 1.2. + + .cocciconfig support +~~~~~~~~~~~~~~~~~~~~~~ + +Coccinelle supports reading .cocciconfig for default Coccinelle options that +should be used every time spatch is spawned, the order of precedence for +variables for .cocciconfig is as follows: + + o Your current user's home directory is processed first + o Your directory from which spatch is called is processed next + o The directory provided with the --dir option is processed last, if used + +Since coccicheck runs through make, it naturally runs from the kernel +proper dir, as such the second rule above would be implied for picking up a +.cocciconfig when using 'make coccicheck'. + +'make coccicheck' also supports using M= targets.If you do not supply +any M= target, it is assumed you want to target the entire kernel. +The kernel coccicheck script has: + + if [ "$KBUILD_EXTMOD" = "" ] ; then + OPTIONS="--dir $srctree $COCCIINCLUDE" + else + OPTIONS="--dir $KBUILD_EXTMOD $COCCIINCLUDE" + fi + +KBUILD_EXTMOD is set when an explicit target with M= is used. For both cases +the spatch --dir argument is used, as such third rule applies when whether M= +is used or not, and when M= is used the target directory can have its own +.cocciconfig file. When M= is not passed as an argument to coccicheck the +target directory is the same as the directory from where spatch was called. + +If not using the kernel's coccicheck target, keep the above precedence +order logic of .cocciconfig reading. If using the kernel's coccicheck target, +override any of the kernel's .coccicheck's settings using SPFLAGS. + +We help Coccinelle when used against Linux with a set of sensible defaults +options for Linux with our own Linux .cocciconfig. This hints to coccinelle +git can be used for 'git grep' queries over coccigrep. A timeout of 200 +seconds should suffice for now. + +The options picked up by coccinelle when reading a .cocciconfig do not appear +as arguments to spatch processes running on your system, to confirm what +options will be used by Coccinelle run: + + spatch --print-options-only + +You can override with your own preferred index option by using SPFLAGS. Take +note that when there are conflicting options Coccinelle takes precedence for +the last options passed. Using .cocciconfig is possible to use idutils, however +given the order of precedence followed by Coccinelle, since the kernel now +carries its own .cocciconfig, you will need to use SPFLAGS to use idutils if +desired. See below section "Additional flags" for more details on how to use +idutils. + Additional flags ~~~~~~~~~~~~~~~~~~ Additional flags can be passed to spatch through the SPFLAGS -variable. +variable. This works as Coccinelle respects the last flags +given to it when options are in conflict. make SPFLAGS=--use-glimpse coccicheck + +Coccinelle supports idutils as well but requires coccinelle >= 1.0.6. +When no ID file is specified coccinelle assumes your ID database file +is in the file .id-utils.index on the top level of the kernel, coccinelle +carries a script scripts/idutils_index.sh which creates the database with + + mkid -i C --output .id-utils.index + +If you have another database filename you can also just symlink with this +name. + make SPFLAGS=--use-idutils coccicheck +Alternatively you can specify the database filename explicitly, for +instance: + + make SPFLAGS="--use-idutils /full-path/to/ID" coccicheck + See spatch --help to learn more about spatch options. Note that the '--use-glimpse' and '--use-idutils' options @@ -159,6 +286,25 @@ thus active by default. However, by indexing the code with one of these tools, and according to the cocci file used, spatch could proceed the entire code base more quickly. + SmPL patch specific options +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +SmPL patches can have their own requirements for options passed +to Coccinelle. SmPL patch specific options can be provided by +providing them at the top of the SmPL patch, for instance: + +// Options: --no-includes --include-headers + + SmPL patch Coccinelle requirements +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +As Coccinelle features get added some more advanced SmPL patches +may require newer versions of Coccinelle. If an SmPL patch requires +at least a version of Coccinelle, this can be specified as follows, +as an example if requiring at least Coccinelle >= 1.0.5: + +// Requires: 1.0.5 + Proposing new semantic patches ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index 313dabdc14f9..faa4b44572e3 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -87,10 +87,33 @@ Required properties: implementation for the IDs to use. For Juno R0 and Juno R1 refer to [3]. +Power domain bindings for the power domains based on SCPI Message Protocol +------------------------------------------------------------ + +This binding uses the generic power domain binding[4]. + +PM domain providers +=================== + +Required properties: + - #power-domain-cells : Should be 1. Contains the device or the power + domain ID value used by SCPI commands. + - num-domains: Total number of power domains provided by SCPI. This is + needed as the SCPI message protocol lacks a mechanism to + query this information at runtime. + +PM domain consumers +=================== + +Required properties: + - power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. + [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/thermal/thermal.txt [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html +[4] Documentation/devicetree/bindings/power/power_domain.txt Example: @@ -144,6 +167,12 @@ scpi_protocol: scpi@2e000000 { compatible = "arm,scpi-sensors"; #thermal-sensor-cells = <1>; }; + + scpi_devpd: scpi-power-domains { + compatible = "arm,scpi-power-domains"; + num-domains = <2>; + #power-domain-cells = <1>; + }; }; cpu@0 { @@ -156,6 +185,7 @@ hdlcd@7ff60000 { ... reg = <0 0x7ff60000 0 0x1000>; clocks = <&scpi_clk 4>; + power-domains = <&scpi_devpd 1>; }; thermal-zones { @@ -186,3 +216,7 @@ The thermal-sensors property in the soc_thermal node uses the temperature sensor provided by SCP firmware to setup a thermal zone. The ID "3" is the sensor identifier for the temperature sensor as used by the firmware. + +The num-domains property in scpi-power-domains domain specifies that +SCPI provides 2 power domains. The hdlcd node uses the power domain with +domain ID 1. diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt index 8240c023e202..e3f996920403 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt @@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs: BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664 The enable method is specified by defining the following required -properties in the "cpus" device tree node: +properties in the "cpu" device tree node: - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <...>; @@ -19,8 +19,6 @@ Example: cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; - secondary-boot-reg = <0x3500417c>; cpu0: cpu@0 { device_type = "cpu"; @@ -32,5 +30,7 @@ Example: device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x3500417c>; }; }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt new file mode 100644 index 000000000000..a3af54c0e404 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt @@ -0,0 +1,36 @@ +Broadcom Kona Family CPU Enable Method +-------------------------------------- +This binding defines the enable method used for starting secondary +CPUs in the following Broadcom SoCs: + BCM23550 + +The enable method is specified by defining the following required +properties in the "cpu" device tree node: + - enable-method = "brcm,bcm23550"; + - secondary-boot-reg = <...>; + +The secondary-boot-reg property is a u32 value that specifies the +physical address of the register used to request the ROM holding pen +code release a secondary CPU. The value written to the register is +formed by encoding the target CPU id into the low bits of the +physical start address it should jump to. + +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "brcm,bcm23550"; + secondary-boot-reg = <0x3500417c>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt new file mode 100644 index 000000000000..080baad923d6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt @@ -0,0 +1,15 @@ +Broadcom BCM23550 device tree bindings +-------------------------------------- + +This document describes the device tree bindings for boards with the BCM23550 +SoC. + +Required root node property: + - compatible: brcm,bcm23550 + +Example: + / { + model = "BCM23550 SoC"; + compatible = "brcm,bcm23550"; + [...] + } diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 11d3056dc2bd..6ffe08778465 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -30,6 +30,10 @@ Raspberry Pi 2 Model B Required root node properties: compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; +Raspberry Pi 3 Model B +Required root node properties: +compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + Raspberry Pi Compute Module Required root node properties: compatible = "raspberrypi,compute-module", "brcm,bcm2835"; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 93147c0c8a0e..fcbae6a5e6c1 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -12,14 +12,33 @@ its hardware characteristcs. * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - - "arm,coresight-etb10", "arm,primecell"; - - "arm,coresight-tpiu", "arm,primecell"; - - "arm,coresight-tmc", "arm,primecell"; - - "arm,coresight-funnel", "arm,primecell"; - - "arm,coresight-etm3x", "arm,primecell"; - - "arm,coresight-etm4x", "arm,primecell"; - - "qcom,coresight-replicator1x", "arm,primecell"; - - "arm,coresight-stm", "arm,primecell"; [1] + - Embedded Trace Buffer (version 1.0): + "arm,coresight-etb10", "arm,primecell"; + + - Trace Port Interface Unit: + "arm,coresight-tpiu", "arm,primecell"; + + - Trace Memory Controller, used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) + configuration. The configuration mode (ETB, ETF, ETR) is + discovered at boot time when the device is probed. + "arm,coresight-tmc", "arm,primecell"; + + - Trace Funnel: + "arm,coresight-funnel", "arm,primecell"; + + - Embedded Trace Macrocell (version 3.x) and + Program Flow Trace Macrocell: + "arm,coresight-etm3x", "arm,primecell"; + + - Embedded Trace Macrocell (version 4.x): + "arm,coresight-etm4x", "arm,primecell"; + + - Qualcomm Configurable Replicator (version 1.x): + "qcom,coresight-replicator1x", "arm,primecell"; + + - System Trace Macrocell: + "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3f0cbbb8395f..e6782d50cbcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -193,6 +193,8 @@ nodes to be present and contain the properties described below. "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,realview-smp" + "brcm,bcm11351-cpu-method" + "brcm,bcm23550" "brcm,bcm-nsp-smp" "brcm,brahma-b15" "marvell,armada-375-smp" @@ -204,6 +206,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "renesas,apmu" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp" diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt new file mode 100644 index 000000000000..115c5be0bd0b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt @@ -0,0 +1,14 @@ +* Hisilicon Hi3519 System Controller Block + +This bindings use the following binding: +Documentation/devicetree/bindings/mfd/syscon.txt + +Required properties: +- compatible: "hisilicon,hi3519-sysctrl". +- reg: the register region of this block + +Examples: +sysctrl: system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index c453ab5553cd..917199f17965 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -86,10 +86,10 @@ Optional properties: firmware) - arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, - preferrably retain firmware settings) + preferably retain firmware settings) - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, - preferrably retain firmware settings) + preferably retain firmware settings) Example: diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index d9c2a37a4090..c860b245d8c8 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -10,6 +10,7 @@ compatible: Must contain one of "mediatek,mt6580" "mediatek,mt6589" "mediatek,mt6592" + "mediatek,mt6755" "mediatek,mt6795" "mediatek,mt7623" "mediatek,mt8127" @@ -31,6 +32,9 @@ Supported boards: - Evaluation board for MT6592: Required root node properties: - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; +- Evaluation phone for MT6755(Helio P10): + Required root node properties: + - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - Evaluation board for MT6795(Helio X10): Required root node properties: - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt index 007fb5c685a1..d726aeca56be 100644 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ b/Documentation/devicetree/bindings/arm/olimex.txt @@ -1,5 +1,9 @@ -Olimex i.MX Platforms Device Tree Bindings ------------------------------------------- +Olimex Device Tree Bindings +--------------------------- + +SAM9-L9260 Board +Required root node properties: + - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; i.MX23 Olinuxino Low Cost Board Required root node properties: diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 715d960d5eea..666864517069 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -107,6 +107,9 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; +- Rockchip RK3229 Evaluation board: + - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + - Rockchip RK3399 evb: Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index f5deace2b380..0ea7f14ef294 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -47,6 +47,7 @@ Required root node properties: - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. + - "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU. - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel Odroid XU3 Lite board. diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 9cf67e48f222..1df32d339da5 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -29,6 +29,8 @@ SoCs: compatible = "renesas,r8a7794" - R-Car H3 (R8A77950) compatible = "renesas,r8a7795" + - R-Car M3-W (R8A77960) + compatible = "renesas,r8a7796" Boards: @@ -39,6 +41,8 @@ Boards: compatible = "renesas,ape6evm", "renesas,r8a73a4" - Atmark Techno Armadillo-800 EVA compatible = "renesas,armadillo800eva" + - Blanche (RTP0RC7792SEB00010S) + compatible = "renesas,blanche", "renesas,r8a7792" - BOCK-W compatible = "renesas,bockw", "renesas,r8a7778" - Genmai (RTK772100BC00000BR) @@ -61,5 +65,7 @@ Boards: compatible = "renesas,porter", "renesas,r8a7791" - Salvator-X (RTP0RC7795SIPB0010S) compatible = "renesas,salvator-x", "renesas,r8a7795"; + - Salvator-X + compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 73278c6d2dc3..b5a4342c1d46 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -32,7 +32,11 @@ board-specific compatible values: nvidia,whistler toradex,apalis_t30 toradex,apalis_t30-eval + toradex,apalis-tk1 + toradex,apalis-tk1-eval toradex,colibri_t20-512 + toradex,colibri_t30 + toradex,colibri_t30-eval-v3 toradex,iris Trusted Foundations diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index 87adfb227ca9..fedc213b5f1a 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -10,6 +10,7 @@ PHYs. Required properties: - compatible : compatible string, one of: - "allwinner,sun4i-a10-ahci" + - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" - "ibm,476gtr-ahci" diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt new file mode 100644 index 000000000000..7ff13be1750b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt @@ -0,0 +1,45 @@ +NVIDIA Tegra ACONNECT Bus + +The Tegra ACONNECT bus is an AXI switch which is used to connnect various +components inside the Audio Processing Engine (APE). All CPU accesses to +the APE subsystem go through the ACONNECT via an APB to AXI wrapper. + +Required properties: +- compatible: Must be "nvidia,tegra210-aconnect". +- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), + and APE interface clock (TEGRA210_CLK_APB2APE). +- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding + 'clocks' entries. +- power-domains: Must contain a phandle that points to the audio powergate + (namely 'aud') for Tegra210. +- #address-cells: The number of cells used to represent physical base addresses + in the aconnect address space. Should be 1. +- #size-cells: The number of cells used to represent the size of an address + range in the aconnect address space. Should be 1. +- ranges: Mapping of the aconnect address space to the CPU address space. + +All devices accessed via the ACONNNECT are described by child-nodes. + +Example: + + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; + + status = "disabled"; + + child1 { + ... + }; + + child2 { + ... + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt new file mode 100644 index 000000000000..ce06435d28ed --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -0,0 +1,36 @@ +* Amlogic GXBB Clock and Reset Unit + +The Amlogic GXBB clock controller generates and supplies clock to various +controllers within the SoC. + +Required Properties: + +- compatible: should be "amlogic,gxbb-clkc" +- reg: physical base address of the clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be +used in device tree sources. + +Example: Clock controller node: + + clkc: clock-controller@c883c000 { + #clock-cells = <1>; + compatible = "amlogic,gxbb-clkc"; + reg = <0x0 0xc883c000 0x0 0x3db>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clkc CLKID_CLK81>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt index ce5a7476f05d..f1bd53f79d91 100644 --- a/Documentation/devicetree/bindings/clock/clps711x-clock.txt +++ b/Documentation/devicetree/bindings/clock/clps711x-clock.txt @@ -1,7 +1,7 @@ * Clock bindings for the Cirrus Logic CLPS711X CPUs Required properties: -- compatible : Shall contain "cirrus,clps711x-clk". +- compatible : Shall contain "cirrus,ep7209-clk". - reg : Address of the internal register set. - startup-frequency: Factory set CPU startup frequency in HZ. - #clock-cells : Should be <1>. @@ -13,7 +13,7 @@ for the full list of CLPS711X clock IDs. Example: clks: clks@80000000 { #clock-cells = <1>; - compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk"; + compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk"; reg = <0x80000000 0xc000>; startup-frequency = <73728000>; }; diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt index 1bae8527eb9b..189467a7188a 100644 --- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt @@ -14,6 +14,10 @@ Required properties: Optional properties: - clock-output-names : From common clock binding. +Some clocks that require special treatments are also handled by that +driver, with the compatibles: + - allwinner,sun4i-a10-pll3-2x-clk + Example: clock { compatible = "fixed-factor-clock"; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index fefb8023020f..394d725ac7e0 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -13,7 +13,8 @@ They provide the following functionalities: Required Properties: - compatible: Must be one of: - - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC + - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) + - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) - reg: Base address and length of the memory resource used by the CPG/MSSR block @@ -21,8 +22,8 @@ Required Properties: - clocks: References to external parent clocks, one entry for each entry in clock-names - clock-names: List of external parent clock names. Valid names are: - - "extal" (r8a7795) - - "extalr" (r8a7795) + - "extal" (r8a7795, r8a7796) + - "extalr" (r8a7795, r8a7796) - #clock-cells: Must be 2 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 16ed18155160..da578ebdda28 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt @@ -17,6 +17,7 @@ Required Properties: - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks + - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index 2a9a8edc8f35..f8c05bb4116e 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: Must be one of - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG + - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG and "renesas,rcar-gen2-cpg-clocks" as a fallback. diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt new file mode 100644 index 000000000000..cb91507ffb1e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -0,0 +1,24 @@ +Allwinner Clock Control Unit Binding +------------------------------------ + +Required properties : +- compatible: must contain one of the following compatible: + - "allwinner,sun8i-h3-ccu" + +- reg: Must contain the registers base address and length +- clocks: phandle to the oscillators feeding the CCU. Two are needed: + - "hosc": the high frequency oscillator (usually at 24MHz) + - "losc": the low frequency oscillator (usually at 32kHz) +- clock-names: Must contain the clock names described just above +- #clock-cells : must contain 1 +- #reset-cells : must contain 1 + +Example: +ccu: clock@01c20000 { + compatible = "allwinner,sun8i-h3-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt new file mode 100644 index 000000000000..2f7870983ef1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/arm,malidp.txt @@ -0,0 +1,65 @@ +ARM Mali-DP + +The following bindings apply to a family of Display Processors sold as +licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and +DP650 processors that offer multiple composition layers, support for +rotation and scaling output. + +Required properties: + - compatible: should be one of + "arm,mali-dp500" + "arm,mali-dp550" + "arm,mali-dp650" + depending on the particular implementation present in the hardware + - reg: Physical base address and size of the block of registers used by + the processor. + - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt, + interrupt client nodes. + - interrupt-names: name of the engine inside the processor that will + use the corresponding interrupt. Should be one of "DE" or "SE". + - clocks: A list of phandle + clock-specifier pairs, one for each entry + in 'clock-names' + - clock-names: A list of clock names. It should contain: + - "pclk": for the APB interface clock + - "aclk": for the AXI interface clock + - "mclk": for the main processor clock + - "pxlclk": for the pixel clock feeding the output PLL of the processor. + - arm,malidp-output-port-lines: Array of u8 values describing the number + of output lines per channel (R, G and B). + +Required sub-nodes: + - port: The Mali DP connection to an encoder input port. The connection + is modelled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt + +Optional properties: + - memory-region: phandle to a node describing memory (see + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) + to be used for the framebuffer; if not present, the framebuffer may + be located anywhere in memory. + + +Example: + +/ { + ... + + dp0: malidp@6f200000 { + compatible = "arm,mali-dp650"; + reg = <0 0x6f200000 0 0x20000>; + memory-region = <&display_reserved>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>, + <0 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DE", "SE"; + clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; + clock-names = "pxlclk", "mclk", "aclk", "pclk"; + arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + port { + dp0_output: endpoint { + remote-endpoint = <&tda998x_2_input>; + }; + }; + }; + + ... +}; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index 96c25ee01501..6532a59c9b43 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,13 +1,19 @@ -Analog Device ADV7511(W)/13 HDMI Encoders +Analog Device ADV7511(W)/13/33 HDMI Encoders ----------------------------------------- -The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters +The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. +S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while +the others support RGB interface. Required properties: -- compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513" +- compatible: Should be one of: + "adi,adv7511" + "adi,adv7511w" + "adi,adv7513" + "adi,adv7533" + - reg: I2C slave address The ADV7511 supports a large number of input data formats that differ by their @@ -32,6 +38,11 @@ The following input format properties are required except in "rgb 1x" and - adi,input-justification: The input bit justification ("left", "evenly", "right"). +The following properties are required for ADV7533: + +- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should + be one of 1, 2, 3 or 4. + Optional properties: - interrupts: Specifier for the ADV7511 interrupt @@ -42,13 +53,18 @@ Optional properties: - adi,embedded-sync: The input uses synchronization signals embedded in the data stream (similar to BT.656). Defaults to separate H/V synchronization signals. +- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing + generator. The chip will rely on the sync signals in the DSI data lanes, + rather than generate its own timings for HDMI output. Required nodes: The ADV7511 has two video ports. Their connections are modelled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. -- Video port 0 for the RGB or YUV input +- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the + remote endpoint phandle should be a reference to a valid mipi_dsi_host device + node. - Video port 1 for the HDMI output diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt index 4f2ba8c13d92..4a0f4f7682ad 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt +++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt @@ -5,6 +5,7 @@ Required properties for dp-controller: platform specific such as: * "samsung,exynos5-dp" * "rockchip,rk3288-dp" + * "rockchip,rk3399-edp" -reg: physical base address of the controller and length of memory mapped region. diff --git a/Documentation/devicetree/bindings/display/bridge/sii902x.txt b/Documentation/devicetree/bindings/display/bridge/sii902x.txt new file mode 100644 index 000000000000..56a3e68ccb80 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sii902x.txt @@ -0,0 +1,35 @@ +sii902x HDMI bridge bindings + +Required properties: + - compatible: "sil,sii9022" + - reg: i2c address of the bridge + +Optional properties: + - interrupts-extended or interrupt-parent + interrupts: describe + the interrupt line used to inform the host about hotplug events. + - reset-gpios: OF device-tree gpio specification for RST_N pin. + +Optional subnodes: + - video input: this subnode can contain a video input port node + to connect the bridge to a display controller output (See this + documentation [1]). + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + hdmi-bridge@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&pioA 1 0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dc_out>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt new file mode 100644 index 000000000000..e3f6aa6a214d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt @@ -0,0 +1,53 @@ +Toshiba TC358767 eDP bridge bindings + +Required properties: + - compatible: "toshiba,tc358767" + - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins + - clock-names: should be "ref" + - clocks: OF device-tree clock specification for refclk input. The reference + clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. + +Optional properties: + - shutdown-gpios: OF device-tree gpio specification for SD pin + (active high shutdown input) + - reset-gpios: OF device-tree gpio specification for RSTX pin + (active low system reset) + - ports: the ports node can contain video interface port nodes to connect + to a DPI/DSI source and to an eDP/DP sink according to [1][2]: + - port@0: DSI input port + - port@1: DPI input port + - port@2: eDP/DP output port + +[1]: Documentation/devicetree/bindings/graph.txt +[2]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + edp-bridge@68 { + compatible = "toshiba,tc358767"; + reg = <0x68>; + shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + clock-names = "ref"; + clocks = <&edp_refclk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@2 { + reg = <2>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt index d685be898d0c..e9c65746e2f1 100644 --- a/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt +++ b/Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt @@ -1,7 +1,7 @@ * Currus Logic CLPS711X Framebuffer Required properties: -- compatible: Shall contain "cirrus,clps711x-fb". +- compatible: Shall contain "cirrus,ep7209-fb". - reg : Physical base address and length of the controller's registers + location and size of the framebuffer memory. - clocks : phandle + clock specifier pair of the FB reference clock. @@ -18,7 +18,7 @@ Optional properties: Example: fb: fb@800002c0 { - compatible = "cirrus,ep7312-fb", "cirrus,clps711x-fb"; + compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb"; reg = <0x800002c0 0xd44>, <0x60000000 0xc000>; clocks = <&clks 2>; lcd-supply = <®5v0>; diff --git a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt index acd5668b1ce1..508aee461e0d 100644 --- a/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt +++ b/Documentation/devicetree/bindings/display/connector/hdmi-connector.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - label: a symbolic name for the connector - hpd-gpios: HPD GPIO number +- ddc-i2c-bus: phandle link to the I2C controller used for DDC EDID probing Required nodes: - Video port for HDMI input diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt index ae55cde1b69e..63ec2a624aa9 100644 --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt @@ -12,7 +12,7 @@ Required properties: - clock-names: Should be "dcu" and "pix" See ../clocks/clock-bindings.txt for details. - big-endian Boolean property, LS1021A DCU registers are big-endian. -- fsl,panel: The phandle to panel node. +- port Video port for the panel output Optional properties: - fsl,tcon: The phandle to the timing controller node. @@ -24,6 +24,11 @@ dcu: dcu@2ce0000 { clocks = <&platform_clk 0>, <&platform_clk 0>; clock-names = "dcu", "pix"; big-endian; - fsl,panel = <&panel>; fsl,tcon = <&tcon>; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_out>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt new file mode 100644 index 000000000000..7b124242b0c5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -0,0 +1,148 @@ +Mediatek HDMI Encoder +===================== + +The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from +its parallel input. + +Required properties: +- compatible: Should be "mediatek,<chip>-hdmi". +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clocks + See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "pixel", "pll", "bclk", and "spdif". +- phys: phandle link to the HDMI PHY node. + See Documentation/devicetree/bindings/phy/phy-bindings.txt for details. +- phy-names: must contain "hdmi" +- mediatek,syscon-hdmi: phandle link and register offset to the system + configuration registers. For mt8173 this must be offset 0x900 into the + MMSYS_CONFIG region: <&mmsys 0x900>. +- ports: A node containing input and output port nodes with endpoint + definitions as documented in Documentation/devicetree/bindings/graph.txt. +- port@0: The input port in the ports node should be connected to a DPI output + port. +- port@1: The output port in the ports node should be connected to the input + port of a connector node that contains a ddc-i2c-bus property, or to the + input port of an attached bridge chip, such as a SlimPort transmitter. + +HDMI CEC +======== + +The HDMI CEC controller handles hotplug detection and CEC communication. + +Required properties: +- compatible: Should be "mediatek,<chip>-cec" +- reg: Physical base address and length of the controller's registers +- interrupts: The interrupt signal from the function block. +- clocks: device clock + +HDMI DDC +======== + +The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. +The Mediatek's I2C controller is used to interface with I2C devices. + +Required properties: +- compatible: Should be "mediatek,<chip>-hdmi-ddc" +- reg: Physical base address and length of the controller's registers +- clocks: device clock +- clock-names: Should be "ddc-i2c". + +HDMI PHY +======== + +The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel +output and drives the HDMI pads. + +Required properties: +- compatible: "mediatek,<chip>-hdmi-phy" +- reg: Physical base address and length of the module's registers +- clocks: PLL reference clock +- clock-names: must contain "pll_ref" +- clock-output-names: must be "hdmitx_dig_cts" on mt8173 +- #phy-cells: must be <0> +- #clock-cells: must be <0> + +Optional properties: +- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa +- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c + +Example: + +cec: cec@10013000 { + compatible = "mediatek,mt8173-cec"; + reg = <0 0x10013000 0 0xbc>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CEC>; +}; + +hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt8173-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + #clock-cells = <0>; + #phy-cells = <0>; +}; + +hdmi_ddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + reg = <0 0x11012000 0 0x1c>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_I2C5>; + clock-names = "ddc-i2c"; +}; + +hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0 0x14025000 0 0x400>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; + assigned-clock-parents = <&hdmi_phy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; +}; + +connector { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index f5948c48b9a2..6b1cab17f52d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -11,8 +11,7 @@ Required properties: be 0 or 1, since we have 2 DSI controllers at most for now. - interrupts: The interrupt signal from the DSI block. - power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clocks: Phandles to device clocks. - clock-names: the following clocks are required: * "mdp_core_clk" * "iface_clk" @@ -23,16 +22,21 @@ Required properties: * "core_clk" For DSIv2, we need an additional clock: * "src_clk" +- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. - vdd-supply: phandle to vdd regulator device node - vddio-supply: phandle to vdd-io regulator device node - vdda-supply: phandle to vdda regulator device node -- qcom,dsi-phy: phandle to DSI PHY device node +- phys: phandle to DSI PHY device node +- phy-names: the name of the corresponding PHY device - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) +- ports: Contains 2 DSI controller ports as child nodes. Each port contains + an endpoint subnode as defined in [2] and [3]. Optional properties: - panel@0: Node of panel connected to this DSI controller. - See files in Documentation/devicetree/bindings/display/panel/ for each supported - panel. + See files in [4] for each supported panel. - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is driving a panel which needs 2 DSI links. - qcom,master-dsi: Boolean value indicating if the DSI controller is driving @@ -44,34 +48,38 @@ Optional properties: - pinctrl-names: the pin control state names; should contain "default" - pinctrl-0: the default pinctrl state (active) - pinctrl-n: the "sleep" pinctrl state -- port: DSI controller output port, containing one endpoint subnode. +- ports: contains DSI controller input and output ports as children, each + containing one endpoint subnode. DSI Endpoint properties: - - remote-endpoint: set to phandle of the connected panel's endpoint. - See Documentation/devicetree/bindings/graph.txt for device graph info. - - qcom,data-lane-map: this describes how the logical DSI lanes are mapped - to the physical lanes on the given platform. The value contained in - index n describes what logical data lane is mapped to the physical data - lane n (DATAn, where n lies between 0 and 3). + - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's + input endpoint. For port@1, set to the MDP interface output. See [2] for + device graph info. + + - data-lanes: this describes how the physical DSI data lanes are mapped + to the logical lanes on the given platform. The value contained in + index n describes what physical lane is mapped to the logical lane n + (DATAn, where n lies between 0 and 3). The clock lane position is fixed + and can't be changed. Hence, they aren't a part of the DT bindings. See + [3] for more info on the data-lanes property. For example: - qcom,data-lane-map = <3 0 1 2>; + data-lanes = <3 0 1 2>; - The above mapping describes that the logical data lane DATA3 is mapped to - the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1 - to phys DATA2 and logic DATA2 to phys DATA3. + The above mapping describes that the logical data lane DATA0 is mapped to + the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 + to phys DATA1 and logic DATA3 to phys DATA2. There are only a limited number of physical to logical mappings possible: - - "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3; - "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; - "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3; - "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3; - "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3; - "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3; - "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3; - "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3; + <0 1 2 3> + <1 2 3 0> + <2 3 0 1> + <3 0 1 2> + <0 3 2 1> + <1 0 3 2> + <2 1 0 3> + <3 2 1 0> DSI PHY: Required properties: @@ -86,11 +94,12 @@ Required properties: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should be 0 or 1, since we have 2 DSI PHYs at most for now. - power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details. +- clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface_clk" - vddio-supply: phandle to vdd-io regulator device node @@ -99,11 +108,16 @@ Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY regulator is wanted. +[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt +[2] Documentation/devicetree/bindings/graph.txt +[3] Documentation/devicetree/bindings/media/video-interfaces.txt +[4] Documentation/devicetree/bindings/display/panel/ + Example: - mdss_dsi0: qcom,mdss_dsi@fd922800 { + dsi0: dsi@fd922800 { compatible = "qcom,mdss-dsi-ctrl"; qcom,dsi-host-index = <0>; - interrupt-parent = <&mdss_mdp>; + interrupt-parent = <&mdp>; interrupts = <4 0>; reg-names = "dsi_ctrl"; reg = <0xfd922800 0x200>; @@ -124,19 +138,48 @@ Example: <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + vdda-supply = <&pma8084_l2>; vdd-supply = <&pma8084_l22>; vddio-supply = <&pma8084_l12>; - qcom,dsi-phy = <&mdss_dsi_phy0>; + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; qcom,dual-dsi-mode; qcom,master-dsi; qcom,sync-dual-dsi; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_dsi_active>; - pinctrl-1 = <&mdss_dsi_suspend>; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; panel: panel@0 { compatible = "sharp,lq101r1sx01"; @@ -152,16 +195,9 @@ Example: }; }; }; - - port { - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - lanes = <0 1 2 3>; - }; - }; }; - mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 { + dsi_phy0: dsi-phy@fd922a00 { compatible = "qcom,dsi-phy-28nm-hpm"; qcom,dsi-phy-index = <0>; reg-names = @@ -173,6 +209,7 @@ Example: <0xfd922d80 0x7b>; clock-names = "iface_clk"; clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; vddio-supply = <&pma8084_l12>; qcom,dsi-phy-regulator-ldo-mode; diff --git a/Documentation/devicetree/bindings/display/msm/mdp.txt b/Documentation/devicetree/bindings/display/msm/mdp.txt deleted file mode 100644 index a214f6cd0363..000000000000 --- a/Documentation/devicetree/bindings/display/msm/mdp.txt +++ /dev/null @@ -1,59 +0,0 @@ -Qualcomm adreno/snapdragon display controller - -Required properties: -- compatible: - * "qcom,mdp4" - mdp4 - * "qcom,mdp5" - mdp5 -- reg: Physical base address and length of the controller's registers. -- interrupts: The interrupt signal from the display controller. -- connectors: array of phandles for output device(s) -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - For MDP4: - * "core_clk" - * "iface_clk" - * "lut_clk" - * "src_clk" - * "hdmi_clk" - * "mdp_clk" - For MDP5: - * "bus_clk" - * "iface_clk" - * "core_clk_src" - * "core_clk" - * "lut_clk" (some MDP5 versions may not need this) - * "vsync_clk" - -Optional properties: -- gpus: phandle for gpu device -- clock-names: the following clocks are optional: - * "lut_clk" - -Example: - -/ { - ... - - mdp: qcom,mdp@5100000 { - compatible = "qcom,mdp4"; - reg = <0x05100000 0xf0000>; - interrupts = <GIC_SPI 75 0>; - connectors = <&hdmi>; - gpus = <&gpu>; - clock-names = - "core_clk", - "iface_clk", - "lut_clk", - "src_clk", - "hdmi_clk", - "mdp_clk"; - clocks = - <&mmcc MDP_SRC>, - <&mmcc MDP_AHB_CLK>, - <&mmcc MDP_LUT_CLK>, - <&mmcc TV_SRC>, - <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt new file mode 100644 index 000000000000..3c341a15ccdc --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -0,0 +1,112 @@ +Qualcomm adreno/snapdragon MDP4 display controller + +Description: + +This is the bindings documentation for the MDP4 display controller found in +SoCs like MSM8960, APQ8064 and MSM8660. + +Required properties: +- compatible: + * "qcom,mdp4" - mdp4 +- reg: Physical base address and length of the controller's registers. +- interrupts: The interrupt signal from the display controller. +- clocks: device clocks + See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. + * "core_clk" + * "iface_clk" + * "bus_clk" + * "lut_clk" + * "hdmi_clk" + * "tv_clk" +- ports: contains the list of output ports from MDP. These connect to interfaces + that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a + special case since it is a part of the MDP block itself). + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + The output port mappings are: + Port 0 -> LCDC/LVDS + Port 1 -> DSI1 Cmd/Video + Port 2 -> DSI2 Cmd/Video + Port 3 -> DTV + +Optional properties: +- clock-names: the following clocks are optional: + * "lut_clk" + +Example: + +/ { + ... + + hdmi: hdmi@4a00000 { + ... + ports { + ... + port@0 { + reg = <0>; + hdmi_in: endpoint { + remote-endpoint = <&mdp_dtv_out>; + }; + }; + ... + }; + ... + }; + + ... + + mdp: mdp@5100000 { + compatible = "qcom,mdp4"; + reg = <0x05100000 0xf0000>; + interrupts = <GIC_SPI 75 0>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "hdmi_clk", + "tv_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_AXI_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp_lvds_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + mdp_dsi1_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + mdp_dsi2_out: endpoint { + }; + }; + + port@3 { + reg = <3>; + mdp_dtv_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt new file mode 100644 index 000000000000..30c11ea83754 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -0,0 +1,160 @@ +Qualcomm adreno/snapdragon MDP5 display controller + +Description: + +This is the bindings documentation for the Mobile Display Subsytem(MDSS) that +encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. + +MDSS: +Required properties: +- compatible: + * "qcom,mdss" - MDSS +- reg: Physical base address and length of the controller's registers. +- reg-names: The names of register regions. The following regions are required: + * "mdss_phys" + * "vbif_phys" +- interrupts: The interrupt signal from MDSS. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an interrupt + source, should be 1. +- power-domains: a power domain consumer specifier according to + Documentation/devicetree/bindings/power/power_domain.txt +- clocks: device clocks. See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. + * "iface_clk" + * "bus_clk" + * "vsync_clk" +- #address-cells: number of address cells for the MDSS children. Should be 1. +- #size-cells: Should be 1. +- ranges: parent bus address space is the same as the child bus address space. + +Optional properties: +- clock-names: the following clocks are optional: + * "lut_clk" + +MDP5: +Required properties: +- compatible: + * "qcom,mdp5" - MDP5 +- reg: Physical base address and length of the controller's registers. +- reg-names: The names of register regions. The following regions are required: + * "mdp_phys" +- interrupts: Interrupt line from MDP5 to MDSS interrupt controller. +- interrupt-parent: phandle to the MDSS block + through MDP block +- clocks: device clocks. See ../clocks/clock-bindings.txt for details. +- clock-names: the following clocks are required. +- * "bus_clk" +- * "iface_clk" +- * "core_clk" +- * "vsync_clk" +- ports: contains the list of output ports from MDP. These connect to interfaces + that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a + special case since it is a part of the MDP block itself). + + Each output port contains an endpoint that describes how it is connected to an + external interface. These are described by the standard properties documented + here: + Documentation/devicetree/bindings/graph.txt + Documentation/devicetree/bindings/media/video-interfaces.txt + + The availability of output ports can vary across SoC revisions: + + For MSM8974 and APQ8084: + Port 0 -> MDP_INTF0 (eDP) + Port 1 -> MDP_INTF1 (DSI1) + Port 2 -> MDP_INTF2 (DSI2) + Port 3 -> MDP_INTF3 (HDMI) + + For MSM8916: + Port 0 -> MDP_INTF1 (DSI1) + + For MSM8994 and MSM8996: + Port 0 -> MDP_INTF1 (DSI1) + Port 1 -> MDP_INTF2 (DSI2) + Port 2 -> MDP_INTF3 (HDMI) + +Optional properties: +- clock-names: the following clocks are optional: + * "lut_clk" + +Example: + +/ { + ... + + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "vsync_clk" + + interrupts = <0 72 0>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk", + "vsync_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + ... + ports { + ... + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + ... + }; + ... + }; + + dsi_phy0: dsi-phy@1a98300 { + ... + }; + }; +}; diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt b/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt new file mode 100644 index 000000000000..b9877acad012 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lg,lp079qx1-sp0v.txt @@ -0,0 +1,7 @@ +LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lp079qx1-sp0v" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt b/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt new file mode 100644 index 000000000000..42141516f078 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/lg,lp097qx1-spa1.txt @@ -0,0 +1,7 @@ +LG 9.7" (2048x1536 pixels) TFT LCD panel + +Required properties: +- compatible: should be "lg,lp097qx1-spa1" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt index 216c894d4f99..b52ac52757df 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-dpi.txt +++ b/Documentation/devicetree/bindings/display/panel/panel-dpi.txt @@ -7,6 +7,8 @@ Required properties: Optional properties: - label: a symbolic name for the panel - enable-gpios: panel enable gpio +- reset-gpios: GPIO to control the RESET pin +- vcc-supply: phandle of regulator that will be used to enable power to the display Required nodes: - "panel-timing" containing video timings diff --git a/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt b/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt new file mode 100644 index 000000000000..dba298b43b24 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,lsn122dl01-c01.txt @@ -0,0 +1,7 @@ +Samsung 12.2" (2560x1600 pixels) TFT LCD panel + +Required properties: +- compatible: should be "samsung,lsn122dl01-c01" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt new file mode 100644 index 000000000000..4aff25b8dfe6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sharp,lq101k1ly04.txt @@ -0,0 +1,7 @@ +Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel + +Required properties: +- compatible: should be "sharp,lq101k1ly04" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt b/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt new file mode 100644 index 000000000000..bcb0e8a29f71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/sharp,lq123p1jx31.txt @@ -0,0 +1,7 @@ +Sharp 12.3" (2400x1600 pixels) TFT LCD panel + +Required properties: +- compatible: should be "sharp,lq123p1jx31" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt b/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt new file mode 100644 index 000000000000..1e87fe6078af --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/starry,kr122ea0sra.txt @@ -0,0 +1,7 @@ +Starry 12.2" (1920x1200 pixels) TFT LCD panel + +Required properties: +- compatible: should be "starry,kr122ea0sra" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index e832ff98fd61..01cced1c2a18 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port ================================ Required properties: -- compatible: "rockchip,rk3288-edp"; +- compatible: "rockchip,rk3288-dp", + "rockchip,rk3399-edp"; - reg: physical base address of the controller and length @@ -27,6 +28,12 @@ Required properties: Port 0: contained 2 endpoints, connecting to the output of vop. Port 1: contained 1 endpoint, connecting to the input of panel. +Optional property for different chips: +- clocks: from common clock binding: handle to grf_vio clock. + +- clock-names: from common clock binding: + Required elements: "grf" + For the below properties, please refer to Analogix DP binding document: * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt - phys (required) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index a3bd8c050c4e..0fad7ed2ea19 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -208,6 +208,7 @@ of the following host1x client modules: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - sor: clock input for the SOR hardware + - source: source clock for the SOR clock - parent: input for the pixel clock - dp: reference clock for the SOR clock - safe: safe reference for the SOR clock during power up @@ -226,9 +227,9 @@ of the following host1x client modules: - nvidia,dpaux: phandle to a DispayPort AUX interface - dpaux: DisplayPort AUX interface - - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise, - must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where - <chip> is tegra132. + - compatible : Should contain one of the following: + - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 + - "nvidia,tegra210-dpaux": for Tegra210 - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt outputs from the controller. - clocks: Must contain an entry for each entry in clock-names. @@ -241,6 +242,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - dpaux - vdd-supply: phandle of a supply that powers the DisplayPort link + - i2c-bus: Subnode where I2C slave devices are listed. This subnode + must be always present. If there are no I2C slave devices, an empty + node should be added. See ../../i2c/i2c.txt for more information. + + See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information + regarding the DPAUX pad controller bindings. Example: diff --git a/Documentation/devicetree/bindings/dma/mv-xor-v2.txt b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt new file mode 100644 index 000000000000..217a90eaabe7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mv-xor-v2.txt @@ -0,0 +1,24 @@ +* Marvell XOR v2 engines + +Required properties: +- compatible: one of the following values: + "marvell,armada-7k-xor" + "marvell,xor-v2" +- reg: Should contain registers location and length (two sets) + the first set is the DMA registers + the second set is the global registers +- msi-parent: Phandle to the MSI-capable interrupt controller used for + interrupts. + +Optional properties: +- clocks: Optional reference to the clock used by the XOR engine. + +Example: + + xor0@400000 { + compatible = "marvell,xor-v2"; + reg = <0x400000 0x1000>, + <0x410000 0x1000>; + msi-parent = <&gic_v2m0>; + dma-coherent; + }; diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 079b42a81d7c..18090e7226b4 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -15,7 +15,7 @@ Required properties: - reg: Memory map of eDMA CC - reg-names: "edma3_cc" - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. -- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint" +- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" - ti,tptcs: List of TPTCs associated with the eDMA in the following form: <&tptc_phandle TC_priority_number>. The highest priority is 0. @@ -48,7 +48,7 @@ edma: edma@49000000 { reg = <0x49000000 0x10000>; reg-names = "edma3_cc"; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint"; + interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; dma-requests = <64>; #dma-cells = <2>; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 3cf0072d3141..a2b8bfaec43c 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -1,46 +1,96 @@ +Xilinx AXI VDMA engine, it does transfers between memory and video devices. +It can be configured to have one channel or two channels. If configured +as two channels, one is to transmit to the video device and another is +to receive from the video device. + Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream target devices. It can be configured to have one channel or two channels. If configured as two channels, one is to transmit to the device and another is to receive from the device. +Xilinx AXI CDMA engine, it does transfers between memory-mapped source +address and a memory-mapped destination address. + Required properties: -- compatible: Should be "xlnx,axi-dma-1.00.a" +- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or + "xlnx,axi-cdma-1.00.a"" - #dma-cells: Should be <1>, see "dmas" property below -- reg: Should contain DMA registers location and length. +- reg: Should contain VDMA registers location and length. +- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). +- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. - dma-channel child node: Should have at least one channel and can have up to two channels per device. This node specifies the properties of each DMA channel (see child node properties below). +- clocks: Input clock specifier. Refer to common clock bindings. +- clock-names: List of input clocks + For VDMA: + Required elements: "s_axi_lite_aclk" + Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", + "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" + For CDMA: + Required elements: "s_axi_lite_aclk", "m_axi_aclk" + FOR AXIDMA: + Required elements: "s_axi_lite_aclk" + Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", + "m_axi_sg_aclk" + +Required properties for VDMA: +- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. Optional properties: -- xlnx,include-sg: Tells whether configured for Scatter-mode in +- xlnx,include-sg: Tells configured for Scatter-mode in the hardware. +Optional properties for AXI DMA: +- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. +Optional properties for VDMA: +- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. + It takes following values: + {1}, flush both channels + {2}, flush mm2s channel + {3}, flush s2mm channel Required child node properties: -- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or +- compatible: + For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or + "xlnx,axi-vdma-s2mm-channel". + For CDMA: It should be "xlnx,axi-cdma-channel". + For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or "xlnx,axi-dma-s2mm-channel". -- interrupts: Should contain per channel DMA interrupts. +- interrupts: Should contain per channel VDMA interrupts. - xlnx,datawidth: Should contain the stream data width, take values {32,64...1024}. -Option child node properties: -- xlnx,include-dre: Tells whether hardware is configured for Data +Optional child node properties: +- xlnx,include-dre: Tells hardware is configured for Data Realignment Engine. +Optional child node properties for VDMA: +- xlnx,genlock-mode: Tells Genlock synchronization is + enabled/disabled in hardware. +Optional child node properties for AXI DMA: +-dma-channels: Number of dma channels in child node. Example: ++++++++ -axi_dma_0: axidma@40400000 { - compatible = "xlnx,axi-dma-1.00.a"; +axi_vdma_0: axivdma@40030000 { + compatible = "xlnx,axi-vdma-1.00.a"; #dma_cells = <1>; - reg = < 0x40400000 0x10000 >; - dma-channel@40400000 { - compatible = "xlnx,axi-dma-mm2s-channel"; - interrupts = < 0 59 4 >; + reg = < 0x40030000 0x10000 >; + dma-ranges = <0x00000000 0x00000000 0x40000000>; + xlnx,num-fstores = <0x8>; + xlnx,flush-fsync = <0x1>; + xlnx,addrwidth = <0x20>; + clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; + clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", + "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; + dma-channel@40030000 { + compatible = "xlnx,axi-vdma-mm2s-channel"; + interrupts = < 0 54 4 >; xlnx,datawidth = <0x40>; } ; - dma-channel@40400030 { - compatible = "xlnx,axi-dma-s2mm-channel"; - interrupts = < 0 58 4 >; + dma-channel@40030030 { + compatible = "xlnx,axi-vdma-s2mm-channel"; + interrupts = < 0 53 4 >; xlnx,datawidth = <0x40>; } ; } ; @@ -49,7 +99,7 @@ axi_dma_0: axidma@40400000 { * DMA client Required properties: -- dmas: a list of <[DMA device phandle] [Channel ID]> pairs, +- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx channel. - dma-names: a list of DMA channel names, one per "dmas" entry @@ -57,9 +107,9 @@ Required properties: Example: ++++++++ -dmatest_0: dmatest@0 { - compatible ="xlnx,axi-dma-test-1.00.a"; - dmas = <&axi_dma_0 0 - &axi_dma_0 1>; - dma-names = "dma0", "dma1"; +vdmatest_0: vdmatest@0 { + compatible ="xlnx,axi-vdma-test-1.00.a"; + dmas = <&axi_vdma_0 0 + &axi_vdma_0 1>; + dma-names = "vdma0", "vdma1"; } ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt deleted file mode 100644 index a1f2683c49bf..000000000000 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt +++ /dev/null @@ -1,107 +0,0 @@ -Xilinx AXI VDMA engine, it does transfers between memory and video devices. -It can be configured to have one channel or two channels. If configured -as two channels, one is to transmit to the video device and another is -to receive from the video device. - -Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream -target devices. It can be configured to have one channel or two channels. -If configured as two channels, one is to transmit to the device and another -is to receive from the device. - -Xilinx AXI CDMA engine, it does transfers between memory-mapped source -address and a memory-mapped destination address. - -Required properties: -- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or - "xlnx,axi-cdma-1.00.a"" -- #dma-cells: Should be <1>, see "dmas" property below -- reg: Should contain VDMA registers location and length. -- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). -- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. -- dma-channel child node: Should have at least one channel and can have up to - two channels per device. This node specifies the properties of each - DMA channel (see child node properties below). -- clocks: Input clock specifier. Refer to common clock bindings. -- clock-names: List of input clocks - For VDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" - For CDMA: - Required elements: "s_axi_lite_aclk", "m_axi_aclk" - FOR AXIDMA: - Required elements: "s_axi_lite_aclk" - Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axi_sg_aclk" - -Required properties for VDMA: -- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. - -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. -Optional properties for VDMA: -- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. - It takes following values: - {1}, flush both channels - {2}, flush mm2s channel - {3}, flush s2mm channel - -Required child node properties: -- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or - "xlnx,axi-vdma-s2mm-channel". -- interrupts: Should contain per channel VDMA interrupts. -- xlnx,datawidth: Should contain the stream data width, take values - {32,64...1024}. - -Optional child node properties: -- xlnx,include-dre: Tells hardware is configured for Data - Realignment Engine. -Optional child node properties for VDMA: -- xlnx,genlock-mode: Tells Genlock synchronization is - enabled/disabled in hardware. - -Example: -++++++++ - -axi_vdma_0: axivdma@40030000 { - compatible = "xlnx,axi-vdma-1.00.a"; - #dma_cells = <1>; - reg = < 0x40030000 0x10000 >; - dma-ranges = <0x00000000 0x00000000 0x40000000>; - xlnx,num-fstores = <0x8>; - xlnx,flush-fsync = <0x1>; - xlnx,addrwidth = <0x20>; - clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; - clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; - dma-channel@40030000 { - compatible = "xlnx,axi-vdma-mm2s-channel"; - interrupts = < 0 54 4 >; - xlnx,datawidth = <0x40>; - } ; - dma-channel@40030030 { - compatible = "xlnx,axi-vdma-s2mm-channel"; - interrupts = < 0 53 4 >; - xlnx,datawidth = <0x40>; - } ; -} ; - - -* DMA client - -Required properties: -- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, - where Channel ID is '0' for write/tx and '1' for read/rx - channel. -- dma-names: a list of DMA channel names, one per "dmas" entry - -Example: -++++++++ - -vdmatest_0: vdmatest@0 { - compatible ="xlnx,axi-vdma-test-1.00.a"; - dmas = <&axi_vdma_0 0 - &axi_vdma_0 1>; - dma-names = "vdma0", "vdma1"; -} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt new file mode 100644 index 000000000000..a784cdd94790 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt @@ -0,0 +1,27 @@ +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, +memory to device and device to memory transfers. It also has flow +control and rate control support for slave/peripheral dma access. + +Required properties: +- compatible : Should be "xlnx,zynqmp-dma-1.0" +- reg : Memory map for gdma/adma module access. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt. +- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 +- clock-names : List of input clocks "clk_main", "clk_apb" + (see clock bindings for details) + +Optional properties: +- dma-coherent : Present if dma operations are coherent. + +Example: +++++++++ +fpd_dma_chan1: dma@fd500000 { + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xFD500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 117 4>; + clock-names = "clk_main", "clk_apb"; + xlnx,bus-width = <128>; + dma-coherent; +}; diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt new file mode 100644 index 000000000000..3b4436e56865 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -0,0 +1,28 @@ +QCOM Secure Channel Manager (SCM) + +Qualcomm processors include an interface to communicate to the secure firmware. +This interface allows for clients to request different types of actions. These +can include CPU power up/down, HDCP requests, loading of firmware, and other +assorted actions. + +Required properties: +- compatible: must contain one of the following: + * "qcom,scm-apq8064" for APQ8064 platforms + * "qcom,scm-msm8660" for MSM8660 platforms + * "qcom,scm-msm8690" for MSM8690 platforms + * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) +- clocks: One to three clocks may be required based on compatible. + * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" + * Core, iface, and bus clocks required for "qcom,scm" +- clock-names: Must contain "core" for the core clock, "iface" for the interface + clock and "bus" for the bus clock per the requirements of the compatible. + +Example for MSM8916: + + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 000000000000..928ed4f43907 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* Oxford Semiconductor OXNAS SoC GPIO Controller + +Please refer to gpio.txt for generic information regarding GPIO bindings. + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in <dt-bindings/gpio/gpio.h>: + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + <dt-bindings/interrupt-controller/irq.h>: + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the + gpio base and count, should be in the format of numeric-gpio-range as + specified in the gpio.txt file. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; +}; + +keys { + ... + + button-esc { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index acc5cd64711c..5c70ce9c1954 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt @@ -126,6 +126,7 @@ national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware M national,lm85 Temperature sensor with integrated fan control national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface nuvoton,npct501 i2c trusted platform module (TPM) +nuvoton,npct601 i2c trusted platform module (TPM2) nxp,pca9556 Octal SMBus and I2C registered interface nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset nxp,pcf8563 Real-time clock/calendar @@ -145,10 +146,10 @@ samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) sgx,vz89x SGX Sensortech VZ89X Sensors sii,s35390a 2-wire CMOS real-time clock skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply -st-micro,24c256 i2c serial eeprom (24cxx) -stm,m41t00 Serial Access TIMEKEEPER -stm,m41t62 Serial real-time clock (RTC) with alarm -stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS +st,24c256 i2c serial eeprom (24cxx) +st,m41t00 Serial real-time clock (RTC) +st,m41t62 Serial real-time clock (RTC) with alarm +st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface ti,ads7828 8-Channels, 12-bit ADC ti,ads7830 8-Channels, 8-bit ADC diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt index 0f813dec5e08..f65b04fb7962 100644 --- a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt @@ -59,28 +59,24 @@ adc0: adc@fffb0000 { atmel,adc-res-names = "lowres", "highres"; atmel,adc-use-res = "lowres"; - trigger@0 { - reg = <0>; + trigger0 { trigger-name = "external-rising"; trigger-value = <0x1>; trigger-external; }; - trigger@1 { - reg = <1>; + trigger1 { trigger-name = "external-falling"; trigger-value = <0x2>; trigger-external; }; - trigger@2 { - reg = <2>; + trigger2 { trigger-name = "external-any"; trigger-value = <0x3>; trigger-external; }; - trigger@3 { - reg = <3>; + trigger3 { trigger-name = "continuous"; trigger-value = <0x6>; }; diff --git a/Documentation/devicetree/bindings/input/clps711x-keypad.txt b/Documentation/devicetree/bindings/input/clps711x-keypad.txt index e68d2bbc6c07..3eed8819d05d 100644 --- a/Documentation/devicetree/bindings/input/clps711x-keypad.txt +++ b/Documentation/devicetree/bindings/input/clps711x-keypad.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X matrix keypad device tree bindings Required Properties: -- compatible: Shall contain "cirrus,clps711x-keypad". +- compatible: Shall contain "cirrus,ep7209-keypad". - row-gpios: List of GPIOs used as row lines. - poll-interval: Poll interval time in milliseconds. - linux,keymap: The definition can be found at @@ -12,7 +12,7 @@ Optional Properties: Example: keypad { - compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad"; + compatible = "cirrus,ep7312-keypad", "cirrus,ep7209-keypad"; autorepeat; poll-interval = <120>; row-gpios = <&porta 0 0>, diff --git a/Documentation/devicetree/bindings/input/rotary-encoder.txt b/Documentation/devicetree/bindings/input/rotary-encoder.txt index 6c9f0c8a846c..e85ce3dea480 100644 --- a/Documentation/devicetree/bindings/input/rotary-encoder.txt +++ b/Documentation/devicetree/bindings/input/rotary-encoder.txt @@ -20,6 +20,8 @@ Optional properties: 2: Half-period mode 4: Quarter-period mode - wakeup-source: Boolean, rotary encoder can wake up the system. +- rotary-encoder,encoding: String, the method used to encode steps. + Supported are "gray" (the default and more common) and "binary". Deprecated properties: - rotary-encoder,half-period: Makes the driver work on half-period mode. @@ -34,6 +36,7 @@ Example: compatible = "rotary-encoder"; gpios = <&gpio 19 1>, <&gpio 20 0>; /* GPIO19 is inverted */ linux,axis = <0>; /* REL_X */ + rotary-encoder,encoding = "gray"; rotary-encoder,relative-axis; }; @@ -42,5 +45,6 @@ Example: gpios = <&gpio 21 0>, <&gpio 22 0>; linux,axis = <1>; /* ABS_Y */ rotary-encoder,steps = <24>; + rotary-encoder,encoding = "binary"; rotary-encoder,rollover; }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt new file mode 100644 index 000000000000..1112e0d794e1 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt @@ -0,0 +1,36 @@ +* GSL 1680 touchscreen controller + +Required properties: +- compatible : "silead,gsl1680" +- reg : I2C slave address of the chip (0x40) +- interrupt-parent : a phandle pointing to the interrupt controller + serving the interrupt for this chip +- interrupts : interrupt specification for the gsl1680 interrupt +- power-gpios : Specification for the pin connected to the gsl1680's + shutdown input. This needs to be driven high to take the + gsl1680 out of its low power state +- touchscreen-size-x : See touchscreen.txt +- touchscreen-size-y : See touchscreen.txt + +Optional properties: +- touchscreen-inverted-x : See touchscreen.txt +- touchscreen-inverted-y : See touchscreen.txt +- touchscreen-swapped-x-y : See touchscreen.txt +- silead,max-fingers : maximum number of fingers the touchscreen can detect + +Example: + +i2c@00000000 { + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + silead,max-fingers = <5>; + }; +}; diff --git a/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt b/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt new file mode 100644 index 000000000000..d87ad14f1efe --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/sis_i2c.txt @@ -0,0 +1,33 @@ +* SiS I2C Multiple Touch Controller + +Required properties: +- compatible: must be "sis,9200-ts" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller + (see interrupt binding [0]) +- interrupts: touch controller interrupt (see interrupt + binding [0]) + +Optional properties: +- pinctrl-names: should be "default" (see pinctrl binding [1]). +- pinctrl-0: a phandle pointing to the pin settings for the + device (see pinctrl binding [1]). +- attn-gpios: the gpio pin used as attention line +- reset-gpios: the gpio pin used to reset the controller +- wakeup-source: touchscreen can be used as a wakeup source + +[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + + sis9255@5c { + compatible = "sis,9200-ts"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sis>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt index 759339c34e4f..969b4582ec60 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt @@ -2,7 +2,7 @@ Cirrus Logic CLPS711X Interrupt Controller Required properties: -- compatible: Should be "cirrus,clps711x-intc". +- compatible: Should be "cirrus,ep7209-intc". - reg: Specifies base physical address of the registers set. - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: Specifies the number of cells needed to encode an @@ -34,7 +34,7 @@ ID Name Description Example: intc: interrupt-controller { - compatible = "cirrus,clps711x-intc"; + compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; reg = <0x80000000 0x4000>; interrupt-controller; #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 8cf564d083d2..9d1d72c65489 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -9,6 +9,7 @@ Required properties: "mediatek,mt8135-sysirq" "mediatek,mt8127-sysirq" "mediatek,mt6795-sysirq" + "mediatek,mt6755-sysirq" "mediatek,mt6592-sysirq" "mediatek,mt6589-sysirq" "mediatek,mt6582-sysirq" diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index 947863acc2d4..7b94c88cf2ee 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -1,6 +1,6 @@ * ARM SMMUv3 Architecture Implementation -The SMMUv3 architecture is a significant deparature from previous +The SMMUv3 architecture is a significant departure from previous revisions, replacing the MMIO register interface with in-memory command and event queues and adding support for the ATS and PRI components of the PCIe specification. diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index cd1b1cd7b5c4..53c20cae309f 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -1,7 +1,9 @@ * Mediatek IOMMU Architecture Implementation - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which -uses the ARM Short-Descriptor translation table format for address translation. + Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and +this M4U have two generations of HW architecture. Generation one uses flat +pagetable, and only supports 4K size page mapping. Generation two uses the +ARM Short-Descriptor translation table format for address translation. About the M4U Hardware Block Diagram, please check below: @@ -36,7 +38,9 @@ in each larb. Take a example, There are many ports like MC, PP, VLD in the video decode local arbiter, all these ports are according to the video HW. Required properties: -- compatible : must be "mediatek,mt8173-m4u". +- compatible : must be one of the following string: + "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. + "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - reg : m4u register base and size. - interrupts : the interrupt of m4u. - clocks : must contain one entry for each clock-names. @@ -46,7 +50,8 @@ Required properties: according to the local arbiter index, like larb0, larb1, larb2... - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt8173-larb-port.h. + dt-binding/memory/mt2701-larb-port.h for mt2701 and + dt-binding/memory/mt8173-larb-port.h for mt8173 Example: iommu: iommu@10205000 { diff --git a/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt b/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt new file mode 100644 index 000000000000..20236385f26e --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/msm,iommu-v0.txt @@ -0,0 +1,64 @@ +* QCOM IOMMU + +The MSM IOMMU is an implementation compatible with the ARM VMSA short +descriptor page tables. It provides address translation for bus masters outside +of the CPU, each connected to the IOMMU through a port called micro-TLB. + +Required Properties: + + - compatible: Must contain "qcom,apq8064-iommu". + - reg: Base address and size of the IOMMU registers. + - interrupts: Specifiers for the MMU fault interrupts. For instances that + support secure mode two interrupts must be specified, for non-secure and + secure mode, in that order. For instances that don't support secure mode a + single interrupt must be specified. + - #iommu-cells: The number of cells needed to specify the stream id. This + is always 1. + - qcom,ncb: The total number of context banks in the IOMMU. + - clocks : List of clocks to be used during SMMU register access. See + Documentation/devicetree/bindings/clock/clock-bindings.txt + for information about the format. For each clock specified + here, there must be a corresponding entry in clock-names + (see below). + + - clock-names : List of clock names corresponding to the clocks specified in + the "clocks" property (above). + Should be "smmu_pclk" for specifying the interface clock + required for iommu's register accesses. + Should be "smmu_clk" for specifying the functional clock + required by iommu for bus accesses. + +Each bus master connected to an IOMMU must reference the IOMMU in its device +node with the following property: + + - iommus: A reference to the IOMMU in multiple cells. The first cell is a + phandle to the IOMMU and the second cell is the stream id. + A single master device can be connected to more than one iommu + and multiple contexts in each of the iommu. So multiple entries + are required to list all the iommus and the stream ids that the + master is connected to. + +Example: mdp iommu and its bus master + + mdp_port0: iommu@7500000 { + compatible = "qcom,apq8064-iommu"; + #iommu-cells = <1>; + clock-names = + "smmu_pclk", + "smmu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg = <0x07500000 0x100000>; + interrupts = + <GIC_SPI 63 0>, + <GIC_SPI 64 0>; + qcom,ncb = <2>; + }; + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp"; + ... + iommus = <&mdp_port0 0 + &mdp_port0 2>; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/lp855x.txt b/Documentation/devicetree/bindings/leds/backlight/lp855x.txt index 0a3ecbc3a1b9..88f56641fc28 100644 --- a/Documentation/devicetree/bindings/leds/backlight/lp855x.txt +++ b/Documentation/devicetree/bindings/leds/backlight/lp855x.txt @@ -13,6 +13,7 @@ Optional properties: - rom-addr: Register address of ROM area to be updated (u8) - rom-val: Register value to be updated (u8) - power-supply: Regulator which controls the 3V rail + - enable-supply: Regulator which controls the EN/VDDIO input Example: @@ -57,6 +58,7 @@ Example: backlight@2c { compatible = "ti,lp8557"; reg = <0x2c>; + enable-supply = <&backlight_vddio>; power-supply = <&backlight_vdd>; dev-ctrl = /bits/ 8 <0x41>; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt new file mode 100644 index 000000000000..411ccf421584 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt @@ -0,0 +1,23 @@ +The PDC driver manages data transfer to and from various offload engines +on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is +one device tree entry per block. + +Required properties: +- compatible : Should be "brcm,iproc-pdc-mbox". +- reg: Should contain PDC registers location and length. +- interrupts: Should contain the IRQ line for the PDC. +- #mbox-cells: 1 +- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. + +Optional properties: +- brcm,use-bcm-hdr: present if a BCM header precedes each frame. + +Example: + pdc0: iproc-pdc0@0x612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; /* one cell per mailbox channel */ + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; diff --git a/Documentation/devicetree/bindings/media/nokia,n900-ir b/Documentation/devicetree/bindings/media/nokia,n900-ir new file mode 100644 index 000000000000..13a18ce37dd1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nokia,n900-ir @@ -0,0 +1,20 @@ +Device-Tree bindings for LIRC TX driver for Nokia N900(RX51) + +Required properties: + - compatible: should be "nokia,n900-ir". + - pwms: specifies PWM used for IR signal transmission. + +Example node: + + pwm9: dmtimer-pwm@9 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer9>; + ti,clock-source = <0x00>; /* timer_sys_ck */ + #pwm-cells = <3>; + }; + + ir: n900-ir { + compatible = "nokia,n900-ir"; + + pwms = <&pwm9 0 26316 0>; /* 38000 Hz */ + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt new file mode 100644 index 000000000000..9bb5f57e2066 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt @@ -0,0 +1,136 @@ +* Device tree bindings for Atmel EBI + +The External Bus Interface (EBI) controller is a bus where you can connect +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). +The EBI provides a glue-less interface to asynchronous memories through the SMC +(Static Memory Controller). + +Required properties: + +- compatible: "atmel,at91sam9260-ebi" + "atmel,at91sam9261-ebi" + "atmel,at91sam9263-ebi0" + "atmel,at91sam9263-ebi1" + "atmel,at91sam9rl-ebi" + "atmel,at91sam9g45-ebi" + "atmel,at91sam9x5-ebi" + "atmel,sama5d3-ebi" + +- reg: Contains offset/length value for EBI memory mapping. + This property might contain several entries if the EBI + memory range is not contiguous + +- #address-cells: Must be 2. + The first cell encodes the CS. + The second cell encode the offset into the CS memory + range. + +- #size-cells: Must be set to 1. + +- ranges: Encodes CS to memory region association. + +- clocks: Clock feeding the EBI controller. + See clock-bindings.txt + +Children device nodes are representing device connected to the EBI bus. + +Required device node properties: + +- reg: Contains the chip-select id, the offset and the length + of the memory region requested by the device. + +EBI bus configuration will be defined directly in the device subnode. + +Optional EBI/SMC properties: + +- atmel,smc-bus-width: width of the asynchronous device's data bus + 8, 16 or 32. + Default to 8 when undefined. + +- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet). + Default to "select" when undefined. + +- atmel,smc-read-mode "nrd" or "ncs". + Default to "ncs" when undefined. + +- atmel,smc-write-mode "nwe" or "ncs". + Default to "ncs" when undefined. + +- atmel,smc-exnw-mode "disabled", "frozen" or "ready". + Default to "disabled" when undefined. + +- atmel,smc-page-mode enable page mode if present. The provided value + defines the page size (supported values: 4, 8, + 16 and 32). + +- atmel,smc-tdf-mode: "normal" or "optimized". When set to + "optimized" the data float time is optimized + depending on the next device being accessed + (next device setup time is subtracted to the + current device data float time). + Default to "normal" when undefined. + +If at least one atmel,smc- property is defined the following SMC timing +properties become mandatory. In the other hand, if none of the atmel,smc- +properties are specified, we assume that the EBI bus configuration will be +handled by the sub-device driver, and none of those properties should be +defined. + +All the timings are expressed in nanoseconds (see Atmel datasheet for a full +description). + +- atmel,smc-ncs-rd-setup-ns +- atmel,smc-nrd-setup-ns +- atmel,smc-ncs-wr-setup-ns +- atmel,smc-nwe-setup-ns +- atmel,smc-ncs-rd-pulse-ns +- atmel,smc-nrd-pulse-ns +- atmel,smc-ncs-wr-pulse-ns +- atmel,smc-nwe-pulse-ns +- atmel,smc-nwe-cycle-ns +- atmel,smc-nrd-cycle-ns +- atmel,smc-tdf-ns + +Example: + + ebi: ebi@10000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + atmel,matrix = <&matrix>; + reg = <0x10000000 0x10000000 + 0x40000000 0x30000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x40000000 0x10000000 + 0x2 0x0 0x50000000 0x10000000 + 0x3 0x0 0x60000000 0x10000000>; + clocks = <&mck>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr>; + + nor: flash@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x1000000>; + bank-width = <2>; + + atmel,smc-read-mode = "nrd"; + atmel,smc-write-mode = "nwe"; + atmel,smc-bus-width = <16>; + atmel,smc-ncs-rd-setup-ns = <0>; + atmel,smc-ncs-wr-setup-ns = <0>; + atmel,smc-nwe-setup-ns = <8>; + atmel,smc-nrd-setup-ns = <16>; + atmel,smc-ncs-rd-pulse-ns = <84>; + atmel,smc-ncs-wr-pulse-ns = <84>; + atmel,smc-nrd-pulse-ns = <76>; + atmel,smc-nwe-pulse-ns = <76>; + atmel,smc-nrd-cycle-ns = <107>; + atmel,smc-nwe-cycle-ns = <84>; + atmel,smc-tdf-ns = <16>; + }; + }; + diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index 06a83ceebba7..aa614b2d7cab 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -2,16 +2,31 @@ SMI (Smart Multimedia Interface) Common The hardware block diagram please check bindings/iommu/mediatek,iommu.txt +Mediatek SMI have two generations of HW architecture, mt8173 uses the second +generation of SMI HW while mt2701 uses the first generation HW of SMI. + +There's slight differences between the two SMI, for generation 2, the +register which control the iommu port is at each larb's register base. But +for generation 1, the register is at smi ao base(smi always on register +base). Besides that, the smi async clock should be prepared and enabled for +SMI generation 1 to transform the smi clock into emi clock domain, but that is +not needed for SMI generation 2. + Required properties: -- compatible : must be "mediatek,mt8173-smi-common" +- compatible : must be one of : + "mediatek,mt2701-smi-common" + "mediatek,mt8173-smi-common" - reg : the register and size of the SMI block. - power-domains : a phandle to the power domain of this local arbiter. - clocks : Must contain an entry for each entry in clock-names. -- clock-names : must contain 2 entries, as follows: +- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries + for generation 2 smi HW as follows: - "apb" : Advanced Peripheral Bus clock, It's the clock for setting the register. - "smi" : It's the clock for transfer data and command. - They may be the same if both source clocks are the same. + They may be the same if both source clocks are the same. + - "async" : asynchronous clock, it help transform the smi clock into the emi + clock domain, this clock is only needed by generation 1 smi HW. Example: smi_common: smi@14022000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt index 55ff3b7e0bb9..21277a56e94c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt @@ -3,7 +3,9 @@ SMI (Smart Multimedia Interface) Local Arbiter The hardware block diagram please check bindings/iommu/mediatek,iommu.txt Required properties: -- compatible : must be "mediatek,mt8173-smi-larb" +- compatible : must be one of : + "mediatek,mt8173-smi-larb" + "mediatek,mt2701-smi-larb" - reg : the register and size of this local arbiter. - mediatek,smi : a phandle to the smi_common node. - power-domains : a phandle to the power domain of this local arbiter. diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt index 21055e210234..c1359f4d48d7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt @@ -46,6 +46,10 @@ Required properties: 0 maps to GPMC_WAIT0 pin. - gpio-cells: Must be set to 2 +Required properties when using NAND prefetch dma: + - dmas GPMC NAND prefetch dma channel + - dma-names Must be set to "rxtx" + Timing properties for child nodes. All are optional and default to 0. - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds @@ -137,7 +141,8 @@ Example for an AM33xx board: ti,hwmods = "gpmc"; reg = <0x50000000 0x2000>; interrupts = <100>; - + dmas = <&edma 52 0>; + dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt index 1857f4a6b9a9..9554292dc6cb 100644 --- a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt +++ b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt @@ -8,10 +8,13 @@ Sub-nodes: - regulators : Contain the regulator nodes. The DA9052/53 regulators are bound using their names as listed below: - buck0 : regulator BUCK0 - buck1 : regulator BUCK1 - buck2 : regulator BUCK2 - buck3 : regulator BUCK3 + buck1 : regulator BUCK CORE + buck2 : regulator BUCK PRO + buck3 : regulator BUCK MEM + buck4 : regulator BUCK PERI + ldo1 : regulator LDO1 + ldo2 : regulator LDO2 + ldo3 : regulator LDO3 ldo4 : regulator LDO4 ldo5 : regulator LDO5 ldo6 : regulator LDO6 @@ -19,9 +22,6 @@ Sub-nodes: ldo8 : regulator LDO8 ldo9 : regulator LDO9 ldo10 : regulator LDO10 - ldo11 : regulator LDO11 - ldo12 : regulator LDO12 - ldo13 : regulator LDO13 The bindings details of individual regulator device can be found in: Documentation/devicetree/bindings/regulator/regulator.txt @@ -36,22 +36,22 @@ i2c@63fc8000 { /* I2C1 */ reg = <0x48>; regulators { - buck0 { + buck1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <2075000>; }; - buck1 { + buck2 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <2075000>; }; - buck2 { + buck3 { regulator-min-microvolt = <925000>; regulator-max-microvolt = <2500000>; }; - buck3 { + buck4 { regulator-min-microvolt = <925000>; regulator-max-microvolt = <2500000>; }; diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt index a41157b5d930..e6afdfa3543d 100644 --- a/Documentation/devicetree/bindings/mfd/twl6040.txt +++ b/Documentation/devicetree/bindings/mfd/twl6040.txt @@ -19,8 +19,8 @@ Required properties: Optional properties, nodes: - enable-active-high: To power on the twl6040 during boot. -- clocks: phandle to the clk32k clock provider -- clock-names: Must be "clk32k" +- clocks: phandle to the clk32k and/or to mclk clock provider +- clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK. Vibra functionality Required properties: diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 31b35c3a5e47..3404afa9b938 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller [4] Documentation/devicetree/bindings/phy/phy-bindings.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or - 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1' + - compatible: Compatibility string. One of: + - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY + - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY + - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY + - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY + For this device it is strongly suggested to include arasan,soc-ctl-syscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" @@ -22,6 +26,17 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Optional Properties: + - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) + used to access core corecfg registers. Offsets of registers in this + syscon are determined based on the main compatible string for the device. + - clock-output-names: If specified, this will be the name of the card clock + which will be exposed by this device. Required if #clock-cells is + specified. + - #clock-cells: If specified this should be the value <0>. With this property + in place we will export a clock representing the Card Clock. This clock + is expected to be consumed by our PHY. You must also specify + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -42,3 +57,19 @@ Example: phys = <&emmc_phy>; phy-names = "phy_arasan"; } ; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + #clock-cells = <0>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt deleted file mode 100644 index 59476fbdbfa1..000000000000 --- a/Documentation/devicetree/bindings/mmc/brcm,bcm2835-sdhci.txt +++ /dev/null @@ -1,18 +0,0 @@ -Broadcom BCM2835 SDHCI controller - -This file documents differences between the core properties described -by mmc.txt and the properties that represent the BCM2835 controller. - -Required properties: -- compatible : Should be "brcm,bcm2835-sdhci". -- clocks : The clock feeding the SDHCI controller. - -Example: - -sdhci: sdhci { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clk_mmc>; - bus-width = <4>; -}; diff --git a/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt b/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt new file mode 100644 index 000000000000..82847174c37d --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/brcm,bcm7425-sdhci.txt @@ -0,0 +1,36 @@ +* BROADCOM BRCMSTB/BMIPS SDHCI Controller + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-brcmstb driver. + +NOTE: The driver disables all UHS speed modes by default and depends +on Device Tree properties to enable them for SoC/Board combinations +that support them. + +Required properties: +- compatible: "brcm,bcm7425-sdhci" + +Refer to clocks/clock-bindings.txt for generic clock consumer properties. + +Example: + + sdhci@f03e0100 { + compatible = "brcm,bcm7425-sdhci"; + reg = <0xf03e0000 0x100>; + interrupts = <0x0 0x26 0x0>; + sdhci,auto-cmd12; + clocks = <&sw_sdio>; + sd-uhs-sdr50; + sd-uhs-ddr50; + }; + + sdhci@f03e0300 { + non-removable; + bus-width = <0x8>; + compatible = "brcm,bcm7425-sdhci"; + reg = <0xf03e0200 0x100>; + interrupts = <0x0 0x27 0x0>; + sdhci,auto-cmd12; + clocks = <sw_sdio>; + mmc-hs200-1_8v; + }; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index dca56d6248f5..3e29050ec769 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -28,6 +28,8 @@ Optional properties: transparent level shifters on the outputs of the controller. Two cells are required, first cell specifies minimum slot voltage (mV), second cell specifies maximum slot voltage (mV). Several ranges could be specified. +- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19 + in tuning procedure. - fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. The uSDHC use one delay cell as default increasing step to do tuning process. This property allows user to change the tuning step to more than one delay diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index ed23b9bedfdc..22d1e1f3f38b 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt @@ -46,8 +46,12 @@ Optional properties: - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported +- mmc-hs400-enhanced-strobe: eMMC HS400 enhanced strobe mode is supported - dsr: Value the card's (optional) Driver Stage Register (DSR) should be programmed with. Valid range: [0 .. 0xffff]. +- no-sdio: controller is limited to send sdio cmd during initialization +- no-sd: controller is limited to send sd cmd during initialization +- no-mmc: controller is limited to send mmc cmd during initialization *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line polarity properties, we have to fix the meaning of the "normal" and "inverted" diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt new file mode 100644 index 000000000000..489807005eda --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt @@ -0,0 +1,32 @@ +* Atmel Quad Serial Peripheral Interface (QSPI) + +Required properties: +- compatible: Should be "atmel,sama5d2-qspi". +- reg: Should contain the locations and lengths of the base registers + and the mapped memory. +- reg-names: Should contain the resource reg names: + - qspi_base: configuration register address space + - qspi_mmap: memory mapped address space +- interrupts: Should contain the interrupt for the device. +- clocks: The phandle of the clock needed by the QSPI controller. +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. + +Example: + +spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&spi0_clk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + + m25p80@0 { + ... + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt index 7066597c9a81..b40f3a492800 100644 --- a/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt +++ b/Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt @@ -27,6 +27,7 @@ Required properties: brcm,brcmnand-v6.2 brcm,brcmnand-v7.0 brcm,brcmnand-v7.1 + brcm,brcmnand-v7.2 brcm,brcmnand - reg : the register start and length for NAND register region. (optional) Flash DMA register range (if present) diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt new file mode 100644 index 000000000000..f248056da24c --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -0,0 +1,56 @@ +* Cadence Quad SPI controller + +Required properties: +- compatible : Should be "cdns,qspi-nor". +- reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. +- interrupts : Unit interrupt specifier for the controller interrupt. +- clocks : phandle to the Quad SPI clock. +- cdns,fifo-depth : Size of the data FIFO in words. +- cdns,fifo-width : Bus width of the data FIFO in bytes. +- cdns,trigger-address : 32-bit indirect AHB trigger address. + +Optional properties: +- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. + +Optional subnodes: +Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional +custom properties: +- cdns,read-delay : Delay for read capture logic, in clock cycles +- cdns,tshsl-ns : Delay in nanoseconds for the length that the master + mode chip select outputs are de-asserted between + transactions. +- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being + de-activated and the activation of another. +- cdns,tchsh-ns : Delay in nanoseconds between last bit of current + transaction and deasserting the device chip select + (qspi_n_ss_out). +- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low + and first bit transfer. + +Example: + + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,is-decoded-cs; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + + flash0: n25q00@0 { + ... + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 3ee7e202657c..174f68c26c1b 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -39,7 +39,7 @@ Optional properties: "prefetch-polled" Prefetch polled mode (default) "polled" Polled mode, without prefetch - "prefetch-dma" Prefetch enabled sDMA mode + "prefetch-dma" Prefetch enabled DMA mode "prefetch-irq" Prefetch enabled irq mode - elm_id: <deprecated> use "ti,elm-id" instead diff --git a/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt b/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt new file mode 100644 index 000000000000..74981520d6dd --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt @@ -0,0 +1,24 @@ +HiSilicon SPI-NOR Flash Controller + +Required properties: +- compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings: + "hisilicon,hi3519-spi-nor" +- address-cells : Should be 1. +- size-cells : Should be 0. +- reg : Offset and length of the register set for the controller device. +- reg-names : Must include the following two entries: "control", "memory". +- clocks : handle to spi-nor flash controller clock. + +Example: +spi-nor-controller@10000000 { + compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10000000 0x1000>, <0x14000000 0x1000000>; + reg-names = "control", "memory"; + clocks = <&clock HI3519_FMC_CLK>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt new file mode 100644 index 000000000000..069c192ed5c2 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt @@ -0,0 +1,160 @@ +MTK SoCs NAND FLASH controller (NFC) DT binding + +This file documents the device tree bindings for MTK SoCs NAND controllers. +The functional split of the controller requires two drivers to operate: +the nand controller interface driver and the ECC engine driver. + +The hardware description for both devices must be captured as device +tree nodes. + +1) NFC NAND Controller Interface (NFI): +======================================= + +The first part of NFC is NAND Controller Interface (NFI) HW. +Required NFI properties: +- compatible: Should be "mediatek,mtxxxx-nfc". +- reg: Base physical address and size of NFI. +- interrupts: Interrupts of NFI. +- clocks: NFI required clocks. +- clock-names: NFI clocks internal name. +- status: Disabled default. Then set "okay" by platform. +- ecc-engine: Required ECC Engine node. +- #address-cells: NAND chip index, should be 1. +- #size-cells: Should be 0. + +Example: + + nandc: nfi@1100d000 { + compatible = "mediatek,mt2701-nfc"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names = "nfi_clk", "pad_clk"; + status = "disabled"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + }; + +Platform related properties, should be set in {platform_name}.dts: +- children nodes: NAND chips. + +Children nodes properties: +- reg: Chip Select Signal, default 0. + Set as reg = <0>, <1> when need 2 CS. +Optional: +- nand-on-flash-bbt: Store BBT on NAND Flash. +- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) +- nand-ecc-step-size: Number of data bytes covered by a single ECC step. + valid values: 512 and 1024. + 1024 is recommended for large page NANDs. +- nand-ecc-strength: Number of bits to correct per ECC step. + The valid values that the controller supports are: 4, 6, + 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44, + 48, 52, 56, 60. + The strength should be calculated as follows: + E = (S - F) * 8 / 14 + S = O / (P / Q) + E : nand-ecc-strength. + S : spare size per sector. + F : FDM size, should be in the range [1,8]. + It is used to store free oob data. + O : oob size. + P : page size. + Q : nand-ecc-step-size. + If the result does not match any one of the listed + choices above, please select the smaller valid value from + the list. + (otherwise the driver will do the adjustment at runtime) +- pinctrl-names: Default NAND pin GPIO setting name. +- pinctrl-0: GPIO setting node. + +Example: + &pio { + nand_pins_default: nanddefault { + pins_dat { + pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>, + <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>, + <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>, + <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>, + <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>, + <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>, + <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>, + <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>, + <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up; + }; + + pins_we { + pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_ale { + pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + }; + + &nandc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_default>; + nand@0 { + reg = <0>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + }; + }; + +NAND chip optional subnodes: +- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt + +Example: + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + preloader@0 { + label = "pl"; + read-only; + reg = <0x00000000 0x00400000>; + }; + android@0x00400000 { + label = "android"; + reg = <0x00400000 0x12c00000>; + }; + }; + }; + +2) ECC Engine: +============== + +Required BCH properties: +- compatible: Should be "mediatek,mtxxxx-ecc". +- reg: Base physical address and size of ECC. +- interrupts: Interrupts of ECC. +- clocks: ECC required clocks. +- clock-names: ECC clocks internal name. +- status: Disabled default. Then set "okay" by platform. + +Example: + + bch: ecc@1100e000 { + compatible = "mediatek,mt2701-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_ECC>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt index 086d6f44c4b9..f322f56aef74 100644 --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt @@ -11,10 +11,16 @@ Required properties: * "ahb" : AHB gating clock * "mod" : nand controller clock +Optional properties: +- dmas : shall reference DMA channel associated to the NAND controller. +- dma-names : shall be "rxtx". + Optional children nodes: Children nodes represent the available nand chips. Optional properties: +- reset : phandle + reset specifier pair +- reset-names : must contain "ahb" - allwinner,rb : shall contain the native Ready/Busy ids. or - rb-gpios : shall contain the gpios used as R/B pins. diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt index 05f705e32a4a..e41b2d59ca7f 100644 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt @@ -59,8 +59,8 @@ Example: compatible = "apm,xgene-enet"; status = "disabled"; reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0X17030000 0x0 0X400>, - <0x0 0X10000000 0x0 0X200>; + <0x0 0x17030000 0x0 0x400>, + <0x0 0x10000000 0x0 0x200>; reg-names = "enet_csr", "ring_csr", "ring_cmd"; interrupts = <0x0 0x3c 0x4>; port-id = <0>; diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt index 7dbd158810d2..e3b8fe71762b 100644 --- a/Documentation/devicetree/bindings/net/cavium-pip.txt +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt @@ -37,6 +37,12 @@ Properties for PIP port which is a child the PIP interface: - phy-handle: Optional, see ethernet.txt file in the same directory. +- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0. + Value range is 1-31, and mapping to the actual delay varies depending on HW. + +- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0. + Value range is 1-31, and mapping to the actual delay varies depending on HW. + Example: pip@11800a0000000 { diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt index 9bbbe7f87d67..a4a570fb2494 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt @@ -317,7 +317,7 @@ Each port children node must have the following mandatory properties: Note that a port labelled "dsa" will imply checking for the uplink phandle described below. -Optionnal property: +Optional property: - link : Should be a list of phandles to another switch's DSA port. This property is only used when switches are being chained/cascaded together. This port is used as outgoing port diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index b037a9d78d93..a1e3693cca16 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -27,6 +27,9 @@ Optional properties: number to 1. - fsl,magic-packet : If present, indicates that the hardware supports waking up via magic packet. +- fsl,err006687-workaround-present: If present indicates that the system has + the hardware workaround for ERR006687 applied and does not need a software + workaround. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt new file mode 100644 index 000000000000..bbcd9f4c501f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -0,0 +1,56 @@ +Aardvark PCIe controller + +This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC. + +The Device Tree node describing an Aardvark PCIe controller must +contain the following properties: + + - compatible: Should be "marvell,armada-3700-pcie" + - reg: range of registers for the PCIe controller + - interrupts: the interrupt line of the PCIe controller + - #address-cells: set to <3> + - #size-cells: set to <2> + - device_type: set to "pci" + - ranges: ranges for the PCI memory and I/O regions + - #interrupt-cells: set to <1> + - msi-controller: indicates that the PCIe controller can itself + handle MSI interrupts + - msi-parent: pointer to the MSI controller to be used + - interrupt-map-mask and interrupt-map: standard PCI properties to + define the mapping of the PCIe interface to interrupt numbers. + - bus-range: PCI bus numbers covered + +In addition, the Device Tree describing an Aardvark PCIe controller +must include a sub-node that describes the legacy interrupt controller +built into the PCIe controller. This sub-node must have the following +properties: + + - interrupt-controller + - #interrupt-cells: set to <1> + +Example: + + pcie0: pcie@d0070000 { + compatible = "marvell,armada-3700-pcie"; + device_type = "pci"; + status = "disabled"; + reg = <0 0xd0070000 0 0x20000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + msi-controller; + msi-parent = <&pcie0>; + ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ + 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt new file mode 100644 index 000000000000..330a45b5f0b5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -0,0 +1,46 @@ +* Axis ARTPEC-6 PCIe interface + +This PCIe host controller is based on the Synopsys DesignWare PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: "axis,artpec6-pcie", "snps,dw-pcie" +- reg: base addresses and lengths of the PCIe controller (DBI), + the phy controller, and configuration address space. +- reg-names: Must include the following entries: + - "dbi" + - "phy" + - "config" +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: Must include the following entries: + - "msi": The interrupt that is asserted when an MSI is received +- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, + used to enable and control the Synopsys IP. + +Example: + + pcie@f8050000 { + compatible = "axis,artpec6-pcie", "snps,dw-pcie"; + reg = <0xf8050000 0x2000 + 0xf8040000 0x1000 + 0xc0000000 0x1000>; + reg-names = "dbi", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* downstream I/O */ + ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>; + num-lanes = <2>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + axis,syscon-pcie = <&syscon>; + }; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2fd23a..41e9f55a1467 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example: @@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 0bf1ae243552..3742c152c467 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -124,7 +124,7 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below: - functions: "usb3-ss", "sata" For Tegra210, the list of valid PHY nodes is given below: -- utmi: utmi-0, utmi-1, utmi-2, utmi-3 +- usb2: usb2-0, usb2-1, usb2-2, usb2-3 - functions: "snps", "xusb", "uart" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index 555cb0f40690..e3ea55763b0a 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt @@ -7,6 +7,13 @@ Required properties: - reg: PHY register address offset and length in "general register files" +Optional clocks using the clock bindings (see ../clock/clock-bindings.txt), +specified by name: + - clock-names: Should contain "emmcclk". Although this is listed as optional + (because most boards can get basic functionality without having + access to it), it is strongly suggested. + - clocks: Should have a phandle to the card clock exported by the SDHCI driver. + Example: @@ -20,6 +27,8 @@ grf: syscon@ff770000 { emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x20>; + clocks = <&sdhci>; + clock-names = "emmcclk"; #phy-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt index e4277921f3e3..a73cbeb0f309 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt @@ -3,8 +3,22 @@ Broadcom iProc GPIO/PINCONF Controller Required properties: - compatible: - Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", - "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio" + "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that + supports full-featured pinctrl and GPIO functions used in various iProc + based SoCs + + May contain an SoC-specific compatibility string to accommodate any + SoC-specific features + + "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or + "brcm,cygnus-crmu-gpio" for Cygnus SoCs + + "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support + disabled + + "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general + pinctrl support completely disabled in this IP block. In Stingray, a + different IP block is used to handle pinctrl related functions - reg: Define the base and range of the I/O address space that contains SoC diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt new file mode 100644 index 000000000000..603564e5fe6f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt @@ -0,0 +1,79 @@ +Broadcom NSP (Northstar plus) IOMUX Controller + +The NSP IOMUX controller supports group based mux configuration. In +addition, certain pins can be muxed to GPIO function individually. + +Required properties: +- compatible: + Must be "brcm,nsp-pinmux" + +- reg: + Should contain the register physical address and length for each of + GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers + +Properties in subnodes: +- function: + The mux function to select + +- groups: + The list of groups to select with a given function + +For more details, refer to +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +For example: + + pinmux: pinmux@1803f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x1803f1c0 0x04>, + <0x18030028 0x04>, + <0x1803f408 0x04>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm &gpio_b &nand_sel>; + + pwm: pwm { + function = "pwm"; + groups = "pwm0_grp", "pwm1_grp"; + }; + + gpio_b: gpio_b { + function = "gpio_b"; + groups = "gpio_b_0_grp", "gpio_b_1_grp"; + }; + + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; + }; + +List of supported functions and groups in Northstar Plus: + +"spi": "spi_grp" + +"i2c": "i2c_grp" + +"mdio": "mdio_grp" + +"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" + +"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp" + +"uart1": "uart1_grp" + +"uart2": "uart2_grp" + +"synce": "synce_grp" + +"sata_led_grps": "sata0_led_grp", "sata1_led_grp" + +"xtal_out": "xtal_out_grp" + +"sdio": "sdio_pwr_grp", "sdio_1p8v_grp" + +"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp" + +"nand": "nand_grp" + +"emmc": "emmc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 32f4a2d6d0b3..fe7fe0b03cfb 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -5,6 +5,8 @@ Required properties for the root node: "amlogic,meson8b-cbus-pinctrl" "amlogic,meson8-aobus-pinctrl" "amlogic,meson8b-aobus-pinctrl" + "amlogic,meson-gxbb-periphs-pinctrl" + "amlogic,meson-gxbb-aobus-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt new file mode 100644 index 000000000000..f2abdaee9022 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt @@ -0,0 +1,60 @@ +Device tree binding for NVIDIA Tegra DPAUX pad controller +======================================================== + +The Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins +which can be assigned to either the DPAUX channel or to an I2C +controller. + +This document defines the device-specific binding for the DPAUX pad +controller. Refer to pinctrl-bindings.txt in this directory for generic +information about pin controller device tree bindings. Please refer to +the binding document ../display/tegra/nvidia,tegra20-host1x.txt for more +details on the DPAUX binding. + +Pin muxing: +----------- + +Child nodes contain the pinmux configurations following the conventions +from the pinctrl-bindings.txt document. + +Since only three configurations are possible, only three child nodes are +needed to describe the pin mux'ing options for the DPAUX pads. +Furthermore, given that the pad functions are only applicable to a +single set of pads, the child nodes only need to describe the pad group +the functions are being applied to rather than the individual pads. + +Required properties: +- groups: Must be "dpaux-io" +- function: Must be either "aux", "i2c" or "off". + +Example: +-------- + + dpaux@545c0000 { + ... + + state_dpaux_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + }; + + ... + + i2c@7000d100 { + ... + pinctrl-0 = <&state_dpaux_i2c>; + pinctrl-1 = <&state_dpaux_off>; + pinctrl-names = "default", "idle"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt new file mode 100644 index 000000000000..d6074321f730 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt @@ -0,0 +1,57 @@ +* Oxford Semiconductor OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - oxsemi,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt new file mode 100644 index 000000000000..ad4fce3552bb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt @@ -0,0 +1,127 @@ +Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor. + +Device has 8 GPIO pins which can be configured as GPIO as well as the +special IO functions. + +Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt> +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are required if default setting of pins are required +at boot. +- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>. +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + <pinctrl-binding.txt>. + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +------------------ +- pins: List of pins. Valid values of pins properties are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7. + +Optional properties: +------------------- +Following are optional properties defined as pinmux DT binding document +<pinctrl-bindings.txt>. Absence of properties will leave the configuration +on default. + function, + drive-push-pull, + drive-open-drain, + bias-pull-up, + bias-pull-down. + +Valid values for function properties are: + gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, + reference-out + +Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These +customised properties are required to configure FPS configuration parameters +of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more +detail of Flexible Power Sequence (FPS). + +- maxim,active-fps-source: FPS source for the GPIOs to get + enabled/disabled when system is in + active state. Valid values are: + - MAX77620_FPS_SRC_0, + FPS source is FPS0. + - MAX77620_FPS_SRC_1, + FPS source is FPS1 + - MAX77620_FPS_SRC_2 and + FPS source is FPS2 + - MAX77620_FPS_SRC_NONE. + GPIO is not controlled + by FPS events and it gets + enabled/disabled by register + access. + Absence of this property will leave + the FPS configuration register for that + GPIO to default configuration. + +- maxim,active-fps-power-up-slot: Sequencing event slot number on which + the GPIO get enabled when + master FPS input event set to HIGH. + Valid values are 0 to 7. + This is applicable if FPS source is + selected as FPS0, FPS1 or FPS2. + +- maxim,active-fps-power-down-slot: Sequencing event slot number on which + the GPIO get disabled when master + FPS input event set to LOW. + Valid values are 0 to 7. + This is applicable if FPS source is + selected as FPS0, FPS1 or FPS2. + +- maxim,suspend-fps-source: This is same as property + "maxim,active-fps-source" but value + get configured when system enters in + to suspend state. + +- maxim,suspend-fps-power-up-slot: This is same as property + "maxim,active-fps-power-up-slot" but + this value get configured into FPS + configuration register when system + enters into suspend. + This is applicable if suspend state + FPS source is selected as FPS0, FPS1 or + +- maxim,suspend-fps-power-down-slot: This is same as property + "maxim,active-fps-power-down-slot" but + this value get configured into FPS + configuration register when system + enters into suspend. + This is applicable if suspend state + FPS source is selected as FPS0, FPS1 or + FPS2. + +Example: +-------- +#include <dt-bindings/mfd/max77620.h> +... +max77620@3c { + + pinctrl-names = "default"; + pinctrl-0 = <&spmic_default>; + + spmic_default: pinmux@0 { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = <MAX77620_FPS_SRC_0>; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = <MAX77620_FPS_SRC_1>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt new file mode 100644 index 000000000000..1b52f01ddcb7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt @@ -0,0 +1,152 @@ +Qualcomm MDM9615 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +MDM9615 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,mdm9615-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio87 + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. + Valid values are: + gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, + sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, + cdc_mclk + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + msmgpio: pinctrl@800000 { + compatible = "qcom,mdm9615-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 0x4>; + + gsbi8_uart: gsbi8-uart { + mux { + pins = "gpio34", "gpio35"; + function = "gsbi8"; + }; + + tx { + pins = "gpio34"; + drive-strength = <4>; + bias-disable; + }; + + rx { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt index 77aa11790163..df9a838ec5f9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt @@ -52,7 +52,7 @@ Valid values for function are: gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1, - usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, + usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs Example: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt index e4d6a9d20f7d..453bd7c76d6b 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt @@ -49,6 +49,9 @@ Valid values for pins are: sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data Supports bias and drive-strength + hsic_data, hsic_strobe + Supports only mux + Valid values for function are: cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, @@ -70,7 +73,7 @@ Valid values for function are: cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s, - ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, gpio + ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio (Note that this is not yet the complete list of functions) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index d74e631e10da..b484ba1af78c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -9,6 +9,7 @@ of PMIC's from Qualcomm. Definition: Should contain one of: "qcom,pm8018-mpp", "qcom,pm8038-mpp", + "qcom,pm8058-mpp", "qcom,pm8821-mpp", "qcom,pm8841-mpp", "qcom,pm8916-mpp", diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 74e6ec0339d6..e4cf022c992e 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -72,7 +72,7 @@ Pin Configuration Node Properties: The pin configuration parameters use the generic pinconf bindings defined in pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive strength and power-source. For +bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For pins that have a configurable I/O voltage, the power-source value should be the nominal I/O voltage in millivolts. diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 7b4800cc251e..587bffb9cbc6 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -9,6 +9,7 @@ Pin controller node: Required properies: - compatible: value should be one of the following: (a) "st,stm32f429-pinctrl" + (b) "st,stm32f746-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt new file mode 100644 index 000000000000..84404c9edff7 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt @@ -0,0 +1,31 @@ +DT bindings for the Renesas Advanced Power Management Unit + +Renesas R-Car line of SoCs utilize one or more APMU hardware units +for CPU core power domain control including SMP boot and CPU Hotplug. + +Required properties: + +- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback. + Examples with soctypes are: + - "renesas,r8a7790-apmu" (R-Car H2) + - "renesas,r8a7791-apmu" (R-Car M2-W) + - "renesas,r8a7792-apmu" (R-Car V2H) + - "renesas,r8a7793-apmu" (R-Car M2-N) + - "renesas,r8a7794-apmu" (R-Car E2) + +- reg: Base address and length of the I/O registers used by the APMU. + +- cpus: This node contains a list of CPU cores, which should match the order + of CPU cores used by the WUPCR and PSTR registers in the Advanced Power + Management Unit section of the device's datasheet. + + +Example: + +This shows the r8a7791 APMU that can control CPU0 and CPU1. + + apmu@e6152000 { + compatible = "renesas,r8a7791-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index b74e4d4785ab..0725fb37a973 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -14,6 +14,7 @@ Required properties: - "renesas,r8a7793-sysc" (R-Car M2-N) - "renesas,r8a7794-sysc" (R-Car E2) - "renesas,r8a7795-sysc" (R-Car H3) + - "renesas,r8a7796-sysc" (R-Car M3-W) - reg: Address start and address range for the device. - #power-domain-cells: Must be 1. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt deleted file mode 100644 index 29b28b8f9a89..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Network - -Currently defined compatibles: -- fsl,cpm1-scc-enet -- fsl,cpm2-scc-enet -- fsl,cpm1-fec-enet -- fsl,cpm2-fcc-enet (third resource is GFEMR) -- fsl,qe-enet - -Example: - - ethernet@11300 { - compatible = "fsl,mpc8272-fcc-enet", - "fsl,cpm2-fcc-enet"; - reg = <11300 20 8400 100 11390 1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <20 8>; - interrupt-parent = <&PIC>; - phy-handle = <&PHY0>; - fsl,cpm-command = <12000300>; - }; - -* MDIO - -Currently defined compatibles: -fsl,pq1-fec-mdio (reg is same as first resource of FEC device) -fsl,cpm2-mdio-bitbang (reg is port C registers) - -Properties for fsl,cpm2-mdio-bitbang: -fsl,mdio-pin : pin of port C controlling mdio data -fsl,mdc-pin : pin of port C controlling mdio clock - -Example: - mdio@10d40 { - compatible = "fsl,mpc8272ads-mdio-bitbang", - "fsl,mpc8272-mdio-bitbang", - "fsl,cpm2-mdio-bitbang"; - reg = <10d40 14>; - #address-cells = <1>; - #size-cells = <0>; - fsl,mdio-pin = <12>; - fsl,mdc-pin = <13>; - }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt index 55c2c03fc81e..df873d1f3b7c 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt @@ -35,7 +35,7 @@ PROPERTIES Definition: Specifies the index of the FMan unit. The cell-index value may be used by the SoC, to identify the - FMan unit in the SoC memory map. In the table bellow, + FMan unit in the SoC memory map. In the table below, there's a description of the cell-index use in each SoC: - P1023: @@ -247,7 +247,7 @@ PROPERTIES The cell-index value may be used by the FMan or the SoC, to identify the MAC unit in the FMan (or SoC) memory map. - In the tables bellow there's a description of the cell-index + In the tables below there's a description of the cell-index use, there are two tables, one describes the use of cell-index by the FMan, the second describes the use by the SoC: diff --git a/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt b/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt new file mode 100644 index 000000000000..dffb79108b61 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/opal/oppanel-opal.txt @@ -0,0 +1,14 @@ +IBM OPAL Operator Panel Binding +------------------------------- + +Required properties: +- compatible : Should be "ibm,opal-oppanel". +- #lines : Number of lines on the operator panel e.g. <0x2>. +- #length : Number of characters per line of the operator panel e.g. <0x10>. + +Example: + oppanel { + compatible = "ibm,opal-oppanel"; + #lines = <0x2>; + #length = <0x10>; + }; diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt new file mode 100644 index 000000000000..21f75bbd6dae --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt @@ -0,0 +1,21 @@ +Broadcom iProc PWM controller device tree bindings + +This controller has 4 channels. + +Required Properties : +- compatible: must be "brcm,iproc-pwm" +- reg: physical base address and length of the controller's registers +- clocks: phandle + clock specifier pair for the external clock +- #pwm-cells: Should be 3. See pwm.txt in this directory for a + description of the cells format. + +Refer to clocks/clock-bindings.txt for generic clock consumer properties. + +Example: + +pwm: pwm@18031000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18031000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; +}; diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt index a183db48f910..c0b2028238d6 100644 --- a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt @@ -1,15 +1,14 @@ * Cirris Logic CLPS711X PWM controller Required properties: -- compatible: Shall contain "cirrus,clps711x-pwm". +- compatible: Shall contain "cirrus,ep7209-pwm". - reg: Physical base address and length of the controller's registers. - clocks: phandle + clock specifier pair of the PWM reference clock. - #pwm-cells: Should be 1. The cell specifies the index of the channel. Example: pwm: pwm@80000400 { - compatible = "cirrus,ep7312-pwm", - "cirrus,clps711x-pwm"; + compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm"; reg = <0x80000400 0x4>; clocks = <&clks 8>; #pwm-cells = <1>; diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt new file mode 100644 index 000000000000..472bd46ab5a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.txt @@ -0,0 +1,23 @@ +* PWM controlled by ChromeOS EC + +Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller +(EC) and controlled via a host-command interface. + +An EC PWM node should be only found as a sub-node of the EC node (see +Documentation/devicetree/bindings/mfd/cros-ec.txt). + +Required properties: +- compatible: Must contain "google,cros-ec-pwm" +- #pwm-cells: Should be 1. The cell specifies the PWM index. + +Example: + cros-ec@0 { + compatible = "google,cros-ec-spi"; + + ... + + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index c52f03b5032f..b4e73778dda3 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -1,10 +1,14 @@ Tegra SoC PWFM controller Required properties: -- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30, - must contain "nvidia,tegra30-pwm". Otherwise, must contain - "nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114, - tegra124, tegra132, or tegra210. +- compatible: Must be: + - "nvidia,tegra20-pwm": for Tegra20 + - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30 + - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114 + - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124 + - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 + - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 + - "nvidia,tegra186-pwm": for Tegra186 - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt index 5befb538db95..2e53324fb720 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt @@ -9,6 +9,10 @@ Required properties: Optional properties: - ti,prescaler: Should be a value between 0 and 7, see the timers datasheet +- ti,clock-source: Set dmtimer parent clock, values between 0 and 2: + - 0x00 - high-frequency system clock (timer_sys_ck) + - 0x01 - 32-kHz always-on clock (timer_32k_ck) + - 0x02 - external clock (timer_ext_ck, OMAP2 only) Example: pwm9: dmtimer-pwm@9 { diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index fb81179dce37..8007e839a716 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -2,28 +2,48 @@ TI SOC ECAP based APWM controller Required properties: - compatible: Must be "ti,<soc>-ecap". - for am33xx - compatible = "ti,am33xx-ecap"; - for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; + for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the ECAP: - "ecap<x>", <x> being the 0-based instance number from the HW spec +- clocks: Handle to the ECAP's functional clock. +- clock-names: Must be set to "fck". Example: -ecap0: ecap@0 { /* ECAP on am33xx */ - compatible = "ti,am33xx-ecap"; +ecap0: ecap@48300100 { /* ECAP on am33xx */ + compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; +}; + +ecap0: ecap@48300100 { /* ECAP on am4372 */ + compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; ti,hwmods = "ecap0"; + clocks = <&l4ls_gclk>; + clock-names = "fck"; +}; + +ecap0: ecap@1f06000 { /* ECAP on da850 */ + compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x1f06000 0x80>; }; -ecap0: ecap@0 { /* ECAP on da850 */ - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; +ecap0: ecap@4843e100 { + compatible = "ti,dra746-ecap", "ti,am3352-ecap"; #pwm-cells = <3>; - reg = <0x306000 0x80>; + reg = <0x4843e100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 9c100b2c5b23..944fe356bb45 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -2,28 +2,48 @@ TI SOC EHRPWM based PWM controller Required properties: - compatible: Must be "ti,<soc>-ehrpwm". - for am33xx - compatible = "ti,am33xx-ehrpwm"; - for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm"; + for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the EHRPWM: - "ehrpwm<x>", <x> being the 0-based instance number from the HW spec +- clocks: Handle to the PWM's time-base and functional clock. +- clock-names: Must be set to "tbclk" and "fck". Example: -ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ - compatible = "ti,am33xx-ehrpwm"; +ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ + compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; +}; + +ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */ + compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; ti,hwmods = "ehrpwm0"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; +ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */ + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x1f00000 0x2000>; +}; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */ + compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; - reg = <0x300000 0x2000>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index f7eae77f8354..1a5d7b71db89 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -1,7 +1,11 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,<soc>-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss"; + for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss" + - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -16,7 +20,7 @@ Required properties: Also child nodes should also populated under PWMSS DT node. Example: -pwmss0: pwmss@48300000 { +epwmss0: epwmss@48300000 { /* PWMSS for am33xx */ compatible = "ti,am33xx-pwmss"; reg = <0x48300000 0x10>; ti,hwmods = "epwmss0"; @@ -29,3 +33,28 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; + +epwmss0: epwmss@48300000 { /* PWMSS for am4372 */ + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss" + reg = <0x48300000 0x10>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + /* child nodes go here */ +}; + +epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */ + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 0822a083fc57..d6de64335022 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,pwm-r8a7790": for R-Car H2 - "renesas,pwm-r8a7791": for R-Car M2-W - "renesas,pwm-r8a7794": for R-Car E2 + - "renesas,pwm-r8a7795": for R-Car H3 - reg: base address and length of the registers block for the PWM. - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. diff --git a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt new file mode 100644 index 000000000000..cb209646bf13 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt @@ -0,0 +1,18 @@ +== ST STMPE PWM controller == + +This is a PWM block embedded in the ST Microelectronics STMPE +(ST Multi-Purpose Expander) chips. The PWM is registered as a +subdevices of the STMPE MFD device. + +Required properties: +- compatible: should be: + - "st,stmpe-pwm" +- #pwm-cells: should be 2. See pwm.txt in this directory for a description of + the cells format. + +Example: + +pwm0: pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; +}; diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt index 0127be360fe8..873096be0278 100644 --- a/Documentation/devicetree/bindings/regmap/regmap.txt +++ b/Documentation/devicetree/bindings/regmap/regmap.txt @@ -14,7 +14,7 @@ architectures that typically run big-endian operating systems be marked that way in the devicetree. On SoCs that can be operated in both big-endian and little-endian -modes, with a single hardware switch controlling both the endianess +modes, with a single hardware switch controlling both the endianness of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS chips), "native-endian" is used to allow using the same device tree blob in both cases. diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt index dd6f59cf1455..3aeba9f86ed8 100644 --- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt @@ -34,6 +34,18 @@ Only required for Voltage Table Mode: First cell is voltage in microvolts (uV) Second cell is duty-cycle in percent (%) +Optional properties for Continuous mode: +- pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not + defined, <100> is assumed, meaning that + pwm-dutycycle-range contains values expressed in + percent. + +- pwm-dutycycle-range: Should contain 2 entries. The first entry is encoding + the dutycycle for regulator-min-microvolt and the + second one the dutycycle for regulator-max-microvolt. + Duty cycle values are expressed in pwm-dutycycle-unit. + If not defined, <0 100> is assumed. + NB: To be clear, if voltage-table is provided, then the device will be used in Voltage Table Mode. If no voltage-table is provided, then the device will be used in Continuous Voltage Mode. @@ -53,6 +65,13 @@ Continuous Voltage With Enable GPIO Example: regulator-min-microvolt = <1016000>; regulator-max-microvolt = <1114000>; regulator-name = "vdd_logic"; + /* unit == per-mille */ + pwm-dutycycle-unit = <1000>; + /* + * Inverted PWM logic, and the duty cycle range is limited + * to 30%-70%. + */ + pwm-dutycycle-range <700 300>; /* */ }; Voltage Table Example: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt new file mode 100644 index 000000000000..57cb49ec55ca --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -0,0 +1,137 @@ +Qualcomm Hexagon Peripheral Image Loader + +This document defines the binding for a component that loads and boots firmware +on the Qualcomm Hexagon core. + +- compatible: + Usage: required + Value type: <string> + Definition: must be one of: + "qcom,q6v5-pil" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: must specify the base address and size of the qdsp6 and + rmb register blocks + +- reg-names: + Usage: required + Value type: <stringlist> + Definition: must be "q6dsp" and "rmb" + +- interrupts-extended: + Usage: required + Value type: <prop-encoded-array> + Definition: must list the watchdog, fatal IRQs ready, handover and + stop-ack IRQs + +- interrupt-names: + Usage: required + Value type: <stringlist> + Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" + +- clocks: + Usage: required + Value type: <phandle> + Definition: reference to the iface, bus and mem clocks to be held on + behalf of the booting of the Hexagon core + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: must be "iface", "bus", "mem" + +- resets: + Usage: required + Value type: <phandle> + Definition: reference to the reset-controller for the modem sub-system + +- reset-names: + Usage: required + Value type: <stringlist> + Definition: must be "mss_restart" + +- cx-supply: +- mss-supply: +- mx-supply: +- pll-supply: + Usage: required + Value type: <phandle> + Definition: reference to the regulators to be held on behalf of the + booting of the Hexagon core + +- qcom,smem-states: + Usage: required + Value type: <phandle> + Definition: reference to the smem state for requesting the Hexagon to + shut down + +- qcom,smem-state-names: + Usage: required + Value type: <stringlist> + Definition: must be "stop" + +- qcom,halt-regs: + Usage: required + Value type: <prop-encoded-array> + Definition: a phandle reference to a syscon representing TCSR followed + by the three offsets within syscon for q6, modem and nc + halt registers. + += SUBNODES: +The Hexagon node must contain two subnodes, named "mba" and "mpss" representing +the memory regions used by the Hexagon firmware. Each sub-node must contain: + +- memory-region: + Usage: required + Value type: <phandle> + Definition: reference to the reserved-memory for the region + += EXAMPLE +The following example describes the resources needed to boot control the +Hexagon, as it is found on MSM8974 boards. + + modem-rproc@fc880000 { + compatible = "qcom,q6v5-pil"; + reg = <0xfc880000 0x100>, + <0xfc820000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 24 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>; + clock-names = "iface", "bus", "mem"; + + qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + }; diff --git a/Documentation/devicetree/bindings/misc/ramoops.txt b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt index cd02cec67d38..e81f821a2135 100644 --- a/Documentation/devicetree/bindings/misc/ramoops.txt +++ b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt @@ -2,8 +2,9 @@ Ramoops oops/panic logger ========================= ramoops provides persistent RAM storage for oops and panics, so they can be -recovered after a reboot. It is a backend to pstore, so this node is named -"ramoops" after the backend, rather than "pstore" which is the subsystem. +recovered after a reboot. This is a child-node of "/reserved-memory", and +is named "ramoops" after the backend, rather than "pstore" which is the +subsystem. Parts of this storage may be set aside for other persistent log buffers, such as kernel log messages, or for optional ECC error-correction data. The total @@ -21,8 +22,7 @@ Required properties: - compatible: must be "ramoops" -- memory-region: phandle to a region of memory that is preserved between - reboots +- reg: region of memory that is preserved between reboots Optional properties: diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt new file mode 100644 index 000000000000..e746b631793a --- /dev/null +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt @@ -0,0 +1,18 @@ +Amlogic Meson SoC Reset Controller +======================================= + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset" +- reg: should contain the register address base +- #reset-cells: 1, see below + +example: + +reset: reset-controller { + compatible = "amlogic,meson-gxbb-reset"; + reg = <0x0 0x04404 0x0 0x20>; + #reset-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt index e0b185a944ba..c25da39df707 100644 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -8,7 +8,9 @@ The reset controller registers are part of the system-ctl block on hi6220 SoC. Required properties: -- compatible: may be "hisilicon,hi6220-sysctrl" +- compatible: should be one of the following: + - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. + - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. - reg: should be register base and length as documented in the datasheet - #reset-cells: 1, see below diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt new file mode 100644 index 000000000000..164c7f34c451 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt @@ -0,0 +1,91 @@ +TI SysCon Reset Controller +======================= + +Almost all SoCs have hardware modules that require reset control in addition +to clock and power control for their functionality. The reset control is +typically provided by means of memory-mapped I/O registers. These registers are +sometimes a part of a larger register space region implementing various +functionalities. This register range is best represented as a syscon node to +allow multiple entities to access their relevant registers in the common +register space. + +A SysCon Reset Controller node defines a device that uses a syscon node +and provides reset management functionality for various hardware modules +present on the SoC. + +SysCon Reset Controller Node +============================ +Each of the reset provider/controller nodes should be a child of a syscon +node and have the following properties. + +Required properties: +-------------------- + - compatible : Should be, + "ti,k2e-pscrst" + "ti,k2l-pscrst" + "ti,k2hk-pscrst" + "ti,syscon-reset" + - #reset-cells : Should be 1. Please see the reset consumer node below + for usage details + - ti,reset-bits : Contains the reset control register information + Should contain 7 cells for each reset exposed to + consumers, defined as: + Cell #1 : offset of the reset assert control + register from the syscon register base + Cell #2 : bit position of the reset in the reset + assert control register + Cell #3 : offset of the reset deassert control + register from the syscon register base + Cell #4 : bit position of the reset in the reset + deassert control register + Cell #5 : offset of the reset status register + from the syscon register base + Cell #6 : bit position of the reset in the + reset status register + Cell #7 : Flags used to control reset behavior, + availible flags defined in the DT include + file <dt-bindings/reset/ti-syscon.h> + +SysCon Reset Consumer Nodes +=========================== +Each of the reset consumer nodes should have the following properties, +in addition to their own properties. + +Required properties: +-------------------- + - resets : A phandle to the reset controller node and an index number + to a reset specifier as defined above. + +Please also refer to Documentation/devicetree/bindings/reset/reset.txt for +common reset controller usage by consumers. + +Example: +-------- +The following example demonstrates a syscon node, the reset controller node +using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 +Edison SoC. + +/ { + soc { + psc: power-sleep-controller@02350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + + pscrst: psc-reset { + compatible = "ti,k2e-pscrst", "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */ + 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */ + >; + }; + }; + + dsp0: dsp0 { + ... + resets = <&pscrst 0>; + ... + }; + }; +}; diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt new file mode 100644 index 000000000000..202f2d09a23f --- /dev/null +++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt @@ -0,0 +1,14 @@ +Amlogic Meson Random number generator +===================================== + +Required properties: + +- compatible : should be "amlogic,meson-rng" +- reg : Specifies base physical address and size of the registers. + +Example: + +rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0xc8834000 0x0 0x4>; +}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-opal.txt b/Documentation/devicetree/bindings/rtc/rtc-opal.txt index a1734e5cb75b..2340938cd0f5 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-opal.txt +++ b/Documentation/devicetree/bindings/rtc/rtc-opal.txt @@ -2,7 +2,7 @@ IBM OPAL real-time clock ------------------------ Required properties: -- comapatible: Should be "ibm,opal-rtc" +- compatible: Should be "ibm,opal-rtc" Optional properties: - wakeup-source: Decides if the wakeup is supported or not diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt new file mode 100644 index 000000000000..85741cd468cc --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_spi.txt @@ -0,0 +1,24 @@ +Required properties: +- compatible: should be one of the following + "st,st33htpm-spi" + "infineon,slb9670" + "tcg,tpm_tis-spi" +- spi-max-frequency: Maximum SPI frequency (depends on TPMs). + +Optional SoC Specific Properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. + +Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4): + +&mcspi4 { + + status = "okay"; + + tpm_tis@0 { + + compatible = "tcg,tpm_tis-spi"; + + spi-max-frequency = <10000000>; + }; +}; diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt index caaeb2583579..07013fa60a48 100644 --- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt +++ b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) Required properties: -- compatible: Should be "cirrus,clps711x-uart". +- compatible: Should be "cirrus,ep7209-uart". - reg: Address and length of the register set for the device. - interrupts: Should contain UART TX and RX interrupt. - clocks: Should contain UART core clock number. @@ -20,7 +20,7 @@ Example: }; uart1: uart@80000480 { - compatible = "cirrus,clps711x-uart"; + compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; reg = <0x80000480 0x80>; interrupts = <12 13>; clocks = <&clks 11>; diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index e99e10ab9ecb..0015c722be7b 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -6,6 +6,7 @@ Required properties: * "mediatek,mt6580-uart" for MT6580 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS + * "mediatek,mt6755-uart" for MT6755 compatible UARTS * "mediatek,mt6795-uart" for MT6795 compatible UARTS * "mediatek,mt7623-uart" for MT7623 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt index 182777fac9a2..d5f73b8f614f 100644 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt @@ -28,10 +28,10 @@ Optional properties: - dma-names: Should contain "tx" for transmit and "rx" for receive channels - qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be used with TX DMA channel. Required when using DMA for transmission - with UARTDM v1.3 and bellow. + with UARTDM v1.3 and below. - qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be used with RX DMA channel. Required when using DMA for reception - with UARTDM v1.3 and bellow. + with UARTDM v1.3 and below. Note: Aliases may be defined to ensure the correct ordering of the UARTs. The alias serialN will result in the UART being assigned port N. If any diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt index 160c752484b4..160c752484b4 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt index 4c7d45eaf025..4c7d45eaf025 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/brg.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/brg.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt index 87bc6048667e..87bc6048667e 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/i2c.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt index 8e3ee1681618..8e3ee1681618 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/pic.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/pic.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt index 74bfda4bb824..74bfda4bb824 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/cpm/usb.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/usb.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt index 349f79fd7076..349f79fd7076 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt new file mode 100644 index 000000000000..03c741602c6d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt @@ -0,0 +1,124 @@ +* Network + +Currently defined compatibles: +- fsl,cpm1-scc-enet +- fsl,cpm2-scc-enet +- fsl,cpm1-fec-enet +- fsl,cpm2-fcc-enet (third resource is GFEMR) +- fsl,qe-enet + +Example: + + ethernet@11300 { + compatible = "fsl,mpc8272-fcc-enet", + "fsl,cpm2-fcc-enet"; + reg = <11300 20 8400 100 11390 1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <20 8>; + interrupt-parent = <&PIC>; + phy-handle = <&PHY0>; + fsl,cpm-command = <12000300>; + }; + +* MDIO + +Currently defined compatibles: +fsl,pq1-fec-mdio (reg is same as first resource of FEC device) +fsl,cpm2-mdio-bitbang (reg is port C registers) + +Properties for fsl,cpm2-mdio-bitbang: +fsl,mdio-pin : pin of port C controlling mdio data +fsl,mdc-pin : pin of port C controlling mdio clock + +Example: + mdio@10d40 { + compatible = "fsl,mpc8272ads-mdio-bitbang", + "fsl,mpc8272-mdio-bitbang", + "fsl,cpm2-mdio-bitbang"; + reg = <10d40 14>; + #address-cells = <1>; + #size-cells = <0>; + fsl,mdio-pin = <12>; + fsl,mdc-pin = <13>; + }; + +* HDLC + +Currently defined compatibles: +- fsl,ucc-hdlc + +Properties for fsl,ucc-hdlc: +- rx-clock-name +- tx-clock-name + Usage: required + Value type: <string> + Definition : Must be "brg1"-"brg16" for internal clock source, + Must be "clk1"-"clk24" for external clock source. + +- fsl,tdm-interface + Usage: optional + Value type: <empty> + Definition : Specify that hdlc is based on tdm-interface + +The property below is dependent on fsl,tdm-interface: +- fsl,rx-sync-clock + Usage: required + Value type: <string> + Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15". + +- fsl,tx-sync-clock + Usage: required + Value type: <string> + Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15". + +- fsl,tdm-framer-type + Usage: required for tdm interface + Value type: <string> + Definition : "e1" or "t1".Now e1 and t1 are used, other framer types + are not supported. + +- fsl,tdm-id + Usage: required for tdm interface + Value type: <u32> + Definition : number of TDM ID + +- fsl,tx-timeslot-mask +- fsl,rx-timeslot-mask + Usage: required for tdm interface + Value type: <u32> + Definition : time slot mask for TDM operation. Indicates which time + slots used for transmitting and receiving. + +- fsl,siram-entry-id + Usage: required for tdm interface + Value type: <u32> + Definition : Must be 0,2,4...64. the number of TDM entry. + +- fsl,tdm-internal-loopback + usage: optional for tdm interface + value type: <empty> + Definition : Internal loopback connecting on TDM layer. + +Example for tdm interface: + + ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; + +Example for hdlc without tdm interface: + + ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "brg1"; + tx-clock-name = "brg1"; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt index 4f8930263dd9..d7afaff5faff 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt @@ -69,6 +69,58 @@ Example: }; }; +* Interrupt Controller (IC) + +Required properties: +- compatible : should be "fsl,qe-ic". +- reg : Address range of IC register set. +- interrupts : interrupts generated by the device. +- interrupt-controller : this device is a interrupt controller. + +Example: + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <95 2 0 0 94 2 0 0>; + }; + +* Serial Interface Block (SI) + +The SI manages the routing of eight TDM lines to the QE block serial drivers +, the MCC and the UCCs, for receive and transmit. + +Required properties: +- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain + "fsl,t1040-qe-si". +- reg : Address range of SI register set. + +Example: + + si1: si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + +* Serial Interface Block RAM(SIRAM) + +store the routing entries of SI + +Required properties: +- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain + "fsl,t1040-qe-siram". +- reg : Address range of SI RAM. + +Example: + + siram1: siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + * QE Firmware Node This node defines a firmware binary that is embedded in the device tree, for diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt index 249db3a15d15..249db3a15d15 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/firmware.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/firmware.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 60984260207b..60984260207b 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt index ec6ee2e864a2..ec6ee2e864a2 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/pincfg.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt index e47734bee3f0..e47734bee3f0 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/ucc.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ucc.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt index 9ccd5f30405b..9ccd5f30405b 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe/usb.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/usb.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt index 2ea76d9d137c..2ea76d9d137c 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/serial.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/serial.txt diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt new file mode 100644 index 000000000000..8823c86c8085 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/uqe_serial.txt @@ -0,0 +1,17 @@ +* Serial + +Required Properties: +compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be +"fsl,t1040-ucc-uart". +port-number : port number of UCC-UART +tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source, + should be "clk1"-"clk28" for external clock source. + +Example: + + ucc_serial: ucc@2200 { + compatible = "fsl,t1040-ucc-uart"; + port-number = <0>; + rx-clock-name = "brg2"; + tx-clock-name = "brg2"; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt index 5cc82b8353d8..af9ca37221ce 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt @@ -68,7 +68,7 @@ important. Value type: <u32> Definition: must be 2 - denoting the bit in the entry and IRQ flags -- #qcom,state-cells: +- #qcom,smem-state-cells: Usage: required for outgoing entries Value type: <u32> Definition: must be 1 - denoting the bit in the entry @@ -92,7 +92,7 @@ wcnss-smp2p { wcnss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; wcnss_smp2p_in: slave-kernel { diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt index a6634c70850d..2993b5a97dd6 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt @@ -51,7 +51,7 @@ important. Definition: specifies the offset, in words, of the first bit for this entry -- #qcom,state-cells: +- #qcom,smem-state-cells: Usage: required for local entry Value type: <u32> Definition: must be 1 - denotes bit number @@ -91,7 +91,7 @@ smsm { apps_smsm: apps@0 { reg = <0>; - #qcom,state-cells = <1>; + #qcom,smem-state-cells = <1>; }; wcnss_smsm: wcnss@7 { diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt new file mode 100644 index 000000000000..4ea39e9186a7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt @@ -0,0 +1,116 @@ +Qualcomm WCNSS Binding + +This binding describes the Qualcomm WCNSS hardware. It consists of control +block and a BT, WiFi and FM radio block, all using SMD as command channels. + +- compatible: + Usage: required + Value type: <string> + Definition: must be: "qcom,wcnss", + +- qcom,smd-channel: + Usage: required + Value type: <string> + Definition: standard SMD property specifying the SMD channel used for + communication with the WiFi firmware. + Should be "WCNSS_CTRL". + +- qcom,mmio: + Usage: required + Value type: <prop-encoded-array> + Definition: reference to a node specifying the wcnss "ccu" and "dxe" + register blocks. The node must be compatible with one of + the following: + "qcom,riva", + "qcom,pronto" + += SUBNODES +The subnodes of the wcnss node are optional and describe the individual blocks in +the WCNSS. + +== Bluetooth +The following properties are defined to the bluetooth node: + +- compatible: + Usage: required + Value type: <string> + Definition: must be: + "qcom,wcnss-bt" + +== WiFi +The following properties are defined to the WiFi node: + +- compatible: + Usage: required + Value type: <string> + Definition: must be one of: + "qcom,wcnss-wlan", + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the "rx" and "tx" interrupts + +- interrupt-names: + Usage: required + Value type: <stringlist> + Definition: must contain "rx" and "tx" + +- qcom,smem-state: + Usage: required + Value type: <prop-encoded-array> + Definition: should reference the tx-enable and tx-rings-empty SMEM states + +- qcom,smem-state-names: + Usage: required + Value type: <stringlist> + Definition: must contain "tx-enable" and "tx-rings-empty" + += EXAMPLE +The following example represents a SMD node, with one edge representing the +"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks +described; as found on the 8974 platform. + +smd { + compatible = "qcom,smd"; + + pronto-edge { + interrupts = <0 142 1>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + #address-cells = <1>; + #size-cells = <1>; + + qcom,mmio = <&pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wlan { + compatible = "qcom,wcnss-wlan"; + + interrupts = <0 145 0>, <0 146 0>; + interrupt-names = "tx", "rx"; + + qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; +}; + +soc { + pronto: pronto { + compatible = "qcom,pronto"; + + reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt b/Documentation/devicetree/bindings/sound/adi,adau17x1.txt index 8dbce0e18dda..1447dec28125 100644 --- a/Documentation/devicetree/bindings/sound/adi,adau17x1.txt +++ b/Documentation/devicetree/bindings/sound/adi,adau17x1.txt @@ -13,6 +13,11 @@ Required properties: - reg: The i2c address. Value depends on the state of ADDR0 and ADDR1, as wired in hardware. +Optional properties: + - clock-names: If provided must be "mclk". + - clocks: phandle + clock-specifiers for the clock that provides + the audio master clock for the device. + Examples: #include <dt-bindings/sound/adau17x1.h> @@ -20,5 +25,8 @@ Examples: adau1361@38 { compatible = "adi,adau1761"; reg = <0x38>; + + clock-names = "mclk"; + clocks = <&audio_clock>; }; }; diff --git a/Documentation/devicetree/bindings/sound/adi,adau7002.txt b/Documentation/devicetree/bindings/sound/adi,adau7002.txt new file mode 100644 index 000000000000..f144ee1abf85 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/adi,adau7002.txt @@ -0,0 +1,19 @@ +Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter + +Required properties: + + - compatible: Must be "adi,adau7002" + +Optional properties: + + - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD + supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt + + If this property is not present it is assumed that the supply pin is + hardwired to always on. + +Example: + adau7002: pdm-to-i2s { + compatible = "adi,adau7002"; + IOVDD-supply = <&supply>; + }; diff --git a/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt b/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt new file mode 100644 index 000000000000..b139e66d2a11 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/brcm,cygnus-audio.txt @@ -0,0 +1,67 @@ +BROADCOM Cygnus Audio I2S/TDM/SPDIF controller + +Required properties: + - compatible : "brcm,cygnus-audio" + - #address-cells: 32bit valued, 1 cell. + - #size-cells: 32bit valued, 0 cell. + - reg : Should contain audio registers location and length + - reg-names: names of the registers listed in "reg" property + Valid names are "aud" and "i2s_in". "aud" contains a + set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains + a set of I2S_IN registers. + - clocks: PLL and leaf clocks used by audio ports + - assigned-clocks: PLL and leaf clocks + - assigned-clock-parents: parent clocks of the assigned clocks + (usually the PLL) + - assigned-clock-rates: List of clock frequencies of the + assigned clocks + - clock-names: names of 3 leaf clocks used by audio ports + Valid names are "ch0_audio", "ch1_audio", "ch2_audio" + - interrupts: audio DMA interrupt number + +SSP Subnode properties: +- reg: The index of ssp port interface to use + Valid value are 0, 1, 2, or 3 (for spdif) + +Example: + cygnus_audio: audio@180ae000 { + compatible = "brcm,cygnus-audio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>; + reg-names = "aud", "i2s_in"; + clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; + assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, + <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; + assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>; + assigned-clock-rates = <1769470191>, + <0>, + <0>, + <0>; + clock-names = "ch0_audio", "ch1_audio", "ch2_audio"; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + + ssp0: ssp_port@0 { + reg = <0>; + status = "okay"; + }; + + ssp1: ssp_port@1 { + reg = <1>; + status = "disabled"; + }; + + ssp2: ssp_port@2 { + reg = <2>; + status = "disabled"; + }; + + spdif: spdif_port@3 { + reg = <3>; + status = "disabled"; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/bt-sco.txt b/Documentation/devicetree/bindings/sound/bt-sco.txt index 29b8e5d40203..641edf75e184 100644 --- a/Documentation/devicetree/bindings/sound/bt-sco.txt +++ b/Documentation/devicetree/bindings/sound/bt-sco.txt @@ -4,7 +4,7 @@ This device support generic Bluetooth SCO link. Required properties: - - compatible : "delta,dfbmcs320" + - compatible : "delta,dfbmcs320" or "linux,bt-sco" Example: diff --git a/Documentation/devicetree/bindings/sound/cs35l33.txt b/Documentation/devicetree/bindings/sound/cs35l33.txt new file mode 100644 index 000000000000..acfb47525b49 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l33.txt @@ -0,0 +1,126 @@ +CS35L33 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l33" + + - reg : the I2C address of the device for I2C + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : gpio used to reset the amplifier + + - interrupt-parent : Specifies the phandle of the interrupt controller to + which the IRQs from CS35L33 are delivered to. + - interrupts : IRQ line info CS35L33. + (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt + for further information relating to interrupt properties) + + - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is + 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with + a value of 1 and will increase at a step size of 100mV until a maximum of + 8000mV. + + - cirrus,ramp-rate : On power up, it affects the time from when the power + up sequence begins to the time the audio reaches a full-scale output. + On power down, it affects the time from when the power-down sequence + begins to when the amplifier disables the PWM outputs. If this property + is not set then soft ramping will be disabled and ramp time would be + 20ms. If this property is set to 0,1,2,3 then ramp times would be 40ms, + 60ms,100ms,175ms respectively for 48KHz sample rate. + + - cirrus,boost-ipk : The maximum current allowed for the boost converter. + The range starts at 1850000uA and goes to a maximum of 3600000uA + with a step size of 15625uA. The default is 2500000uA. + + - cirrus,imon-adc-scale : Configures the scaling of data bits from the IMON + ADC data word. This property can be set as a value of 0 for bits 15 down + to 0, 6 for 21 down to 6, 7, for 22 down to 7, 8 for 23 down to 8. + + +Optional H/G Algorithm sub-node: + +The cs35l33 node can have a single "cirrus,hg-algo" sub-node that will enable +the internal H/G Algorithm. + + - cirrus,hg-algo : Sub-node for internal Class H/G algorithm that + controls the amplifier supplies. + +Optional properties for the "cirrus,hg-algo" sub-node: + + - cirrus,mem-depth : Memory depth for the Class H/G algorithm measured in + LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory + depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles. + + cirrus,release-rate : The number of consecutive LRCLK periods before + allowing release condition tracking updates. The number of LRCLK periods + start at 3 to a maximum of 255. + + - cirrus,ldo-thld : Configures the signal threshold at which the PWM output + stage enters LDO operation. Starts as a default value of 50mV for a value + of 1 and increases with a step size of 50mV to a maximum of 750mV (value of + 0xF). + + - cirrus,ldo-path-disable : This is a boolean property. If present, the H/G + algorithm uses the max detection path. If not present, the LDO + detection path is used. + + - cirrus,ldo-entry-delay : The LDO entry delay in milliseconds before the H/G + algorithm switches to the LDO voltage. This property can be set to values + from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms. + The default is 100ms. + + - cirrus,vp-hg-auto : This is a boolean property. When set, class H/G VPhg + automatic updating is enabled. + + - cirrus,vp-hg : Class H/G algorithm VPhg. Controls the H/G algorithm's + reference to the VP voltage for when to start generating a boosted VBST. + The reference voltage starts at 3000mV with a value of 0x3 and is increased + by 100mV per step to a maximum of 5500mV. + + - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is + allowed to increase to a higher voltage when using VPhg automatic + tracking. This property can be set to values from 0 to 3 with rates of 128 + periods, 2048 periods, 32768 periods, and 524288 periods. + The default is 32768 periods. + + - cirrus,vp-hg-va : VA calculation reference for automatic VPhg tracking + using VPMON. This property can be set to values from 0 to 6 starting at + 1800mV with a step size of 50mV up to a maximum value of 1750mV. + Default is 1800mV. + +Example: + +cs35l33: cs35l33@40 { + compatible = "cirrus,cs35l33"; + reg = <0x40>; + + VA-supply = <&ldo5_reg>; + VP-supply = <&ldo5_reg>; + + interrupt-parent = <&gpio8>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&cs47l91 34 0>; + + cirrus,ramp-rate = <0x0>; + cirrus,boost-ctl = <0x30>; /* VBST = 8000mV */ + cirrus,boost-ipk = <0xE0>; /* 3600mA */ + cirrus,imon-adc-scale = <0> /* Bits 15 down to 0 */ + + cirrus,hg-algo { + cirrus,mem-depth = <0x3>; + cirrus,release-rate = <0x3>; + cirrus,ldo-thld = <0x1>; + cirrus,ldo-path-disable = <0x0>; + cirrus,ldo-entry-delay=<0x4>; + cirrus,vp-hg-auto; + cirrus,vp-hg=<0xF>; + cirrus,vp-hg-rate=<0x2>; + cirrus,vp-hg-va=<0x0>; + }; +}; diff --git a/Documentation/devicetree/bindings/sound/cs53l30.txt b/Documentation/devicetree/bindings/sound/cs53l30.txt new file mode 100644 index 000000000000..4dbfb8274cd9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs53l30.txt @@ -0,0 +1,44 @@ +CS53L30 audio CODEC + +Required properties: + + - compatible : "cirrus,cs53l30" + + - reg : the I2C address of the device + + - VA-supply, VP-supply : power supplies for the device, + as covered in Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + + - reset-gpios : a GPIO spec for the reset pin. + + - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either + GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled + by the driver automatically. + + - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin. + 0 = Hi-Z + 1 = 1.80 V + 2 = 2.75 V + + - cirrus,use-sdout2 : This is a boolean property. If present, it indicates + the hardware design connects both SDOUT1 and SDOUT2 + pins to output data. Otherwise, it indicates that + only SDOUT1 is connected for data output. + * CS53l30 supports 4-channel data output in the same + * frame using two different ways: + * 1) Normal I2S mode on two data pins -- each SDOUT + * carries 2-channel data in the same time. + * 2) TDM mode on one signle data pin -- SDOUT1 carries + * 4-channel data per frame. + +Example: + +codec: cs53l30@48 { + compatible = "cirrus,cs53l30"; + reg = <0x48>; + reset-gpios = <&gpio 54 0>; + VA-supply = <&cs53l30_va>; + VP-supply = <&cs53l30_vp>; +}; diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt index 7bb54247f8e8..6a536d570e29 100644 --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt +++ b/Documentation/devicetree/bindings/sound/designware-i2s.txt @@ -12,6 +12,10 @@ Required properties: one for receive. - dma-names : "tx" for the transmit channel, "rx" for the receive channel. +Optional properties: + - interrupts: The interrupt line number for the I2S controller. Add this + parameter if the I2S controller that you are using does not support DMA. + For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties please check: * resource-names.txt diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt index ceaef5126989..f749e2744824 100644 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -58,7 +58,7 @@ Required properties: * DMIC (stands for Digital Microphone Jack) Note: The "Mic Jack" and "AMIC" are redundant while - coexsiting in order to support the old bindings + coexisting in order to support the old bindings of wm8962 and sgtl5000. Optional properties: diff --git a/Documentation/devicetree/bindings/sound/max98504.txt b/Documentation/devicetree/bindings/sound/max98504.txt new file mode 100644 index 000000000000..583ed5fdfb28 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/max98504.txt @@ -0,0 +1,44 @@ +Maxim MAX98504 class D mono speaker amplifier + +This device supports I2C control interface and an IRQ output signal. It features +a PCM and PDM digital audio interface (DAI) and a differential analog input. + +Required properties: + + - compatible : "maxim,max98504" + - reg : should contain the I2C slave device address + - DVDD-supply, DIOVDD-supply, PVDD-supply: power supplies for the device, + as covered in ../regulator/regulator.txt + - interrupts : should specify the interrupt line the device is connected to, + as described in ../interrupt-controller/interrupts.txt + +Optional properties: + + - maxim,brownout-threshold - the PVDD brownout threshold, the value must be + from 0, 1...21 range, corresponding to 2.6V, 2.65V...3.65V voltage range + - maxim,brownout-attenuation - the brownout attenuation to the speaker gain + applied during the "attack hold" and "timed hold" phase, the value must be + from 0...6 (dB) range + - maxim,brownout-attack-hold-ms - the brownout attack hold phase time in ms, + 0...255 (VBATBROWN_ATTK_HOLD, register 0x0018) + - maxim,brownout-timed-hold-ms - the brownout timed hold phase time in ms, + 0...255 (VBATBROWN_TIME_HOLD, register 0x0019) + - maxim,brownout-release-rate-ms - the brownout release phase step time in ms, + 0...255 (VBATBROWN_RELEASE, register 0x001A) + +The default value when the above properties are not specified is 0, +the maxim,brownout-threshold property must be specified to actually enable +the PVDD brownout protection. + +Example: + + max98504@31 { + compatible = "maxim,max98504"; + reg = <0x31>; + interrupt-parent = <&gpio_bank_0>; + interrupts = <2 0>; + + DVDD-supply = <®ulator>; + DIOVDD-supply = <®ulator>; + PVDD-supply = <®ulator>; +}; diff --git a/Documentation/devicetree/bindings/sound/max9860.txt b/Documentation/devicetree/bindings/sound/max9860.txt new file mode 100644 index 000000000000..e0d4e95e31b3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/max9860.txt @@ -0,0 +1,28 @@ +MAX9860 Mono Audio Voice Codec + +Required properties: + + - compatible : "maxim,max9860" + + - reg : the I2C address of the device + + - AVDD-supply, DVDD-supply and DVDDIO-supply : power supplies for + the device, as covered in bindings/regulator/regulator.txt + + - clock-names : Required element: "mclk". + + - clocks : A clock specifier for the clock connected as MCLK. + +Examples: + + max9860: max9860@10 { + compatible = "maxim,max9860"; + reg = <0x10>; + + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v8>; + DVDDIO-supply = <®_3v0>; + + clock-names = "mclk"; + clocks = <&pck2>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt new file mode 100644 index 000000000000..3e623a724e55 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt @@ -0,0 +1,150 @@ +Mediatek AFE PCM controller for mt2701 + +Required properties: +- compatible = "mediatek,mt2701-audio"; +- reg: register location and size +- interrupts: Should contain AFE interrupt +- clock-names: should have these clock names: + "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + +Example: + + afe: mt2701-afe-pcm@11220000 { + compatible = "mediatek,mt2701-audio"; + reg = <0 0x11220000 0 0x2000>, + <0 0x112A0000 0 0x20000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, + <&topckgen CLK_TOP_APLL_SEL>, + <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>, + <&topckgen CLK_TOP_HADDS2PLL_98M>, + <&topckgen CLK_TOP_HADDS2PLL_294M>, + <&topckgen CLK_TOP_AUDPLL>, + <&topckgen CLK_TOP_AUDPLL_D4>, + <&topckgen CLK_TOP_AUDPLL_D8>, + <&topckgen CLK_TOP_AUDPLL_D16>, + <&topckgen CLK_TOP_AUDPLL_D24>, + <&topckgen CLK_TOP_AUDINTBUS_SEL>, + <&clk26m>, + <&topckgen CLK_TOP_SYSPLL1_D4>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&topckgen CLK_TOP_AUD_I2S5_MCLK>, + <&topckgen CLK_TOP_AUD_I2S6_MCLK>, + <&topckgen CLK_TOP_ASM_M_SEL>, + <&topckgen CLK_TOP_ASM_H_SEL>, + <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_UNIVPLL2_D2>, + <&topckgen CLK_TOP_SYSPLL_D5>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_mux1_div", + "top_audio_mux2_div", + "top_audio_48k_timing", + "top_audio_44k_timing", + "top_audpll_mux_sel", + "top_apll_sel", + "top_aud1_pll_98M", + "top_aud2_pll_90M", + "top_hadds2_pll_98M", + "top_hadds2_pll_294M", + "top_audpll", + "top_audpll_d4", + "top_audpll_d8", + "top_audpll_d16", + "top_audpll_d24", + "top_audintbus_sel", + "clk_26m", + "top_syspll1_d4", + "top_aud_k1_src_sel", + "top_aud_k2_src_sel", + "top_aud_k3_src_sel", + "top_aud_k4_src_sel", + "top_aud_k5_src_sel", + "top_aud_k6_src_sel", + "top_aud_k1_src_div", + "top_aud_k2_src_div", + "top_aud_k3_src_div", + "top_aud_k4_src_div", + "top_aud_k5_src_div", + "top_aud_k6_src_div", + "top_aud_i2s1_mclk", + "top_aud_i2s2_mclk", + "top_aud_i2s3_mclk", + "top_aud_i2s4_mclk", + "top_aud_i2s5_mclk", + "top_aud_i2s6_mclk", + "top_asm_m_sel", + "top_asm_h_sel", + "top_univpll2_d4", + "top_univpll2_d2", + "top_syspll_d5"; + }; diff --git a/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt new file mode 100644 index 000000000000..05574446ceb6 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt2701-cs42448.txt @@ -0,0 +1,43 @@ +MT2701 with CS42448 CODEC + +Required properties: +- compatible: "mediatek,mt2701-cs42448-machine" +- mediatek,platform: the phandle of MT2701 ASoC platform +- audio-routing: a list of the connections between audio +- mediatek,audio-codec: the phandles of cs42448 codec +- mediatek,audio-codec-bt-mrg the phandles of bt-sco dummy codec +- pinctrl-names: Should contain only one value - "default" +- pinctrl-0: Should specify pin control groups used for this controller. +- i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to + control I2S1-in mux. + +Example: + + sound:sound { + compatible = "mediatek,mt2701-cs42448-machine"; + mediatek,platform = <&afe>; + /* CS42448 Machine name */ + audio-routing = + "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "AMIC", + "AIN1R", "AMIC", + "AIN2L", "Tuner In", + "AIN2R", "Tuner In", + "AIN3L", "Satellite Tuner In", + "AIN3R", "Satellite Tuner In", + "AIN3L", "AUX In", + "AIN3R", "AUX In"; + mediatek,audio-codec = <&cs42448>; + mediatek,audio-codec-bt-mrg = <&bt_sco_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + i2s1-in-sel-gpio1 = <&pio 53 0>; + i2s1-in-sel-gpio2 = <&pio 54 0>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt index 5bfa6b60530b..29dce2ac8773 100644 --- a/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt +++ b/Documentation/devicetree/bindings/sound/mt8173-rt5650.txt @@ -1,8 +1,9 @@ -MT8173 with RT5650 CODECS +MT8173 with RT5650 CODECS and HDMI via I2S Required properties: - compatible : "mediatek,mt8173-rt5650" - mediatek,audio-codec: the phandles of rt5650 codecs + and of the hdmi encoder node - mediatek,platform: the phandle of MT8173 ASoC platform Optional subnodes: @@ -12,12 +13,17 @@ Required codec-capture subnode properties: <&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1) <&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2) +- mediatek,mclk: the MCLK source + 0 : external oscillator, MCLK = 12.288M + 1 : internal source from mt8173, MCLK = sampling rate*256 + Example: sound { compatible = "mediatek,mt8173-rt5650"; - mediatek,audio-codec = <&rt5650>; + mediatek,audio-codec = <&rt5650 &hdmi0>; mediatek,platform = <&afe>; + mediatek,mclk = <0>; codec-capture { sound-dai = <&rt5650 1>; }; diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt index 0741dff048dd..6f6c2f8e908d 100644 --- a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt +++ b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt @@ -8,6 +8,8 @@ Required properties: - interrupts: Interrupt number for McPDM - interrupt-parent: The parent interrupt controller - ti,hwmods: Name of the hwmod associated to the McPDM +- clocks: phandle for the pdmclk provider, likely <&twl6040> +- clock-names: Must be "pdmclk" Example: @@ -19,3 +21,11 @@ mcpdm: mcpdm@40132000 { interrupt-parent = <&gic>; ti,hwmods = "mcpdm"; }; + +In board DTS file the pdmclk needs to be added: + +&mcpdm { + clocks = <&twl6040>; + clock-names = "pdmclk"; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index c7b29df4a963..15a7316e4c91 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -373,6 +373,8 @@ Optional properties: - #clock-cells : it must be 0 if your system has audio_clkout it must be 1 if your system has audio_clkout0/1/2/3 - clock-frequency : for all audio_clkout0/1/2/3 +- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn + is asynchronizes with lr-clock. SSI subnode properties: - interrupts : Should contain SSI interrupt for PIO transfer diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt index 6e86d8aa29b4..4ea29aa9af59 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt +++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt @@ -23,6 +23,11 @@ Required properties: - rockchip,playback-channels: max playback channels, if not set, 8 channels default. - rockchip,capture-channels: max capture channels, if not set, 2 channels default. +Required properties for controller which support multi channels +playback/capture: + +- rockchip,grf: the phandle of the syscon node for GRF register. + Example for rk3288 I2S controller: i2s@ff890000 { diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt index e24436fc5ea9..9cabfc18cb57 100644 --- a/Documentation/devicetree/bindings/sound/rt5514.txt +++ b/Documentation/devicetree/bindings/sound/rt5514.txt @@ -8,6 +8,11 @@ Required properties: - reg : The I2C address of the device. +Optional properties: + +- clocks: The phandle of the master clock to the CODEC +- clock-names: Should be "mclk" + Pins on the device (for linking into audio routes) for RT5514: * DMIC1L diff --git a/Documentation/devicetree/bindings/sound/samsung,odroidx2-max98090.txt b/Documentation/devicetree/bindings/sound/samsung,odroidx2-max98090.txt deleted file mode 100644 index 9148f72319e1..000000000000 --- a/Documentation/devicetree/bindings/sound/samsung,odroidx2-max98090.txt +++ /dev/null @@ -1,35 +0,0 @@ -Samsung Exynos Odroid X2/U3 audio complex with MAX98090 codec - -Required properties: - - compatible : "samsung,odroidx2-audio" - for Odroid X2 board, - "samsung,odroidu3-audio" - for Odroid U3 board - - samsung,model : the user-visible name of this sound complex - - samsung,i2s-controller : the phandle of the I2S controller - - samsung,audio-codec : the phandle of the MAX98090 audio codec - - samsung,audio-routing : a list of the connections between audio - components; each entry is a pair of strings, the first being the - connection's sink, the second being the connection's source; - valid names for sources and sinks are the MAX98090's pins (as - documented in its binding), and the jacks on the board - For Odroid X2: - * Headphone Jack - * Mic Jack - * DMIC - - For Odroid U3: - * Headphone Jack - * Speakers - -Example: - -sound { - compatible = "samsung,odroidu3-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98090>; - samsung,model = "Odroid-X2"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; -}; diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 0e5e4eb3ef1b..5666da7b8605 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt @@ -7,6 +7,14 @@ Required properties: - clocks : the clock provider of SYS_MCLK +- VDDA-supply : the regulator provider of VDDA + +- VDDIO-supply: the regulator provider of VDDIO + +Optional properties: + +- VDDD-supply : the regulator provider of VDDD + - micbias-resistor-k-ohms : the bias resistor to be used in kOmhs The resistor can take values of 2k, 4k or 8k. If set to 0 it will be off. @@ -15,17 +23,9 @@ Required properties: - micbias-voltage-m-volts : the bias voltage to be used in mVolts The voltage can take values from 1.25V to 3V by 250mV steps - If this node is not mentionned or the value is unknown, then + If this node is not mentioned or the value is unknown, then the value is set to 1.25V. -- VDDA-supply : the regulator provider of VDDA - -- VDDIO-supply: the regulator provider of VDDIO - -Optional properties: - -- VDDD-supply : the regulator provider of VDDD - Example: codec: sgtl5000@0a { diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index cf3979eb3578..59d862801e59 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt @@ -30,7 +30,7 @@ Optional subnodes: sub-nodes. This container may be omitted when the card has only one DAI link. See the examples and the - section bellow. + section below. Dai-link subnode properties and subnodes: diff --git a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt index 4d9a83d9a017..16bcdfb6760e 100644 --- a/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt @@ -33,11 +33,11 @@ Required properties: "tx" for "st,sti-uni-player" compatibility "rx" for "st,sti-uni-reader" compatibility - - version: IP version integrated in SOC. + - st,version: IP version integrated in SOC. - dai-name: DAI name that describes the IP. - - IP mode: IP working mode depending on associated codec. + - st,mode: IP working mode depending on associated codec. "HDMI" connected to HDMI codec and support IEC HDMI formats (player only). "SPDIF" connected to SPDIF codec and support SPDIF formats (player only). "PCM" PCM standard mode for I2S or TDM bus. @@ -47,7 +47,7 @@ Required properties ("st,sti-uni-player" compatibility only): - clocks: CPU_DAI IP clock source, listed in the same order than the CPU_DAI properties. - - uniperiph-id: internal SOC IP instance ID. + - st,uniperiph-id: internal SOC IP instance ID. Optional properties: - pinctrl-0: defined for CPU_DAI@1 and CPU_DAI@4 to describe I2S PIOs for @@ -84,9 +84,9 @@ Example: dmas = <&fdma0 4 0 1>; dai-name = "Uni Player #2 (DAC)"; dma-names = "tx"; - uniperiph-id = <2>; - version = <5>; - mode = "PCM"; + st,uniperiph-id = <2>; + st,version = <5>; + st,mode = "PCM"; }; sti_uni_player3: sti-uni-player@3 { @@ -100,9 +100,9 @@ Example: dmas = <&fdma0 7 0 1>; dma-names = "tx"; dai-name = "Uni Player #3 (SPDIF)"; - uniperiph-id = <3>; - version = <5>; - mode = "SPDIF"; + st,uniperiph-id = <3>; + st,version = <5>; + st,mode = "SPDIF"; }; sti_uni_reader1: sti-uni-reader@1 { @@ -115,7 +115,7 @@ Example: dmas = <&fdma0 6 0 1>; dma-names = "rx"; dai-name = "Uni Reader #1 (HDMI RX)"; - version = <3>; + st,version = <3>; st,mode = "PCM"; }; diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt new file mode 100644 index 000000000000..7b526ec64991 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt @@ -0,0 +1,34 @@ +* Allwinner A10 I2S controller + +The I2S bus (Inter-IC sound bus) is a serial link for digital +audio data transfer between devices in the system. + +Required properties: + +- compatible: should be one of the followings + - "allwinner,sun4i-a10-i2s" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: should contain the I2S interrupt. +- dmas: DMA specifiers for tx and rx dma. See the DMA client binding, + Documentation/devicetree/bindings/dma/dma.txt +- dma-names: should include "tx" and "rx". +- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names. +- clock-names: should contain followings: + - "apb" : clock for the I2S bus interface + - "mod" : module clock for the I2S controller +- #sound-dai-cells : Must be equal to 0 + +Example: + +i2s0: i2s@01c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + clock-names = "apb", "mod"; + dmas = <&dma SUN4I_DMA_NORMAL 3>, + <&dma SUN4I_DMA_NORMAL 3>; + dma-names = "rx", "tx"; +}; diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt index 27cfc7d7ccd7..8d6e4fd2468e 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt @@ -9,7 +9,7 @@ Required properties: one) - clocks: phandle to the source clock (usually the AHB clock) -Optionnal properties: +Optional properties: - resets: phandle to a reset controller asserting the timer Example: diff --git a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt index cd55b52548e4..d4c62e7b1714 100644 --- a/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt +++ b/Documentation/devicetree/bindings/timer/cirrus,clps711x-timer.txt @@ -1,7 +1,7 @@ * Cirrus Logic CLPS711X Timer Counter Required properties: -- compatible: Shall contain "cirrus,clps711x-timer". +- compatible: Shall contain "cirrus,ep7209-timer". - reg : Address and length of the register set. - interrupts: The interrupt number of the timer. - clocks : phandle of timer reference clock. @@ -15,14 +15,14 @@ Example: }; timer1: timer@80000300 { - compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer"; + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; reg = <0x80000300 0x4>; interrupts = <8>; clocks = <&clks 5>; }; timer2: timer@80000340 { - compatible = "cirrus,ep7312-timer", "cirrus,clps711x-timer"; + compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer"; reg = <0x80000340 0x4>; interrupts = <9>; clocks = <&clks 6>; diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 5883b73ea1b5..f4262ed60582 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -113,13 +113,13 @@ usb2: gadget@fff78000 { clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; - ep0 { + ep@0 { reg = <0>; atmel,fifo-size = <64>; atmel,nb-banks = <1>; }; - ep1 { + ep@1 { reg = <1>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -127,7 +127,7 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep2 { + ep@2 { reg = <2>; atmel,fifo-size = <1024>; atmel,nb-banks = <2>; @@ -135,21 +135,21 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep3 { + ep@3 { reg = <3>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep4 { + ep@4 { reg = <4>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; atmel,can-dma; }; - ep5 { + ep@5 { reg = <5>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; @@ -157,7 +157,7 @@ usb2: gadget@fff78000 { atmel,can-isoc; }; - ep6 { + ep@6 { reg = <6>; atmel,fifo-size = <1024>; atmel,nb-banks = <3>; diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index d28295a3e55f..3eee9e505400 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -104,10 +104,10 @@ Example: nvidia,xusb-padctl = <&padctl>; - phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */ - <&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */ - <&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */ - phy-names = "utmi-1", "utmi-2", "usb3-0"; + phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */ + <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */ + <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */ + phy-names = "usb2-1", "usb2-2", "usb3-0"; avddio-pex-supply = <&vdd_1v05_run>; dvddio-pex-supply = <&vdd_1v05_run>; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index d2bce2239769..1992aa97d45a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -128,6 +128,7 @@ idt Integrated Device Technologies, Inc. ifi Ingenieurburo Fur Ic-Technologie (I/F/I) iom Iomega Corporation img Imagination Technologies Ltd. +infineon Infineon Technologies inforce Inforce Computing ingenic Ingenic Semiconductor innolux Innolux Corporation @@ -237,6 +238,7 @@ simtek sii Seiko Instruments, Inc. silergy Silergy Corp. sirf SiRF Technology, Inc. +sis Silicon Integrated Systems Corp. sitronix Sitronix Technology Corporation skyworks Skyworks Solutions, Inc. smsc Standard Microsystems Corporation @@ -248,6 +250,7 @@ sony Sony Corporation spansion Spansion Inc. sprd Spreadtrum Communications Inc. st STMicroelectronics +starry Starry Electronic Technology (ShenZhen) Co., LTD startek Startek ste ST-Ericsson stericsson ST-Ericsson @@ -255,6 +258,7 @@ syna Synaptics Inc. synology Synology, Inc. SUNW Sun Microsystems, Inc tbs TBS Technologies +tcg Trusted Computing Group tcl Toby Churchill Ltd. technexion TechNexion technologic Technologic Systems diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt new file mode 100644 index 000000000000..c5e74d7b4406 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt @@ -0,0 +1,16 @@ +Aspeed Watchdog Timer + +Required properties: + - compatible: must be one of: + - "aspeed,ast2400-wdt" + - "aspeed,ast2500-wdt" + + - reg: physical base address of the controller and length of memory mapped + region + +Example: + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2400-wdt"; + reg = <0x1e785000 0x1c>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt new file mode 100644 index 000000000000..c7fe36fa739c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt @@ -0,0 +1,16 @@ +Meson GXBB SoCs Watchdog timer + +Required properties: + +- compatible : should be "amlogic,meson-gxbb-wdt" +- reg : Specifies base physical address and size of the registers. +- clocks : Should be a phandle to the Watchdog clock source, for GXBB the xtal + is the default clock source. + +Example: + +wdt: watchdog@98d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0 0x98d0 0x0 0x10>; + clocks = <&xtal>; +}; diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt index 4726924d034e..41aeaa2ff0f8 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt @@ -7,6 +7,10 @@ Required properties : "qcom,kpss-wdt-msm8960" "qcom,kpss-wdt-apq8064" "qcom,kpss-wdt-ipq8064" + "qcom,kpss-wdt-ipq4019" + "qcom,kpss-timer" + "qcom,scss-timer" + "qcom,kpss-wdt" - reg : shall contain base register location and length - clocks : shall contain the input clock diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt index b9512f1eb80a..da24e3133417 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt @@ -1,7 +1,11 @@ Renesas Watchdog Timer (WDT) Controller Required properties: -- compatible : Should be "renesas,r8a7795-wdt", or "renesas,rcar-gen3-wdt" +- compatible : Should be "renesas,<soctype>-wdt", and + "renesas,rcar-gen3-wdt" as fallback. + Examples with soctypes are: + - "renesas,r8a7795-wdt" (R-Car H3) + - "renesas,r8a7796-wdt" (R-Car M3-W) When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first, followed by the generic diff --git a/Documentation/dontdiff b/Documentation/dontdiff index 8ea834f6b289..5385cba941d2 100644 --- a/Documentation/dontdiff +++ b/Documentation/dontdiff @@ -3,6 +3,7 @@ *.bc *.bin *.bz2 +*.c.[012]*.* *.cis *.cpio *.csp diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index c63eea0c1c8c..b0d775d28e97 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -352,8 +352,15 @@ REGULATOR devm_regulator_put() devm_regulator_register() +RESET + devm_reset_control_get() + devm_reset_controller_register() + SLAVE DMA ENGINE devm_acpi_dma_controller_register() SPI devm_spi_register_master() + +WATCHDOG + devm_watchdog_register_device() diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking index 5a7386e38e2d..1b3c39a7de62 100644 --- a/Documentation/filesystems/Locking +++ b/Documentation/filesystems/Locking @@ -15,11 +15,14 @@ prototypes: int (*d_compare)(const struct dentry *, const struct dentry *, unsigned int, const char *, const struct qstr *); int (*d_delete)(struct dentry *); + int (*d_init)(struct dentry *); void (*d_release)(struct dentry *); void (*d_iput)(struct dentry *, struct inode *); char *(*d_dname)((struct dentry *dentry, char *buffer, int buflen); struct vfsmount *(*d_automount)(struct path *path); int (*d_manage)(struct dentry *, bool); + struct dentry *(*d_real)(struct dentry *, const struct inode *, + unsigned int); locking rules: rename_lock ->d_lock may block rcu-walk @@ -28,12 +31,14 @@ d_weak_revalidate:no no yes no d_hash no no no maybe d_compare: yes no no maybe d_delete: no yes no no +d_init: no no yes no d_release: no no yes no d_prune: no yes no no d_iput: no no yes no d_dname: no no no no d_automount: no no yes no d_manage: no no yes (ref-walk) maybe +d_real no no yes no --------------------------- inode_operations --------------------------- prototypes: @@ -66,7 +71,6 @@ prototypes: struct file *, unsigned open_flag, umode_t create_mode, int *opened); int (*tmpfile) (struct inode *, struct dentry *, umode_t); - int (*dentry_open)(struct dentry *, struct file *, const struct cred *); locking rules: all may block @@ -95,7 +99,6 @@ fiemap: no update_time: no atomic_open: yes tmpfile: no -dentry_open: no Additionally, ->rmdir(), ->unlink() and ->rename() have ->i_mutex on victim. @@ -179,7 +182,6 @@ unlocks and drops the reference. prototypes: int (*writepage)(struct page *page, struct writeback_control *wbc); int (*readpage)(struct file *, struct page *); - int (*sync_page)(struct page *); int (*writepages)(struct address_space *, struct writeback_control *); int (*set_page_dirty)(struct page *page); int (*readpages)(struct file *filp, struct address_space *mapping, @@ -210,7 +212,6 @@ locking rules: PageLocked(page) i_mutex writepage: yes, unlocks (see below) readpage: yes, unlocks -sync_page: maybe writepages: set_page_dirty no readpages: @@ -230,8 +231,8 @@ error_remove_page: yes swap_activate: no swap_deactivate: no - ->write_begin(), ->write_end(), ->sync_page() and ->readpage() -may be called from the request handler (/dev/loop). + ->write_begin(), ->write_end() and ->readpage() may be called from +the request handler (/dev/loop). ->readpage() unlocks the page, either synchronously or via I/O completion. @@ -287,11 +288,6 @@ will leave the page itself marked clean but it will be tagged as dirty in the radix tree. This incoherency can lead to all sorts of hard-to-debug problems in the filesystem like having dirty inodes at umount and losing written data. - ->sync_page() locking rules are not well-defined - usually it is called -with lock on page, but that is not guaranteed. Considering the currently -existing instances of this method ->sync_page() itself doesn't look -well-defined... - ->writepages() is used for periodic writeback and for syscall-initiated sync operations. The address_space should start I/O against at least *nr_to_write pages. *nr_to_write must be decremented for each page which is @@ -399,7 +395,7 @@ prototypes: int (*release) (struct gendisk *, fmode_t); int (*ioctl) (struct block_device *, fmode_t, unsigned, unsigned long); int (*compat_ioctl) (struct block_device *, fmode_t, unsigned, unsigned long); - int (*direct_access) (struct block_device *, sector_t, void __pmem **, + int (*direct_access) (struct block_device *, sector_t, void **, unsigned long *); int (*media_changed) (struct gendisk *); void (*unlock_native_capacity) (struct gendisk *); diff --git a/Documentation/filesystems/nilfs2.txt b/Documentation/filesystems/nilfs2.txt index 5b21ef76f751..c0727dc36271 100644 --- a/Documentation/filesystems/nilfs2.txt +++ b/Documentation/filesystems/nilfs2.txt @@ -267,7 +267,8 @@ among NILFS2 files can be depicted as follows: `-- file (ino=yy) ( regular file, directory, or symlink ) -For detail on the format of each file, please see include/linux/nilfs2_fs.h. +For detail on the format of each file, please see nilfs2_ondisk.h +located at include/uapi/linux directory. There are no patents or other intellectual property that we protect with regard to the design of NILFS2. It is allowed to replicate the diff --git a/Documentation/filesystems/orangefs.txt b/Documentation/filesystems/orangefs.txt index e1a0056a365f..1dfdec790946 100644 --- a/Documentation/filesystems/orangefs.txt +++ b/Documentation/filesystems/orangefs.txt @@ -281,7 +281,7 @@ on the wait queue and one attempt is made to recycle them. Obviously, if the client-core stays dead too long, the arbitrary userspace processes trying to use Orangefs will be negatively affected. Waiting ops that can't be serviced will be removed from the request list and -have their states set to "given up". In-progress ops that can't +have their states set to "given up". In-progress ops that can't be serviced will be removed from the in_progress hash table and have their states set to "given up". @@ -338,7 +338,7 @@ particular response. PVFS2_VFS_OP_STATFS fill a pvfs2_statfs_response_t with useless info <g>. It is hard for us to know, in a timely fashion, these statistics about our - distributed network filesystem. + distributed network filesystem. PVFS2_VFS_OP_FS_MOUNT fill a pvfs2_fs_mount_response_t which is just like a PVFS_object_kref @@ -386,7 +386,7 @@ responses: io_array[1].iov_base = address of global variable "pdev_magic" (int32_t) io_array[1].iov_len = sizeof(int32_t) - + io_array[2].iov_base = address of parameter "tag" (PVFS_id_gen_t) io_array[2].iov_len = sizeof(int64_t) @@ -402,5 +402,47 @@ Readdir responses initialize the fifth element io_array like this: io_array[4].iov_len = contents of member trailer_size (PVFS_size) from out_downcall member of global variable vfs_request - + +Orangefs exploits the dcache in order to avoid sending redundant +requests to userspace. We keep object inode attributes up-to-date with +orangefs_inode_getattr. Orangefs_inode_getattr uses two arguments to +help it decide whether or not to update an inode: "new" and "bypass". +Orangefs keeps private data in an object's inode that includes a short +timeout value, getattr_time, which allows any iteration of +orangefs_inode_getattr to know how long it has been since the inode was +updated. When the object is not new (new == 0) and the bypass flag is not +set (bypass == 0) orangefs_inode_getattr returns without updating the inode +if getattr_time has not timed out. Getattr_time is updated each time the +inode is updated. + +Creation of a new object (file, dir, sym-link) includes the evaluation of +its pathname, resulting in a negative directory entry for the object. +A new inode is allocated and associated with the dentry, turning it from +a negative dentry into a "productive full member of society". Orangefs +obtains the new inode from Linux with new_inode() and associates +the inode with the dentry by sending the pair back to Linux with +d_instantiate(). + +The evaluation of a pathname for an object resolves to its corresponding +dentry. If there is no corresponding dentry, one is created for it in +the dcache. Whenever a dentry is modified or verified Orangefs stores a +short timeout value in the dentry's d_time, and the dentry will be trusted +for that amount of time. Orangefs is a network filesystem, and objects +can potentially change out-of-band with any particular Orangefs kernel module +instance, so trusting a dentry is risky. The alternative to trusting +dentries is to always obtain the needed information from userspace - at +least a trip to the client-core, maybe to the servers. Obtaining information +from a dentry is cheap, obtaining it from userspace is relatively expensive, +hence the motivation to use the dentry when possible. + +The timeout values d_time and getattr_time are jiffy based, and the +code is designed to avoid the jiffy-wrap problem: + +"In general, if the clock may have wrapped around more than once, there +is no way to tell how much time has elapsed. However, if the times t1 +and t2 are known to be fairly close, we can reliably compute the +difference in a way that takes into account the possibility that the +clock may have wrapped between times." + + from course notes by instructor Andy Wang diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt index 900360cbcdae..8a196851f01d 100644 --- a/Documentation/filesystems/vfs.txt +++ b/Documentation/filesystems/vfs.txt @@ -364,7 +364,6 @@ struct inode_operations { int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned open_flag, umode_t create_mode, int *opened); int (*tmpfile) (struct inode *, struct dentry *, umode_t); - int (*dentry_open)(struct dentry *, struct file *, const struct cred *); }; Again, all methods are called without any locks being held, unless @@ -534,9 +533,7 @@ __sync_single_inode) to check if ->writepages has been successful in writing out the whole address_space. The Writeback tag is used by filemap*wait* and sync_page* functions, -via filemap_fdatawait_range, to wait for all writeback to -complete. While waiting ->sync_page (if defined) will be called on -each page that is found to require writeback. +via filemap_fdatawait_range, to wait for all writeback to complete. An address_space handler may attach extra information to a page, typically using the 'private' field in the 'struct page'. If such @@ -554,8 +551,8 @@ address_space has finer control of write sizes. The read process essentially only requires 'readpage'. The write process is more complicated and uses write_begin/write_end or -set_page_dirty to write data into the address_space, and writepage, -sync_page, and writepages to writeback data to storage. +set_page_dirty to write data into the address_space, and writepage +and writepages to writeback data to storage. Adding and removing pages to/from an address_space is protected by the inode's i_mutex. @@ -701,13 +698,6 @@ struct address_space_operations { but instead uses bmap to find out where the blocks in the file are and uses those addresses directly. - dentry_open: *WARNING: probably going away soon, do not use!* This is an - alternative to f_op->open(), the difference is that this method may open - a file not necessarily originating from the same filesystem as the one - i_op->open() was called on. It may be useful for stacking filesystems - which want to allow native I/O directly on underlying files. - - invalidatepage: If a page has PagePrivate set, then invalidatepage will be called when part or all of the page is to be removed from the address space. This generally corresponds to either a @@ -944,11 +934,14 @@ struct dentry_operations { int (*d_compare)(const struct dentry *, const struct dentry *, unsigned int, const char *, const struct qstr *); int (*d_delete)(const struct dentry *); + int (*d_init)(struct dentry *); void (*d_release)(struct dentry *); void (*d_iput)(struct dentry *, struct inode *); char *(*d_dname)(struct dentry *, char *, int); struct vfsmount *(*d_automount)(struct path *); int (*d_manage)(struct dentry *, bool); + struct dentry *(*d_real)(struct dentry *, const struct inode *, + unsigned int); }; d_revalidate: called when the VFS needs to revalidate a dentry. This @@ -1014,6 +1007,8 @@ struct dentry_operations { always cache a reachable dentry. d_delete must be constant and idempotent. + d_init: called when a dentry is allocated + d_release: called when a dentry is really deallocated d_iput: called when a dentry loses its inode (just prior to its @@ -1033,6 +1028,14 @@ struct dentry_operations { at the end of the buffer, and returns a pointer to the first char. dynamic_dname() helper function is provided to take care of this. + Example : + + static char *pipefs_dname(struct dentry *dent, char *buffer, int buflen) + { + return dynamic_dname(dentry, buffer, buflen, "pipe:[%lu]", + dentry->d_inode->i_ino); + } + d_automount: called when an automount dentry is to be traversed (optional). This should create a new VFS mount record and return the record to the caller. The caller is supplied with a path parameter giving the @@ -1071,13 +1074,23 @@ struct dentry_operations { This function is only used if DCACHE_MANAGE_TRANSIT is set on the dentry being transited from. -Example : + d_real: overlay/union type filesystems implement this method to return one of + the underlying dentries hidden by the overlay. It is used in three + different modes: -static char *pipefs_dname(struct dentry *dent, char *buffer, int buflen) -{ - return dynamic_dname(dentry, buffer, buflen, "pipe:[%lu]", - dentry->d_inode->i_ino); -} + Called from open it may need to copy-up the file depending on the + supplied open flags. This mode is selected with a non-zero flags + argument. In this mode the d_real method can return an error. + + Called from file_dentry() it returns the real dentry matching the inode + argument. The real dentry may be from a lower layer already copied up, + but still referenced from the file. This mode is selected with a + non-NULL inode argument. This will always succeed. + + With NULL inode and zero flags the topmost real underlying dentry is + returned. This will always succeed. + + This method is never called with both non-NULL inode and non-zero flags. Each dentry has a pointer to its parent dentry, as well as a hash list of child dentries. Child dentries are basically like files in a diff --git a/Documentation/gcc-plugins.txt b/Documentation/gcc-plugins.txt new file mode 100644 index 000000000000..891c69464434 --- /dev/null +++ b/Documentation/gcc-plugins.txt @@ -0,0 +1,87 @@ +GCC plugin infrastructure +========================= + + +1. Introduction +=============== + +GCC plugins are loadable modules that provide extra features to the +compiler [1]. They are useful for runtime instrumentation and static analysis. +We can analyse, change and add further code during compilation via +callbacks [2], GIMPLE [3], IPA [4] and RTL passes [5]. + +The GCC plugin infrastructure of the kernel supports all gcc versions from +4.5 to 6.0, building out-of-tree modules, cross-compilation and building in a +separate directory. +Plugin source files have to be compilable by both a C and a C++ compiler as well +because gcc versions 4.5 and 4.6 are compiled by a C compiler, +gcc-4.7 can be compiled by a C or a C++ compiler, +and versions 4.8+ can only be compiled by a C++ compiler. + +Currently the GCC plugin infrastructure supports only the x86, arm and arm64 +architectures. + +This infrastructure was ported from grsecurity [6] and PaX [7]. + +-- +[1] https://gcc.gnu.org/onlinedocs/gccint/Plugins.html +[2] https://gcc.gnu.org/onlinedocs/gccint/Plugin-API.html#Plugin-API +[3] https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html +[4] https://gcc.gnu.org/onlinedocs/gccint/IPA.html +[5] https://gcc.gnu.org/onlinedocs/gccint/RTL.html +[6] https://grsecurity.net/ +[7] https://pax.grsecurity.net/ + + +2. Files +======== + +$(src)/scripts/gcc-plugins + This is the directory of the GCC plugins. + +$(src)/scripts/gcc-plugins/gcc-common.h + This is a compatibility header for GCC plugins. + It should be always included instead of individual gcc headers. + +$(src)/scripts/gcc-plugin.sh + This script checks the availability of the included headers in + gcc-common.h and chooses the proper host compiler to build the plugins + (gcc-4.7 can be built by either gcc or g++). + +$(src)/scripts/gcc-plugins/gcc-generate-gimple-pass.h +$(src)/scripts/gcc-plugins/gcc-generate-ipa-pass.h +$(src)/scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h +$(src)/scripts/gcc-plugins/gcc-generate-rtl-pass.h + These headers automatically generate the registration structures for + GIMPLE, SIMPLE_IPA, IPA and RTL passes. They support all gcc versions + from 4.5 to 6.0. + They should be preferred to creating the structures by hand. + + +3. Usage +======== + +You must install the gcc plugin headers for your gcc version, +e.g., on Ubuntu for gcc-4.9: + + apt-get install gcc-4.9-plugin-dev + +Enable a GCC plugin based feature in the kernel config: + + CONFIG_GCC_PLUGIN_CYC_COMPLEXITY = y + +To compile only the plugin(s): + + make gcc-plugins + +or just run the kernel make and compile the whole kernel with +the cyclomatic complexity GCC plugin. + + +4. How to add a new GCC plugin +============================== + +The GCC plugins are in $(src)/scripts/gcc-plugins/. You can use a file or a directory +here. It must be added to $(src)/scripts/gcc-plugins/Makefile, +$(src)/scripts/Makefile.gcc-plugins and $(src)/arch/Kconfig. +See the cyc_complexity_plugin.c (CONFIG_GCC_PLUGIN_CYC_COMPLEXITY) GCC plugin. diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst new file mode 100644 index 000000000000..3bb26135971f --- /dev/null +++ b/Documentation/gpu/drm-internals.rst @@ -0,0 +1,381 @@ +============= +DRM Internals +============= + +This chapter documents DRM internals relevant to driver authors and +developers working to add support for the latest features to existing +drivers. + +First, we go over some typical driver initialization requirements, like +setting up command buffers, creating an initial output configuration, +and initializing core services. Subsequent sections cover core internals +in more detail, providing implementation notes and examples. + +The DRM layer provides several services to graphics drivers, many of +them driven by the application interfaces it provides through libdrm, +the library that wraps most of the DRM ioctls. These include vblank +event handling, memory management, output management, framebuffer +management, command submission & fencing, suspend/resume support, and +DMA services. + +Driver Initialization +===================== + +At the core of every DRM driver is a :c:type:`struct drm_driver +<drm_driver>` structure. Drivers typically statically initialize +a drm_driver structure, and then pass it to +:c:func:`drm_dev_alloc()` to allocate a device instance. After the +device instance is fully initialized it can be registered (which makes +it accessible from userspace) using :c:func:`drm_dev_register()`. + +The :c:type:`struct drm_driver <drm_driver>` structure +contains static information that describes the driver and features it +supports, and pointers to methods that the DRM core will call to +implement the DRM API. We will first go through the :c:type:`struct +drm_driver <drm_driver>` static information fields, and will +then describe individual operations in details as they get used in later +sections. + +Driver Information +------------------ + +Driver Features +~~~~~~~~~~~~~~~ + +Drivers inform the DRM core about their requirements and supported +features by setting appropriate flags in the driver_features field. +Since those flags influence the DRM core behaviour since registration +time, most of them must be set to registering the :c:type:`struct +drm_driver <drm_driver>` instance. + +u32 driver_features; + +DRIVER_USE_AGP + Driver uses AGP interface, the DRM core will manage AGP resources. + +DRIVER_REQUIRE_AGP + Driver needs AGP interface to function. AGP initialization failure + will become a fatal error. + +DRIVER_PCI_DMA + Driver is capable of PCI DMA, mapping of PCI DMA buffers to + userspace will be enabled. Deprecated. + +DRIVER_SG + Driver can perform scatter/gather DMA, allocation and mapping of + scatter/gather buffers will be enabled. Deprecated. + +DRIVER_HAVE_DMA + Driver supports DMA, the userspace DMA API will be supported. + Deprecated. + +DRIVER_HAVE_IRQ; DRIVER_IRQ_SHARED + DRIVER_HAVE_IRQ indicates whether the driver has an IRQ handler + managed by the DRM Core. The core will support simple IRQ handler + installation when the flag is set. The installation process is + described in ?. + + DRIVER_IRQ_SHARED indicates whether the device & handler support + shared IRQs (note that this is required of PCI drivers). + +DRIVER_GEM + Driver use the GEM memory manager. + +DRIVER_MODESET + Driver supports mode setting interfaces (KMS). + +DRIVER_PRIME + Driver implements DRM PRIME buffer sharing. + +DRIVER_RENDER + Driver supports dedicated render nodes. + +DRIVER_ATOMIC + Driver supports atomic properties. In this case the driver must + implement appropriate obj->atomic_get_property() vfuncs for any + modeset objects with driver specific properties. + +Major, Minor and Patchlevel +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +int major; int minor; int patchlevel; +The DRM core identifies driver versions by a major, minor and patch +level triplet. The information is printed to the kernel log at +initialization time and passed to userspace through the +DRM_IOCTL_VERSION ioctl. + +The major and minor numbers are also used to verify the requested driver +API version passed to DRM_IOCTL_SET_VERSION. When the driver API +changes between minor versions, applications can call +DRM_IOCTL_SET_VERSION to select a specific version of the API. If the +requested major isn't equal to the driver major, or the requested minor +is larger than the driver minor, the DRM_IOCTL_SET_VERSION call will +return an error. Otherwise the driver's set_version() method will be +called with the requested version. + +Name, Description and Date +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +char \*name; char \*desc; char \*date; +The driver name is printed to the kernel log at initialization time, +used for IRQ registration and passed to userspace through +DRM_IOCTL_VERSION. + +The driver description is a purely informative string passed to +userspace through the DRM_IOCTL_VERSION ioctl and otherwise unused by +the kernel. + +The driver date, formatted as YYYYMMDD, is meant to identify the date of +the latest modification to the driver. However, as most drivers fail to +update it, its value is mostly useless. The DRM core prints it to the +kernel log at initialization time and passes it to userspace through the +DRM_IOCTL_VERSION ioctl. + +Device Instance and Driver Handling +----------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_drv.c + :doc: driver instance overview + +.. kernel-doc:: drivers/gpu/drm/drm_drv.c + :export: + +Driver Load +----------- + +IRQ Registration +~~~~~~~~~~~~~~~~ + +The DRM core tries to facilitate IRQ handler registration and +unregistration by providing :c:func:`drm_irq_install()` and +:c:func:`drm_irq_uninstall()` functions. Those functions only +support a single interrupt per device, devices that use more than one +IRQs need to be handled manually. + +Managed IRQ Registration +'''''''''''''''''''''''' + +:c:func:`drm_irq_install()` starts by calling the irq_preinstall +driver operation. The operation is optional and must make sure that the +interrupt will not get fired by clearing all pending interrupt flags or +disabling the interrupt. + +The passed-in IRQ will then be requested by a call to +:c:func:`request_irq()`. If the DRIVER_IRQ_SHARED driver feature +flag is set, a shared (IRQF_SHARED) IRQ handler will be requested. + +The IRQ handler function must be provided as the mandatory irq_handler +driver operation. It will get passed directly to +:c:func:`request_irq()` and thus has the same prototype as all IRQ +handlers. It will get called with a pointer to the DRM device as the +second argument. + +Finally the function calls the optional irq_postinstall driver +operation. The operation usually enables interrupts (excluding the +vblank interrupt, which is enabled separately), but drivers may choose +to enable/disable interrupts at a different time. + +:c:func:`drm_irq_uninstall()` is similarly used to uninstall an +IRQ handler. It starts by waking up all processes waiting on a vblank +interrupt to make sure they don't hang, and then calls the optional +irq_uninstall driver operation. The operation must disable all hardware +interrupts. Finally the function frees the IRQ by calling +:c:func:`free_irq()`. + +Manual IRQ Registration +''''''''''''''''''''''' + +Drivers that require multiple interrupt handlers can't use the managed +IRQ registration functions. In that case IRQs must be registered and +unregistered manually (usually with the :c:func:`request_irq()` and +:c:func:`free_irq()` functions, or their :c:func:`devm_request_irq()` and +:c:func:`devm_free_irq()` equivalents). + +When manually registering IRQs, drivers must not set the +DRIVER_HAVE_IRQ driver feature flag, and must not provide the +irq_handler driver operation. They must set the :c:type:`struct +drm_device <drm_device>` irq_enabled field to 1 upon +registration of the IRQs, and clear it to 0 after unregistering the +IRQs. + +Memory Manager Initialization +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Every DRM driver requires a memory manager which must be initialized at +load time. DRM currently contains two memory managers, the Translation +Table Manager (TTM) and the Graphics Execution Manager (GEM). This +document describes the use of the GEM memory manager only. See ? for +details. + +Miscellaneous Device Configuration +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Another task that may be necessary for PCI devices during configuration +is mapping the video BIOS. On many devices, the VBIOS describes device +configuration, LCD panel timings (if any), and contains flags indicating +device state. Mapping the BIOS can be done using the pci_map_rom() +call, a convenience function that takes care of mapping the actual ROM, +whether it has been shadowed into memory (typically at address 0xc0000) +or exists on the PCI device in the ROM BAR. Note that after the ROM has +been mapped and any necessary information has been extracted, it should +be unmapped; on many devices, the ROM address decoder is shared with +other BARs, so leaving it mapped could cause undesired behaviour like +hangs or memory corruption. + +Bus-specific Device Registration and PCI Support +------------------------------------------------ + +A number of functions are provided to help with device registration. The +functions deal with PCI and platform devices respectively and are only +provided for historical reasons. These are all deprecated and shouldn't +be used in new drivers. Besides that there's a few helpers for pci +drivers. + +.. kernel-doc:: drivers/gpu/drm/drm_pci.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_platform.c + :export: + +Open/Close, File Operations and IOCTLs +====================================== + +Open and Close +-------------- + +Open and close handlers. None of those methods are mandatory:: + + int (*firstopen) (struct drm_device *); + void (*lastclose) (struct drm_device *); + int (*open) (struct drm_device *, struct drm_file *); + void (*preclose) (struct drm_device *, struct drm_file *); + void (*postclose) (struct drm_device *, struct drm_file *); + +The firstopen method is called by the DRM core for legacy UMS (User Mode +Setting) drivers only when an application opens a device that has no +other opened file handle. UMS drivers can implement it to acquire device +resources. KMS drivers can't use the method and must acquire resources +in the load method instead. + +Similarly the lastclose method is called when the last application +holding a file handle opened on the device closes it, for both UMS and +KMS drivers. Additionally, the method is also called at module unload +time or, for hot-pluggable devices, when the device is unplugged. The +firstopen and lastclose calls can thus be unbalanced. + +The open method is called every time the device is opened by an +application. Drivers can allocate per-file private data in this method +and store them in the struct :c:type:`struct drm_file +<drm_file>` driver_priv field. Note that the open method is +called before firstopen. + +The close operation is split into preclose and postclose methods. +Drivers must stop and cleanup all per-file operations in the preclose +method. For instance pending vertical blanking and page flip events must +be cancelled. No per-file operation is allowed on the file handle after +returning from the preclose method. + +Finally the postclose method is called as the last step of the close +operation, right before calling the lastclose method if no other open +file handle exists for the device. Drivers that have allocated per-file +private data in the open method should free it here. + +The lastclose method should restore CRTC and plane properties to default +value, so that a subsequent open of the device will not inherit state +from the previous user. It can also be used to execute delayed power +switching state changes, e.g. in conjunction with the :ref:`vga_switcheroo` +infrastructure. Beyond that KMS drivers should not do any +further cleanup. Only legacy UMS drivers might need to clean up device +state so that the vga console or an independent fbdev driver could take +over. + +File Operations +--------------- + +.. kernel-doc:: drivers/gpu/drm/drm_fops.c + :doc: file operations + +.. kernel-doc:: drivers/gpu/drm/drm_fops.c + :export: + +IOCTLs +------ + +struct drm_ioctl_desc \*ioctls; int num_ioctls; + Driver-specific ioctls descriptors table. + +Driver-specific ioctls numbers start at DRM_COMMAND_BASE. The ioctls +descriptors table is indexed by the ioctl number offset from the base +value. Drivers can use the DRM_IOCTL_DEF_DRV() macro to initialize +the table entries. + +:: + + DRM_IOCTL_DEF_DRV(ioctl, func, flags) + +``ioctl`` is the ioctl name. Drivers must define the DRM_##ioctl and +DRM_IOCTL_##ioctl macros to the ioctl number offset from +DRM_COMMAND_BASE and the ioctl number respectively. The first macro is +private to the device while the second must be exposed to userspace in a +public header. + +``func`` is a pointer to the ioctl handler function compatible with the +``drm_ioctl_t`` type. + +:: + + typedef int drm_ioctl_t(struct drm_device *dev, void *data, + struct drm_file *file_priv); + +``flags`` is a bitmask combination of the following values. It restricts +how the ioctl is allowed to be called. + +- DRM_AUTH - Only authenticated callers allowed + +- DRM_MASTER - The ioctl can only be called on the master file handle + +- DRM_ROOT_ONLY - Only callers with the SYSADMIN capability allowed + +- DRM_CONTROL_ALLOW - The ioctl can only be called on a control + device + +- DRM_UNLOCKED - The ioctl handler will be called without locking the + DRM global mutex. This is the enforced default for kms drivers (i.e. + using the DRIVER_MODESET flag) and hence shouldn't be used any more + for new drivers. + +.. kernel-doc:: drivers/gpu/drm/drm_ioctl.c + :export: + +Legacy Support Code +=================== + +The section very briefly covers some of the old legacy support code +which is only used by old DRM drivers which have done a so-called +shadow-attach to the underlying device instead of registering as a real +driver. This also includes some of the old generic buffer management and +command submission code. Do not use any of this in new and modern +drivers. + +Legacy Suspend/Resume +--------------------- + +The DRM core provides some suspend/resume code, but drivers wanting full +suspend/resume support should provide save() and restore() functions. +These are called at suspend, hibernate, or resume time, and should +perform any state save or restore required by your device across suspend +or hibernate states. + +int (\*suspend) (struct drm_device \*, pm_message_t state); int +(\*resume) (struct drm_device \*); +Those are legacy suspend and resume methods which *only* work with the +legacy shadow-attach driver registration functions. New driver should +use the power management interface provided by their bus type (usually +through the :c:type:`struct device_driver <device_driver>` +dev_pm_ops) and set these methods to NULL. + +Legacy DMA Services +------------------- + +This should cover how DMA mapping etc. is supported by the core. These +functions are deprecated and should not be used. diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst new file mode 100644 index 000000000000..0b302fedf1af --- /dev/null +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -0,0 +1,260 @@ +============================= +Mode Setting Helper Functions +============================= + +The plane, CRTC, encoder and connector functions provided by the drivers +implement the DRM API. They're called by the DRM core and ioctl handlers +to handle device state changes and configuration request. As +implementing those functions often requires logic not specific to +drivers, mid-layer helper functions are available to avoid duplicating +boilerplate code. + +The DRM core contains one mid-layer implementation. The mid-layer +provides implementations of several plane, CRTC, encoder and connector +functions (called from the top of the mid-layer) that pre-process +requests and call lower-level functions provided by the driver (at the +bottom of the mid-layer). For instance, the +:c:func:`drm_crtc_helper_set_config()` function can be used to +fill the :c:type:`struct drm_crtc_funcs <drm_crtc_funcs>` +set_config field. When called, it will split the set_config operation +in smaller, simpler operations and call the driver to handle them. + +To use the mid-layer, drivers call +:c:func:`drm_crtc_helper_add()`, +:c:func:`drm_encoder_helper_add()` and +:c:func:`drm_connector_helper_add()` functions to install their +mid-layer bottom operations handlers, and fill the :c:type:`struct +drm_crtc_funcs <drm_crtc_funcs>`, :c:type:`struct +drm_encoder_funcs <drm_encoder_funcs>` and :c:type:`struct +drm_connector_funcs <drm_connector_funcs>` structures with +pointers to the mid-layer top API functions. Installing the mid-layer +bottom operation handlers is best done right after registering the +corresponding KMS object. + +The mid-layer is not split between CRTC, encoder and connector +operations. To use it, a driver must provide bottom functions for all of +the three KMS entities. + +Atomic Modeset Helper Functions Reference +========================================= + +Overview +-------- + +.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c + :doc: overview + +Implementing Asynchronous Atomic Commit +--------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c + :doc: implementing nonblocking commit + +Atomic State Reset and Initialization +------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c + :doc: atomic state reset and initialization + +.. kernel-doc:: include/drm/drm_atomic_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c + :export: + +Modeset Helper Reference for Common Vtables +=========================================== + +.. kernel-doc:: include/drm/drm_modeset_helper_vtables.h + :internal: + +.. kernel-doc:: include/drm/drm_modeset_helper_vtables.h + :doc: overview + +Legacy CRTC/Modeset Helper Functions Reference +============================================== + +.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_crtc_helper.c + :doc: overview + +Output Probing Helper Functions Reference +========================================= + +.. kernel-doc:: drivers/gpu/drm/drm_probe_helper.c + :doc: output probing helper overview + +.. kernel-doc:: drivers/gpu/drm/drm_probe_helper.c + :export: + +fbdev Helper Functions Reference +================================ + +.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c + :doc: fbdev helpers + +.. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c + :export: + +.. kernel-doc:: include/drm/drm_fb_helper.h + :internal: + +Framebuffer CMA Helper Functions Reference +========================================== + +.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c + :doc: framebuffer cma helper functions + +.. kernel-doc:: drivers/gpu/drm/drm_fb_cma_helper.c + :export: + +Display Port Helper Functions Reference +======================================= + +.. kernel-doc:: drivers/gpu/drm/drm_dp_helper.c + :doc: dp helpers + +.. kernel-doc:: include/drm/drm_dp_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_dp_helper.c + :export: + +Display Port Dual Mode Adaptor Helper Functions Reference +========================================================= + +.. kernel-doc:: drivers/gpu/drm/drm_dp_dual_mode_helper.c + :doc: dp dual mode helpers + +.. kernel-doc:: include/drm/drm_dp_dual_mode_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_dp_dual_mode_helper.c + :export: + +Display Port MST Helper Functions Reference +=========================================== + +.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c + :doc: dp mst helper + +.. kernel-doc:: include/drm/drm_dp_mst_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_dp_mst_topology.c + :export: + +MIPI DSI Helper Functions Reference +=================================== + +.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c + :doc: dsi helpers + +.. kernel-doc:: include/drm/drm_mipi_dsi.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c + :export: + +EDID Helper Functions Reference +=============================== + +.. kernel-doc:: drivers/gpu/drm/drm_edid.c + :export: + +Rectangle Utilities Reference +============================= + +.. kernel-doc:: include/drm/drm_rect.h + :doc: rect utils + +.. kernel-doc:: include/drm/drm_rect.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_rect.c + :export: + +Flip-work Helper Reference +========================== + +.. kernel-doc:: include/drm/drm_flip_work.h + :doc: flip utils + +.. kernel-doc:: include/drm/drm_flip_work.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_flip_work.c + :export: + +HDMI Infoframes Helper Reference +================================ + +Strictly speaking this is not a DRM helper library but generally useable +by any driver interfacing with HDMI outputs like v4l or alsa drivers. +But it nicely fits into the overall topic of mode setting helper +libraries and hence is also included here. + +.. kernel-doc:: include/linux/hdmi.h + :internal: + +.. kernel-doc:: drivers/video/hdmi.c + :export: + +Plane Helper Reference +====================== + +.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_plane_helper.c + :doc: overview + +Tile group +---------- + +.. kernel-doc:: drivers/gpu/drm/drm_crtc.c + :doc: Tile group + +Bridges +======= + +Overview +-------- + +.. kernel-doc:: drivers/gpu/drm/drm_bridge.c + :doc: overview + +Default bridge callback sequence +-------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_bridge.c + :doc: bridge callbacks + +.. kernel-doc:: drivers/gpu/drm/drm_bridge.c + :export: + +Panel Helper Reference +====================== + +.. kernel-doc:: include/drm/drm_panel.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_panel.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_panel.c + :doc: drm panel + +Simple KMS Helper Reference +=========================== + +.. kernel-doc:: include/drm/drm_simple_kms_helper.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c + :doc: overview diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst new file mode 100644 index 000000000000..8dfa4b214b96 --- /dev/null +++ b/Documentation/gpu/drm-kms.rst @@ -0,0 +1,653 @@ +========================= +Kernel Mode Setting (KMS) +========================= + +Mode Setting +============ + +Drivers must initialize the mode setting core by calling +:c:func:`drm_mode_config_init()` on the DRM device. The function +initializes the :c:type:`struct drm_device <drm_device>` +mode_config field and never fails. Once done, mode configuration must +be setup by initializing the following fields. + +- int min_width, min_height; int max_width, max_height; + Minimum and maximum width and height of the frame buffers in pixel + units. + +- struct drm_mode_config_funcs \*funcs; + Mode setting functions. + +Display Modes Function Reference +-------------------------------- + +.. kernel-doc:: include/drm/drm_modes.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_modes.c + :export: + +Atomic Mode Setting Function Reference +-------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_atomic.c + :export: + +.. kernel-doc:: drivers/gpu/drm/drm_atomic.c + :internal: + +Frame Buffer Abstraction +------------------------ + +Frame buffers are abstract memory objects that provide a source of +pixels to scanout to a CRTC. Applications explicitly request the +creation of frame buffers through the DRM_IOCTL_MODE_ADDFB(2) ioctls +and receive an opaque handle that can be passed to the KMS CRTC control, +plane configuration and page flip functions. + +Frame buffers rely on the underneath memory manager for low-level memory +operations. When creating a frame buffer applications pass a memory +handle (or a list of memory handles for multi-planar formats) through +the ``drm_mode_fb_cmd2`` argument. For drivers using GEM as their +userspace buffer management interface this would be a GEM handle. +Drivers are however free to use their own backing storage object +handles, e.g. vmwgfx directly exposes special TTM handles to userspace +and so expects TTM handles in the create ioctl and not GEM handles. + +The lifetime of a drm framebuffer is controlled with a reference count, +drivers can grab additional references with +:c:func:`drm_framebuffer_reference()`and drop them again with +:c:func:`drm_framebuffer_unreference()`. For driver-private +framebuffers for which the last reference is never dropped (e.g. for the +fbdev framebuffer when the struct :c:type:`struct drm_framebuffer +<drm_framebuffer>` is embedded into the fbdev helper struct) +drivers can manually clean up a framebuffer at module unload time with +:c:func:`drm_framebuffer_unregister_private()`. + +DRM Format Handling +------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_fourcc.c + :export: + +Dumb Buffer Objects +------------------- + +The KMS API doesn't standardize backing storage object creation and +leaves it to driver-specific ioctls. Furthermore actually creating a +buffer object even for GEM-based drivers is done through a +driver-specific ioctl - GEM only has a common userspace interface for +sharing and destroying objects. While not an issue for full-fledged +graphics stacks that include device-specific userspace components (in +libdrm for instance), this limit makes DRM-based early boot graphics +unnecessarily complex. + +Dumb objects partly alleviate the problem by providing a standard API to +create dumb buffers suitable for scanout, which can then be used to +create KMS frame buffers. + +To support dumb objects drivers must implement the dumb_create, +dumb_destroy and dumb_map_offset operations. + +- int (\*dumb_create)(struct drm_file \*file_priv, struct + drm_device \*dev, struct drm_mode_create_dumb \*args); + The dumb_create operation creates a driver object (GEM or TTM + handle) suitable for scanout based on the width, height and depth + from the struct :c:type:`struct drm_mode_create_dumb + <drm_mode_create_dumb>` argument. It fills the argument's + handle, pitch and size fields with a handle for the newly created + object and its line pitch and size in bytes. + +- int (\*dumb_destroy)(struct drm_file \*file_priv, struct + drm_device \*dev, uint32_t handle); + The dumb_destroy operation destroys a dumb object created by + dumb_create. + +- int (\*dumb_map_offset)(struct drm_file \*file_priv, struct + drm_device \*dev, uint32_t handle, uint64_t \*offset); + The dumb_map_offset operation associates an mmap fake offset with + the object given by the handle and returns it. Drivers must use the + :c:func:`drm_gem_create_mmap_offset()` function to associate + the fake offset as described in ?. + +Note that dumb objects may not be used for gpu acceleration, as has been +attempted on some ARM embedded platforms. Such drivers really must have +a hardware-specific ioctl to allocate suitable buffer objects. + +Output Polling +-------------- + +void (\*output_poll_changed)(struct drm_device \*dev); +This operation notifies the driver that the status of one or more +connectors has changed. Drivers that use the fb helper can just call the +:c:func:`drm_fb_helper_hotplug_event()` function to handle this +operation. + +KMS Initialization and Cleanup +============================== + +A KMS device is abstracted and exposed as a set of planes, CRTCs, +encoders and connectors. KMS drivers must thus create and initialize all +those objects at load time after initializing mode setting. + +CRTCs (:c:type:`struct drm_crtc <drm_crtc>`) +-------------------------------------------- + +A CRTC is an abstraction representing a part of the chip that contains a +pointer to a scanout buffer. Therefore, the number of CRTCs available +determines how many independent scanout buffers can be active at any +given time. The CRTC structure contains several fields to support this: +a pointer to some video memory (abstracted as a frame buffer object), a +display mode, and an (x, y) offset into the video memory to support +panning or configurations where one piece of video memory spans multiple +CRTCs. + +CRTC Initialization +~~~~~~~~~~~~~~~~~~~ + +A KMS device must create and register at least one struct +:c:type:`struct drm_crtc <drm_crtc>` instance. The instance is +allocated and zeroed by the driver, possibly as part of a larger +structure, and registered with a call to :c:func:`drm_crtc_init()` +with a pointer to CRTC functions. + +Planes (:c:type:`struct drm_plane <drm_plane>`) +----------------------------------------------- + +A plane represents an image source that can be blended with or overlayed +on top of a CRTC during the scanout process. Planes are associated with +a frame buffer to crop a portion of the image memory (source) and +optionally scale it to a destination size. The result is then blended +with or overlayed on top of a CRTC. + +The DRM core recognizes three types of planes: + +- DRM_PLANE_TYPE_PRIMARY represents a "main" plane for a CRTC. + Primary planes are the planes operated upon by CRTC modesetting and + flipping operations described in the page_flip hook in + :c:type:`struct drm_crtc_funcs <drm_crtc_funcs>`. +- DRM_PLANE_TYPE_CURSOR represents a "cursor" plane for a CRTC. + Cursor planes are the planes operated upon by the + DRM_IOCTL_MODE_CURSOR and DRM_IOCTL_MODE_CURSOR2 ioctls. +- DRM_PLANE_TYPE_OVERLAY represents all non-primary, non-cursor + planes. Some drivers refer to these types of planes as "sprites" + internally. + +For compatibility with legacy userspace, only overlay planes are made +available to userspace by default. Userspace clients may set the +DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate +that they wish to receive a universal plane list containing all plane +types. + +Plane Initialization +~~~~~~~~~~~~~~~~~~~~ + +To create a plane, a KMS drivers allocates and zeroes an instances of +:c:type:`struct drm_plane <drm_plane>` (possibly as part of a +larger structure) and registers it with a call to +:c:func:`drm_universal_plane_init()`. The function takes a +bitmask of the CRTCs that can be associated with the plane, a pointer to +the plane functions, a list of format supported formats, and the type of +plane (primary, cursor, or overlay) being initialized. + +Cursor and overlay planes are optional. All drivers should provide one +primary plane per CRTC (although this requirement may change in the +future); drivers that do not wish to provide special handling for +primary planes may make use of the helper functions described in ? to +create and register a primary plane with standard capabilities. + +Encoders (:c:type:`struct drm_encoder <drm_encoder>`) +----------------------------------------------------- + +An encoder takes pixel data from a CRTC and converts it to a format +suitable for any attached connectors. On some devices, it may be +possible to have a CRTC send data to more than one encoder. In that +case, both encoders would receive data from the same scanout buffer, +resulting in a "cloned" display configuration across the connectors +attached to each encoder. + +Encoder Initialization +~~~~~~~~~~~~~~~~~~~~~~ + +As for CRTCs, a KMS driver must create, initialize and register at least +one :c:type:`struct drm_encoder <drm_encoder>` instance. The +instance is allocated and zeroed by the driver, possibly as part of a +larger structure. + +Drivers must initialize the :c:type:`struct drm_encoder +<drm_encoder>` possible_crtcs and possible_clones fields before +registering the encoder. Both fields are bitmasks of respectively the +CRTCs that the encoder can be connected to, and sibling encoders +candidate for cloning. + +After being initialized, the encoder must be registered with a call to +:c:func:`drm_encoder_init()`. The function takes a pointer to the +encoder functions and an encoder type. Supported types are + +- DRM_MODE_ENCODER_DAC for VGA and analog on DVI-I/DVI-A +- DRM_MODE_ENCODER_TMDS for DVI, HDMI and (embedded) DisplayPort +- DRM_MODE_ENCODER_LVDS for display panels +- DRM_MODE_ENCODER_TVDAC for TV output (Composite, S-Video, + Component, SCART) +- DRM_MODE_ENCODER_VIRTUAL for virtual machine displays + +Encoders must be attached to a CRTC to be used. DRM drivers leave +encoders unattached at initialization time. Applications (or the fbdev +compatibility layer when implemented) are responsible for attaching the +encoders they want to use to a CRTC. + +Connectors (:c:type:`struct drm_connector <drm_connector>`) +----------------------------------------------------------- + +A connector is the final destination for pixel data on a device, and +usually connects directly to an external display device like a monitor +or laptop panel. A connector can only be attached to one encoder at a +time. The connector is also the structure where information about the +attached display is kept, so it contains fields for display data, EDID +data, DPMS & connection status, and information about modes supported on +the attached displays. + +Connector Initialization +~~~~~~~~~~~~~~~~~~~~~~~~ + +Finally a KMS driver must create, initialize, register and attach at +least one :c:type:`struct drm_connector <drm_connector>` +instance. The instance is created as other KMS objects and initialized +by setting the following fields. + +interlace_allowed + Whether the connector can handle interlaced modes. + +doublescan_allowed + Whether the connector can handle doublescan. + +display_info + Display information is filled from EDID information when a display + is detected. For non hot-pluggable displays such as flat panels in + embedded systems, the driver should initialize the + display_info.width_mm and display_info.height_mm fields with the + physical size of the display. + +polled + Connector polling mode, a combination of + + DRM_CONNECTOR_POLL_HPD + The connector generates hotplug events and doesn't need to be + periodically polled. The CONNECT and DISCONNECT flags must not + be set together with the HPD flag. + + DRM_CONNECTOR_POLL_CONNECT + Periodically poll the connector for connection. + + DRM_CONNECTOR_POLL_DISCONNECT + Periodically poll the connector for disconnection. + + Set to 0 for connectors that don't support connection status + discovery. + +The connector is then registered with a call to +:c:func:`drm_connector_init()` with a pointer to the connector +functions and a connector type, and exposed through sysfs with a call to +:c:func:`drm_connector_register()`. + +Supported connector types are + +- DRM_MODE_CONNECTOR_VGA +- DRM_MODE_CONNECTOR_DVII +- DRM_MODE_CONNECTOR_DVID +- DRM_MODE_CONNECTOR_DVIA +- DRM_MODE_CONNECTOR_Composite +- DRM_MODE_CONNECTOR_SVIDEO +- DRM_MODE_CONNECTOR_LVDS +- DRM_MODE_CONNECTOR_Component +- DRM_MODE_CONNECTOR_9PinDIN +- DRM_MODE_CONNECTOR_DisplayPort +- DRM_MODE_CONNECTOR_HDMIA +- DRM_MODE_CONNECTOR_HDMIB +- DRM_MODE_CONNECTOR_TV +- DRM_MODE_CONNECTOR_eDP +- DRM_MODE_CONNECTOR_VIRTUAL + +Connectors must be attached to an encoder to be used. For devices that +map connectors to encoders 1:1, the connector should be attached at +initialization time with a call to +:c:func:`drm_mode_connector_attach_encoder()`. The driver must +also set the :c:type:`struct drm_connector <drm_connector>` +encoder field to point to the attached encoder. + +Finally, drivers must initialize the connectors state change detection +with a call to :c:func:`drm_kms_helper_poll_init()`. If at least +one connector is pollable but can't generate hotplug interrupts +(indicated by the DRM_CONNECTOR_POLL_CONNECT and +DRM_CONNECTOR_POLL_DISCONNECT connector flags), a delayed work will +automatically be queued to periodically poll for changes. Connectors +that can generate hotplug interrupts must be marked with the +DRM_CONNECTOR_POLL_HPD flag instead, and their interrupt handler must +call :c:func:`drm_helper_hpd_irq_event()`. The function will +queue a delayed work to check the state of all connectors, but no +periodic polling will be done. + +Connector Operations +~~~~~~~~~~~~~~~~~~~~ + + **Note** + + Unless otherwise state, all operations are mandatory. + +DPMS +'''' + +void (\*dpms)(struct drm_connector \*connector, int mode); +The DPMS operation sets the power state of a connector. The mode +argument is one of + +- DRM_MODE_DPMS_ON + +- DRM_MODE_DPMS_STANDBY + +- DRM_MODE_DPMS_SUSPEND + +- DRM_MODE_DPMS_OFF + +In all but DPMS_ON mode the encoder to which the connector is attached +should put the display in low-power mode by driving its signals +appropriately. If more than one connector is attached to the encoder +care should be taken not to change the power state of other displays as +a side effect. Low-power mode should be propagated to the encoders and +CRTCs when all related connectors are put in low-power mode. + +Modes +''''' + +int (\*fill_modes)(struct drm_connector \*connector, uint32_t +max_width, uint32_t max_height); +Fill the mode list with all supported modes for the connector. If the +``max_width`` and ``max_height`` arguments are non-zero, the +implementation must ignore all modes wider than ``max_width`` or higher +than ``max_height``. + +The connector must also fill in this operation its display_info +width_mm and height_mm fields with the connected display physical size +in millimeters. The fields should be set to 0 if the value isn't known +or is not applicable (for instance for projector devices). + +Connection Status +''''''''''''''''' + +The connection status is updated through polling or hotplug events when +supported (see ?). The status value is reported to userspace through +ioctls and must not be used inside the driver, as it only gets +initialized by a call to :c:func:`drm_mode_getconnector()` from +userspace. + +enum drm_connector_status (\*detect)(struct drm_connector +\*connector, bool force); +Check to see if anything is attached to the connector. The ``force`` +parameter is set to false whilst polling or to true when checking the +connector due to user request. ``force`` can be used by the driver to +avoid expensive, destructive operations during automated probing. + +Return connector_status_connected if something is connected to the +connector, connector_status_disconnected if nothing is connected and +connector_status_unknown if the connection state isn't known. + +Drivers should only return connector_status_connected if the +connection status has really been probed as connected. Connectors that +can't detect the connection status, or failed connection status probes, +should return connector_status_unknown. + +Cleanup +------- + +The DRM core manages its objects' lifetime. When an object is not needed +anymore the core calls its destroy function, which must clean up and +free every resource allocated for the object. Every +:c:func:`drm_\*_init()` call must be matched with a corresponding +:c:func:`drm_\*_cleanup()` call to cleanup CRTCs +(:c:func:`drm_crtc_cleanup()`), planes +(:c:func:`drm_plane_cleanup()`), encoders +(:c:func:`drm_encoder_cleanup()`) and connectors +(:c:func:`drm_connector_cleanup()`). Furthermore, connectors that +have been added to sysfs must be removed by a call to +:c:func:`drm_connector_unregister()` before calling +:c:func:`drm_connector_cleanup()`. + +Connectors state change detection must be cleanup up with a call to +:c:func:`drm_kms_helper_poll_fini()`. + +Output discovery and initialization example +------------------------------------------- + +:: + + void intel_crt_init(struct drm_device *dev) + { + struct drm_connector *connector; + struct intel_output *intel_output; + + intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); + if (!intel_output) + return; + + connector = &intel_output->base; + drm_connector_init(dev, &intel_output->base, + &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); + + drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs, + DRM_MODE_ENCODER_DAC); + + drm_mode_connector_attach_encoder(&intel_output->base, + &intel_output->enc); + + /* Set up the DDC bus. */ + intel_output->ddc_bus = intel_i2c_create(dev, GPIOA, "CRTDDC_A"); + if (!intel_output->ddc_bus) { + dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " + "failed.\n"); + return; + } + + intel_output->type = INTEL_OUTPUT_ANALOG; + connector->interlace_allowed = 0; + connector->doublescan_allowed = 0; + + drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs); + drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); + + drm_connector_register(connector); + } + +In the example above (taken from the i915 driver), a CRTC, connector and +encoder combination is created. A device-specific i2c bus is also +created for fetching EDID data and performing monitor detection. Once +the process is complete, the new connector is registered with sysfs to +make its properties available to applications. + +KMS API Functions +----------------- + +.. kernel-doc:: drivers/gpu/drm/drm_crtc.c + :export: + +KMS Data Structures +------------------- + +.. kernel-doc:: include/drm/drm_crtc.h + :internal: + +KMS Locking +----------- + +.. kernel-doc:: drivers/gpu/drm/drm_modeset_lock.c + :doc: kms locking + +.. kernel-doc:: include/drm/drm_modeset_lock.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/drm_modeset_lock.c + :export: + +KMS Properties +============== + +Drivers may need to expose additional parameters to applications than +those described in the previous sections. KMS supports attaching +properties to CRTCs, connectors and planes and offers a userspace API to +list, get and set the property values. + +Properties are identified by a name that uniquely defines the property +purpose, and store an associated value. For all property types except +blob properties the value is a 64-bit unsigned integer. + +KMS differentiates between properties and property instances. Drivers +first create properties and then create and associate individual +instances of those properties to objects. A property can be instantiated +multiple times and associated with different objects. Values are stored +in property instances, and all other property information are stored in +the property and shared between all instances of the property. + +Every property is created with a type that influences how the KMS core +handles the property. Supported property types are + +DRM_MODE_PROP_RANGE + Range properties report their minimum and maximum admissible values. + The KMS core verifies that values set by application fit in that + range. + +DRM_MODE_PROP_ENUM + Enumerated properties take a numerical value that ranges from 0 to + the number of enumerated values defined by the property minus one, + and associate a free-formed string name to each value. Applications + can retrieve the list of defined value-name pairs and use the + numerical value to get and set property instance values. + +DRM_MODE_PROP_BITMASK + Bitmask properties are enumeration properties that additionally + restrict all enumerated values to the 0..63 range. Bitmask property + instance values combine one or more of the enumerated bits defined + by the property. + +DRM_MODE_PROP_BLOB + Blob properties store a binary blob without any format restriction. + The binary blobs are created as KMS standalone objects, and blob + property instance values store the ID of their associated blob + object. + + Blob properties are only used for the connector EDID property and + cannot be created by drivers. + +To create a property drivers call one of the following functions +depending on the property type. All property creation functions take +property flags and name, as well as type-specific arguments. + +- struct drm_property \*drm_property_create_range(struct + drm_device \*dev, int flags, const char \*name, uint64_t min, + uint64_t max); + Create a range property with the given minimum and maximum values. + +- struct drm_property \*drm_property_create_enum(struct drm_device + \*dev, int flags, const char \*name, const struct + drm_prop_enum_list \*props, int num_values); + Create an enumerated property. The ``props`` argument points to an + array of ``num_values`` value-name pairs. + +- struct drm_property \*drm_property_create_bitmask(struct + drm_device \*dev, int flags, const char \*name, const struct + drm_prop_enum_list \*props, int num_values); + Create a bitmask property. The ``props`` argument points to an array + of ``num_values`` value-name pairs. + +Properties can additionally be created as immutable, in which case they +will be read-only for applications but can be modified by the driver. To +create an immutable property drivers must set the +DRM_MODE_PROP_IMMUTABLE flag at property creation time. + +When no array of value-name pairs is readily available at property +creation time for enumerated or range properties, drivers can create the +property using the :c:func:`drm_property_create()` function and +manually add enumeration value-name pairs by calling the +:c:func:`drm_property_add_enum()` function. Care must be taken to +properly specify the property type through the ``flags`` argument. + +After creating properties drivers can attach property instances to CRTC, +connector and plane objects by calling the +:c:func:`drm_object_attach_property()`. The function takes a +pointer to the target object, a pointer to the previously created +property and an initial instance value. + +Existing KMS Properties +----------------------- + +The following table gives description of drm properties exposed by +various modules/drivers. + +.. csv-table:: + :header-rows: 1 + :file: kms-properties.csv + +Vertical Blanking +================= + +Vertical blanking plays a major role in graphics rendering. To achieve +tear-free display, users must synchronize page flips and/or rendering to +vertical blanking. The DRM API offers ioctls to perform page flips +synchronized to vertical blanking and wait for vertical blanking. + +The DRM core handles most of the vertical blanking management logic, +which involves filtering out spurious interrupts, keeping race-free +blanking counters, coping with counter wrap-around and resets and +keeping use counts. It relies on the driver to generate vertical +blanking interrupts and optionally provide a hardware vertical blanking +counter. Drivers must implement the following operations. + +- int (\*enable_vblank) (struct drm_device \*dev, int crtc); void + (\*disable_vblank) (struct drm_device \*dev, int crtc); + Enable or disable vertical blanking interrupts for the given CRTC. + +- u32 (\*get_vblank_counter) (struct drm_device \*dev, int crtc); + Retrieve the value of the vertical blanking counter for the given + CRTC. If the hardware maintains a vertical blanking counter its value + should be returned. Otherwise drivers can use the + :c:func:`drm_vblank_count()` helper function to handle this + operation. + +Drivers must initialize the vertical blanking handling core with a call +to :c:func:`drm_vblank_init()` in their load operation. + +Vertical blanking interrupts can be enabled by the DRM core or by +drivers themselves (for instance to handle page flipping operations). +The DRM core maintains a vertical blanking use count to ensure that the +interrupts are not disabled while a user still needs them. To increment +the use count, drivers call :c:func:`drm_vblank_get()`. Upon +return vertical blanking interrupts are guaranteed to be enabled. + +To decrement the use count drivers call +:c:func:`drm_vblank_put()`. Only when the use count drops to zero +will the DRM core disable the vertical blanking interrupts after a delay +by scheduling a timer. The delay is accessible through the +vblankoffdelay module parameter or the ``drm_vblank_offdelay`` global +variable and expressed in milliseconds. Its default value is 5000 ms. +Zero means never disable, and a negative value means disable +immediately. Drivers may override the behaviour by setting the +:c:type:`struct drm_device <drm_device>` +vblank_disable_immediate flag, which when set causes vblank interrupts +to be disabled immediately regardless of the drm_vblank_offdelay +value. The flag should only be set if there's a properly working +hardware vblank counter present. + +When a vertical blanking interrupt occurs drivers only need to call the +:c:func:`drm_handle_vblank()` function to account for the +interrupt. + +Resources allocated by :c:func:`drm_vblank_init()` must be freed +with a call to :c:func:`drm_vblank_cleanup()` in the driver unload +operation handler. + +Vertical Blanking and Interrupt Handling Functions Reference +------------------------------------------------------------ + +.. kernel-doc:: drivers/gpu/drm/drm_irq.c + :export: + +.. kernel-doc:: include/drm/drm_irq.h + :internal: diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst new file mode 100644 index 000000000000..59f9822fecd0 --- /dev/null +++ b/Documentation/gpu/drm-mm.rst @@ -0,0 +1,454 @@ +===================== +DRM Memory Management +===================== + +Modern Linux systems require large amount of graphics memory to store +frame buffers, textures, vertices and other graphics-related data. Given +the very dynamic nature of many of that data, managing graphics memory +efficiently is thus crucial for the graphics stack and plays a central +role in the DRM infrastructure. + +The DRM core includes two memory managers, namely Translation Table Maps +(TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory +manager to be developed and tried to be a one-size-fits-them all +solution. It provides a single userspace API to accommodate the need of +all hardware, supporting both Unified Memory Architecture (UMA) devices +and devices with dedicated video RAM (i.e. most discrete video cards). +This resulted in a large, complex piece of code that turned out to be +hard to use for driver development. + +GEM started as an Intel-sponsored project in reaction to TTM's +complexity. Its design philosophy is completely different: instead of +providing a solution to every graphics memory-related problems, GEM +identified common code between drivers and created a support library to +share it. GEM has simpler initialization and execution requirements than +TTM, but has no video RAM management capabilities and is thus limited to +UMA devices. + +The Translation Table Manager (TTM) +----------------------------------- + +TTM design background and information belongs here. + +TTM initialization +~~~~~~~~~~~~~~~~~~ + + **Warning** + + This section is outdated. + +Drivers wishing to support TTM must fill out a drm_bo_driver +structure. The structure contains several fields with function pointers +for initializing the TTM, allocating and freeing memory, waiting for +command completion and fence synchronization, and memory migration. See +the radeon_ttm.c file for an example of usage. + +The ttm_global_reference structure is made up of several fields: + +:: + + struct ttm_global_reference { + enum ttm_global_types global_type; + size_t size; + void *object; + int (*init) (struct ttm_global_reference *); + void (*release) (struct ttm_global_reference *); + }; + + +There should be one global reference structure for your memory manager +as a whole, and there will be others for each object created by the +memory manager at runtime. Your global TTM should have a type of +TTM_GLOBAL_TTM_MEM. The size field for the global object should be +sizeof(struct ttm_mem_global), and the init and release hooks should +point at your driver-specific init and release routines, which probably +eventually call ttm_mem_global_init and ttm_mem_global_release, +respectively. + +Once your global TTM accounting structure is set up and initialized by +calling ttm_global_item_ref() on it, you need to create a buffer +object TTM to provide a pool for buffer object allocation by clients and +the kernel itself. The type of this object should be +TTM_GLOBAL_TTM_BO, and its size should be sizeof(struct +ttm_bo_global). Again, driver-specific init and release functions may +be provided, likely eventually calling ttm_bo_global_init() and +ttm_bo_global_release(), respectively. Also, like the previous +object, ttm_global_item_ref() is used to create an initial reference +count for the TTM, which will call your initialization function. + +The Graphics Execution Manager (GEM) +------------------------------------ + +The GEM design approach has resulted in a memory manager that doesn't +provide full coverage of all (or even all common) use cases in its +userspace or kernel API. GEM exposes a set of standard memory-related +operations to userspace and a set of helper functions to drivers, and +let drivers implement hardware-specific operations with their own +private API. + +The GEM userspace API is described in the `GEM - the Graphics Execution +Manager <http://lwn.net/Articles/283798/>`__ article on LWN. While +slightly outdated, the document provides a good overview of the GEM API +principles. Buffer allocation and read and write operations, described +as part of the common GEM API, are currently implemented using +driver-specific ioctls. + +GEM is data-agnostic. It manages abstract buffer objects without knowing +what individual buffers contain. APIs that require knowledge of buffer +contents or purpose, such as buffer allocation or synchronization +primitives, are thus outside of the scope of GEM and must be implemented +using driver-specific ioctls. + +On a fundamental level, GEM involves several operations: + +- Memory allocation and freeing +- Command execution +- Aperture management at command execution time + +Buffer object allocation is relatively straightforward and largely +provided by Linux's shmem layer, which provides memory to back each +object. + +Device-specific operations, such as command execution, pinning, buffer +read & write, mapping, and domain ownership transfers are left to +driver-specific ioctls. + +GEM Initialization +~~~~~~~~~~~~~~~~~~ + +Drivers that use GEM must set the DRIVER_GEM bit in the struct +:c:type:`struct drm_driver <drm_driver>` driver_features +field. The DRM core will then automatically initialize the GEM core +before calling the load operation. Behind the scene, this will create a +DRM Memory Manager object which provides an address space pool for +object allocation. + +In a KMS configuration, drivers need to allocate and initialize a +command ring buffer following core GEM initialization if required by the +hardware. UMA devices usually have what is called a "stolen" memory +region, which provides space for the initial framebuffer and large, +contiguous memory regions required by the device. This space is +typically not managed by GEM, and must be initialized separately into +its own DRM MM object. + +GEM Objects Creation +~~~~~~~~~~~~~~~~~~~~ + +GEM splits creation of GEM objects and allocation of the memory that +backs them in two distinct operations. + +GEM objects are represented by an instance of struct :c:type:`struct +drm_gem_object <drm_gem_object>`. Drivers usually need to +extend GEM objects with private information and thus create a +driver-specific GEM object structure type that embeds an instance of +struct :c:type:`struct drm_gem_object <drm_gem_object>`. + +To create a GEM object, a driver allocates memory for an instance of its +specific GEM object type and initializes the embedded struct +:c:type:`struct drm_gem_object <drm_gem_object>` with a call +to :c:func:`drm_gem_object_init()`. The function takes a pointer +to the DRM device, a pointer to the GEM object and the buffer object +size in bytes. + +GEM uses shmem to allocate anonymous pageable memory. +:c:func:`drm_gem_object_init()` will create an shmfs file of the +requested size and store it into the struct :c:type:`struct +drm_gem_object <drm_gem_object>` filp field. The memory is +used as either main storage for the object when the graphics hardware +uses system memory directly or as a backing store otherwise. + +Drivers are responsible for the actual physical pages allocation by +calling :c:func:`shmem_read_mapping_page_gfp()` for each page. +Note that they can decide to allocate pages when initializing the GEM +object, or to delay allocation until the memory is needed (for instance +when a page fault occurs as a result of a userspace memory access or +when the driver needs to start a DMA transfer involving the memory). + +Anonymous pageable memory allocation is not always desired, for instance +when the hardware requires physically contiguous system memory as is +often the case in embedded devices. Drivers can create GEM objects with +no shmfs backing (called private GEM objects) by initializing them with +a call to :c:func:`drm_gem_private_object_init()` instead of +:c:func:`drm_gem_object_init()`. Storage for private GEM objects +must be managed by drivers. + +GEM Objects Lifetime +~~~~~~~~~~~~~~~~~~~~ + +All GEM objects are reference-counted by the GEM core. References can be +acquired and release by :c:func:`calling +drm_gem_object_reference()` and +:c:func:`drm_gem_object_unreference()` respectively. The caller +must hold the :c:type:`struct drm_device <drm_device>` +struct_mutex lock when calling +:c:func:`drm_gem_object_reference()`. As a convenience, GEM +provides :c:func:`drm_gem_object_unreference_unlocked()` +functions that can be called without holding the lock. + +When the last reference to a GEM object is released the GEM core calls +the :c:type:`struct drm_driver <drm_driver>` gem_free_object +operation. That operation is mandatory for GEM-enabled drivers and must +free the GEM object and all associated resources. + +void (\*gem_free_object) (struct drm_gem_object \*obj); Drivers are +responsible for freeing all GEM object resources. This includes the +resources created by the GEM core, which need to be released with +:c:func:`drm_gem_object_release()`. + +GEM Objects Naming +~~~~~~~~~~~~~~~~~~ + +Communication between userspace and the kernel refers to GEM objects +using local handles, global names or, more recently, file descriptors. +All of those are 32-bit integer values; the usual Linux kernel limits +apply to the file descriptors. + +GEM handles are local to a DRM file. Applications get a handle to a GEM +object through a driver-specific ioctl, and can use that handle to refer +to the GEM object in other standard or driver-specific ioctls. Closing a +DRM file handle frees all its GEM handles and dereferences the +associated GEM objects. + +To create a handle for a GEM object drivers call +:c:func:`drm_gem_handle_create()`. The function takes a pointer +to the DRM file and the GEM object and returns a locally unique handle. +When the handle is no longer needed drivers delete it with a call to +:c:func:`drm_gem_handle_delete()`. Finally the GEM object +associated with a handle can be retrieved by a call to +:c:func:`drm_gem_object_lookup()`. + +Handles don't take ownership of GEM objects, they only take a reference +to the object that will be dropped when the handle is destroyed. To +avoid leaking GEM objects, drivers must make sure they drop the +reference(s) they own (such as the initial reference taken at object +creation time) as appropriate, without any special consideration for the +handle. For example, in the particular case of combined GEM object and +handle creation in the implementation of the dumb_create operation, +drivers must drop the initial reference to the GEM object before +returning the handle. + +GEM names are similar in purpose to handles but are not local to DRM +files. They can be passed between processes to reference a GEM object +globally. Names can't be used directly to refer to objects in the DRM +API, applications must convert handles to names and names to handles +using the DRM_IOCTL_GEM_FLINK and DRM_IOCTL_GEM_OPEN ioctls +respectively. The conversion is handled by the DRM core without any +driver-specific support. + +GEM also supports buffer sharing with dma-buf file descriptors through +PRIME. GEM-based drivers must use the provided helpers functions to +implement the exporting and importing correctly. See ?. Since sharing +file descriptors is inherently more secure than the easily guessable and +global GEM names it is the preferred buffer sharing mechanism. Sharing +buffers through GEM names is only supported for legacy userspace. +Furthermore PRIME also allows cross-device buffer sharing since it is +based on dma-bufs. + +GEM Objects Mapping +~~~~~~~~~~~~~~~~~~~ + +Because mapping operations are fairly heavyweight GEM favours +read/write-like access to buffers, implemented through driver-specific +ioctls, over mapping buffers to userspace. However, when random access +to the buffer is needed (to perform software rendering for instance), +direct access to the object can be more efficient. + +The mmap system call can't be used directly to map GEM objects, as they +don't have their own file handle. Two alternative methods currently +co-exist to map GEM objects to userspace. The first method uses a +driver-specific ioctl to perform the mapping operation, calling +:c:func:`do_mmap()` under the hood. This is often considered +dubious, seems to be discouraged for new GEM-enabled drivers, and will +thus not be described here. + +The second method uses the mmap system call on the DRM file handle. void +\*mmap(void \*addr, size_t length, int prot, int flags, int fd, off_t +offset); DRM identifies the GEM object to be mapped by a fake offset +passed through the mmap offset argument. Prior to being mapped, a GEM +object must thus be associated with a fake offset. To do so, drivers +must call :c:func:`drm_gem_create_mmap_offset()` on the object. + +Once allocated, the fake offset value must be passed to the application +in a driver-specific way and can then be used as the mmap offset +argument. + +The GEM core provides a helper method :c:func:`drm_gem_mmap()` to +handle object mapping. The method can be set directly as the mmap file +operation handler. It will look up the GEM object based on the offset +value and set the VMA operations to the :c:type:`struct drm_driver +<drm_driver>` gem_vm_ops field. Note that +:c:func:`drm_gem_mmap()` doesn't map memory to userspace, but +relies on the driver-provided fault handler to map pages individually. + +To use :c:func:`drm_gem_mmap()`, drivers must fill the struct +:c:type:`struct drm_driver <drm_driver>` gem_vm_ops field +with a pointer to VM operations. + +struct vm_operations_struct \*gem_vm_ops struct +vm_operations_struct { void (\*open)(struct vm_area_struct \* area); +void (\*close)(struct vm_area_struct \* area); int (\*fault)(struct +vm_area_struct \*vma, struct vm_fault \*vmf); }; + +The open and close operations must update the GEM object reference +count. Drivers can use the :c:func:`drm_gem_vm_open()` and +:c:func:`drm_gem_vm_close()` helper functions directly as open +and close handlers. + +The fault operation handler is responsible for mapping individual pages +to userspace when a page fault occurs. Depending on the memory +allocation scheme, drivers can allocate pages at fault time, or can +decide to allocate memory for the GEM object at the time the object is +created. + +Drivers that want to map the GEM object upfront instead of handling page +faults can implement their own mmap file operation handler. + +Memory Coherency +~~~~~~~~~~~~~~~~ + +When mapped to the device or used in a command buffer, backing pages for +an object are flushed to memory and marked write combined so as to be +coherent with the GPU. Likewise, if the CPU accesses an object after the +GPU has finished rendering to the object, then the object must be made +coherent with the CPU's view of memory, usually involving GPU cache +flushing of various kinds. This core CPU<->GPU coherency management is +provided by a device-specific ioctl, which evaluates an object's current +domain and performs any necessary flushing or synchronization to put the +object into the desired coherency domain (note that the object may be +busy, i.e. an active render target; in that case, setting the domain +blocks the client and waits for rendering to complete before performing +any necessary flushing operations). + +Command Execution +~~~~~~~~~~~~~~~~~ + +Perhaps the most important GEM function for GPU devices is providing a +command execution interface to clients. Client programs construct +command buffers containing references to previously allocated memory +objects, and then submit them to GEM. At that point, GEM takes care to +bind all the objects into the GTT, execute the buffer, and provide +necessary synchronization between clients accessing the same buffers. +This often involves evicting some objects from the GTT and re-binding +others (a fairly expensive operation), and providing relocation support +which hides fixed GTT offsets from clients. Clients must take care not +to submit command buffers that reference more objects than can fit in +the GTT; otherwise, GEM will reject them and no rendering will occur. +Similarly, if several objects in the buffer require fence registers to +be allocated for correct rendering (e.g. 2D blits on pre-965 chips), +care must be taken not to require more fence registers than are +available to the client. Such resource management should be abstracted +from the client in libdrm. + +GEM Function Reference +---------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_gem.c + :export: + +.. kernel-doc:: include/drm/drm_gem.h + :internal: + +VMA Offset Manager +------------------ + +.. kernel-doc:: drivers/gpu/drm/drm_vma_manager.c + :doc: vma offset manager + +.. kernel-doc:: drivers/gpu/drm/drm_vma_manager.c + :export: + +.. kernel-doc:: include/drm/drm_vma_manager.h + :internal: + +PRIME Buffer Sharing +-------------------- + +PRIME is the cross device buffer sharing framework in drm, originally +created for the OPTIMUS range of multi-gpu platforms. To userspace PRIME +buffers are dma-buf based file descriptors. + +Overview and Driver Interface +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Similar to GEM global names, PRIME file descriptors are also used to +share buffer objects across processes. They offer additional security: +as file descriptors must be explicitly sent over UNIX domain sockets to +be shared between applications, they can't be guessed like the globally +unique GEM names. + +Drivers that support the PRIME API must set the DRIVER_PRIME bit in the +struct :c:type:`struct drm_driver <drm_driver>` +driver_features field, and implement the prime_handle_to_fd and +prime_fd_to_handle operations. + +int (\*prime_handle_to_fd)(struct drm_device \*dev, struct drm_file +\*file_priv, uint32_t handle, uint32_t flags, int \*prime_fd); int +(\*prime_fd_to_handle)(struct drm_device \*dev, struct drm_file +\*file_priv, int prime_fd, uint32_t \*handle); Those two operations +convert a handle to a PRIME file descriptor and vice versa. Drivers must +use the kernel dma-buf buffer sharing framework to manage the PRIME file +descriptors. Similar to the mode setting API PRIME is agnostic to the +underlying buffer object manager, as long as handles are 32bit unsigned +integers. + +While non-GEM drivers must implement the operations themselves, GEM +drivers must use the :c:func:`drm_gem_prime_handle_to_fd()` and +:c:func:`drm_gem_prime_fd_to_handle()` helper functions. Those +helpers rely on the driver gem_prime_export and gem_prime_import +operations to create a dma-buf instance from a GEM object (dma-buf +exporter role) and to create a GEM object from a dma-buf instance +(dma-buf importer role). + +struct dma_buf \* (\*gem_prime_export)(struct drm_device \*dev, +struct drm_gem_object \*obj, int flags); struct drm_gem_object \* +(\*gem_prime_import)(struct drm_device \*dev, struct dma_buf +\*dma_buf); These two operations are mandatory for GEM drivers that +support PRIME. + +PRIME Helper Functions +~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/gpu/drm/drm_prime.c + :doc: PRIME Helpers + +PRIME Function References +------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_prime.c + :export: + +DRM MM Range Allocator +---------------------- + +Overview +~~~~~~~~ + +.. kernel-doc:: drivers/gpu/drm/drm_mm.c + :doc: Overview + +LRU Scan/Eviction Support +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/gpu/drm/drm_mm.c + :doc: lru scan roaster + +DRM MM Range Allocator Function References +------------------------------------------ + +.. kernel-doc:: drivers/gpu/drm/drm_mm.c + :export: + +.. kernel-doc:: include/drm/drm_mm.h + :internal: + +CMA Helper Functions Reference +------------------------------ + +.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c + :doc: cma helpers + +.. kernel-doc:: drivers/gpu/drm/drm_gem_cma_helper.c + :export: + +.. kernel-doc:: include/drm/drm_gem_cma_helper.h + :internal: diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst new file mode 100644 index 000000000000..536bf3eaadd4 --- /dev/null +++ b/Documentation/gpu/drm-uapi.rst @@ -0,0 +1,111 @@ +=================== +Userland interfaces +=================== + +The DRM core exports several interfaces to applications, generally +intended to be used through corresponding libdrm wrapper functions. In +addition, drivers export device-specific interfaces for use by userspace +drivers & device-aware applications through ioctls and sysfs files. + +External interfaces include: memory mapping, context management, DMA +operations, AGP management, vblank control, fence management, memory +management, and output management. + +Cover generic ioctls and sysfs layout here. We only need high-level +info, since man pages should cover the rest. + +libdrm Device Lookup +==================== + +.. kernel-doc:: drivers/gpu/drm/drm_ioctl.c + :doc: getunique and setversion story + + +Primary Nodes, DRM Master and Authentication +============================================ + +.. kernel-doc:: drivers/gpu/drm/drm_auth.c + :doc: master and authentication + +.. kernel-doc:: drivers/gpu/drm/drm_auth.c + :export: + +.. kernel-doc:: include/drm/drm_auth.h + :internal: + +Render nodes +============ + +DRM core provides multiple character-devices for user-space to use. +Depending on which device is opened, user-space can perform a different +set of operations (mainly ioctls). The primary node is always created +and called card<num>. Additionally, a currently unused control node, +called controlD<num> is also created. The primary node provides all +legacy operations and historically was the only interface used by +userspace. With KMS, the control node was introduced. However, the +planned KMS control interface has never been written and so the control +node stays unused to date. + +With the increased use of offscreen renderers and GPGPU applications, +clients no longer require running compositors or graphics servers to +make use of a GPU. But the DRM API required unprivileged clients to +authenticate to a DRM-Master prior to getting GPU access. To avoid this +step and to grant clients GPU access without authenticating, render +nodes were introduced. Render nodes solely serve render clients, that +is, no modesetting or privileged ioctls can be issued on render nodes. +Only non-global rendering commands are allowed. If a driver supports +render nodes, it must advertise it via the DRIVER_RENDER DRM driver +capability. If not supported, the primary node must be used for render +clients together with the legacy drmAuth authentication procedure. + +If a driver advertises render node support, DRM core will create a +separate render node called renderD<num>. There will be one render node +per device. No ioctls except PRIME-related ioctls will be allowed on +this node. Especially GEM_OPEN will be explicitly prohibited. Render +nodes are designed to avoid the buffer-leaks, which occur if clients +guess the flink names or mmap offsets on the legacy interface. +Additionally to this basic interface, drivers must mark their +driver-dependent render-only ioctls as DRM_RENDER_ALLOW so render +clients can use them. Driver authors must be careful not to allow any +privileged ioctls on render nodes. + +With render nodes, user-space can now control access to the render node +via basic file-system access-modes. A running graphics server which +authenticates clients on the privileged primary/legacy node is no longer +required. Instead, a client can open the render node and is immediately +granted GPU access. Communication between clients (or servers) is done +via PRIME. FLINK from render node to legacy node is not supported. New +clients must not use the insecure FLINK interface. + +Besides dropping all modeset/global ioctls, render nodes also drop the +DRM-Master concept. There is no reason to associate render clients with +a DRM-Master as they are independent of any graphics server. Besides, +they must work without any running master, anyway. Drivers must be able +to run without a master object if they support render nodes. If, on the +other hand, a driver requires shared state between clients which is +visible to user-space and accessible beyond open-file boundaries, they +cannot support render nodes. + +VBlank event handling +===================== + +The DRM core exposes two vertical blank related ioctls: + +DRM_IOCTL_WAIT_VBLANK + This takes a struct drm_wait_vblank structure as its argument, and + it is used to block or request a signal when a specified vblank + event occurs. + +DRM_IOCTL_MODESET_CTL + This was only used for user-mode-settind drivers around modesetting + changes to allow the kernel to update the vblank interrupt after + mode setting, since on many devices the vertical blank counter is + reset to 0 at some point during modeset. Modern drivers should not + call this any more since with kernel mode setting it is a no-op. + +This second part of the GPU Driver Developer's Guide documents driver +code, implementation details and also all the driver-specific userspace +interfaces. Especially since all hardware-acceleration interfaces to +userspace are driver specific for efficiency and other reasons these +interfaces can be rather substantial. Hence every driver has its own +chapter. diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst new file mode 100644 index 000000000000..2fe5952e90f1 --- /dev/null +++ b/Documentation/gpu/i915.rst @@ -0,0 +1,347 @@ +=========================== + drm/i915 Intel GFX Driver +=========================== + +The drm/i915 driver supports all (with the exception of some very early +models) integrated GFX chipsets with both Intel display and rendering +blocks. This excludes a set of SoC platforms with an SGX rendering unit, +those have basic support through the gma500 drm driver. + +Core Driver Infrastructure +========================== + +This section covers core driver infrastructure used by both the display +and the GEM parts of the driver. + +Runtime Power Management +------------------------ + +.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c + :doc: runtime pm + +.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c + :internal: + +Interrupt Handling +------------------ + +.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c + :doc: interrupt handling + +.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c + :functions: intel_irq_init intel_irq_init_hw intel_hpd_init + +.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c + :functions: intel_runtime_pm_disable_interrupts + +.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c + :functions: intel_runtime_pm_enable_interrupts + +Intel GVT-g Guest Support(vGPU) +------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c + :doc: Intel GVT-g guest support + +.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c + :internal: + +Display Hardware Handling +========================= + +This section covers everything related to the display hardware including +the mode setting infrastructure, plane, sprite and cursor handling and +display, output probing and related topics. + +Mode Setting Infrastructure +--------------------------- + +The i915 driver is thus far the only DRM driver which doesn't use the +common DRM helper code to implement mode setting sequences. Thus it has +its own tailor-made infrastructure for executing a display configuration +change. + +Frontbuffer Tracking +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c + :doc: frontbuffer tracking + +.. kernel-doc:: drivers/gpu/drm/i915/intel_frontbuffer.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem.c + :functions: i915_gem_track_fb + +Display FIFO Underrun Reporting +------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c + :doc: fifo underrun handling + +.. kernel-doc:: drivers/gpu/drm/i915/intel_fifo_underrun.c + :internal: + +Plane Configuration +------------------- + +This section covers plane configuration and composition with the primary +plane, sprites, cursors and overlays. This includes the infrastructure +to do atomic vsync'ed updates of all this state and also tightly coupled +topics like watermark setup and computation, framebuffer compression and +panel self refresh. + +Atomic Plane Helpers +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c + :doc: atomic plane helpers + +.. kernel-doc:: drivers/gpu/drm/i915/intel_atomic_plane.c + :internal: + +Output Probing +-------------- + +This section covers output probing and related infrastructure like the +hotplug interrupt storm detection and mitigation code. Note that the +i915 driver still uses most of the common DRM helper code for output +probing, so those sections fully apply. + +Hotplug +------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c + :doc: Hotplug + +.. kernel-doc:: drivers/gpu/drm/i915/intel_hotplug.c + :internal: + +High Definition Audio +--------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c + :doc: High Definition Audio over HDMI and Display Port + +.. kernel-doc:: drivers/gpu/drm/i915/intel_audio.c + :internal: + +.. kernel-doc:: include/drm/i915_component.h + :internal: + +Panel Self Refresh PSR (PSR/SRD) +-------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c + :doc: Panel Self Refresh (PSR/SRD) + +.. kernel-doc:: drivers/gpu/drm/i915/intel_psr.c + :internal: + +Frame Buffer Compression (FBC) +------------------------------ + +.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c + :doc: Frame Buffer Compression (FBC) + +.. kernel-doc:: drivers/gpu/drm/i915/intel_fbc.c + :internal: + +Display Refresh Rate Switching (DRRS) +------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :doc: Display Refresh Rate Switching (DRRS) + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_dp_set_drrs_state + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_edp_drrs_enable + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_edp_drrs_disable + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_edp_drrs_invalidate + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_edp_drrs_flush + +.. kernel-doc:: drivers/gpu/drm/i915/intel_dp.c + :functions: intel_dp_drrs_init + +DPIO +---- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h + :doc: DPIO + +CSR firmware support for DMC +---------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c + :doc: csr support for dmc + +.. kernel-doc:: drivers/gpu/drm/i915/intel_csr.c + :internal: + +Video BIOS Table (VBT) +---------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c + :doc: Video BIOS Table (VBT) + +.. kernel-doc:: drivers/gpu/drm/i915/intel_bios.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/intel_vbt_defs.h + :internal: + +Memory Management and Command Submission +======================================== + +This sections covers all things related to the GEM implementation in the +i915 driver. + +Batchbuffer Parsing +------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c + :doc: batch buffer command parser + +.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c + :internal: + +Batchbuffer Pools +----------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c + :doc: batch pool + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_batch_pool.c + :internal: + +Logical Rings, Logical Ring Contexts and Execlists +-------------------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c + :doc: Logical Rings, Logical Ring Contexts and Execlists + +.. kernel-doc:: drivers/gpu/drm/i915/intel_lrc.c + :internal: + +Global GTT views +---------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c + :doc: Global GTT views + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c + :internal: + +GTT Fences and Swizzling +------------------------ + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c + :internal: + +Global GTT Fence Handling +~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c + :doc: fence register handling + +Hardware Tiling and Swizzling Details +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence.c + :doc: tiling swizzling details + +Object Tiling IOCTLs +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_tiling.c + :doc: buffer object tiling + +Buffer Object Eviction +---------------------- + +This section documents the interface functions for evicting buffer +objects to make space available in the virtual gpu address spaces. Note +that this is mostly orthogonal to shrinking buffer objects caches, which +has the goal to make main memory (shared with the gpu through the +unified memory architecture) available. + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c + :internal: + +Buffer Object Memory Shrinking +------------------------------ + +This section documents the interface function for shrinking memory usage +of buffer object caches. Shrinking is used to make main memory +available. Note that this is mostly orthogonal to evicting buffer +objects, which has the goal to make space in gpu virtual address spaces. + +.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c + :internal: + +GuC +=== + +GuC-specific firmware loader +---------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c + :doc: GuC-specific firmware loader + +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c + :internal: + +GuC-based command submission +---------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_guc_submission.c + :doc: GuC-based command submission + +.. kernel-doc:: drivers/gpu/drm/i915/i915_guc_submission.c + :internal: + +GuC Firmware Layout +------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h + :doc: GuC Firmware Layout + +Tracing +======= + +This sections covers all things related to the tracepoints implemented +in the i915 driver. + +i915_ppgtt_create and i915_ppgtt_release +---------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h + :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints + +i915_context_create and i915_context_free +----------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h + :doc: i915_context_create and i915_context_free tracepoints + +switch_mm +--------- + +.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h + :doc: switch_mm tracepoint + +.. WARNING: DOCPROC directive not supported: !Cdrivers/gpu/drm/i915/i915_irq.c diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst new file mode 100644 index 000000000000..fcac0fa72056 --- /dev/null +++ b/Documentation/gpu/index.rst @@ -0,0 +1,14 @@ +================================== +Linux GPU Driver Developer's Guide +================================== + +.. toctree:: + + introduction + drm-internals + drm-mm + drm-kms + drm-kms-helpers + drm-uapi + i915 + vga-switcheroo diff --git a/Documentation/gpu/introduction.rst b/Documentation/gpu/introduction.rst new file mode 100644 index 000000000000..1903595b5310 --- /dev/null +++ b/Documentation/gpu/introduction.rst @@ -0,0 +1,51 @@ +============ +Introduction +============ + +The Linux DRM layer contains code intended to support the needs of +complex graphics devices, usually containing programmable pipelines well +suited to 3D graphics acceleration. Graphics drivers in the kernel may +make use of DRM functions to make tasks like memory management, +interrupt handling and DMA easier, and provide a uniform interface to +applications. + +A note on versions: this guide covers features found in the DRM tree, +including the TTM memory manager, output configuration and mode setting, +and the new vblank internals, in addition to all the regular features +found in current kernels. + +[Insert diagram of typical DRM stack here] + +Style Guidelines +================ + +For consistency this documentation uses American English. Abbreviations +are written as all-uppercase, for example: DRM, KMS, IOCTL, CRTC, and so +on. To aid in reading, documentations make full use of the markup +characters kerneldoc provides: @parameter for function parameters, +@member for structure members, &structure to reference structures and +function() for functions. These all get automatically hyperlinked if +kerneldoc for the referenced objects exists. When referencing entries in +function vtables please use ->vfunc(). Note that kerneldoc does not +support referencing struct members directly, so please add a reference +to the vtable struct somewhere in the same paragraph or at least +section. + +Except in special situations (to separate locked from unlocked variants) +locking requirements for functions aren't documented in the kerneldoc. +Instead locking should be check at runtime using e.g. +``WARN_ON(!mutex_is_locked(...));``. Since it's much easier to ignore +documentation than runtime noise this provides more value. And on top of +that runtime checks do need to be updated when the locking rules change, +increasing the chances that they're correct. Within the documentation +the locking rules should be explained in the relevant structures: Either +in the comment for the lock explaining what it protects, or data fields +need a note about which lock protects them, or both. + +Functions which have a non-\ ``void`` return value should have a section +called "Returns" explaining the expected return values in different +cases and their meanings. Currently there's no consensus whether that +section name should be all upper-case or not, and whether it should end +in a colon or not. Go with the file-local style. Other common section +names are "Notes" with information for dangerous or tricky corner cases, +and "FIXME" where the interface could be cleaned up. diff --git a/Documentation/gpu/kms-properties.csv b/Documentation/gpu/kms-properties.csv new file mode 100644 index 000000000000..b6fcaf639c04 --- /dev/null +++ b/Documentation/gpu/kms-properties.csv @@ -0,0 +1,128 @@ +Owner Module/Drivers,Group,Property Name,Type,Property Values,Object attached,Description/Restrictions +DRM,Generic,“rotation”,BITMASK,"{ 0, ""rotate-0"" }, { 1, ""rotate-90"" }, { 2, ""rotate-180"" }, { 3, ""rotate-270"" }, { 4, ""reflect-x"" }, { 5, ""reflect-y"" }","CRTC, Plane",rotate-(degrees) rotates the image by the specified amount in degrees in counter clockwise direction. reflect-x and reflect-y reflects the image along the specified axis prior to rotation +,,“scaling mode”,ENUM,"{ ""None"", ""Full"", ""Center"", ""Full aspect"" }",Connector,"Supported by: amdgpu, gma500, i915, nouveau and radeon." +,Connector,“EDID”,BLOB | IMMUTABLE,0,Connector,Contains id of edid blob ptr object. +,,“DPMS”,ENUM,"{ “On”, “Standby”, “Suspend”, “Off” }",Connector,Contains DPMS operation mode value. +,,“PATH”,BLOB | IMMUTABLE,0,Connector,Contains topology path to a connector. +,,“TILE”,BLOB | IMMUTABLE,0,Connector,Contains tiling information for a connector. +,,“CRTC_ID”,OBJECT,DRM_MODE_OBJECT_CRTC,Connector,CRTC that connector is attached to (atomic) +,Plane,“type”,ENUM | IMMUTABLE,"{ ""Overlay"", ""Primary"", ""Cursor"" }",Plane,Plane type +,,“SRC_X”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source x coordinate in 16.16 fixed point (atomic) +,,“SRC_Y”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source y coordinate in 16.16 fixed point (atomic) +,,“SRC_W”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source width in 16.16 fixed point (atomic) +,,“SRC_H”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout source height in 16.16 fixed point (atomic) +,,“CRTC_X”,SIGNED_RANGE,"Min=INT_MIN, Max=INT_MAX",Plane,Scanout CRTC (destination) x coordinate (atomic) +,,“CRTC_Y”,SIGNED_RANGE,"Min=INT_MIN, Max=INT_MAX",Plane,Scanout CRTC (destination) y coordinate (atomic) +,,“CRTC_W”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout CRTC (destination) width (atomic) +,,“CRTC_H”,RANGE,"Min=0, Max=UINT_MAX",Plane,Scanout CRTC (destination) height (atomic) +,,“FB_ID”,OBJECT,DRM_MODE_OBJECT_FB,Plane,Scanout framebuffer (atomic) +,,“CRTC_ID”,OBJECT,DRM_MODE_OBJECT_CRTC,Plane,CRTC that plane is attached to (atomic) +,DVI-I,“subconnector”,ENUM,"{ “Unknown”, “DVI-D”, “DVI-A” }",Connector,TBD +,,“select subconnector”,ENUM,"{ “Automatic”, “DVI-D”, “DVI-A” }",Connector,TBD +,TV,“subconnector”,ENUM,"{ ""Unknown"", ""Composite"", ""SVIDEO"", ""Component"", ""SCART"" }",Connector,TBD +,,“select subconnector”,ENUM,"{ ""Automatic"", ""Composite"", ""SVIDEO"", ""Component"", ""SCART"" }",Connector,TBD +,,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD +,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD +,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD +,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD +,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD +,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD +,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD +,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD +,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD +,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD +,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD +,Virtual GPU,“suggested X”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an X offset for a connector +,,“suggested Y”,RANGE,"Min=0, Max=0xffffffff",Connector,property to suggest an Y offset for a connector +,Optional,"""aspect ratio""",ENUM,"{ ""None"", ""4:3"", ""16:9"" }",Connector,TDB +,,“dirty”,ENUM | IMMUTABLE,"{ ""Off"", ""On"", ""Annotate"" }",Connector,TBD +,,“DEGAMMA_LUT”,BLOB,0,CRTC,DRM property to set the degamma lookup table (LUT) mapping pixel data from the framebuffer before it is given to the transformation matrix. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]). +,,“DEGAMMA_LUT_SIZE”,RANGE | IMMUTABLE,"Min=0, Max=UINT_MAX",CRTC,DRM property to gives the size of the lookup table to be set on the DEGAMMA_LUT property (the size depends on the underlying hardware). +,,“CTM”,BLOB,0,CRTC,DRM property to set the current transformation matrix (CTM) apply to pixel data after the lookup through the degamma LUT and before the lookup through the gamma LUT. The data is an interpreted as a struct drm_color_ctm. +,,“GAMMA_LUT”,BLOB,0,CRTC,DRM property to set the gamma lookup table (LUT) mapping pixel data after to the transformation matrix to data sent to the connector. The data is an interpreted as an array of struct drm_color_lut elements. Hardware might choose not to use the full precision of the LUT elements nor use all the elements of the LUT (for example the hardware might choose to interpolate between LUT[0] and LUT[4]). +,,“GAMMA_LUT_SIZE”,RANGE | IMMUTABLE,"Min=0, Max=UINT_MAX",CRTC,DRM property to gives the size of the lookup table to be set on the GAMMA_LUT property (the size depends on the underlying hardware). +i915,Generic,"""Broadcast RGB""",ENUM,"{ ""Automatic"", ""Full"", ""Limited 16:235"" }",Connector,"When this property is set to Limited 16:235 and CTM is set, the hardware will be programmed with the result of the multiplication of CTM by the limited range matrix to ensure the pixels normaly in the range 0..1.0 are remapped to the range 16/255..235/255." +,,“audio”,ENUM,"{ ""force-dvi"", ""off"", ""auto"", ""on"" }",Connector,TBD +,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD +,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""right_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""top_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""bottom_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“hpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“vpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“contrast”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“saturation”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“hue”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“sharpness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter_adaptive”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter_2d”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“tv_chroma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“tv_luma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD +,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +CDV gma-500,Generic,"""Broadcast RGB""",ENUM,"{ “Full”, “Limited 16:235” }",Connector,TBD +,,"""Broadcast RGB""",ENUM,"{ “off”, “auto”, “on” }",Connector,TBD +Poulsbo,Generic,“backlight”,RANGE,"Min=0, Max=100",Connector,TBD +,SDVO-TV,“mode”,ENUM,"{ ""NTSC_M"", ""NTSC_J"", ""NTSC_443"", ""PAL_B"" } etc.",Connector,TBD +,,"""left_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""right_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""top_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,"""bottom_margin""",RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“hpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“vpos”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“contrast”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“saturation”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“hue”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“sharpness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter_adaptive”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“flicker_filter_2d”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“tv_chroma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“tv_luma_filter”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +,,“dot_crawl”,RANGE,"Min=0, Max=1",Connector,TBD +,SDVO-TV/LVDS,“brightness”,RANGE,"Min=0, Max= SDVO dependent",Connector,TBD +armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD +,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD +,Overlay,"""colorkey""",RANGE,"Min=0, Max=0xffffff",Plane,TBD +,,"""colorkey_min""",RANGE,"Min=0, Max=0xffffff",Plane,TBD +,,"""colorkey_max""",RANGE,"Min=0, Max=0xffffff",Plane,TBD +,,"""colorkey_val""",RANGE,"Min=0, Max=0xffffff",Plane,TBD +,,"""colorkey_alpha""",RANGE,"Min=0, Max=0xffffff",Plane,TBD +,,"""colorkey_mode""",ENUM,"{ ""disabled"", ""Y component"", ""U component"" , ""V component"", ""RGB"", “R component"", ""G component"", ""B component"" }",Plane,TBD +,,"""brightness""",RANGE,"Min=0, Max=256 + 255",Plane,TBD +,,"""contrast""",RANGE,"Min=0, Max=0x7fff",Plane,TBD +,,"""saturation""",RANGE,"Min=0, Max=0x7fff",Plane,TBD +exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD +,Overlay,“zpos”,RANGE,"Min=0, Max=MAX_PLANE-1",Plane,TBD +i2c/ch7006_drv,Generic,“scale”,RANGE,"Min=0, Max=2",Connector,TBD +,TV,“mode”,ENUM,"{ ""PAL"", ""PAL-M"",""PAL-N""}, ”PAL-Nc"" , ""PAL-60"", ""NTSC-M"", ""NTSC-J"" }",Connector,TBD +nouveau,NV10 Overlay,"""colorkey""",RANGE,"Min=0, Max=0x01ffffff",Plane,TBD +,,“contrast”,RANGE,"Min=0, Max=8192-1",Plane,TBD +,,“brightness”,RANGE,"Min=0, Max=1024",Plane,TBD +,,“hue”,RANGE,"Min=0, Max=359",Plane,TBD +,,“saturation”,RANGE,"Min=0, Max=8192-1",Plane,TBD +,,“iturbt_709”,RANGE,"Min=0, Max=1",Plane,TBD +,Nv04 Overlay,“colorkey”,RANGE,"Min=0, Max=0x01ffffff",Plane,TBD +,,“brightness”,RANGE,"Min=0, Max=1024",Plane,TBD +,Display,“dithering mode”,ENUM,"{ ""auto"", ""off"", ""on"" }",Connector,TBD +,,“dithering depth”,ENUM,"{ ""auto"", ""off"", ""on"", ""static 2x2"", ""dynamic 2x2"", ""temporal"" }",Connector,TBD +,,“underscan”,ENUM,"{ ""auto"", ""6 bpc"", ""8 bpc"" }",Connector,TBD +,,“underscan hborder”,RANGE,"Min=0, Max=128",Connector,TBD +,,“underscan vborder”,RANGE,"Min=0, Max=128",Connector,TBD +,,“vibrant hue”,RANGE,"Min=0, Max=180",Connector,TBD +,,“color vibrance”,RANGE,"Min=0, Max=200",Connector,TBD +omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD +qxl,Generic,"“hotplug_mode_update""",RANGE,"Min=0, Max=1",Connector,TBD +radeon,DVI-I,“coherent”,RANGE,"Min=0, Max=1",Connector,TBD +,DAC enable load detect,“load detection”,RANGE,"Min=0, Max=1",Connector,TBD +,TV Standard,"""tv standard""",ENUM,"{ ""ntsc"", ""pal"", ""pal-m"", ""pal-60"", ""ntsc-j"" , ""scart-pal"", ""pal-cn"", ""secam"" }",Connector,TBD +,legacy TMDS PLL detect,"""tmds_pll""",ENUM,"{ ""driver"", ""bios"" }",-,TBD +,Underscan,"""underscan""",ENUM,"{ ""off"", ""on"", ""auto"" }",Connector,TBD +,,"""underscan hborder""",RANGE,"Min=0, Max=128",Connector,TBD +,,"""underscan vborder""",RANGE,"Min=0, Max=128",Connector,TBD +,Audio,“audio”,ENUM,"{ ""off"", ""on"", ""auto"" }",Connector,TBD +,FMT Dithering,“dither”,ENUM,"{ ""off"", ""on"" }",Connector,TBD +rcar-du,Generic,"""alpha""",RANGE,"Min=0, Max=255",Plane,TBD +,,"""colorkey""",RANGE,"Min=0, Max=0x01ffffff",Plane,TBD +,,"""zpos""",RANGE,"Min=1, Max=7",Plane,TBD diff --git a/Documentation/gpu/vga-switcheroo.rst b/Documentation/gpu/vga-switcheroo.rst new file mode 100644 index 000000000000..cbbdb994f1dd --- /dev/null +++ b/Documentation/gpu/vga-switcheroo.rst @@ -0,0 +1,98 @@ +.. _vga_switcheroo: + +============== +VGA Switcheroo +============== + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :doc: Overview + +Modes of Use +============ + +Manual switching and manual power control +----------------------------------------- + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :doc: Manual switching and manual power control + +Driver power control +-------------------- + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :doc: Driver power control + +API +=== + +Public functions +---------------- + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :export: + +Public structures +----------------- + +.. kernel-doc:: include/linux/vga_switcheroo.h + :functions: vga_switcheroo_handler + +.. kernel-doc:: include/linux/vga_switcheroo.h + :functions: vga_switcheroo_client_ops + +Public constants +---------------- + +.. kernel-doc:: include/linux/vga_switcheroo.h + :functions: vga_switcheroo_handler_flags_t + +.. kernel-doc:: include/linux/vga_switcheroo.h + :functions: vga_switcheroo_client_id + +.. kernel-doc:: include/linux/vga_switcheroo.h + :functions: vga_switcheroo_state + +Private structures +------------------ + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :functions: vgasr_priv + +.. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c + :functions: vga_switcheroo_client + +Handlers +======== + +apple-gmux Handler +------------------ + +.. kernel-doc:: drivers/platform/x86/apple-gmux.c + :doc: Overview + +.. kernel-doc:: drivers/platform/x86/apple-gmux.c + :doc: Interrupt + +Graphics mux +~~~~~~~~~~~~ + +.. kernel-doc:: drivers/platform/x86/apple-gmux.c + :doc: Graphics mux + +Power control +~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/platform/x86/apple-gmux.c + :doc: Power control + +Backlight control +~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/platform/x86/apple-gmux.c + :doc: Backlight control + +Public functions +~~~~~~~~~~~~~~~~ + +.. kernel-doc:: include/linux/apple-gmux.h + :internal: diff --git a/Documentation/hid/hid-alps.txt b/Documentation/hid/hid-alps.txt new file mode 100644 index 000000000000..6b02a2447c77 --- /dev/null +++ b/Documentation/hid/hid-alps.txt @@ -0,0 +1,139 @@ +ALPS HID Touchpad Protocol +---------------------- + +Introduction +------------ +Currently ALPS HID driver supports U1 Touchpad device. + +U1 devuce basic information. +Vender ID 0x044E +Product ID 0x120B +Version ID 0x0121 + + +HID Descriptor +------------ +Byte Field Value Notes +0 wHIDDescLength 001E Length of HID Descriptor : 30 bytes +2 bcdVersion 0100 Compliant with Version 1.00 +4 wReportDescLength 00B2 Report Descriptor is 178 Bytes (0x00B2) +6 wReportDescRegister 0002 Identifier to read Report Descriptor +8 wInputRegister 0003 Identifier to read Input Report +10 wMaxInputLength 0053 Input Report is 80 Bytes + 2 +12 wOutputRegister 0000 Identifier to read Output Report +14 wMaxOutputLength 0000 No Output Reports +16 wCommandRegister 0005 Identifier for Command Register +18 wDataRegister 0006 Identifier for Data Register +20 wVendorID 044E Vendor ID 0x044E +22 wProductID 120B Product ID 0x120B +24 wVersionID 0121 Version 01.21 +26 RESERVED 0000 RESERVED + + +Report ID +------------ +ReportID-1 (Input Reports) (HIDUsage-Mouse) for TP&SP +ReportID-2 (Input Reports) (HIDUsage-keyboard) for TP +ReportID-3 (Input Reports) (Vendor Usage: Max 10 finger data) for TP +ReportID-4 (Input Reports) (Vendor Usage: ON bit data) for GP +ReportID-5 (Feature Reports) Feature Reports +ReportID-6 (Input Reports) (Vendor Usage: StickPointer data) for SP +ReportID-7 (Feature Reports) Flash update (Bootloader) + + +Data pattern +------------ +Case1 ReportID_1 TP/SP Relative/Relative +Case2 ReportID_3 TP Absolute + ReportID_6 SP Absolute + + +Command Read/Write +------------------ +To read/write to RAM, need to send a commands to the device. +The command format is as below. + +DataByte(SET_REPORT) +Byte1 Command Byte +Byte2 Address - Byte 0 (LSB) +Byte3 Address - Byte 1 +Byte4 Address - Byte 2 +Byte5 Address - Byte 3 (MSB) +Byte6 Value Byte +Byte7 Checksum + +Command Byte is read=0xD1/write=0xD2 . +Address is read/write RAM address. +Value Byte is writing data when you send the write commands. +When you read RAM, there is no meaning. + +DataByte(GET_REPORT) +Byte1 Response Byte +Byte2 Address - Byte 0 (LSB) +Byte3 Address - Byte 1 +Byte4 Address - Byte 2 +Byte5 Address - Byte 3 (MSB) +Byte6 Value Byte +Byte7 Checksum + +Read value is stored in Value Byte. + + +Packet Format +Touchpad data byte +------------------ + b7 b6 b5 b4 b3 b2 b1 b0 +1 0 0 SW6 SW5 SW4 SW3 SW2 SW1 +2 0 0 0 Fcv Fn3 Fn2 Fn1 Fn0 +3 Xa0_7 Xa0_6 Xa0_5 Xa0_4 Xa0_3 Xa0_2 Xa0_1 Xa0_0 +4 Xa0_15 Xa0_14 Xa0_13 Xa0_12 Xa0_11 Xa0_10 Xa0_9 Xa0_8 +5 Ya0_7 Ya0_6 Ya0_5 Ya0_4 Ya0_3 Ya0_2 Ya0_1 Ya0_0 +6 Ya0_15 Ya0_14 Ya0_13 Ya0_12 Ya0_11 Ya0_10 Ya0_9 Ya0_8 +7 LFB0 Zs0_6 Zs0_5 Zs0_4 Zs0_3 Zs0_2 Zs0_1 Zs0_0 + +8 Xa1_7 Xa1_6 Xa1_5 Xa1_4 Xa1_3 Xa1_2 Xa1_1 Xa1_0 +9 Xa1_15 Xa1_14 Xa1_13 Xa1_12 Xa1_11 Xa1_10 Xa1_9 Xa1_8 +10 Ya1_7 Ya1_6 Ya1_5 Ya1_4 Ya1_3 Ya1_2 Ya1_1 Ya1_0 +11 Ya1_15 Ya1_14 Ya1_13 Ya1_12 Ya1_11 Ya1_10 Ya1_9 Ya1_8 +12 LFB1 Zs1_6 Zs1_5 Zs1_4 Zs1_3 Zs1_2 Zs1_1 Zs1_0 + +13 Xa2_7 Xa2_6 Xa2_5 Xa2_4 Xa2_3 Xa2_2 Xa2_1 Xa2_0 +14 Xa2_15 Xa2_14 Xa2_13 Xa2_12 Xa2_11 Xa2_10 Xa2_9 Xa2_8 +15 Ya2_7 Ya2_6 Ya2_5 Ya2_4 Ya2_3 Ya2_2 Ya2_1 Ya2_0 +16 Ya2_15 Ya2_14 Ya2_13 Ya2_12 Ya2_11 Ya2_10 Ya2_9 Ya2_8 +17 LFB2 Zs2_6 Zs2_5 Zs2_4 Zs2_3 Zs2_2 Zs2_1 Zs2_0 + +18 Xa3_7 Xa3_6 Xa3_5 Xa3_4 Xa3_3 Xa3_2 Xa3_1 Xa3_0 +19 Xa3_15 Xa3_14 Xa3_13 Xa3_12 Xa3_11 Xa3_10 Xa3_9 Xa3_8 +20 Ya3_7 Ya3_6 Ya3_5 Ya3_4 Ya3_3 Ya3_2 Ya3_1 Ya3_0 +21 Ya3_15 Ya3_14 Ya3_13 Ya3_12 Ya3_11 Ya3_10 Ya3_9 Ya3_8 +22 LFB3 Zs3_6 Zs3_5 Zs3_4 Zs3_3 Zs3_2 Zs3_1 Zs3_0 + +23 Xa4_7 Xa4_6 Xa4_5 Xa4_4 Xa4_3 Xa4_2 Xa4_1 Xa4_0 +24 Xa4_15 Xa4_14 Xa4_13 Xa4_12 Xa4_11 Xa4_10 Xa4_9 Xa4_8 +25 Ya4_7 Ya4_6 Ya4_5 Ya4_4 Ya4_3 Ya4_2 Ya4_1 Ya4_0 +26 Ya4_15 Ya4_14 Ya4_13 Ya4_12 Ya4_11 Ya4_10 Ya4_9 Ya4_8 +27 LFB4 Zs4_6 Zs4_5 Zs4_4 Zs4_3 Zs4_2 Zs4_1 Zs4_0 + + +SW1-SW6: SW ON/OFF status +Xan_15-0(16bit):X Absolute data of the "n"th finger +Yan_15-0(16bit):Y Absolute data of the "n"th finger +Zsn_6-0(7bit): Operation area of the "n"th finger + + +StickPointer data byte +------------------ + b7 b6 b5 b4 b3 b2 b1 b0 +Byte1 1 1 1 0 1 SW3 SW2 SW1 +Byte2 X7 X6 X5 X4 X3 X2 X1 X0 +Byte3 X15 X14 X13 X12 X11 X10 X9 X8 +Byte4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 +Byte5 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 +Byte6 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 +Byte7 T&P Z14 Z13 Z12 Z11 Z10 Z9 Z8 + +SW1-SW3: SW ON/OFF status +Xn_15-0(16bit):X Absolute data +Yn_15-0(16bit):Y Absolute data +Zn_14-0(15bit):Z diff --git a/Documentation/index.rst b/Documentation/index.rst index 43c722f15292..e0fc72963e87 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -18,6 +18,7 @@ Contents: media/media_kapi media/dvb-drivers/index media/v4l-drivers/index + gpu/index Indices and tables ================== diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 9369d3b0f09a..81c7f2bb7daf 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -248,7 +248,7 @@ Code Seq#(hex) Include File Comments 'm' 00 drivers/scsi/megaraid/megaraid_ioctl.h conflict! 'm' 00-1F net/irda/irmod.h conflict! 'n' 00-7F linux/ncp_fs.h and fs/ncpfs/ioctl.c -'n' 80-8F linux/nilfs2_fs.h NILFS2 +'n' 80-8F uapi/linux/nilfs2_api.h NILFS2 'n' E0-FF linux/matroxfb.h matroxfb 'o' 00-1F fs/ocfs2/ocfs2_fs.h OCFS2 'o' 00-03 mtd/ubi-user.h conflict! (OCFS2 and UBI overlaps) @@ -303,6 +303,7 @@ Code Seq#(hex) Include File Comments <mailto:buk@buks.ipn.de> 0xA0 all linux/sdp/sdp.h Industrial Device Project <mailto:kenji@bitgate.com> +0xA1 0 linux/vtpm_proxy.h TPM Emulator Proxy Driver 0xA2 00-0F arch/tile/include/asm/hardwall.h 0xA3 80-8F Port ACL in development: <mailto:tlewis@mindspring.com> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 769db8399ac8..eb0a0582d912 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -931,9 +931,18 @@ bytes respectively. Such letter suffixes can also be entirely omitted. dhash_entries= [KNL] Set number of hash buckets for dentry cache. + disable_1tb_segments [PPC] + Disables the use of 1TB hash page table segments. This + causes the kernel to fall back to 256MB segments which + can be useful when debugging issues that require an SLB + miss to occur. + disable= [IPV6] See Documentation/networking/ipv6.txt. + disable_radix [PPC] + Disable RADIX MMU mode on POWER9 + disable_cpu_apicid= [X86,APIC,SMP] Format: <int> The number of initial APIC ID for the @@ -2311,6 +2320,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Note that if CONFIG_MODULE_SIG_FORCE is set, that is always true, so this option does nothing. + module_blacklist= [KNL] Do not load a comma-separated list of + modules. Useful for debugging problem modules. + mousedev.tap_time= [MOUSE] Maximum time between finger touching and leaving touchpad surface for touch to be considered @@ -3012,6 +3024,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. resource_alignment= Format: [<order of align>@][<domain>:]<bus>:<slot>.<func>[; ...] + [<order of align>@]pci:<vendor>:<device>\ + [:<subvendor>:<subdevice>][; ...] Specifies alignment and device to reassign aligned memory resources. If <order of align> is not specified, @@ -3030,6 +3044,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. hpmemsize=nn[KMG] The fixed amount of bus space which is reserved for hotplug bridge's memory window. Default size is 2 megabytes. + hpbussize=nn The minimum amount of additional bus numbers + reserved for buses below a hotplug bridge. + Default is 1. realloc= Enable/disable reallocating PCI bridge resources if allocations done by BIOS are too small to accommodate resources required by all child @@ -3061,6 +3078,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted. compat Treat PCIe ports as PCI-to-PCI bridges, disable the PCIe ports driver. + pcie_port_pm= [PCIE] PCIe port power management handling: + off Disable power management of all PCIe ports + force Forcibly enable power management of all PCIe ports + pcie_pme= [PCIE,PM] Native PCIe PME signaling options: nomsi Do not use MSI for native PCIe PME signaling (this makes all PCIe root ports use INTx for all services). @@ -3164,6 +3185,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Format: <bool> (1/Y/y=enable, 0/N/n=disable) default: disabled + printk.devkmsg={on,off,ratelimit} + Control writing to /dev/kmsg. + on - unlimited logging to /dev/kmsg from userspace + off - logging to /dev/kmsg disabled + ratelimit - ratelimit the logging + Default: ratelimit + printk.time= Show timing data prefixed to each printk message line Format: <bool> (1/Y/y=enable, 0/N/n=disable) @@ -3849,6 +3877,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. using these two parameters to set the minimum and maximum port values. + sunrpc.svc_rpc_per_connection_limit= + [NFS,SUNRPC] + Limit the number of requests that the server will + process in parallel from a single connection. + The default value is 0 (no limit). + sunrpc.pool_mode= [NFS] Control how the NFS server code allocates CPUs to diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt index caa555706f89..404a0e9e92b0 100644 --- a/Documentation/mmc/mmc-dev-attrs.txt +++ b/Documentation/mmc/mmc-dev-attrs.txt @@ -28,6 +28,8 @@ All attributes are read-only. preferred_erase_size Preferred erase size raw_rpmb_size_mult RPMB partition size rel_sectors Reliable write sector count + ocr Operation Conditions Register + dsr Driver Stage Register Note on Erase Size and Preferred Erase Size: diff --git a/Documentation/module-signing.txt b/Documentation/module-signing.txt index 696d5caf4fd8..f0e3361db20c 100644 --- a/Documentation/module-signing.txt +++ b/Documentation/module-signing.txt @@ -271,3 +271,9 @@ Since the private key is used to sign modules, viruses and malware could use the private key to sign modules and compromise the operating system. The private key must be either destroyed or moved to a secure location and not kept in the root node of the kernel source tree. + +If you use the same private key to sign modules for multiple kernel +configurations, you must ensure that the module version information is +sufficient to prevent loading a module into a different kernel. Either +set CONFIG_MODVERSIONS=y or ensure that each configuration has a different +kernel release string by changing EXTRAVERSION or CONFIG_LOCALVERSION. diff --git a/Documentation/nvdimm/btt.txt b/Documentation/nvdimm/btt.txt index b91443f577dc..e293fb664924 100644 --- a/Documentation/nvdimm/btt.txt +++ b/Documentation/nvdimm/btt.txt @@ -256,28 +256,18 @@ If any of these error conditions are encountered, the arena is put into a read only state using a flag in the info block. -5. In-kernel usage -================== +5. Usage +======== -Any block driver that supports byte granularity IO to the storage may register -with the BTT. It will have to provide the rw_bytes interface in its -block_device_operations struct: +The BTT can be set up on any disk (namespace) exposed by the libnvdimm subsystem +(pmem, or blk mode). The easiest way to set up such a namespace is using the +'ndctl' utility [1]: - int (*rw_bytes)(struct gendisk *, void *, size_t, off_t, int rw); +For example, the ndctl command line to setup a btt with a 4k sector size is: -It may register with the BTT after it adds its own gendisk, using btt_init: + ndctl create-namespace -f -e namespace0.0 -m sector -l 4k - struct btt *btt_init(struct gendisk *disk, unsigned long long rawsize, - u32 lbasize, u8 uuid[], int maxlane); +See ndctl create-namespace --help for more options. -note that maxlane is the maximum amount of concurrency the driver wishes to -allow the BTT to use. - -The BTT 'disk' appears as a stacked block device that grabs the underlying block -device in the O_EXCL mode. - -When the driver wishes to remove the backing disk, it should similarly call -btt_fini using the same struct btt* handle that was provided to it by btt_init. - - void btt_fini(struct btt *btt); +[1]: https://github.com/pmem/ndctl diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 4976389e432d..0d3b9ce0a0b9 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -286,13 +286,13 @@ see the section named "pin control requests from drivers" and "drivers needing both pin control and GPIOs" below for details. But in some situations a cross-subsystem mapping between pins and GPIOs is needed. -Since the pin controller subsystem have its pinspace local to the pin -controller we need a mapping so that the pin control subsystem can figure out -which pin controller handles control of a certain GPIO pin. Since a single -pin controller may be muxing several GPIO ranges (typically SoCs that have -one set of pins, but internally several GPIO silicon blocks, each modelled as -a struct gpio_chip) any number of GPIO ranges can be added to a pin controller -instance like this: +Since the pin controller subsystem has its pinspace local to the pin controller +we need a mapping so that the pin control subsystem can figure out which pin +controller handles control of a certain GPIO pin. Since a single pin controller +may be muxing several GPIO ranges (typically SoCs that have one set of pins, +but internally several GPIO silicon blocks, each modelled as a struct +gpio_chip) any number of GPIO ranges can be added to a pin controller instance +like this: struct gpio_chip chip_a; struct gpio_chip chip_b; @@ -493,12 +493,12 @@ Definitions: - The combination of a FUNCTION and a PIN GROUP determine a certain function for a certain set of pins. The knowledge of the functions and pin groups and their machine-specific particulars are kept inside the pinmux driver, - from the outside only the enumerators are known, and the driver core can: + from the outside only the enumerators are known, and the driver core can + request: - - Request the name of a function with a certain selector (>= 0) + - The name of a function with a certain selector (>= 0) - A list of groups associated with a certain function - - Request that a certain group in that list to be activated for a certain - function + - That a certain group in that list to be activated for a certain function As already described above, pin groups are in turn self-descriptive, so the core will retrieve the actual pin range in a certain group from the @@ -831,7 +831,7 @@ separate memory range only intended for GPIO driving, and the register range dealing with pin config and pin multiplexing get placed into a different memory range and a separate section of the data sheet. -A flag "strict" in struct pinctrl_desc is available to check and deny +A flag "strict" in struct pinmux_ops is available to check and deny simultaneous access to the same pin from GPIO and pin multiplexing consumers on hardware of this type. The pinctrl driver should set this flag accordingly. diff --git a/Documentation/ramoops.txt b/Documentation/ramoops.txt index 9264bcab4099..26b9f31cf65a 100644 --- a/Documentation/ramoops.txt +++ b/Documentation/ramoops.txt @@ -45,18 +45,34 @@ corrupt, but usually it is restorable. 2. Setting the parameters -Setting the ramoops parameters can be done in 3 different manners: - 1. Use the module parameters (which have the names of the variables described - as before). - For quick debugging, you can also reserve parts of memory during boot - and then use the reserved memory for ramoops. For example, assuming a machine - with > 128 MB of memory, the following kernel command line will tell the - kernel to use only the first 128 MB of memory, and place ECC-protected ramoops - region at 128 MB boundary: +Setting the ramoops parameters can be done in several different manners: + + A. Use the module parameters (which have the names of the variables described + as before). For quick debugging, you can also reserve parts of memory during + boot and then use the reserved memory for ramoops. For example, assuming a + machine with > 128 MB of memory, the following kernel command line will tell + the kernel to use only the first 128 MB of memory, and place ECC-protected + ramoops region at 128 MB boundary: "mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1" - 2. Use Device Tree bindings, as described in - Documentation/device-tree/bindings/misc/ramoops.txt. - 3. Use a platform device and set the platform data. The parameters can then + + B. Use Device Tree bindings, as described in + Documentation/device-tree/bindings/reserved-memory/ramoops.txt. + For example: + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@8f000000 { + compatible = "ramoops"; + reg = <0 0x8f000000 0 0x100000>; + record-size = <0x4000>; + console-size = <0x4000>; + }; + }; + + C. Use a platform device and set the platform data. The parameters can then be set through that platform data. An example of doing that is: #include <linux/pstore_ram.h> diff --git a/Documentation/rapidio/mport_cdev.txt b/Documentation/rapidio/mport_cdev.txt index 20c120d4b3b8..6e491a662461 100644 --- a/Documentation/rapidio/mport_cdev.txt +++ b/Documentation/rapidio/mport_cdev.txt @@ -82,8 +82,7 @@ III. Module parameters - 'dbg_level' - This parameter allows to control amount of debug information generated by this device driver. This parameter is formed by set of - This parameter can be changed bit masks that correspond to the specific - functional block. + bit masks that correspond to the specific functional blocks. For mask definitions see 'drivers/rapidio/devices/rio_mport_cdev.c' This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. diff --git a/Documentation/rapidio/rio_cm.txt b/Documentation/rapidio/rio_cm.txt new file mode 100644 index 000000000000..27aa401f1126 --- /dev/null +++ b/Documentation/rapidio/rio_cm.txt @@ -0,0 +1,119 @@ +RapidIO subsystem Channelized Messaging character device driver (rio_cm.c) +========================================================================== + +Version History: +---------------- + 1.0.0 - Initial driver release. + +========================================================================== + +I. Overview + +This device driver is the result of collaboration within the RapidIO.org +Software Task Group (STG) between Texas Instruments, Prodrive Technologies, +Nokia Networks, BAE and IDT. Additional input was received from other members +of RapidIO.org. + +The objective was to create a character mode driver interface which exposes +messaging capabilities of RapidIO endpoint devices (mports) directly +to applications, in a manner that allows the numerous and varied RapidIO +implementations to interoperate. + +This driver (RIO_CM) provides to user-space applications shared access to +RapidIO mailbox messaging resources. + +RapidIO specification (Part 2) defines that endpoint devices may have up to four +messaging mailboxes in case of multi-packet message (up to 4KB) and +up to 64 mailboxes if single-packet messages (up to 256 B) are used. In addition +to protocol definition limitations, a particular hardware implementation can +have reduced number of messaging mailboxes. RapidIO aware applications must +therefore share the messaging resources of a RapidIO endpoint. + +Main purpose of this device driver is to provide RapidIO mailbox messaging +capability to large number of user-space processes by introducing socket-like +operations using a single messaging mailbox. This allows applications to +use the limited RapidIO messaging hardware resources efficiently. + +Most of device driver's operations are supported through 'ioctl' system calls. + +When loaded this device driver creates a single file system node named rio_cm +in /dev directory common for all registered RapidIO mport devices. + +Following ioctl commands are available to user-space applications: + +- RIO_CM_MPORT_GET_LIST : Returns to caller list of local mport devices that + support messaging operations (number of entries up to RIO_MAX_MPORTS). + Each list entry is combination of mport's index in the system and RapidIO + destination ID assigned to the port. +- RIO_CM_EP_GET_LIST_SIZE : Returns number of messaging capable remote endpoints + in a RapidIO network associated with the specified mport device. +- RIO_CM_EP_GET_LIST : Returns list of RapidIO destination IDs for messaging + capable remote endpoints (peers) available in a RapidIO network associated + with the specified mport device. +- RIO_CM_CHAN_CREATE : Creates RapidIO message exchange channel data structure + with channel ID assigned automatically or as requested by a caller. +- RIO_CM_CHAN_BIND : Binds the specified channel data structure to the specified + mport device. +- RIO_CM_CHAN_LISTEN : Enables listening for connection requests on the specified + channel. +- RIO_CM_CHAN_ACCEPT : Accepts a connection request from peer on the specified + channel. If wait timeout for this request is specified by a caller it is + a blocking call. If timeout set to 0 this is non-blocking call - ioctl + handler checks for a pending connection request and if one is not available + exits with -EGAIN error status immediately. +- RIO_CM_CHAN_CONNECT : Sends a connection request to a remote peer/channel. +- RIO_CM_CHAN_SEND : Sends a data message through the specified channel. + The handler for this request assumes that message buffer specified by + a caller includes the reserved space for a packet header required by + this driver. +- RIO_CM_CHAN_RECEIVE : Receives a data message through a connected channel. + If the channel does not have an incoming message ready to return this ioctl + handler will wait for new message until timeout specified by a caller + expires. If timeout value is set to 0, ioctl handler uses a default value + defined by MAX_SCHEDULE_TIMEOUT. +- RIO_CM_CHAN_CLOSE : Closes a specified channel and frees associated buffers. + If the specified channel is in the CONNECTED state, sends close notification + to the remote peer. + +The ioctl command codes and corresponding data structures intended for use by +user-space applications are defined in 'include/uapi/linux/rio_cm_cdev.h'. + +II. Hardware Compatibility + +This device driver uses standard interfaces defined by kernel RapidIO subsystem +and therefore it can be used with any mport device driver registered by RapidIO +subsystem with limitations set by available mport HW implementation of messaging +mailboxes. + +III. Module parameters + +- 'dbg_level' - This parameter allows to control amount of debug information + generated by this device driver. This parameter is formed by set of + bit masks that correspond to the specific functional block. + For mask definitions see 'drivers/rapidio/devices/rio_cm.c' + This parameter can be changed dynamically. + Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. + +- 'cmbox' - Number of RapidIO mailbox to use (default value is 1). + This parameter allows to set messaging mailbox number that will be used + within entire RapidIO network. It can be used when default mailbox is + used by other device drivers or is not supported by some nodes in the + RapidIO network. + +- 'chstart' - Start channel number for dynamic assignment. Default value - 256. + Allows to exclude channel numbers below this parameter from dynamic + allocation to avoid conflicts with software components that use + reserved predefined channel numbers. + +IV. Known problems + + None. + +V. User-space Applications and API Library + +Messaging API library and applications that use this device driver are available +from RapidIO.org. + +VI. TODO List + +- Add support for system notification messages (reserved channel 0). diff --git a/Documentation/rapidio/tsi721.txt b/Documentation/rapidio/tsi721.txt index 7c1c7bf48ec0..cd2a2935d51d 100644 --- a/Documentation/rapidio/tsi721.txt +++ b/Documentation/rapidio/tsi721.txt @@ -25,6 +25,32 @@ fully compatible with RIONET driver (Ethernet over RapidIO messaging services). This parameter can be changed dynamically. Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. +- 'dma_desc_per_channel' - This parameter defines number of hardware buffer + descriptors allocated for each registered Tsi721 DMA channel. + Its default value is 128. + +- 'dma_txqueue_sz' - DMA transactions queue size. Defines number of pending + transaction requests that can be accepted by each DMA channel. + Default value is 16. + +- 'dma_sel' - DMA channel selection mask. Bitmask that defines which hardware + DMA channels (0 ... 6) will be registered with DmaEngine core. + If bit is set to 1, the corresponding DMA channel will be registered. + DMA channels not selected by this mask will not be used by this device + driver. Default value is 0x7f (use all channels). + +- 'pcie_mrrs' - override value for PCIe Maximum Read Request Size (MRRS). + This parameter gives an ability to override MRRS value set during PCIe + configuration process. Tsi721 supports read request sizes up to 4096B. + Value for this parameter must be set as defined by PCIe specification: + 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. + Default value is '-1' (= keep platform setting). + +- 'mbox_sel' - RIO messaging MBOX selection mask. This is a bitmask that defines + messaging MBOXes are managed by this device driver. Mask bits 0 - 3 + correspond to MBOX0 - MBOX3. MBOX is under driver's control if the + corresponding bit is set to '1'. Default value is 0x0f (= all). + II. Known problems None. diff --git a/Documentation/sound/alsa/soc/machine.txt b/Documentation/sound/alsa/soc/machine.txt index 74056dba52be..6bf2d2063b52 100644 --- a/Documentation/sound/alsa/soc/machine.txt +++ b/Documentation/sound/alsa/soc/machine.txt @@ -3,7 +3,7 @@ ASoC Machine Driver The ASoC machine (or board) driver is the code that glues together all the component drivers (e.g. codecs, platforms and DAIs). It also describes the -relationships between each componnent which include audio paths, GPIOs, +relationships between each component which include audio paths, GPIOs, interrupts, clocking, jacks and voltage regulators. The machine driver can contain codec and platform specific code. It registers diff --git a/Documentation/sound/alsa/timestamping.txt b/Documentation/sound/alsa/timestamping.txt index 1b6473f393a8..9d579aefbffd 100644 --- a/Documentation/sound/alsa/timestamping.txt +++ b/Documentation/sound/alsa/timestamping.txt @@ -14,7 +14,7 @@ provides a refined estimate with a delay. event or application query. The difference (tstamp - trigger_tstamp) defines the elapsed time. -The ALSA API provides reports two basic pieces of information, avail +The ALSA API provides two basic pieces of information, avail and delay, which combined with the trigger and current system timestamps allow for applications to keep track of the 'fullness' of the ring buffer and the amount of queued samples. @@ -53,21 +53,21 @@ case): The analog time is taken at the last stage of the playback, as close as possible to the actual transducer -The link time is taken at the output of the SOC/chipset as the samples +The link time is taken at the output of the SoC/chipset as the samples are pushed on a link. The link time can be directly measured if supported in hardware by sample counters or wallclocks (e.g. with HDAudio 24MHz or PTP clock for networked solutions) or indirectly estimated (e.g. with the frame counter in USB). The DMA time is measured using counters - typically the least reliable -of all measurements due to the bursty natured of DMA transfers. +of all measurements due to the bursty nature of DMA transfers. The app time corresponds to the time tracked by an application after writing in the ring buffer. -The application can query what the hardware supports, define which +The application can query the hardware capabilities, define which audio time it wants reported by selecting the relevant settings in -audio_tstamp_config fields, get an estimate of the timestamp +audio_tstamp_config fields, thus get an estimate of the timestamp accuracy. It can also request the delay-to-analog be included in the measurement. Direct access to the link time is very interesting on platforms that provide an embedded DSP; measuring directly the link @@ -169,7 +169,7 @@ playback: systime: 938107562 nsec, audio time 938112708 nsec, systime delta -51 Example 1 shows that the timestamp at the DMA level is close to 1ms ahead of the actual playback time (as a side time this sort of measurement can help define rewind safeguards). Compensating for the -DMA-link delay in example 2 helps remove the hardware buffering abut +DMA-link delay in example 2 helps remove the hardware buffering but the information is still very jittery, with up to one sample of error. In example 3 where the timestamps are measured with the link wallclock, the timestamps show a monotonic behavior and a lower diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt index 33204604de6c..ffab8b5caa60 100644 --- a/Documentation/sysctl/kernel.txt +++ b/Documentation/sysctl/kernel.txt @@ -764,6 +764,20 @@ send before ratelimiting kicks in. ============================================================== +printk_devkmsg: + +Control the logging to /dev/kmsg from userspace: + +ratelimit: default, ratelimited +on: unlimited logging to /dev/kmsg from userspace +off: logging to /dev/kmsg disabled + +The kernel command line parameter printk.devkmsg= overrides this and is +a one-time setting until next reboot: once set, it cannot be changed by +this sysctl interface anymore. + +============================================================== + randomize_va_space: This option can be used to select the type of process address diff --git a/Documentation/tpm/tpm_vtpm_proxy.txt b/Documentation/tpm/tpm_vtpm_proxy.txt new file mode 100644 index 000000000000..30d19022f869 --- /dev/null +++ b/Documentation/tpm/tpm_vtpm_proxy.txt @@ -0,0 +1,71 @@ +Virtual TPM Proxy Driver for Linux Containers + +Authors: Stefan Berger (IBM) + +This document describes the virtual Trusted Platform Module (vTPM) +proxy device driver for Linux containers. + +INTRODUCTION +------------ + +The goal of this work is to provide TPM functionality to each Linux +container. This allows programs to interact with a TPM in a container +the same way they interact with a TPM on the physical system. Each +container gets its own unique, emulated, software TPM. + + +DESIGN +------ + +To make an emulated software TPM available to each container, the container +management stack needs to create a device pair consisting of a client TPM +character device /dev/tpmX (with X=0,1,2...) and a 'server side' file +descriptor. The former is moved into the container by creating a character +device with the appropriate major and minor numbers while the file descriptor +is passed to the TPM emulator. Software inside the container can then send +TPM commands using the character device and the emulator will receive the +commands via the file descriptor and use it for sending back responses. + +To support this, the virtual TPM proxy driver provides a device /dev/vtpmx +that is used to create device pairs using an ioctl. The ioctl takes as +an input flags for configuring the device. The flags for example indicate +whether TPM 1.2 or TPM 2 functionality is supported by the TPM emulator. +The result of the ioctl are the file descriptor for the 'server side' +as well as the major and minor numbers of the character device that was created. +Besides that the number of the TPM character device is return. If for +example /dev/tpm10 was created, the number (dev_num) 10 is returned. + +The following is the data structure of the TPM_PROXY_IOC_NEW_DEV ioctl: + +struct vtpm_proxy_new_dev { + __u32 flags; /* input */ + __u32 tpm_num; /* output */ + __u32 fd; /* output */ + __u32 major; /* output */ + __u32 minor; /* output */ +}; + +Note that if unsupported flags are passed to the device driver, the ioctl will +fail and errno will be set to EOPNOTSUPP. Similarly, if an unsupported ioctl is +called on the device driver, the ioctl will fail and errno will be set to +ENOTTY. + +See /usr/include/linux/vtpm_proxy.h for definitions related to the public interface +of this vTPM device driver. + +Once the device has been created, the driver will immediately try to talk +to the TPM. All commands from the driver can be read from the file descriptor +returned by the ioctl. The commands should be responded to immediately. + +Depending on the version of TPM the following commands will be sent by the +driver: + +- TPM 1.2: + - the driver will send a TPM_Startup command to the TPM emulator + - the driver will send commands to read the command durations and + interface timeouts from the TPM emulator +- TPM 2: + - the driver will send a TPM2_Startup command to the TPM emulator + +The TPM device /dev/tpmX will only appear if all of the relevant commands +were responded to properly. diff --git a/Documentation/trace/kprobetrace.txt b/Documentation/trace/kprobetrace.txt index d68ea5fc812b..ea52ec1f8484 100644 --- a/Documentation/trace/kprobetrace.txt +++ b/Documentation/trace/kprobetrace.txt @@ -40,6 +40,7 @@ Synopsis of kprobe_events $stackN : Fetch Nth entry of stack (N >= 0) $stack : Fetch stack address. $retval : Fetch return value.(*) + $comm : Fetch current task comm. +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**) NAME=FETCHARG : Set NAME as the argument name of FETCHARG. FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types @@ -62,6 +63,8 @@ offset, and container-size (usually 32). The syntax is; b<bit-width>@<bit-offset>/<container-size> +For $comm, the default type is "string"; any other type is invalid. + Per-Probe Event Filtering ------------------------- diff --git a/Documentation/trace/uprobetracer.txt b/Documentation/trace/uprobetracer.txt index f1cf9a34ad9d..72d1cd4f7bf3 100644 --- a/Documentation/trace/uprobetracer.txt +++ b/Documentation/trace/uprobetracer.txt @@ -36,6 +36,7 @@ Synopsis of uprobe_tracer $stackN : Fetch Nth entry of stack (N >= 0) $stack : Fetch stack address. $retval : Fetch return value.(*) + $comm : Fetch current task comm. +|-offs(FETCHARG) : Fetch memory at FETCHARG +|- offs address.(**) NAME=FETCHARG : Set NAME as the argument name of FETCHARG. FETCHARG:TYPE : Set TYPE as the type of FETCHARG. Currently, basic types @@ -57,6 +58,8 @@ offset, and container-size (usually 32). The syntax is; b<bit-width>@<bit-offset>/<container-size> +For $comm, the default type is "string"; any other type is invalid. + Event Profiling --------------- diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index a4482cce4bae..739db9ab16b2 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -1433,13 +1433,16 @@ KVM_ASSIGN_DEV_IRQ. Partial deassignment of host or guest IRQ is allowed. 4.52 KVM_SET_GSI_ROUTING Capability: KVM_CAP_IRQ_ROUTING -Architectures: x86 s390 +Architectures: x86 s390 arm arm64 Type: vm ioctl Parameters: struct kvm_irq_routing (in) Returns: 0 on success, -1 on error Sets the GSI routing table entries, overwriting any previously set entries. +On arm/arm64, GSI routing has the following limitation: +- GSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD. + struct kvm_irq_routing { __u32 nr; __u32 flags; @@ -1468,7 +1471,13 @@ struct kvm_irq_routing_entry { #define KVM_IRQ_ROUTING_S390_ADAPTER 3 #define KVM_IRQ_ROUTING_HV_SINT 4 -No flags are specified so far, the corresponding field must be set to zero. +flags: +- KVM_MSI_VALID_DEVID: used along with KVM_IRQ_ROUTING_MSI routing entry + type, specifies that the devid field contains a valid value. The per-VM + KVM_CAP_MSI_DEVID capability advertises the requirement to provide + the device ID. If this capability is not available, userspace should + never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail. +- zero otherwise struct kvm_irq_routing_irqchip { __u32 irqchip; @@ -1479,9 +1488,21 @@ struct kvm_irq_routing_msi { __u32 address_lo; __u32 address_hi; __u32 data; - __u32 pad; + union { + __u32 pad; + __u32 devid; + }; }; +If KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier +for the device that wrote the MSI message. For PCI, this is usually a +BFD identifier in the lower 16 bits. + +On x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS +feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, +address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of +address_hi must be zero. + struct kvm_irq_routing_s390_adapter { __u64 ind_addr; __u64 summary_addr; @@ -1583,6 +1604,17 @@ struct kvm_lapic_state { Reads the Local APIC registers and copies them into the input argument. The data format and layout are the same as documented in the architecture manual. +If KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API is +enabled, then the format of APIC_ID register depends on the APIC mode +(reported by MSR_IA32_APICBASE) of its VCPU. x2APIC stores APIC ID in +the APIC_ID register (bytes 32-35). xAPIC only allows an 8-bit APIC ID +which is stored in bits 31-24 of the APIC register, or equivalently in +byte 35 of struct kvm_lapic_state's regs field. KVM_GET_LAPIC must then +be called after MSR_IA32_APICBASE has been set with KVM_SET_MSR. + +If KVM_X2APIC_API_USE_32BIT_IDS feature is disabled, struct kvm_lapic_state +always uses xAPIC format. + 4.58 KVM_SET_LAPIC @@ -1600,6 +1632,10 @@ struct kvm_lapic_state { Copies the input argument into the Local APIC registers. The data format and layout are the same as documented in the architecture manual. +The format of the APIC ID register (bytes 32-35 of struct kvm_lapic_state's +regs field) depends on the state of the KVM_CAP_X2APIC_API capability. +See the note in KVM_GET_LAPIC. + 4.59 KVM_IOEVENTFD @@ -2032,6 +2068,12 @@ registers, find a list below: MIPS | KVM_REG_MIPS_CP0_CONFIG5 | 32 MIPS | KVM_REG_MIPS_CP0_CONFIG7 | 32 MIPS | KVM_REG_MIPS_CP0_ERROREPC | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH1 | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH2 | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH3 | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH4 | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH5 | 64 + MIPS | KVM_REG_MIPS_CP0_KSCRATCH6 | 64 MIPS | KVM_REG_MIPS_COUNT_CTL | 64 MIPS | KVM_REG_MIPS_COUNT_RESUME | 64 MIPS | KVM_REG_MIPS_COUNT_HZ | 64 @@ -2156,7 +2198,7 @@ after pausing the vcpu, but before it is resumed. 4.71 KVM_SIGNAL_MSI Capability: KVM_CAP_SIGNAL_MSI -Architectures: x86 +Architectures: x86 arm64 Type: vm ioctl Parameters: struct kvm_msi (in) Returns: >0 on delivery, 0 if guest blocked the MSI, and -1 on error @@ -2169,10 +2211,23 @@ struct kvm_msi { __u32 address_hi; __u32 data; __u32 flags; - __u8 pad[16]; + __u32 devid; + __u8 pad[12]; }; -No flags are defined so far. The corresponding field must be 0. +flags: KVM_MSI_VALID_DEVID: devid contains a valid value. The per-VM + KVM_CAP_MSI_DEVID capability advertises the requirement to provide + the device ID. If this capability is not available, userspace + should never set the KVM_MSI_VALID_DEVID flag as the ioctl might fail. + +If KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier +for the device that wrote the MSI message. For PCI, this is usually a +BFD identifier in the lower 16 bits. + +On x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS +feature of KVM_CAP_X2APIC_API capability is enabled. If it is enabled, +address_hi bits 31-8 provide bits 31-8 of the destination id. Bits 7-0 of +address_hi must be zero. 4.71 KVM_CREATE_PIT2 @@ -2345,9 +2400,13 @@ Note that closing the resamplefd is not sufficient to disable the irqfd. The KVM_IRQFD_FLAG_RESAMPLE is only necessary on assignment and need not be specified with KVM_IRQFD_FLAG_DEASSIGN. -On ARM/ARM64, the gsi field in the kvm_irqfd struct specifies the Shared -Peripheral Interrupt (SPI) index, such that the GIC interrupt ID is -given by gsi + 32. +On arm/arm64, gsi routing being supported, the following can happen: +- in case no routing entry is associated to this gsi, injection fails +- in case the gsi is associated to an irqchip routing entry, + irqchip.pin + 32 corresponds to the injected SPI ID. +- in case the gsi is associated to an MSI routing entry, the MSI + message and device ID are translated into an LPI (support restricted + to GICv3 ITS in-kernel emulation). 4.76 KVM_PPC_ALLOCATE_HTAB @@ -2520,6 +2579,7 @@ Parameters: struct kvm_device_attr Returns: 0 on success, -1 on error Errors: ENXIO: The group or attribute is unknown/unsupported for this device + or hardware support is missing. EPERM: The attribute cannot (currently) be accessed this way (e.g. read-only attribute, or attribute that only makes sense when the device is in a different state) @@ -2547,6 +2607,7 @@ Parameters: struct kvm_device_attr Returns: 0 on success, -1 on error Errors: ENXIO: The group or attribute is unknown/unsupported for this device + or hardware support is missing. Tests whether a device supports a particular attribute. A successful return indicates the attribute is implemented. It does not necessarily @@ -3803,6 +3864,42 @@ Allows use of runtime-instrumentation introduced with zEC12 processor. Will return -EINVAL if the machine does not support runtime-instrumentation. Will return -EBUSY if a VCPU has already been created. +7.7 KVM_CAP_X2APIC_API + +Architectures: x86 +Parameters: args[0] - features that should be enabled +Returns: 0 on success, -EINVAL when args[0] contains invalid features + +Valid feature flags in args[0] are + +#define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) +#define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) + +Enabling KVM_X2APIC_API_USE_32BIT_IDS changes the behavior of +KVM_SET_GSI_ROUTING, KVM_SIGNAL_MSI, KVM_SET_LAPIC, and KVM_GET_LAPIC, +allowing the use of 32-bit APIC IDs. See KVM_CAP_X2APIC_API in their +respective sections. + +KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK must be enabled for x2APIC to work +in logical mode or with more than 255 VCPUs. Otherwise, KVM treats 0xff +as a broadcast even in x2APIC mode in order to support physical x2APIC +without interrupt remapping. This is undesirable in logical mode, +where 0xff represents CPUs 0-7 in cluster 0. + +7.8 KVM_CAP_S390_USER_INSTR0 + +Architectures: s390 +Parameters: none + +With this capability enabled, all illegal instructions 0x0000 (2 bytes) will +be intercepted and forwarded to user space. User space can use this +mechanism e.g. to realize 2-byte software breakpoints. The kernel will +not inject an operating exception for these instructions, user space has +to take care of that. + +This capability can be enabled dynamically even if VCPUs were already +created and are running. + 8. Other capabilities. ---------------------- diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt index 59541d49e15c..89182f80cc7f 100644 --- a/Documentation/virtual/kvm/devices/arm-vgic.txt +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt @@ -4,16 +4,22 @@ ARM Virtual Generic Interrupt Controller (VGIC) Device types supported: KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0 + KVM_DEV_TYPE_ARM_VGIC_ITS ARM Interrupt Translation Service Controller -Only one VGIC instance may be instantiated through either this API or the -legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt -controller, requiring emulated user-space devices to inject interrupts to the -VGIC instead of directly to CPUs. +Only one VGIC instance of the V2/V3 types above may be instantiated through +either this API or the legacy KVM_CREATE_IRQCHIP api. The created VGIC will +act as the VM interrupt controller, requiring emulated user-space devices to +inject interrupts to the VGIC instead of directly to CPUs. Creating a guest GICv3 device requires a host GICv3 as well. GICv3 implementations with hardware compatibility support allow a guest GICv2 as well. +Creating a virtual ITS controller requires a host GICv3 (but does not depend +on having physical ITS controllers). +There can be multiple ITS controllers per guest, each of them has to have +a separate, non-overlapping MMIO region. + Groups: KVM_DEV_ARM_VGIC_GRP_ADDR Attributes: @@ -39,6 +45,13 @@ Groups: Only valid for KVM_DEV_TYPE_ARM_VGIC_V3. This address needs to be 64K aligned. + KVM_VGIC_V3_ADDR_TYPE_ITS (rw, 64-bit) + Base address in the guest physical address space of the GICv3 ITS + control register frame. The ITS allows MSI(-X) interrupts to be + injected into guests. This extension is optional. If the kernel + does not support the ITS, the call returns -ENODEV. + Only valid for KVM_DEV_TYPE_ARM_VGIC_ITS. + This address needs to be 64K aligned and the region covers 128K. KVM_DEV_ARM_VGIC_GRP_DIST_REGS Attributes: @@ -109,8 +122,8 @@ Groups: KVM_DEV_ARM_VGIC_GRP_CTRL Attributes: KVM_DEV_ARM_VGIC_CTRL_INIT - request the initialization of the VGIC, no additional parameter in - kvm_device_attr.addr. + request the initialization of the VGIC or ITS, no additional parameter + in kvm_device_attr.addr. Errors: -ENXIO: VGIC not properly configured as required prior to calling this attribute diff --git a/Documentation/virtual/kvm/devices/vm.txt b/Documentation/virtual/kvm/devices/vm.txt index a9ea8774a45f..b6cda49f2ba4 100644 --- a/Documentation/virtual/kvm/devices/vm.txt +++ b/Documentation/virtual/kvm/devices/vm.txt @@ -20,7 +20,8 @@ Enables Collaborative Memory Management Assist (CMMA) for the virtual machine. 1.2. ATTRIBUTE: KVM_S390_VM_MEM_CLR_CMMA Parameters: none -Returns: 0 +Returns: -EINVAL if CMMA was not enabled + 0 otherwise Clear the CMMA status for all guest pages, so any pages the guest marked as unused are again used any may not be reclaimed by the host. @@ -85,6 +86,90 @@ Returns: -EBUSY in case 1 or more vcpus are already activated (only in write -ENOMEM if not enough memory is available to process the ioctl 0 in case of success +2.3. ATTRIBUTE: KVM_S390_VM_CPU_MACHINE_FEAT (r/o) + +Allows user space to retrieve available cpu features. A feature is available if +provided by the hardware and supported by kvm. In theory, cpu features could +even be completely emulated by kvm. + +struct kvm_s390_vm_cpu_feat { + __u64 feat[16]; # Bitmap (1 = feature available), MSB 0 bit numbering +}; + +Parameters: address of a buffer to load the feature list from. +Returns: -EFAULT if the given address is not accessible from kernel space. + 0 in case of success. + +2.4. ATTRIBUTE: KVM_S390_VM_CPU_PROCESSOR_FEAT (r/w) + +Allows user space to retrieve or change enabled cpu features for all VCPUs of a +VM. Features that are not available cannot be enabled. + +See 2.3. for a description of the parameter struct. + +Parameters: address of a buffer to store/load the feature list from. +Returns: -EFAULT if the given address is not accessible from kernel space. + -EINVAL if a cpu feature that is not available is to be enabled. + -EBUSY if at least one VCPU has already been defined. + 0 in case of success. + +2.5. ATTRIBUTE: KVM_S390_VM_CPU_MACHINE_SUBFUNC (r/o) + +Allows user space to retrieve available cpu subfunctions without any filtering +done by a set IBC. These subfunctions are indicated to the guest VCPU via +query or "test bit" subfunctions and used e.g. by cpacf functions, plo and ptff. + +A subfunction block is only valid if KVM_S390_VM_CPU_MACHINE contains the +STFL(E) bit introducing the affected instruction. If the affected instruction +indicates subfunctions via a "query subfunction", the response block is +contained in the returned struct. If the affected instruction +indicates subfunctions via a "test bit" mechanism, the subfunction codes are +contained in the returned struct in MSB 0 bit numbering. + +struct kvm_s390_vm_cpu_subfunc { + u8 plo[32]; # always valid (ESA/390 feature) + u8 ptff[16]; # valid with TOD-clock steering + u8 kmac[16]; # valid with Message-Security-Assist + u8 kmc[16]; # valid with Message-Security-Assist + u8 km[16]; # valid with Message-Security-Assist + u8 kimd[16]; # valid with Message-Security-Assist + u8 klmd[16]; # valid with Message-Security-Assist + u8 pckmo[16]; # valid with Message-Security-Assist-Extension 3 + u8 kmctr[16]; # valid with Message-Security-Assist-Extension 4 + u8 kmf[16]; # valid with Message-Security-Assist-Extension 4 + u8 kmo[16]; # valid with Message-Security-Assist-Extension 4 + u8 pcc[16]; # valid with Message-Security-Assist-Extension 4 + u8 ppno[16]; # valid with Message-Security-Assist-Extension 5 + u8 reserved[1824]; # reserved for future instructions +}; + +Parameters: address of a buffer to load the subfunction blocks from. +Returns: -EFAULT if the given address is not accessible from kernel space. + 0 in case of success. + +2.6. ATTRIBUTE: KVM_S390_VM_CPU_PROCESSOR_SUBFUNC (r/w) + +Allows user space to retrieve or change cpu subfunctions to be indicated for +all VCPUs of a VM. This attribute will only be available if kernel and +hardware support are in place. + +The kernel uses the configured subfunction blocks for indication to +the guest. A subfunction block will only be used if the associated STFL(E) bit +has not been disabled by user space (so the instruction to be queried is +actually available for the guest). + +As long as no data has been written, a read will fail. The IBC will be used +to determine available subfunctions in this case, this will guarantee backward +compatibility. + +See 2.5. for a description of the parameter struct. + +Parameters: address of a buffer to store/load the subfunction blocks from. +Returns: -EFAULT if the given address is not accessible from kernel space. + -EINVAL when reading, if there was no write yet. + -EBUSY if at least one VCPU has already been defined. + 0 in case of success. + 3. GROUP: KVM_S390_VM_TOD Architectures: s390 diff --git a/Documentation/virtual/kvm/locking.txt b/Documentation/virtual/kvm/locking.txt index 19f94a6b9bb0..f2491a8c68b4 100644 --- a/Documentation/virtual/kvm/locking.txt +++ b/Documentation/virtual/kvm/locking.txt @@ -89,7 +89,7 @@ In mmu_spte_clear_track_bits(): old_spte = *spte; /* 'if' condition is satisfied. */ - if (old_spte.Accssed == 1 && + if (old_spte.Accessed == 1 && old_spte.W == 0) spte = 0ull; on fast page fault path: @@ -102,7 +102,7 @@ In mmu_spte_clear_track_bits(): old_spte = xchg(spte, 0ull) - if (old_spte.Accssed == 1) + if (old_spte.Accessed == 1) kvm_set_pfn_accessed(spte.pfn); if (old_spte.Dirty == 1) kvm_set_pfn_dirty(spte.pfn); diff --git a/Documentation/watchdog/hpwdt.txt b/Documentation/watchdog/hpwdt.txt index a40398cce9d1..7a9f635d0258 100644 --- a/Documentation/watchdog/hpwdt.txt +++ b/Documentation/watchdog/hpwdt.txt @@ -1,9 +1,9 @@ -Last reviewed: 04/04/2016 +Last reviewed: 05/20/2016 HPE iLO NMI Watchdog Driver NMI sourcing for iLO based ProLiant Servers Documentation and Driver by - Thomas Mingarelli <thomas.mingarelli@hpe.com> + Thomas Mingarelli The HPE iLO NMI Watchdog driver is a kernel module that provides basic watchdog functionality and the added benefit of NMI sourcing. Both the @@ -95,4 +95,3 @@ Last reviewed: 04/04/2016 -- Tom Mingarelli - (thomas.mingarelli@hpe.com) diff --git a/Documentation/watchdog/src/watchdog-test.c b/Documentation/watchdog/src/watchdog-test.c index fcdde8fc98be..6983d05097e2 100644 --- a/Documentation/watchdog/src/watchdog-test.c +++ b/Documentation/watchdog/src/watchdog-test.c @@ -2,6 +2,7 @@ * Watchdog Driver Test Program */ +#include <errno.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -13,6 +14,7 @@ #include <linux/watchdog.h> int fd; +const char v = 'V'; /* * This function simply sends an IOCTL to the driver, which in turn ticks @@ -23,6 +25,7 @@ static void keep_alive(void) { int dummy; + printf("."); ioctl(fd, WDIOC_KEEPALIVE, &dummy); } @@ -33,8 +36,13 @@ static void keep_alive(void) static void term(int sig) { + int ret = write(fd, &v, 1); + close(fd); - fprintf(stderr, "Stopping watchdog ticks...\n"); + if (ret < 0) + printf("\nStopping watchdog ticks failed (%d)...\n", errno); + else + printf("\nStopping watchdog ticks...\n"); exit(0); } @@ -42,12 +50,14 @@ int main(int argc, char *argv[]) { int flags; unsigned int ping_rate = 1; + int ret; + + setbuf(stdout, NULL); fd = open("/dev/watchdog", O_WRONLY); if (fd == -1) { - fprintf(stderr, "Watchdog device not enabled.\n"); - fflush(stderr); + printf("Watchdog device not enabled.\n"); exit(-1); } @@ -55,36 +65,30 @@ int main(int argc, char *argv[]) if (!strncasecmp(argv[1], "-d", 2)) { flags = WDIOS_DISABLECARD; ioctl(fd, WDIOC_SETOPTIONS, &flags); - fprintf(stderr, "Watchdog card disabled.\n"); - fflush(stderr); + printf("Watchdog card disabled.\n"); goto end; } else if (!strncasecmp(argv[1], "-e", 2)) { flags = WDIOS_ENABLECARD; ioctl(fd, WDIOC_SETOPTIONS, &flags); - fprintf(stderr, "Watchdog card enabled.\n"); - fflush(stderr); + printf("Watchdog card enabled.\n"); goto end; } else if (!strncasecmp(argv[1], "-t", 2) && argv[2]) { flags = atoi(argv[2]); ioctl(fd, WDIOC_SETTIMEOUT, &flags); - fprintf(stderr, "Watchdog timeout set to %u seconds.\n", flags); - fflush(stderr); + printf("Watchdog timeout set to %u seconds.\n", flags); goto end; } else if (!strncasecmp(argv[1], "-p", 2) && argv[2]) { ping_rate = strtoul(argv[2], NULL, 0); - fprintf(stderr, "Watchdog ping rate set to %u seconds.\n", ping_rate); - fflush(stderr); + printf("Watchdog ping rate set to %u seconds.\n", ping_rate); } else { - fprintf(stderr, "-d to disable, -e to enable, -t <n> to set " \ + printf("-d to disable, -e to enable, -t <n> to set " \ "the timeout,\n-p <n> to set the ping rate, and \n"); - fprintf(stderr, "run by itself to tick the card.\n"); - fflush(stderr); + printf("run by itself to tick the card.\n"); goto end; } } - fprintf(stderr, "Watchdog Ticking Away!\n"); - fflush(stderr); + printf("Watchdog Ticking Away!\n"); signal(SIGINT, term); @@ -93,6 +97,9 @@ int main(int argc, char *argv[]) sleep(ping_rate); } end: + ret = write(fd, &v, 1); + if (ret < 0) + printf("Stopping watchdog ticks failed (%d)...\n", errno); close(fd); return 0; } diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt index 917eeeabfa5e..7f31125c123e 100644 --- a/Documentation/watchdog/watchdog-kernel-api.txt +++ b/Documentation/watchdog/watchdog-kernel-api.txt @@ -82,8 +82,9 @@ It contains following fields: * max_timeout: the watchdog timer's maximum timeout value (in seconds), as seen from userspace. If set, the maximum configurable value for 'timeout'. Not used if max_hw_heartbeat_ms is non-zero. -* min_hw_heartbeat_ms: Minimum time between heartbeats sent to the chip, - in milli-seconds. +* min_hw_heartbeat_ms: Hardware limit for minimum time between heartbeats, + in milli-seconds. This value is normally 0; it should only be provided + if the hardware can not tolerate lower intervals between heartbeats. * max_hw_heartbeat_ms: Maximum hardware heartbeat, in milli-seconds. If set, the infrastructure will send heartbeats to the watchdog driver if 'timeout' is larger than max_hw_heartbeat_ms, unless WDOG_ACTIVE @@ -166,6 +167,10 @@ they are supported. These optional routines/operations are: info structure). * status: this routine checks the status of the watchdog timer device. The status of the device is reported with watchdog WDIOF_* status flags/bits. + WDIOF_MAGICCLOSE and WDIOF_KEEPALIVEPING are reported by the watchdog core; + it is not necessary to report those bits from the driver. Also, if no status + function is provided by the driver, the watchdog core reports the status bits + provided in the bootstatus variable of struct watchdog_device. * set_timeout: this routine checks and changes the timeout of the watchdog timer device. It returns 0 on success, -EINVAL for "parameter out of range" and -EIO for "could not write value to the watchdog". On success this diff --git a/Documentation/x86/early-microcode.txt b/Documentation/x86/early-microcode.txt index c956d99cf1de..07749e7f3d50 100644 --- a/Documentation/x86/early-microcode.txt +++ b/Documentation/x86/early-microcode.txt @@ -45,7 +45,10 @@ Builtin microcode ================= We can also load builtin microcode supplied through the regular firmware -builtin method CONFIG_FIRMWARE_IN_KERNEL. Here's an example: +builtin method CONFIG_FIRMWARE_IN_KERNEL. Only 64-bit is currently +supported. + +Here's an example: CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin" |