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-rw-r--r--drivers/clk/at91/clk-generated.c6
-rw-r--r--drivers/clk/at91/sama7g5.c14
2 files changed, 13 insertions, 7 deletions
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index b4fc8d71daf2..b656d25a9767 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -128,6 +128,12 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
int i;
u32 div;
+ /* do not look for a rate that is outside of our range */
+ if (gck->range.max && req->rate > gck->range.max)
+ req->rate = gck->range.max;
+ if (gck->range.min && req->rate < gck->range.min)
+ req->rate = gck->range.min;
+
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
if (gck->chg_pid == i)
continue;
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 9e1ec48c4474..cf8c079aa086 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock);
static DEFINE_SPINLOCK(pmc_mck0_lock);
static DEFINE_SPINLOCK(pmc_mckX_lock);
-/**
+/*
* PLL clocks identifiers
* @PLL_ID_CPU: CPU PLL identifier
* @PLL_ID_SYS: System PLL identifier
@@ -56,7 +56,7 @@ enum pll_ids {
PLL_ID_MAX,
};
-/**
+/*
* PLL type identifiers
* @PLL_TYPE_FRAC: fractional PLL identifier
* @PLL_TYPE_DIV: divider PLL identifier
@@ -118,7 +118,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
.output = pll_outputs,
};
-/**
+/*
* PLL clocks description
* @n: clock name
* @p: clock parent
@@ -285,7 +285,7 @@ static const struct {
},
};
-/**
+/*
* Master clock (MCK[1..4]) description
* @n: clock name
* @ep: extra parents names array
@@ -337,7 +337,7 @@ static const struct {
.c = 1, },
};
-/**
+/*
* System clock description
* @n: clock name
* @p: clock parent name
@@ -361,7 +361,7 @@ static const struct {
/* Mux table for programmable clocks. */
static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
-/**
+/*
* Peripheral clock description
* @n: clock name
* @p: clock parent name
@@ -449,7 +449,7 @@ static const struct {
{ .n = "uhphs_clk", .p = "mck1", .id = 106, },
};
-/**
+/*
* Generic clock description
* @n: clock name
* @pp: PLL parents