diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 60 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 1 | 
6 files changed, 50 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f095a2513aff..1400abee9f40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5524,7 +5524,8 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,  		~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);  	resource_size_t aper_limit =  		adev->gmc.aper_base + adev->gmc.aper_size - 1; -	bool p2p_access = !(pci_p2pdma_distance_many(adev->pdev, +	bool p2p_access = !adev->gmc.xgmi.connected_to_cpu && +			  !(pci_p2pdma_distance_many(adev->pdev,  					&peer_adev->dev, 1, true) < 0);  	return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c index ecada5eadfe3..e325150879df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c @@ -66,10 +66,15 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev)  		return true;  	case CHIP_SIENNA_CICHLID:  		if (strnstr(atom_ctx->vbios_version, "D603", +		    sizeof(atom_ctx->vbios_version))) { +			if (strnstr(atom_ctx->vbios_version, "D603GLXE",  			    sizeof(atom_ctx->vbios_version))) -			return true; -		else +				return false; +			else +				return true; +		} else {  			return false; +		}  	default:  		return false;  	} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index b1099ee79c50..c2fd6f3076a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -159,7 +159,10 @@ void amdgpu_job_free(struct amdgpu_job *job)  	amdgpu_sync_free(&job->sync);  	amdgpu_sync_free(&job->sched_sync); -	dma_fence_put(&job->hw_fence); +	if (!job->hw_fence.ops) +		kfree(job); +	else +		dma_fence_put(&job->hw_fence);  }  int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 1036446abc30..9f7a5e393f85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2401,7 +2401,7 @@ static int psp_load_smu_fw(struct psp_context *psp)  static bool fw_load_skip_check(struct psp_context *psp,  			       struct amdgpu_firmware_info *ucode)  { -	if (!ucode->fw) +	if (!ucode->fw || !ucode->ucode_size)  		return true;  	if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index a2a4dc1844c0..a3cd5c1e8529 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4274,35 +4274,45 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)  		} -		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; -		info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS; -		info->fw = adev->gfx.rlc_fw; -		adev->firmware.fw_size += -			ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); +		if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) { +			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; +			info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS; +			info->fw = adev->gfx.rlc_fw; +			adev->firmware.fw_size += +				ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); +		} -		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; -		info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS; -		info->fw = adev->gfx.rlc_fw; -		adev->firmware.fw_size += -			ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); +		if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) { +			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS]; +			info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS; +			info->fw = adev->gfx.rlc_fw; +			adev->firmware.fw_size += +				ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); +		} -		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; -		info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS; -		info->fw = adev->gfx.rlc_fw; -		adev->firmware.fw_size += -			ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); +		if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) { +			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS]; +			info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS; +			info->fw = adev->gfx.rlc_fw; +			adev->firmware.fw_size += +				ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); +		} -		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; -		info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS; -		info->fw = adev->gfx.rlc_fw; -		adev->firmware.fw_size += -			ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); +		if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) { +			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS]; +			info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS; +			info->fw = adev->gfx.rlc_fw; +			adev->firmware.fw_size += +				ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); +		} -		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS]; -		info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS; -		info->fw = adev->gfx.rlc_fw; -		adev->firmware.fw_size += -			ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); +		if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) { +			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS]; +			info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS; +			info->fw = adev->gfx.rlc_fw; +			adev->firmware.fw_size += +				ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); +		}  		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];  		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 120ea294abef..cc3fdbbcd314 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -183,6 +183,7 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,  	mes_add_queue_pkt.trap_handler_addr = input->tba_addr;  	mes_add_queue_pkt.tma_addr = input->tma_addr;  	mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; +	mes_add_queue_pkt.trap_en = 1;  	return mes_v11_0_submit_pkt_and_poll_completion(mes,  			&mes_add_queue_pkt, sizeof(mes_add_queue_pkt),  | 
