diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp')
19 files changed, 1120 insertions, 187 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 84ea09d9692f..cdec3fbe6ff4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -58,8 +58,8 @@ int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup) return -EINVAL; - return dpu_kms->hw_intr->ops.irq_idx_lookup(intr_type, - instance_idx); + return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr, + intr_type, instance_idx); } /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index b6b3bbab0333..7cba5bbdf4b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -380,7 +380,6 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, } else { DPU_DEBUG("crtc=%d disable\n", crtc->base.id); memset(old, 0, sizeof(*old)); - memset(new, 0, sizeof(*new)); update_bus = true; update_clk = true; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9607a7644d4b..7c29976be243 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -66,6 +66,83 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) kfree(dpu_crtc); } +static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + + drm_for_each_encoder(encoder, dev) + if (encoder->crtc == crtc) + return encoder; + + return NULL; +} + +static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc) +{ + struct drm_encoder *encoder; + + encoder = get_encoder_from_crtc(crtc); + if (!encoder) { + DRM_ERROR("no encoder found for crtc %d\n", crtc->index); + return false; + } + + return dpu_encoder_get_frame_count(encoder); +} + +static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, + bool in_vblank_irq, + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + unsigned int pipe = crtc->index; + struct drm_encoder *encoder; + int line, vsw, vbp, vactive_start, vactive_end, vfp_end; + + encoder = get_encoder_from_crtc(crtc); + if (!encoder) { + DRM_ERROR("no encoder found for crtc %d\n", pipe); + return false; + } + + vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; + vbp = mode->crtc_vtotal - mode->crtc_vsync_end; + + /* + * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at + * the end of VFP. Translate the porch values relative to the line + * counter positions. + */ + + vactive_start = vsw + vbp + 1; + vactive_end = vactive_start + mode->crtc_vdisplay; + + /* last scan line before VSYNC */ + vfp_end = mode->crtc_vtotal; + + if (stime) + *stime = ktime_get(); + + line = dpu_encoder_get_linecount(encoder); + + if (line < vactive_start) + line -= vactive_start; + else if (line > vactive_end) + line = line - vfp_end - vactive_start; + else + line -= vactive_start; + + *vpos = line; + *hpos = 0; + + if (etime) + *etime = ktime_get(); + + return true; +} + static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, struct dpu_plane_state *pstate, struct dpu_format *format) { @@ -130,7 +207,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, uint32_t stage_idx, lm_idx; int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; bool bg_alpha_enable = false; + DECLARE_BITMAP(fetch_active, SSPP_MAX); + memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { state = plane->state; if (!state) @@ -140,7 +219,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, fb = state->fb; dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); - + set_bit(dpu_plane_pipe(plane), fetch_active); DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", crtc->base.id, pstate->stage, @@ -180,6 +259,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, } } + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, fetch_active); + _dpu_crtc_program_lm_output_roi(crtc); } @@ -839,6 +921,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active); + memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); goto end; } @@ -1247,6 +1330,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = { .early_unregister = dpu_crtc_early_unregister, .enable_vblank = msm_crtc_enable_vblank, .disable_vblank = msm_crtc_disable_vblank, + .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, + .get_vblank_counter = dpu_crtc_get_vblank_counter, }; static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { @@ -1255,6 +1340,7 @@ static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { .atomic_check = dpu_crtc_atomic_check, .atomic_begin = dpu_crtc_atomic_begin, .atomic_flush = dpu_crtc_atomic_flush, + .get_scanout_position = dpu_crtc_get_scanout_position, }; /* initialize crtc */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 288e95ee8e1d..8d942052db8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -426,6 +426,36 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, return 0; } +int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_phys *phys; + int framecount = 0; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + phys = dpu_enc ? dpu_enc->cur_master : NULL; + + if (phys && phys->ops.get_frame_count) + framecount = phys->ops.get_frame_count(phys); + + return framecount; +} + +int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + struct dpu_encoder_phys *phys; + int linecount = 0; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + phys = dpu_enc ? dpu_enc->cur_master : NULL; + + if (phys && phys->ops.get_line_count) + linecount = phys->ops.get_line_count(phys); + + return linecount; +} + void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, struct dpu_encoder_hw_resources *hw_res) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index b4913465e602..99a5d73c9b88 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -156,5 +156,16 @@ void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc); */ void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, u32 idle_timeout); +/** + * dpu_encoder_get_linecount - get interface line count for the encoder. + * @drm_enc: Pointer to previously created drm encoder structure + */ +int dpu_encoder_get_linecount(struct drm_encoder *drm_enc); + +/** + * dpu_encoder_get_frame_count - get interface frame count for the encoder. + * @drm_enc: Pointer to previously created drm encoder structure + */ +int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc); #endif /* __DPU_ENCODER_H__ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index f8f25157f635..ecbc4be98980 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -143,6 +143,7 @@ struct dpu_encoder_phys_ops { void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); void (*restore)(struct dpu_encoder_phys *phys); int (*get_line_count)(struct dpu_encoder_phys *phys); + int (*get_frame_count)(struct dpu_encoder_phys *phys); }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 9a69fad832cd..0e06b7e73c7a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -658,6 +658,31 @@ static int dpu_encoder_phys_vid_get_line_count( return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); } +static int dpu_encoder_phys_vid_get_frame_count( + struct dpu_encoder_phys *phys_enc) +{ + struct intf_status s = {0}; + u32 fetch_start = 0; + struct drm_display_mode mode = phys_enc->cached_mode; + + if (!dpu_encoder_phys_vid_is_master(phys_enc)) + return -EINVAL; + + if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status) + return -EINVAL; + + phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s); + + if (s.is_prog_fetch_en && s.is_en) { + fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay); + if ((s.line_count > fetch_start) && + (s.line_count <= mode.vtotal)) + return s.frame_count + 1; + } + + return s.frame_count; +} + static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; @@ -676,6 +701,7 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; ops->get_line_count = dpu_encoder_phys_vid_get_line_count; + ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; } struct dpu_encoder_phys *dpu_encoder_phys_vid_init( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 189f3533525c..b569030a0847 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -22,7 +22,7 @@ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) #define VIG_SM8250_MASK \ - (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3LITE)) + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ @@ -43,6 +43,9 @@ #define PINGPONG_SDM845_SPLIT_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) +#define CTL_SC7280_MASK \ + (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE)) + #define MERGE_3D_SM8150_MASK (0) #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) @@ -51,6 +54,15 @@ #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) +#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) + +#define INTR_SC7180_MASK \ + (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\ + BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\ + BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\ + BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\ + BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK)) + #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 @@ -199,6 +211,18 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_caps sc7280_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .ubwc_version = DPU_HW_UBWC_VER_30, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2400, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_mdp_cfg sdm845_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -268,6 +292,22 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { }, }; +static const struct dpu_mdp_cfg sc7280_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x2014, + .highest_bank_bit = 0x1, + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x2C4, .bit_off = 8}, + }, +}; + /************************************************************* * CTL sub blocks config *************************************************************/ @@ -350,6 +390,29 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { }, }; +static const struct dpu_ctl_cfg sc7280_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x1E8, + .features = CTL_SC7280_MASK + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x1E8, + .features = CTL_SC7280_MASK + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x1E8, + .features = CTL_SC7280_MASK + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x1E8, + .features = CTL_SC7280_MASK + }, +}; + /************************************************************* * SSPP sub blocks config *************************************************************/ @@ -475,6 +538,17 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_cfg sc7280_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + /************************************************************* * MIXER sub blocks config *************************************************************/ @@ -550,6 +624,15 @@ static const struct dpu_lm_cfg sm8150_lm[] = { &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), }; +static const struct dpu_lm_cfg sc7280_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, + &sc7180_lm_sblk, PINGPONG_0, 0, 0), + LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK, + &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), + LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK, + &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), +}; + /************************************************************* * DSPP sub blocks config *************************************************************/ @@ -602,42 +685,47 @@ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { .len = 0x20, .version = 0x10000}, }; -#define PP_BLK_TE(_name, _id, _base, _merge_3d) \ +static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { + .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, + .len = 0x20, .version = 0x20000}, +}; + +#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_SPLIT_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &sdm845_pp_sblk_te \ + .sblk = &_sblk \ } -#define PP_BLK(_name, _id, _base, _merge_3d) \ +#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &sdm845_pp_sblk \ + .sblk = &_sblk \ } static const struct dpu_pingpong_cfg sdm845_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk), }; static struct dpu_pingpong_cfg sc7180_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), }; static const struct dpu_pingpong_cfg sm8150_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk), }; /************************************************************* @@ -657,6 +745,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; +static const struct dpu_pingpong_cfg sc7280_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk), + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk), +}; /************************************************************* * INTF sub blocks config *************************************************************/ @@ -689,6 +783,12 @@ static const struct dpu_intf_cfg sm8150_intf[] = { INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK), }; +static const struct dpu_intf_cfg sc7280_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK), + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK), +}; + /************************************************************* * VBIF sub blocks config *************************************************************/ @@ -817,6 +917,8 @@ static const struct dpu_perf_cfg sdm845_perf_data = { {.rd_enable = 1, .wr_enable = 1}, {.rd_enable = 1, .wr_enable = 0} }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, }; static const struct dpu_perf_cfg sc7180_perf_data = { @@ -852,6 +954,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = { .min_core_ib = 2400000, .min_llcc_ib = 800000, .min_dram_ib = 800000, + .min_prefill_lines = 24, .danger_lut_tbl = {0xf, 0xffff, 0x0}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sm8150_qos_linear), @@ -869,6 +972,8 @@ static const struct dpu_perf_cfg sm8150_perf_data = { {.rd_enable = 1, .wr_enable = 1}, {.rd_enable = 1, .wr_enable = 0} }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, }; static const struct dpu_perf_cfg sm8250_perf_data = { @@ -877,6 +982,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .min_core_ib = 4800000, .min_llcc_ib = 0, .min_dram_ib = 800000, + .min_prefill_lines = 35, .danger_lut_tbl = {0xf, 0xffff, 0x0}, .qos_lut_tbl = { {.nentry = ARRAY_SIZE(sc7180_qos_linear), @@ -894,6 +1000,35 @@ static const struct dpu_perf_cfg sm8250_perf_data = { {.rd_enable = 1, .wr_enable = 1}, {.rd_enable = 1, .wr_enable = 0} }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_perf_cfg sc7280_perf_data = { + .max_bw_low = 4700000, + .max_bw_high = 8800000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 1600000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xffff, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, }; /************************************************************* @@ -957,6 +1092,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .dma_cfg = sdm845_regdma, .perf = sc7180_perf_data, .mdss_irqs = 0x3f, + .obsolete_irq = INTR_SC7180_MASK, }; } @@ -1026,6 +1162,30 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) }; } +static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) +{ + *dpu_cfg = (struct dpu_mdss_cfg){ + .caps = &sc7280_dpu_caps, + .mdp_count = ARRAY_SIZE(sc7280_mdp), + .mdp = sc7280_mdp, + .ctl_count = ARRAY_SIZE(sc7280_ctl), + .ctl = sc7280_ctl, + .sspp_count = ARRAY_SIZE(sc7280_sspp), + .sspp = sc7280_sspp, + .mixer_count = ARRAY_SIZE(sc7280_lm), + .mixer = sc7280_lm, + .pingpong_count = ARRAY_SIZE(sc7280_pp), + .pingpong = sc7280_pp, + .intf_count = ARRAY_SIZE(sc7280_intf), + .intf = sc7280_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = sc7280_perf_data, + .mdss_irqs = 0x1c07, + .obsolete_irq = INTR_SC7180_MASK, + }; +} + static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, @@ -1033,6 +1193,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init}, { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init}, { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, + { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init}, }; void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ea4647d21a20..4dfd8a20ad5c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -41,7 +41,7 @@ #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ - +#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) @@ -49,7 +49,7 @@ #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) - +#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) #define DPU_HW_BLK_NAME_LEN 16 @@ -185,6 +185,7 @@ enum { enum { DPU_CTL_SPLIT_DISPLAY = 0x1, DPU_CTL_ACTIVE_CFG, + DPU_CTL_FETCH_ACTIVE, DPU_CTL_MAX }; @@ -193,11 +194,14 @@ enum { * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which * pixel data arrives to this INTF * @DPU_INTF_TE INTF block has TE configuration support + * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate + than video timing * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL = 0x1, DPU_INTF_TE, + DPU_DATA_HCTL_EN, DPU_INTF_MAX }; @@ -719,6 +723,7 @@ struct dpu_perf_cfg { * @cursor_formats Supported formats for cursor pipe * @vig_formats Supported formats for vig pipe * @mdss_irqs: Bitmap with the irqs supported by the target + * @obsolete_irq: Irq types that are obsolete for a particular target */ struct dpu_mdss_cfg { u32 hwversion; @@ -765,6 +770,7 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; unsigned long mdss_irqs; + unsigned long obsolete_irq; }; struct dpu_mdss_hw_cfg_handler { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 8981cfa9dbc3..2d4645e01ebf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -27,6 +27,7 @@ #define CTL_MERGE_3D_FLUSH 0x100 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 +#define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MIXER_BORDER_OUT BIT(24) #define CTL_FLUSH_MASK_CTL BIT(17) @@ -34,6 +35,11 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 #define INTF_IDX 31 +#define CTL_INVALID_BIT 0xffff + +static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, + CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, + 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT}; static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl, const struct dpu_mdss_cfg *m, @@ -344,6 +350,8 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0); DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0); } + + DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0); } static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, @@ -496,7 +504,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, DPU_REG_WRITE(c, CTL_TOP, mode_sel); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); - DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + if (cfg->merge_3d) + DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, + BIT(cfg->merge_3d - MERGE_3D_0)); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, @@ -529,6 +539,23 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, DPU_REG_WRITE(c, CTL_TOP, intf_cfg); } +static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, + unsigned long *fetch_active) +{ + int i; + u32 val = 0; + + if (fetch_active) { + for (i = 0; i < SSPP_MAX; i++) { + if (test_bit(i, fetch_active) && + fetch_tbl[i] != CTL_INVALID_BIT) + val |= BIT(fetch_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); +} + static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, unsigned long cap) { @@ -558,6 +585,8 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp; ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer; ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp; + if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) + ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; static struct dpu_hw_blk_ops dpu_hw_ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index e93a42ab60b1..806c171e5df2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -167,6 +167,9 @@ struct dpu_hw_ctl_ops { */ void (*setup_blendstage)(struct dpu_hw_ctl *ctx, enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); + + void (*set_active_pipes)(struct dpu_hw_ctl *ctx, + unsigned long *fetch_active); }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 5c521de71567..48c96b812126 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -25,6 +25,9 @@ #define MDP_AD4_INTR_EN_OFF 0x41c #define MDP_AD4_INTR_CLEAR_OFF 0x424 #define MDP_AD4_INTR_STATUS_OFF 0x420 +#define MDP_INTF_0_OFF_REV_7xxx 0x34000 +#define MDP_INTF_1_OFF_REV_7xxx 0x35000 +#define MDP_INTF_5_OFF_REV_7xxx 0x39000 /** * WB interrupt status bit definitions @@ -69,10 +72,12 @@ #define DPU_INTR_INTF_1_UNDERRUN BIT(26) #define DPU_INTR_INTF_2_UNDERRUN BIT(28) #define DPU_INTR_INTF_3_UNDERRUN BIT(30) +#define DPU_INTR_INTF_5_UNDERRUN BIT(22) #define DPU_INTR_INTF_0_VSYNC BIT(25) #define DPU_INTR_INTF_1_VSYNC BIT(27) #define DPU_INTR_INTF_2_VSYNC BIT(29) #define DPU_INTR_INTF_3_VSYNC BIT(31) +#define DPU_INTR_INTF_5_VSYNC BIT(23) /** * Pingpong Secondary interrupt status bit definitions @@ -242,7 +247,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = { MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF, MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF, MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF, - } + }, + { + MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR, + MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN, + MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS + }, + { + MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR, + MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN, + MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS + }, + { + MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR, + MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN, + MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS + }, }; /* @@ -308,24 +328,59 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, - - /* BEGIN MAP_RANGE: 32-64, INTR2 */ - /* irq_idx: 32-35 */ + /* irq_idx:32-33 */ + { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, + { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, + /* irq_idx:34-63 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, + /* BEGIN MAP_RANGE: 64-95, INTR2 */ + /* irq_idx: 64-67 */ { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0, DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 36-39 */ + /* irq_idx: 68-71 */ { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0, DPU_INTR_PING_PONG_S0_WR_PTR, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 40 */ + /* irq_idx: 72 */ { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0, DPU_INTR_PING_PONG_S0_RD_PTR, 1}, - /* irq_idx: 41-45 */ + /* irq_idx: 73-77 */ { DPU_IRQ_TYPE_CTL_START, CTL_0, DPU_INTR_CTL_0_START, 1}, { DPU_IRQ_TYPE_CTL_START, CTL_1, @@ -336,10 +391,10 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_CTL_3_START, 1}, { DPU_IRQ_TYPE_CTL_START, CTL_4, DPU_INTR_CTL_4_START, 1}, - /* irq_idx: 46-47 */ + /* irq_idx: 78-79 */ { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1}, { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1}, - /* irq_idx: 48-51 */ + /* irq_idx: 80-83 */ { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0, DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1}, { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1, @@ -348,13 +403,13 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1}, { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3, DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1}, - /* irq_idx: 52-55 */ + /* irq_idx: 84-87 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0, DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 56-59 */ + /* irq_idx: 88-91 */ { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0, DPU_INTR_PING_PONG_0_TE_DETECTED, 1}, { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1, @@ -363,65 +418,129 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_PING_PONG_2_TE_DETECTED, 1}, { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3, DPU_INTR_PING_PONG_3_TE_DETECTED, 1}, - /* irq_idx: 60-63 */ + /* irq_idx: 92-95 */ { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0, DPU_INTR_PING_PONG_S0_TE_DETECTED, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - - /* BEGIN MAP_RANGE: 64-95 HIST */ - /* irq_idx: 64-67 */ + /* irq_idx: 96-127 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, + /* BEGIN MAP_RANGE: 128-159 HIST */ + /* irq_idx: 128-131 */ { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2}, { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0, DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 68-71 */ + /* irq_idx: 132-135 */ { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2}, { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1, DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 72-75 */ + /* irq_idx: 136-139 */ { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2, DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2}, { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3, DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2}, - /* irq_idx: 76-79 */ + /* irq_idx: 140-143 */ { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2}, { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0, DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 80-83 */ + /* irq_idx: 144-147 */ { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2}, { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1, DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 84-87 */ + /* irq_idx: 148-151 */ { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2}, { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2, DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2}, { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2}, { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3, DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2}, - /* irq_idx: 88-91 */ + /* irq_idx: 152-155 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 92-95 */ + /* irq_idx: 156-159 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - - /* BEGIN MAP_RANGE: 96-127 INTF_0_INTR */ - /* irq_idx: 96-99 */ + /* irq_idx: 160-191 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, + /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */ + /* irq_idx: 192-195 */ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, DPU_INTR_VIDEO_INTO_STATIC, 3}, { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, @@ -430,7 +549,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_0_INTO_STATIC, 3}, { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, DPU_INTR_DSICMD_0_OUTOF_STATIC, 3}, - /* irq_idx: 100-103 */ + /* irq_idx: 196-199 */ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, DPU_INTR_DSICMD_1_INTO_STATIC, 3}, { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, @@ -439,39 +558,71 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_2_INTO_STATIC, 3}, { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, DPU_INTR_DSICMD_2_OUTOF_STATIC, 3}, - /* irq_idx: 104-107 */ + /* irq_idx: 200-203 */ { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 108-111 */ + /* irq_idx: 204-207 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* irq_idx: 208-211 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 112-115 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* irq_idx: 212-215 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 116-119 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* irq_idx: 216-219 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 120-123 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* irq_idx: 220-223 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 124-127 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* irq_idx: 224-255 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - - /* BEGIN MAP_RANGE: 128-159 INTF_1_INTR */ - /* irq_idx: 128-131 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, + /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */ + /* irq_idx: 256-259 */ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, DPU_INTR_VIDEO_INTO_STATIC, 4}, { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, @@ -480,7 +631,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_0_INTO_STATIC, 4}, { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, DPU_INTR_DSICMD_0_OUTOF_STATIC, 4}, - /* irq_idx: 132-135 */ + /* irq_idx: 260-263 */ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, DPU_INTR_DSICMD_1_INTO_STATIC, 4}, { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, @@ -489,39 +640,71 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_2_INTO_STATIC, 4}, { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, DPU_INTR_DSICMD_2_OUTOF_STATIC, 4}, - /* irq_idx: 136-139 */ + /* irq_idx: 264-267 */ { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 140-143 */ + /* irq_idx: 268-271 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 144-147 */ + /* irq_idx: 272-275 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 148-151 */ + /* irq_idx: 276-279 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 152-155 */ + /* irq_idx: 280-283 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 156-159 */ + /* irq_idx: 284-287 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - - /* BEGIN MAP_RANGE: 160-191 INTF_2_INTR */ - /* irq_idx: 160-163 */ + /* irq_idx: 288-319 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, + /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */ + /* irq_idx: 320-323 */ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2, DPU_INTR_VIDEO_INTO_STATIC, 5}, { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2, @@ -530,7 +713,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_0_INTO_STATIC, 5}, { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2, DPU_INTR_DSICMD_0_OUTOF_STATIC, 5}, - /* irq_idx: 164-167 */ + /* irq_idx: 324-327 */ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2, DPU_INTR_DSICMD_1_INTO_STATIC, 5}, { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2, @@ -539,39 +722,71 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_2_INTO_STATIC, 5}, { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2, DPU_INTR_DSICMD_2_OUTOF_STATIC, 5}, - /* irq_idx: 168-171 */ + /* irq_idx: 328-331 */ { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 172-175 */ + /* irq_idx: 332-335 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 176-179 */ + /* irq_idx: 336-339 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 180-183 */ + /* irq_idx: 340-343 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 184-187 */ + /* irq_idx: 344-347 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 188-191 */ + /* irq_idx: 348-351 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - - /* BEGIN MAP_RANGE: 192-223 INTF_3_INTR */ - /* irq_idx: 192-195 */ + /* irq_idx: 352-383 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, + /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */ + /* irq_idx: 384-387 */ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3, DPU_INTR_VIDEO_INTO_STATIC, 6}, { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3, @@ -580,7 +795,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_0_INTO_STATIC, 6}, { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3, DPU_INTR_DSICMD_0_OUTOF_STATIC, 6}, - /* irq_idx: 196-199 */ + /* irq_idx: 388-391 */ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3, DPU_INTR_DSICMD_1_INTO_STATIC, 6}, { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3, @@ -589,39 +804,71 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_2_INTO_STATIC, 6}, { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3, DPU_INTR_DSICMD_2_OUTOF_STATIC, 6}, - /* irq_idx: 200-203 */ + /* irq_idx: 392-395 */ { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 204-207 */ + /* irq_idx: 396-399 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 208-211 */ + /* irq_idx: 400-403 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 212-215 */ + /* irq_idx: 404-407 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 216-219 */ + /* irq_idx: 408-411 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 220-223 */ + /* irq_idx: 412-415 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - - /* BEGIN MAP_RANGE: 224-255 INTF_4_INTR */ - /* irq_idx: 224-227 */ + /* irq_idx: 416-447*/ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, + /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */ + /* irq_idx: 448-451 */ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4, DPU_INTR_VIDEO_INTO_STATIC, 7}, { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4, @@ -630,7 +877,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_0_INTO_STATIC, 7}, { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4, DPU_INTR_DSICMD_0_OUTOF_STATIC, 7}, - /* irq_idx: 228-231 */ + /* irq_idx: 452-455 */ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4, DPU_INTR_DSICMD_1_INTO_STATIC, 7}, { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4, @@ -639,130 +886,474 @@ static const struct dpu_irq_type dpu_irq_map[] = { DPU_INTR_DSICMD_2_INTO_STATIC, 7}, { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4, DPU_INTR_DSICMD_2_OUTOF_STATIC, 7}, - /* irq_idx: 232-235 */ + /* irq_idx: 456-459 */ { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 236-239 */ + /* irq_idx: 460-463 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 240-243 */ + /* irq_idx: 464-467 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 244-247 */ + /* irq_idx: 468-471 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 248-251 */ + /* irq_idx: 472-475 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 252-255 */ + /* irq_idx: 476-479 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - - /* BEGIN MAP_RANGE: 256-287 AD4_0_INTR */ - /* irq_idx: 256-259 */ + /* irq_idx: 480-511 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, + /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */ + /* irq_idx: 512-515 */ { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 260-263 */ + /* irq_idx: 516-519 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 264-267 */ + /* irq_idx: 520-523 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 268-271 */ + /* irq_idx: 524-527 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 272-275 */ + /* irq_idx: 528-531 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 276-279 */ + /* irq_idx: 532-535 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 280-283 */ + /* irq_idx: 536-539 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 284-287 */ + /* irq_idx: 540-543 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - - /* BEGIN MAP_RANGE: 288-319 AD4_1_INTR */ - /* irq_idx: 288-291 */ + /* irq_idx: 544-575*/ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, + /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */ + /* irq_idx: 576-579 */ { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 292-295 */ + /* irq_idx: 580-583 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 584-587 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 296-299 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 588-591 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 300-303 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 592-595 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 304-307 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 596-599 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 308-311 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 600-603 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 312-315 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 604-607 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 315-319 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* irq_idx: 608-639 */ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, + /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */ + /* irq_idx: 640-643 */ + { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, + DPU_INTR_VIDEO_INTO_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, + DPU_INTR_VIDEO_OUTOF_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, + DPU_INTR_DSICMD_0_INTO_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, + DPU_INTR_DSICMD_0_OUTOF_STATIC, 10}, + /* irq_idx: 644-647 */ + { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, + DPU_INTR_DSICMD_1_INTO_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, + DPU_INTR_DSICMD_1_OUTOF_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, + DPU_INTR_DSICMD_2_INTO_STATIC, 10}, + { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, + DPU_INTR_DSICMD_2_OUTOF_STATIC, 10}, + /* irq_idx: 648-651 */ + { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 652-655 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 656-659 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 660-663 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 664-667 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 668-671 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* irq_idx: 672-703 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, + /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */ + /* irq_idx: 704-707 */ + { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, + DPU_INTR_VIDEO_INTO_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, + DPU_INTR_VIDEO_OUTOF_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, + DPU_INTR_DSICMD_0_INTO_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, + DPU_INTR_DSICMD_0_OUTOF_STATIC, 11}, + /* irq_idx: 708-711 */ + { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, + DPU_INTR_DSICMD_1_INTO_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, + DPU_INTR_DSICMD_1_OUTOF_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, + DPU_INTR_DSICMD_2_INTO_STATIC, 11}, + { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, + DPU_INTR_DSICMD_2_OUTOF_STATIC, 11}, + /* irq_idx: 712-715 */ + { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 716-719 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 720-723 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 724-727 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 728-731 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 732-735 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* irq_idx: 736-767 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, + /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */ + /* irq_idx: 768-771 */ + { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5, + DPU_INTR_VIDEO_INTO_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5, + DPU_INTR_VIDEO_OUTOF_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5, + DPU_INTR_DSICMD_0_INTO_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5, + DPU_INTR_DSICMD_0_OUTOF_STATIC, 12}, + /* irq_idx: 772-775 */ + { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5, + DPU_INTR_DSICMD_1_INTO_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5, + DPU_INTR_DSICMD_1_OUTOF_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5, + DPU_INTR_DSICMD_2_INTO_STATIC, 12}, + { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5, + DPU_INTR_DSICMD_2_OUTOF_STATIC, 12}, + /* irq_idx: 776-779 */ + { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 780-783 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 784-787 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 788-791 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 792-795 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 796-799 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + /* irq_idx: 800-831 */ + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, + { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, }; -static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type, - u32 instance_idx) +static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr, + enum dpu_intr_type intr_type, u32 instance_idx) { int i; for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) { if (intr_type == dpu_irq_map[i].intr_type && - instance_idx == dpu_irq_map[i].instance_idx) + instance_idx == dpu_irq_map[i].instance_idx && + !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type))) return i; } @@ -795,11 +1386,11 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, irq_status = intr->save_irq_status[reg_idx]; /* - * Each Interrupt register has a range of 32 indexes, and + * Each Interrupt register has a range of 64 indexes, and * that is static for dpu_irq_map. */ - start_idx = reg_idx * 32; - end_idx = start_idx + 32; + start_idx = reg_idx * 64; + end_idx = start_idx + 64; if (!test_bit(reg_idx, &intr->irq_mask) || start_idx >= ARRAY_SIZE(dpu_irq_map)) @@ -814,7 +1405,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, (irq_idx < end_idx) && irq_status; irq_idx++) if ((irq_status & dpu_irq_map[irq_idx].irq_mask) && - (dpu_irq_map[irq_idx].reg_idx == reg_idx)) { + (dpu_irq_map[irq_idx].reg_idx == reg_idx) && + !(intr->obsolete_irq & + BIT(dpu_irq_map[irq_idx].intr_type))) { /* * Once a match on irq mask, perform a callback * to the given cbfunc. cbfunc will take care @@ -1126,6 +1719,8 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, } intr->irq_mask = m->mdss_irqs; + intr->obsolete_irq = m->obsolete_irq; + spin_lock_init(&intr->irq_lock); return intr; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index fc9c98617281..5d6f9a7a5195 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -83,11 +83,12 @@ struct dpu_hw_intr_ops { /** * irq_idx_lookup - Lookup IRQ index on the HW interrupt type * Used for all irq related ops + * @intr: HW interrupt handle * @intr_type: Interrupt type defined in dpu_intr_type * @instance_idx: HW interrupt block instance * @return: irq_idx or -EINVAL for lookup fail */ - int (*irq_idx_lookup)( + int (*irq_idx_lookup)(struct dpu_hw_intr *intr, enum dpu_intr_type intr_type, u32 instance_idx); @@ -179,6 +180,7 @@ struct dpu_hw_intr_ops { * @save_irq_status: array of IRQ status reg storage created during init * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts * @irq_lock: spinlock for accessing IRQ resources + * @obsolete_irq: irq types that are obsolete for a particular target */ struct dpu_hw_intr { struct dpu_hw_blk_reg_map hw; @@ -188,6 +190,7 @@ struct dpu_hw_intr { u32 irq_idx_tbl_size; spinlock_t irq_lock; unsigned long irq_mask; + unsigned long obsolete_irq; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 6f0f54588124..1599e3f49a4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -31,6 +31,8 @@ #define INTF_TEST_CTL 0x054 #define INTF_TP_COLOR0 0x058 #define INTF_TP_COLOR1 0x05C +#define INTF_CONFIG2 0x060 +#define INTF_DISPLAY_DATA_HCTL 0x064 #define INTF_FRAME_LINE_COUNT_EN 0x0A8 #define INTF_FRAME_COUNT 0x0AC #define INTF_LINE_COUNT 0x0B0 @@ -93,7 +95,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, u32 active_hctl, display_hctl, hsync_ctl; u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity; u32 panel_format; - u32 intf_cfg; + u32 intf_cfg, intf_cfg2 = 0, display_data_hctl = 0; /* read interface_cfg */ intf_cfg = DPU_REG_READ(c, INTF_CONFIG); @@ -178,6 +180,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, (COLOR_8BIT << 4) | (0x21 << 8)); + if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { + intf_cfg2 |= BIT(4); + display_data_hctl = display_hctl; + DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); + DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); + } + DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, @@ -256,6 +265,7 @@ static void dpu_hw_intf_get_status( struct dpu_hw_blk_reg_map *c = &intf->hw; s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); + s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); if (s->is_en) { s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 0ead64d3f63d..3568be80dab5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -40,6 +40,7 @@ struct intf_prog_fetch { struct intf_status { u8 is_en; /* interface timing engine is enabled or not */ + u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */ u32 frame_count; /* frame count since timing engine enabled */ u32 line_count; /* current line count including blanking */ }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index 8018fff5667a..3aa10c89ca1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -30,7 +30,7 @@ struct traffic_shaper_cfg { /** * struct split_pipe_cfg - pipe configuration for dual display panels - * @en : Enable/disable dual pipe confguration + * @en : Enable/disable dual pipe configuration * @mode : Panel interface mode * @intf : Interface id for main control path * @split_flush_en: Allows both the paths to be flushed when master path is @@ -76,7 +76,7 @@ struct dpu_vsync_source_cfg { * @setup_traffic_shaper : programs traffic shaper control */ struct dpu_hw_mdp_ops { - /** setup_split_pipe() : Regsiters are not double buffered, thisk + /** setup_split_pipe() : Registers are not double buffered, thisk * function should be called before timing control enable * @mdp : mdp top context driver * @cfg : upper and lower part of pipe configuration diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 5a8e3e1fc48c..88e9cc38c13b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -14,6 +14,7 @@ #include <drm/drm_crtc.h> #include <drm/drm_file.h> +#include <drm/drm_vblank.h> #include "msm_drv.h" #include "msm_mmu.h" @@ -43,6 +44,8 @@ #define DPU_DEBUGFS_DIR "msm_dpu" #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" +#define MIN_IB_BW 400000000ULL /* Min ib vote 400MB */ + static int dpu_kms_hw_init(struct msm_kms *kms); static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); @@ -931,6 +934,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) DPU_DEBUG("REG_DMA is not defined"); } + dpu_kms_parse_data_bus_icc_path(dpu_kms); + pm_runtime_get_sync(&dpu_kms->pdev->dev); dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0); @@ -1020,6 +1025,10 @@ static int dpu_kms_hw_init(struct msm_kms *kms) */ dev->mode_config.allow_fb_modifiers = true; + dev->max_vblank_count = 0xffffffff; + /* Disable vblank irqs aggressively for power-saving */ + dev->vblank_disable_immediate = true; + /* * _dpu_kms_drm_obj_init should create the DRM related objects * i.e. CRTCs, planes, encoders, connectors and so forth @@ -1032,9 +1041,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_vbif_init_memtypes(dpu_kms); - if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) - dpu_kms_parse_data_bus_icc_path(dpu_kms); - pm_runtime_put_sync(&dpu_kms->pdev->dev); return 0; @@ -1191,10 +1197,10 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev) ddev = dpu_kms->dev; + WARN_ON(!(dpu_kms->num_paths)); /* Min vote of BW is required before turning on AXI clk */ for (i = 0; i < dpu_kms->num_paths; i++) - icc_set_bw(dpu_kms->path[i], 0, - dpu_kms->catalog->perf.min_dram_ib); + icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW)); rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (rc) { @@ -1219,6 +1225,9 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sdm845-dpu", }, { .compatible = "qcom,sc7180-dpu", }, + { .compatible = "qcom,sc7280-dpu", }, + { .compatible = "qcom,sm8150-dpu", }, + { .compatible = "qcom,sm8250-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index cd4078807db1..06b56fec04e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -31,40 +31,8 @@ struct dpu_mdss { void __iomem *mmio; struct dss_module_power mp; struct dpu_irq_controller irq_controller; - struct icc_path *path[2]; - u32 num_paths; }; -static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev, - struct dpu_mdss *dpu_mdss) -{ - struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem"); - struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem"); - - if (IS_ERR_OR_NULL(path0)) - return PTR_ERR_OR_ZERO(path0); - - dpu_mdss->path[0] = path0; - dpu_mdss->num_paths = 1; - - if (!IS_ERR_OR_NULL(path1)) { - dpu_mdss->path[1] = path1; - dpu_mdss->num_paths++; - } - - return 0; -} - -static void dpu_mdss_icc_request_bw(struct msm_mdss *mdss) -{ - struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); - int i; - u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0; - - for (i = 0; i < dpu_mdss->num_paths; i++) - icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW)); -} - static void dpu_mdss_irq(struct irq_desc *desc) { struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc); @@ -178,8 +146,6 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) struct dss_module_power *mp = &dpu_mdss->mp; int ret; - dpu_mdss_icc_request_bw(mdss); - ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (ret) { DPU_ERROR("clock enable failed, ret:%d\n", ret); @@ -204,6 +170,9 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) case DPU_HW_VER_620: writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC); break; + case DPU_HW_VER_720: + writel_relaxed(0x101e, dpu_mdss->mmio + UBWC_STATIC); + break; } return ret; @@ -213,15 +182,12 @@ static int dpu_mdss_disable(struct msm_mdss *mdss) { struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; - int ret, i; + int ret; ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); if (ret) DPU_ERROR("clock disable failed, ret:%d\n", ret); - for (i = 0; i < dpu_mdss->num_paths; i++) - icc_set_bw(dpu_mdss->path[i], 0, 0); - return ret; } @@ -232,7 +198,6 @@ static void dpu_mdss_destroy(struct drm_device *dev) struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); struct dss_module_power *mp = &dpu_mdss->mp; int irq; - int i; pm_runtime_suspend(dev->dev); pm_runtime_disable(dev->dev); @@ -242,9 +207,6 @@ static void dpu_mdss_destroy(struct drm_device *dev) msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); - for (i = 0; i < dpu_mdss->num_paths; i++) - icc_put(dpu_mdss->path[i]); - if (dpu_mdss->mmio) devm_iounmap(&pdev->dev, dpu_mdss->mmio); dpu_mdss->mmio = NULL; @@ -276,12 +238,6 @@ int dpu_mdss_init(struct drm_device *dev) DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio); - if (!of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) { - ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss); - if (ret) - return ret; - } - mp = &dpu_mdss->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { @@ -307,8 +263,6 @@ int dpu_mdss_init(struct drm_device *dev) pm_runtime_enable(dev->dev); - dpu_mdss_icc_request_bw(priv->mdss); - return ret; irq_error: diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c index ff2c1d583c79..ec6c7b09865e 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c @@ -20,7 +20,7 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, { struct mdp5_kms *mdp5_kms = get_kms(encoder); struct device *dev = encoder->dev->dev; - u32 total_lines_x100, vclks_line, cfg; + u32 total_lines, vclks_line, cfg; long vsync_clk_speed; struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc); int pp_id = mixer->pp; @@ -30,8 +30,8 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, return -EINVAL; } - total_lines_x100 = mode->vtotal * drm_mode_vrefresh(mode); - if (!total_lines_x100) { + total_lines = mode->vtotal * drm_mode_vrefresh(mode); + if (!total_lines) { DRM_DEV_ERROR(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n", __func__, mode->vtotal, drm_mode_vrefresh(mode)); return -EINVAL; @@ -43,15 +43,23 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, vsync_clk_speed); return -EINVAL; } - vclks_line = vsync_clk_speed * 100 / total_lines_x100; + vclks_line = vsync_clk_speed / total_lines; cfg = MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN | MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN; cfg |= MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(vclks_line); + /* + * Tearcheck emits a blanking signal every vclks_line * vtotal * 2 ticks on + * the vsync_clk equating to roughly half the desired panel refresh rate. + * This is only necessary as stability fallback if interrupts from the + * panel arrive too late or not at all, but is currently used by default + * because these panel interrupts are not wired up yet. + */ mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg); mdp5_write(mdp5_kms, - REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), 0xfff0); + REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal)); + mdp5_write(mdp5_kms, REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay); mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1); @@ -59,6 +67,7 @@ static int pingpong_tearcheck_setup(struct drm_encoder *encoder, mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id), MDP5_PP_SYNC_THRESH_START(4) | MDP5_PP_SYNC_THRESH_CONTINUE(4)); + mdp5_write(mdp5_kms, REG_MDP5_PP_AUTOREFRESH_CONFIG(pp_id), 0x0); return 0; } |