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-rw-r--r--drivers/gpu/drm/panel/Kconfig31
-rw-r--r--drivers/gpu/drm/panel/Makefile3
-rw-r--r--drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c126
-rw-r--r--drivers/gpu/drm/panel/panel-edp.c2
-rw-r--r--drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c209
-rw-r--r--drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c522
-rw-r--r--drivers/gpu/drm/panel/panel-novatek-nt35950.c10
-rw-r--r--drivers/gpu/drm/panel/panel-novatek-nt36523.c777
-rw-r--r--drivers/gpu/drm/panel/panel-orisetech-otm8009a.c2
-rw-r--r--drivers/gpu/drm/panel/panel-seiko-43wvf1g.c12
-rw-r--r--drivers/gpu/drm/panel/panel-sitronix-st7701.c144
-rw-r--r--drivers/gpu/drm/panel/panel-sony-td4353-jdi.c329
12 files changed, 2164 insertions, 3 deletions
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 8eeee71c0000..2b9d6db7860b 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -318,6 +318,17 @@ config DRM_PANEL_LG_LG4573
Say Y here if you want to enable support for LG4573 RGB panel.
To compile this driver as a module, choose M here.
+config DRM_PANEL_MAGNACHIP_D53E6EA8966
+ tristate "Magnachip D53E6EA8966 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel controlled
+ with the Magnachip D53E6EA8966 panel IC. This panel receives
+ video data via DSI but commands via 9-bit SPI using DBI.
+
config DRM_PANEL_NEC_NL8048HL11
tristate "NEC NL8048HL11 RGB panel"
depends on GPIOLIB && OF && SPI
@@ -377,6 +388,16 @@ config DRM_PANEL_NOVATEK_NT35950
Sharp panels used in Sony Xperia Z5 Premium and XZ Premium
mobile phones.
+config DRM_PANEL_NOVATEK_NT36523
+ tristate "Novatek NT36523 panel driver"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for the panels built
+ around the Novatek NT36523 display controller, such as some
+ Boe panels used in Xiaomi Mi Pad 5 and 5 Pro tablets.
+
config DRM_PANEL_NOVATEK_NT36672A
tristate "Novatek NT36672A DSI panel"
depends on OF
@@ -685,6 +706,16 @@ config DRM_PANEL_SONY_ACX565AKM
Say Y here if you want to enable support for the Sony ACX565AKM
800x600 3.5" panel (found on the Nokia N900).
+config DRM_PANEL_SONY_TD4353_JDI
+ tristate "Sony TD4353 JDI panel"
+ depends on GPIOLIB && OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for the Sony Tama
+ TD4353 JDI command mode panel as found on some Sony Xperia
+ XZ2 and XZ2 Compact smartphones.
+
config DRM_PANEL_SONY_TULIP_TRULY_NT35521
tristate "Sony Tulip Truly NT35521 panel"
depends on GPIOLIB && OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index c05aa9e23907..ff169781e82d 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -29,12 +29,14 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) += panel-leadtek-ltk050h3146w.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
+obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o
+obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o
obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o
@@ -69,6 +71,7 @@ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o
+obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) += panel-sony-td4353-jdi.o
obj-$(CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521) += panel-sony-tulip-truly-nt35521.o
obj-$(CONFIG_DRM_PANEL_TDO_TL070WSH30) += panel-tdo-tl070wsh30.o
obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index c924f1124ebc..783234ae0f57 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -1131,6 +1131,103 @@ static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
{},
};
+static const struct panel_init_cmd starry_qfh032011_53g_init_cmd[] = {
+ _INIT_DCS_CMD(0xB0, 0x01),
+ _INIT_DCS_CMD(0xC3, 0x4F),
+ _INIT_DCS_CMD(0xC4, 0x40),
+ _INIT_DCS_CMD(0xC5, 0x40),
+ _INIT_DCS_CMD(0xC6, 0x40),
+ _INIT_DCS_CMD(0xC7, 0x40),
+ _INIT_DCS_CMD(0xC8, 0x4D),
+ _INIT_DCS_CMD(0xC9, 0x52),
+ _INIT_DCS_CMD(0xCA, 0x51),
+ _INIT_DCS_CMD(0xCD, 0x5D),
+ _INIT_DCS_CMD(0xCE, 0x5B),
+ _INIT_DCS_CMD(0xCF, 0x4B),
+ _INIT_DCS_CMD(0xD0, 0x49),
+ _INIT_DCS_CMD(0xD1, 0x47),
+ _INIT_DCS_CMD(0xD2, 0x45),
+ _INIT_DCS_CMD(0xD3, 0x41),
+ _INIT_DCS_CMD(0xD7, 0x50),
+ _INIT_DCS_CMD(0xD8, 0x40),
+ _INIT_DCS_CMD(0xD9, 0x40),
+ _INIT_DCS_CMD(0xDA, 0x40),
+ _INIT_DCS_CMD(0xDB, 0x40),
+ _INIT_DCS_CMD(0xDC, 0x4E),
+ _INIT_DCS_CMD(0xDD, 0x52),
+ _INIT_DCS_CMD(0xDE, 0x51),
+ _INIT_DCS_CMD(0xE1, 0x5E),
+ _INIT_DCS_CMD(0xE2, 0x5C),
+ _INIT_DCS_CMD(0xE3, 0x4C),
+ _INIT_DCS_CMD(0xE4, 0x4A),
+ _INIT_DCS_CMD(0xE5, 0x48),
+ _INIT_DCS_CMD(0xE6, 0x46),
+ _INIT_DCS_CMD(0xE7, 0x42),
+ _INIT_DCS_CMD(0xB0, 0x03),
+ _INIT_DCS_CMD(0xBE, 0x03),
+ _INIT_DCS_CMD(0xCC, 0x44),
+ _INIT_DCS_CMD(0xC8, 0x07),
+ _INIT_DCS_CMD(0xC9, 0x05),
+ _INIT_DCS_CMD(0xCA, 0x42),
+ _INIT_DCS_CMD(0xCD, 0x3E),
+ _INIT_DCS_CMD(0xCF, 0x60),
+ _INIT_DCS_CMD(0xD2, 0x04),
+ _INIT_DCS_CMD(0xD3, 0x04),
+ _INIT_DCS_CMD(0xD4, 0x01),
+ _INIT_DCS_CMD(0xD5, 0x00),
+ _INIT_DCS_CMD(0xD6, 0x03),
+ _INIT_DCS_CMD(0xD7, 0x04),
+ _INIT_DCS_CMD(0xD9, 0x01),
+ _INIT_DCS_CMD(0xDB, 0x01),
+ _INIT_DCS_CMD(0xE4, 0xF0),
+ _INIT_DCS_CMD(0xE5, 0x0A),
+ _INIT_DCS_CMD(0xB0, 0x00),
+ _INIT_DCS_CMD(0xCC, 0x08),
+ _INIT_DCS_CMD(0xC2, 0x08),
+ _INIT_DCS_CMD(0xC4, 0x10),
+ _INIT_DCS_CMD(0xB0, 0x02),
+ _INIT_DCS_CMD(0xC0, 0x00),
+ _INIT_DCS_CMD(0xC1, 0x0A),
+ _INIT_DCS_CMD(0xC2, 0x20),
+ _INIT_DCS_CMD(0xC3, 0x24),
+ _INIT_DCS_CMD(0xC4, 0x23),
+ _INIT_DCS_CMD(0xC5, 0x29),
+ _INIT_DCS_CMD(0xC6, 0x23),
+ _INIT_DCS_CMD(0xC7, 0x1C),
+ _INIT_DCS_CMD(0xC8, 0x19),
+ _INIT_DCS_CMD(0xC9, 0x17),
+ _INIT_DCS_CMD(0xCA, 0x17),
+ _INIT_DCS_CMD(0xCB, 0x18),
+ _INIT_DCS_CMD(0xCC, 0x1A),
+ _INIT_DCS_CMD(0xCD, 0x1E),
+ _INIT_DCS_CMD(0xCE, 0x20),
+ _INIT_DCS_CMD(0xCF, 0x23),
+ _INIT_DCS_CMD(0xD0, 0x07),
+ _INIT_DCS_CMD(0xD1, 0x00),
+ _INIT_DCS_CMD(0xD2, 0x00),
+ _INIT_DCS_CMD(0xD3, 0x0A),
+ _INIT_DCS_CMD(0xD4, 0x13),
+ _INIT_DCS_CMD(0xD5, 0x1C),
+ _INIT_DCS_CMD(0xD6, 0x1A),
+ _INIT_DCS_CMD(0xD7, 0x13),
+ _INIT_DCS_CMD(0xD8, 0x17),
+ _INIT_DCS_CMD(0xD9, 0x1C),
+ _INIT_DCS_CMD(0xDA, 0x19),
+ _INIT_DCS_CMD(0xDB, 0x17),
+ _INIT_DCS_CMD(0xDC, 0x17),
+ _INIT_DCS_CMD(0xDD, 0x18),
+ _INIT_DCS_CMD(0xDE, 0x1A),
+ _INIT_DCS_CMD(0xDF, 0x1E),
+ _INIT_DCS_CMD(0xE0, 0x20),
+ _INIT_DCS_CMD(0xE1, 0x23),
+ _INIT_DCS_CMD(0xE2, 0x07),
+ _INIT_DCS_CMD(0X11),
+ _INIT_DELAY_CMD(120),
+ _INIT_DCS_CMD(0X29),
+ _INIT_DELAY_CMD(80),
+ {},
+};
+
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
{
return container_of(panel, struct boe_panel, base);
@@ -1497,6 +1594,32 @@ static const struct panel_desc boe_tv105wum_nw0_desc = {
.init_cmds = boe_init_cmd,
};
+static const struct drm_display_mode starry_qfh032011_53g_default_mode = {
+ .clock = 165731,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 100,
+ .hsync_end = 1200 + 100 + 10,
+ .htotal = 1200 + 100 + 10 + 100,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 14,
+ .vsync_end = 1920 + 14 + 10,
+ .vtotal = 1920 + 14 + 10 + 15,
+};
+
+static const struct panel_desc starry_qfh032011_53g_desc = {
+ .modes = &starry_qfh032011_53g_default_mode,
+ .bpc = 8,
+ .size = {
+ .width_mm = 135,
+ .height_mm = 216,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+ .init_cmds = starry_qfh032011_53g_init_cmd,
+};
+
static int boe_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -1667,6 +1790,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "innolux,hj110iz-01a",
.data = &inx_hj110iz_desc
},
+ { .compatible = "starry,2081101qfh032011-53g",
+ .data = &starry_qfh032011_53g_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, boe_of_match);
diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index 01bfe0783304..e23ddab2126e 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -1871,6 +1871,7 @@ static const struct edp_panel_entry edp_panels[] = {
EDP_PANEL_ENTRY('A', 'U', 'O', 0x1e9b, &delay_200_500_e50, "B133UAN02.1"),
EDP_PANEL_ENTRY('A', 'U', 'O', 0x1ea5, &delay_200_500_e50, "B116XAK01.6"),
EDP_PANEL_ENTRY('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01"),
+ EDP_PANEL_ENTRY('A', 'U', 'O', 0x582d, &delay_200_500_e50, "B133UAN01.0"),
EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"),
EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"),
@@ -1878,6 +1879,7 @@ static const struct edp_panel_entry edp_panels[] = {
EDP_PANEL_ENTRY('B', 'O', 'E', 0x07d1, &boe_nv133fhm_n61.delay, "NV133FHM-N61"),
EDP_PANEL_ENTRY('B', 'O', 'E', 0x082d, &boe_nv133fhm_n61.delay, "NV133FHM-N62"),
EDP_PANEL_ENTRY('B', 'O', 'E', 0x094b, &delay_200_500_e50, "NT116WHM-N21"),
+ EDP_PANEL_ENTRY('B', 'O', 'E', 0x095f, &delay_200_500_e50, "NE135FBM-N41 v8.1"),
EDP_PANEL_ENTRY('B', 'O', 'E', 0x098d, &boe_nv110wtm_n61.delay, "NV110WTM-N61"),
EDP_PANEL_ENTRY('B', 'O', 'E', 0x09dd, &delay_200_500_e50, "NT116WHM-N21"),
EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a5d, &delay_200_500_e50, "NV116WHM-N45"),
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 48c1702a863b..323c33c9c37a 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -167,6 +167,202 @@ static const struct drm_panel_funcs jadard_funcs = {
.get_modes = jadard_get_modes,
};
+static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = {
+ { .data = { 0xE0, 0x00 } },
+ { .data = { 0xE1, 0x93 } },
+ { .data = { 0xE2, 0x65 } },
+ { .data = { 0xE3, 0xF8 } },
+ { .data = { 0x80, 0x03 } },
+ { .data = { 0xE0, 0x01 } },
+ { .data = { 0x00, 0x00 } },
+ { .data = { 0x01, 0x7E } },
+ { .data = { 0x03, 0x00 } },
+ { .data = { 0x04, 0x65 } },
+ { .data = { 0x0C, 0x74 } },
+ { .data = { 0x17, 0x00 } },
+ { .data = { 0x18, 0xB7 } },
+ { .data = { 0x19, 0x00 } },
+ { .data = { 0x1A, 0x00 } },
+ { .data = { 0x1B, 0xB7 } },
+ { .data = { 0x1C, 0x00 } },
+ { .data = { 0x24, 0xFE } },
+ { .data = { 0x37, 0x19 } },
+ { .data = { 0x38, 0x05 } },
+ { .data = { 0x39, 0x00 } },
+ { .data = { 0x3A, 0x01 } },
+ { .data = { 0x3B, 0x01 } },
+ { .data = { 0x3C, 0x70 } },
+ { .data = { 0x3D, 0xFF } },
+ { .data = { 0x3E, 0xFF } },
+ { .data = { 0x3F, 0xFF } },
+ { .data = { 0x40, 0x06 } },
+ { .data = { 0x41, 0xA0 } },
+ { .data = { 0x43, 0x1E } },
+ { .data = { 0x44, 0x0F } },
+ { .data = { 0x45, 0x28 } },
+ { .data = { 0x4B, 0x04 } },
+ { .data = { 0x55, 0x02 } },
+ { .data = { 0x56, 0x01 } },
+ { .data = { 0x57, 0xA9 } },
+ { .data = { 0x58, 0x0A } },
+ { .data = { 0x59, 0x0A } },
+ { .data = { 0x5A, 0x37 } },
+ { .data = { 0x5B, 0x19 } },
+ { .data = { 0x5D, 0x78 } },
+ { .data = { 0x5E, 0x63 } },
+ { .data = { 0x5F, 0x54 } },
+ { .data = { 0x60, 0x49 } },
+ { .data = { 0x61, 0x45 } },
+ { .data = { 0x62, 0x38 } },
+ { .data = { 0x63, 0x3D } },
+ { .data = { 0x64, 0x28 } },
+ { .data = { 0x65, 0x43 } },
+ { .data = { 0x66, 0x41 } },
+ { .data = { 0x67, 0x43 } },
+ { .data = { 0x68, 0x62 } },
+ { .data = { 0x69, 0x50 } },
+ { .data = { 0x6A, 0x57 } },
+ { .data = { 0x6B, 0x49 } },
+ { .data = { 0x6C, 0x44 } },
+ { .data = { 0x6D, 0x37 } },
+ { .data = { 0x6E, 0x23 } },
+ { .data = { 0x6F, 0x10 } },
+ { .data = { 0x70, 0x78 } },
+ { .data = { 0x71, 0x63 } },
+ { .data = { 0x72, 0x54 } },
+ { .data = { 0x73, 0x49 } },
+ { .data = { 0x74, 0x45 } },
+ { .data = { 0x75, 0x38 } },
+ { .data = { 0x76, 0x3D } },
+ { .data = { 0x77, 0x28 } },
+ { .data = { 0x78, 0x43 } },
+ { .data = { 0x79, 0x41 } },
+ { .data = { 0x7A, 0x43 } },
+ { .data = { 0x7B, 0x62 } },
+ { .data = { 0x7C, 0x50 } },
+ { .data = { 0x7D, 0x57 } },
+ { .data = { 0x7E, 0x49 } },
+ { .data = { 0x7F, 0x44 } },
+ { .data = { 0x80, 0x37 } },
+ { .data = { 0x81, 0x23 } },
+ { .data = { 0x82, 0x10 } },
+ { .data = { 0xE0, 0x02 } },
+ { .data = { 0x00, 0x47 } },
+ { .data = { 0x01, 0x47 } },
+ { .data = { 0x02, 0x45 } },
+ { .data = { 0x03, 0x45 } },
+ { .data = { 0x04, 0x4B } },
+ { .data = { 0x05, 0x4B } },
+ { .data = { 0x06, 0x49 } },
+ { .data = { 0x07, 0x49 } },
+ { .data = { 0x08, 0x41 } },
+ { .data = { 0x09, 0x1F } },
+ { .data = { 0x0A, 0x1F } },
+ { .data = { 0x0B, 0x1F } },
+ { .data = { 0x0C, 0x1F } },
+ { .data = { 0x0D, 0x1F } },
+ { .data = { 0x0E, 0x1F } },
+ { .data = { 0x0F, 0x5F } },
+ { .data = { 0x10, 0x5F } },
+ { .data = { 0x11, 0x57 } },
+ { .data = { 0x12, 0x77 } },
+ { .data = { 0x13, 0x35 } },
+ { .data = { 0x14, 0x1F } },
+ { .data = { 0x15, 0x1F } },
+ { .data = { 0x16, 0x46 } },
+ { .data = { 0x17, 0x46 } },
+ { .data = { 0x18, 0x44 } },
+ { .data = { 0x19, 0x44 } },
+ { .data = { 0x1A, 0x4A } },
+ { .data = { 0x1B, 0x4A } },
+ { .data = { 0x1C, 0x48 } },
+ { .data = { 0x1D, 0x48 } },
+ { .data = { 0x1E, 0x40 } },
+ { .data = { 0x1F, 0x1F } },
+ { .data = { 0x20, 0x1F } },
+ { .data = { 0x21, 0x1F } },
+ { .data = { 0x22, 0x1F } },
+ { .data = { 0x23, 0x1F } },
+ { .data = { 0x24, 0x1F } },
+ { .data = { 0x25, 0x5F } },
+ { .data = { 0x26, 0x5F } },
+ { .data = { 0x27, 0x57 } },
+ { .data = { 0x28, 0x77 } },
+ { .data = { 0x29, 0x35 } },
+ { .data = { 0x2A, 0x1F } },
+ { .data = { 0x2B, 0x1F } },
+ { .data = { 0x58, 0x40 } },
+ { .data = { 0x59, 0x00 } },
+ { .data = { 0x5A, 0x00 } },
+ { .data = { 0x5B, 0x10 } },
+ { .data = { 0x5C, 0x06 } },
+ { .data = { 0x5D, 0x40 } },
+ { .data = { 0x5E, 0x01 } },
+ { .data = { 0x5F, 0x02 } },
+ { .data = { 0x60, 0x30 } },
+ { .data = { 0x61, 0x01 } },
+ { .data = { 0x62, 0x02 } },
+ { .data = { 0x63, 0x03 } },
+ { .data = { 0x64, 0x6B } },
+ { .data = { 0x65, 0x05 } },
+ { .data = { 0x66, 0x0C } },
+ { .data = { 0x67, 0x73 } },
+ { .data = { 0x68, 0x09 } },
+ { .data = { 0x69, 0x03 } },
+ { .data = { 0x6A, 0x56 } },
+ { .data = { 0x6B, 0x08 } },
+ { .data = { 0x6C, 0x00 } },
+ { .data = { 0x6D, 0x04 } },
+ { .data = { 0x6E, 0x04 } },
+ { .data = { 0x6F, 0x88 } },
+ { .data = { 0x70, 0x00 } },
+ { .data = { 0x71, 0x00 } },
+ { .data = { 0x72, 0x06 } },
+ { .data = { 0x73, 0x7B } },
+ { .data = { 0x74, 0x00 } },
+ { .data = { 0x75, 0xF8 } },
+ { .data = { 0x76, 0x00 } },
+ { .data = { 0x77, 0xD5 } },
+ { .data = { 0x78, 0x2E } },
+ { .data = { 0x79, 0x12 } },
+ { .data = { 0x7A, 0x03 } },
+ { .data = { 0x7B, 0x00 } },
+ { .data = { 0x7C, 0x00 } },
+ { .data = { 0x7D, 0x03 } },
+ { .data = { 0x7E, 0x7B } },
+ { .data = { 0xE0, 0x04 } },
+ { .data = { 0x00, 0x0E } },
+ { .data = { 0x02, 0xB3 } },
+ { .data = { 0x09, 0x60 } },
+ { .data = { 0x0E, 0x2A } },
+ { .data = { 0x36, 0x59 } },
+ { .data = { 0xE0, 0x00 } },
+};
+
+static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = {
+ .mode = {
+ .clock = 70000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 40,
+ .hsync_end = 800 + 40 + 18,
+ .htotal = 800 + 40 + 18 + 20,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 20,
+ .vsync_end = 1280 + 20 + 4,
+ .vtotal = 1280 + 20 + 4 + 20,
+
+ .width_mm = 127,
+ .height_mm = 199,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init_cmds = radxa_display_8hd_ad002_init_cmds,
+ .num_init_cmds = ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds),
+};
+
static const struct jadard_init_cmd cz101b4001_init_cmds[] = {
{ .data = { 0xE0, 0x00 } },
{ .data = { 0xE1, 0x93 } },
@@ -452,7 +648,18 @@ static void jadard_dsi_remove(struct mipi_dsi_device *dsi)
}
static const struct of_device_id jadard_of_match[] = {
- { .compatible = "chongzhou,cz101b4001", .data = &cz101b4001_desc },
+ {
+ .compatible = "chongzhou,cz101b4001",
+ .data = &cz101b4001_desc
+ },
+ {
+ .compatible = "radxa,display-10hd-ad001",
+ .data = &cz101b4001_desc
+ },
+ {
+ .compatible = "radxa,display-8hd-ad002",
+ .data = &radxa_display_8hd_ad002_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
diff --git a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
new file mode 100644
index 000000000000..26d358b9b85a
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Magnachip d53e6ea8966 MIPI-DSI panel driver
+ * Copyright (C) 2023 Chris Morgan
+ */
+
+#include <drm/drm_mipi_dbi.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/media-bus-format.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+
+#include <video/mipi_display.h>
+
+/* Forward declaration for use in backlight function */
+struct d53e6ea8966;
+
+/* Panel info, unique to each panel */
+struct d53e6ea8966_panel_info {
+ /** @display_modes: the supported display modes */
+ const struct drm_display_mode *display_modes;
+ /** @num_modes: the number of supported display modes */
+ unsigned int num_modes;
+ /** @width_mm: panel width in mm */
+ u16 width_mm;
+ /** @height_mm: panel height in mm */
+ u16 height_mm;
+ /** @bus_flags: drm bus flags for panel */
+ u32 bus_flags;
+ /** @panel_init_seq: panel specific init sequence */
+ void (*panel_init_seq)(struct d53e6ea8966 *db);
+ /** @backlight_register: panel backlight registration or NULL */
+ int (*backlight_register)(struct d53e6ea8966 *db);
+};
+
+struct d53e6ea8966 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @reg_vdd: VDD supply regulator for panel logic */
+ struct regulator *reg_vdd;
+ /** @reg_elvdd: ELVDD supply regulator for panel display */
+ struct regulator *reg_elvdd;
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+ /** @panel_info: struct containing panel timing and info */
+ const struct d53e6ea8966_panel_info *panel_info;
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+#define MCS_ELVSS_ON 0xb1
+#define MCS_TEMP_SWIRE 0xb2
+#define MCS_PASSWORD_0 0xf0
+#define MCS_PASSWORD_1 0xf1
+#define MCS_ANALOG_PWR_CTL_0 0xf4
+#define MCS_ANALOG_PWR_CTL_1 0xf5
+#define MCS_GTCON_SET 0xf7
+#define MCS_GATELESS_SIGNAL_SET 0xf8
+#define MCS_SET_GAMMA 0xf9
+
+static inline struct d53e6ea8966 *to_d53e6ea8966(struct drm_panel *panel)
+{
+ return container_of(panel, struct d53e6ea8966, panel);
+}
+
+/* Table of gamma values provided in datasheet */
+static u8 ams495qa01_gamma[NUM_GAMMA_LEVELS][GAMMA_TABLE_COUNT] = {
+ {0x01, 0x79, 0x78, 0x8d, 0xd9, 0xdf, 0xd5, 0xcb, 0xcf, 0xc5,
+ 0xe5, 0xe0, 0xe4, 0xdc, 0xb8, 0xd4, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x7d, 0x7c, 0x92, 0xd7, 0xdd, 0xd2, 0xcb, 0xd0, 0xc6,
+ 0xe5, 0xe1, 0xe3, 0xda, 0xbd, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x7f, 0x7e, 0x95, 0xd7, 0xde, 0xd2, 0xcb, 0xcf, 0xc5,
+ 0xe5, 0xe3, 0xe3, 0xda, 0xbf, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x82, 0x81, 0x99, 0xd6, 0xdd, 0xd1, 0xca, 0xcf, 0xc3,
+ 0xe4, 0xe3, 0xe3, 0xda, 0xc2, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x84, 0x83, 0x9b, 0xd7, 0xde, 0xd2, 0xc8, 0xce, 0xc2,
+ 0xe4, 0xe3, 0xe2, 0xd9, 0xc3, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x87, 0x86, 0x9f, 0xd6, 0xdd, 0xd1, 0xc7, 0xce, 0xc1,
+ 0xe4, 0xe3, 0xe2, 0xd9, 0xc6, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x89, 0x89, 0xa2, 0xd5, 0xdb, 0xcf, 0xc8, 0xcf, 0xc2,
+ 0xe3, 0xe3, 0xe1, 0xd9, 0xc7, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x8b, 0x8b, 0xa5, 0xd5, 0xdb, 0xcf, 0xc7, 0xce, 0xc0,
+ 0xe3, 0xe3, 0xe1, 0xd8, 0xc7, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x8d, 0x8d, 0xa7, 0xd5, 0xdb, 0xcf, 0xc6, 0xce, 0xc0,
+ 0xe4, 0xe4, 0xe1, 0xd7, 0xc8, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x8f, 0x8f, 0xaa, 0xd4, 0xdb, 0xce, 0xc6, 0xcd, 0xbf,
+ 0xe3, 0xe3, 0xe1, 0xd7, 0xca, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x91, 0x91, 0xac, 0xd3, 0xda, 0xce, 0xc5, 0xcd, 0xbe,
+ 0xe3, 0xe3, 0xe0, 0xd7, 0xca, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x93, 0x93, 0xaf, 0xd3, 0xda, 0xcd, 0xc5, 0xcd, 0xbe,
+ 0xe2, 0xe3, 0xdf, 0xd6, 0xca, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x95, 0x95, 0xb1, 0xd2, 0xd9, 0xcc, 0xc4, 0xcd, 0xbe,
+ 0xe2, 0xe3, 0xdf, 0xd7, 0xcc, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x99, 0x99, 0xb6, 0xd1, 0xd9, 0xcc, 0xc3, 0xcb, 0xbc,
+ 0xe2, 0xe4, 0xdf, 0xd6, 0xcc, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x9c, 0x9c, 0xba, 0xd0, 0xd8, 0xcb, 0xc3, 0xcb, 0xbb,
+ 0xe2, 0xe4, 0xdf, 0xd6, 0xce, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+ {0x01, 0x9f, 0x9f, 0xbe, 0xcf, 0xd7, 0xc9, 0xc2, 0xcb, 0xbb,
+ 0xe1, 0xe3, 0xde, 0xd6, 0xd0, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+ 0x00, 0x2f},
+};
+
+/*
+ * Table of elvss values provided in datasheet and corresponds to
+ * gamma values.
+ */
+static u8 ams495qa01_elvss[NUM_GAMMA_LEVELS] = {
+ 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
+ 0x15, 0x15, 0x14, 0x14, 0x13, 0x12,
+};
+
+static int ams495qa01_update_gamma(struct mipi_dbi *dbi, int brightness)
+{
+ int tmp = brightness;
+
+ mipi_dbi_command_buf(dbi, MCS_SET_GAMMA, ams495qa01_gamma[tmp],
+ ARRAY_SIZE(ams495qa01_gamma[tmp]));
+ mipi_dbi_command(dbi, MCS_SET_GAMMA, 0x00);
+
+ /* Undocumented command */
+ mipi_dbi_command(dbi, 0x26, 0x00);
+
+ mipi_dbi_command(dbi, MCS_TEMP_SWIRE, ams495qa01_elvss[tmp]);
+
+ return 0;
+}
+
+static void ams495qa01_panel_init(struct d53e6ea8966 *db)
+{
+ struct mipi_dbi *dbi = &db->dbi;
+
+ mipi_dbi_command(dbi, MCS_PASSWORD_0, 0x5a, 0x5a);
+ mipi_dbi_command(dbi, MCS_PASSWORD_1, 0x5a, 0x5a);
+
+ /* Undocumented commands */
+ mipi_dbi_command(dbi, 0xb0, 0x02);
+ mipi_dbi_command(dbi, 0xf3, 0x3b);
+
+ mipi_dbi_command(dbi, MCS_ANALOG_PWR_CTL_0, 0x33, 0x42, 0x00, 0x08);
+ mipi_dbi_command(dbi, MCS_ANALOG_PWR_CTL_1, 0x00, 0x06, 0x26, 0x35, 0x03);
+
+ /* Undocumented commands */
+ mipi_dbi_command(dbi, 0xf6, 0x02);
+ mipi_dbi_command(dbi, 0xc6, 0x0b, 0x00, 0x00, 0x3c, 0x00, 0x22,
+ 0x00, 0x00, 0x00, 0x00);
+
+ mipi_dbi_command(dbi, MCS_GTCON_SET, 0x20);
+ mipi_dbi_command(dbi, MCS_TEMP_SWIRE, 0x06, 0x06, 0x06, 0x06);
+ mipi_dbi_command(dbi, MCS_ELVSS_ON, 0x07, 0x00, 0x10);
+ mipi_dbi_command(dbi, MCS_GATELESS_SIGNAL_SET, 0x7f, 0x7a,
+ 0x89, 0x67, 0x26, 0x38, 0x00, 0x00, 0x09,
+ 0x67, 0x70, 0x88, 0x7a, 0x76, 0x05, 0x09,
+ 0x23, 0x23, 0x23);
+
+ /* Undocumented commands */
+ mipi_dbi_command(dbi, 0xb5, 0xff, 0xef, 0x35, 0x42, 0x0d, 0xd7,
+ 0xff, 0x07, 0xff, 0xff, 0xfd, 0x00, 0x01,
+ 0xff, 0x05, 0x12, 0x0f, 0xff, 0xff, 0xff,
+ 0xff);
+ mipi_dbi_command(dbi, 0xb4, 0x15);
+ mipi_dbi_command(dbi, 0xb3, 0x00);
+
+ ams495qa01_update_gamma(dbi, MAX_BRIGHTNESS);
+}
+
+static int d53e6ea8966_prepare(struct drm_panel *panel)
+{
+ struct d53e6ea8966 *db = to_d53e6ea8966(panel);
+ int ret;
+
+ /* Power up */
+ ret = regulator_enable(db->reg_vdd);
+ if (ret) {
+ dev_err(db->dev, "failed to enable vdd regulator: %d\n", ret);
+ return ret;
+ }
+
+ if (db->reg_elvdd) {
+ ret = regulator_enable(db->reg_elvdd);
+ if (ret) {
+ dev_err(db->dev,
+ "failed to enable elvdd regulator: %d\n", ret);
+ regulator_disable(db->reg_vdd);
+ return ret;
+ }
+ }
+
+ /* Enable */
+ if (db->enable)
+ gpiod_set_value_cansleep(db->enable, 1);
+
+ msleep(50);
+
+ /* Reset */
+ gpiod_set_value_cansleep(db->reset, 1);
+ usleep_range(1000, 5000);
+ gpiod_set_value_cansleep(db->reset, 0);
+ msleep(20);
+
+ db->panel_info->panel_init_seq(db);
+
+ return 0;
+}
+
+static int d53e6ea8966_enable(struct drm_panel *panel)
+{
+ struct d53e6ea8966 *db = to_d53e6ea8966(panel);
+ struct mipi_dbi *dbi = &db->dbi;
+
+ mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
+ msleep(200);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
+ usleep_range(10000, 15000);
+
+ return 0;
+}
+
+static int d53e6ea8966_disable(struct drm_panel *panel)
+{
+ struct d53e6ea8966 *db = to_d53e6ea8966(panel);
+ struct mipi_dbi *dbi = &db->dbi;
+
+ mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
+ msleep(20);
+ mipi_dbi_command(dbi, MIPI_DCS_ENTER_SLEEP_MODE);
+ msleep(100);
+
+ return 0;
+}
+
+static int d53e6ea8966_unprepare(struct drm_panel *panel)
+{
+ struct d53e6ea8966 *db = to_d53e6ea8966(panel);
+
+ if (db->enable)
+ gpiod_set_value_cansleep(db->enable, 0);
+
+ gpiod_set_value_cansleep(db->reset, 1);
+
+ if (db->reg_elvdd)
+ regulator_disable(db->reg_elvdd);
+
+ regulator_disable(db->reg_vdd);
+ msleep(100);
+
+ return 0;
+}
+
+static int d53e6ea8966_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct d53e6ea8966 *db = to_d53e6ea8966(panel);
+ const struct d53e6ea8966_panel_info *panel_info = db->panel_info;
+ struct drm_display_mode *mode;
+ static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ unsigned int i;
+
+ for (i = 0; i < panel_info->num_modes; i++) {
+ mode = drm_mode_duplicate(connector->dev,
+ &panel_info->display_modes[i]);
+ if (!mode)
+ return -ENOMEM;
+
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
+ }
+
+ connector->display_info.bpc = 8;
+ connector->display_info.width_mm = panel_info->width_mm;
+ connector->display_info.height_mm = panel_info->height_mm;
+ connector->display_info.bus_flags = panel_info->bus_flags;
+
+ drm_display_info_set_bus_formats(&connector->display_info,
+ &bus_format, 1);
+
+ return 1;
+}
+
+static const struct drm_panel_funcs d53e6ea8966_panel_funcs = {
+ .disable = d53e6ea8966_disable,
+ .enable = d53e6ea8966_enable,
+ .get_modes = d53e6ea8966_get_modes,
+ .prepare = d53e6ea8966_prepare,
+ .unprepare = d53e6ea8966_unprepare,
+};
+
+static int ams495qa01_set_brightness(struct backlight_device *bd)
+{
+ struct d53e6ea8966 *db = bl_get_data(bd);
+ struct mipi_dbi *dbi = &db->dbi;
+ int brightness = backlight_get_brightness(bd);
+
+ ams495qa01_update_gamma(dbi, brightness);
+
+ return 0;
+}
+
+static const struct backlight_ops ams495qa01_backlight_ops = {
+ .update_status = ams495qa01_set_brightness,
+};
+
+static int ams495qa01_backlight_register(struct d53e6ea8966 *db)
+{
+ struct backlight_properties props = {
+ .type = BACKLIGHT_RAW,
+ .brightness = MAX_BRIGHTNESS,
+ .max_brightness = MAX_BRIGHTNESS,
+ };
+ struct device *dev = db->dev;
+ int ret = 0;
+
+ db->bl_dev = devm_backlight_device_register(dev, "panel", dev, db,
+ &ams495qa01_backlight_ops,
+ &props);
+ if (IS_ERR(db->bl_dev)) {
+ ret = PTR_ERR(db->bl_dev);
+ dev_err(dev, "error registering backlight device (%d)\n", ret);
+ }
+
+ return ret;
+}
+
+static int d53e6ea8966_probe(struct spi_device *spi)
+{
+ struct device *dev = &spi->dev;
+ struct mipi_dsi_host *dsi_host;
+ struct d53e6ea8966 *db;
+ int ret;
+ struct mipi_dsi_device_info info = {
+ .type = "d53e6ea8966",
+ .channel = 0,
+ .node = NULL,
+ };
+
+ db = devm_kzalloc(dev, sizeof(*db), GFP_KERNEL);
+ if (!db)
+ return -ENOMEM;
+
+ spi_set_drvdata(spi, db);
+
+ db->dev = dev;
+
+ db->panel_info = of_device_get_match_data(dev);
+ if (!db->panel_info)
+ return -EINVAL;
+
+ db->reg_vdd = devm_regulator_get(dev, "vdd");
+ if (IS_ERR(db->reg_vdd))
+ return dev_err_probe(dev, PTR_ERR(db->reg_vdd),
+ "Failed to get vdd supply\n");
+
+ db->reg_elvdd = devm_regulator_get_optional(dev, "elvdd");
+ if (IS_ERR(db->reg_elvdd))
+ db->reg_elvdd = NULL;
+
+ db->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(db->reset)) {
+ ret = PTR_ERR(db->reset);
+ return dev_err_probe(dev, ret, "no RESET GPIO\n");
+ }
+
+ db->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
+ if (IS_ERR(db->enable)) {
+ ret = PTR_ERR(db->enable);
+ return dev_err_probe(dev, ret, "cannot get ENABLE GPIO\n");
+ }
+
+ ret = mipi_dbi_spi_init(spi, &db->dbi, NULL);
+ if (ret)
+ return dev_err_probe(dev, ret, "MIPI DBI init failed\n");
+
+ dsi_host = drm_of_get_dsi_bus(dev);
+ if (IS_ERR(dsi_host)) {
+ ret = PTR_ERR(dsi_host);
+ return dev_err_probe(dev, ret, "Error attaching DSI bus\n");
+ }
+
+ db->dsi_dev = devm_mipi_dsi_device_register_full(dev, dsi_host, &info);
+ if (IS_ERR(db->dsi_dev)) {
+ dev_err(dev, "failed to register dsi device: %ld\n",
+ PTR_ERR(db->dsi_dev));
+ return PTR_ERR(db->dsi_dev);
+ }
+
+ db->dsi_dev->lanes = 2;
+ db->dsi_dev->format = MIPI_DSI_FMT_RGB888;
+ db->dsi_dev->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET;
+
+ drm_panel_init(&db->panel, dev, &d53e6ea8966_panel_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+
+ if (db->panel_info->backlight_register) {
+ ret = db->panel_info->backlight_register(db);
+ if (ret < 0)
+ return ret;
+ db->panel.backlight = db->bl_dev;
+ }
+
+ drm_panel_add(&db->panel);
+
+ ret = devm_mipi_dsi_attach(dev, db->dsi_dev);
+ if (ret < 0) {
+ dev_err(dev, "mipi_dsi_attach failed: %d\n", ret);
+ drm_panel_remove(&db->panel);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void d53e6ea8966_remove(struct spi_device *spi)
+{
+ struct d53e6ea8966 *db = spi_get_drvdata(spi);
+
+ drm_panel_remove(&db->panel);
+}
+
+static const struct drm_display_mode ams495qa01_modes[] = {
+ { /* 60hz */
+ .clock = 33500,
+ .hdisplay = 960,
+ .hsync_start = 960 + 10,
+ .hsync_end = 960 + 10 + 2,
+ .htotal = 960 + 10 + 2 + 10,
+ .vdisplay = 544,
+ .vsync_start = 544 + 10,
+ .vsync_end = 544 + 10 + 2,
+ .vtotal = 544 + 10 + 2 + 10,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ { /* 50hz */
+ .clock = 27800,
+ .hdisplay = 960,
+ .hsync_start = 960 + 10,
+ .hsync_end = 960 + 10 + 2,
+ .htotal = 960 + 10 + 2 + 10,
+ .vdisplay = 544,
+ .vsync_start = 544 + 10,
+ .vsync_end = 544 + 10 + 2,
+ .vtotal = 544 + 10 + 2 + 10,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .type = DRM_MODE_TYPE_DRIVER,
+ },
+};
+
+static const struct d53e6ea8966_panel_info ams495qa01_info = {
+ .display_modes = ams495qa01_modes,
+ .num_modes = ARRAY_SIZE(ams495qa01_modes),
+ .width_mm = 117,
+ .height_mm = 74,
+ .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+ .panel_init_seq = ams495qa01_panel_init,
+ .backlight_register = ams495qa01_backlight_register,
+};
+
+static const struct of_device_id d53e6ea8966_match[] = {
+ { .compatible = "samsung,ams495qa01", .data = &ams495qa01_info },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, d53e6ea8966_match);
+
+static const struct spi_device_id d53e6ea8966_ids[] = {
+ { "ams495qa01", 0 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(spi, d53e6ea8966_ids);
+
+static struct spi_driver d53e6ea8966_driver = {
+ .driver = {
+ .name = "d53e6ea8966-panel",
+ .of_match_table = d53e6ea8966_match,
+ },
+ .id_table = d53e6ea8966_ids,
+ .probe = d53e6ea8966_probe,
+ .remove = d53e6ea8966_remove,
+};
+module_spi_driver(d53e6ea8966_driver);
+
+MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>");
+MODULE_DESCRIPTION("Magnachip d53e6ea8966 panel driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35950.c b/drivers/gpu/drm/panel/panel-novatek-nt35950.c
index abf752b36a52..8b108ac80b55 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt35950.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt35950.c
@@ -585,8 +585,12 @@ static int nt35950_probe(struct mipi_dsi_device *dsi)
DRM_MODE_CONNECTOR_DSI);
ret = drm_panel_of_backlight(&nt->panel);
- if (ret)
+ if (ret) {
+ if (num_dsis == 2)
+ mipi_dsi_device_unregister(nt->dsi[1]);
+
return dev_err_probe(dev, ret, "Failed to get backlight\n");
+ }
drm_panel_add(&nt->panel);
@@ -602,6 +606,10 @@ static int nt35950_probe(struct mipi_dsi_device *dsi)
ret = mipi_dsi_attach(nt->dsi[i]);
if (ret < 0) {
+ /* If we fail to attach to either host, we're done */
+ if (num_dsis == 2)
+ mipi_dsi_device_unregister(nt->dsi[1]);
+
return dev_err_probe(dev, ret,
"Cannot attach to DSI%d host.\n", i);
}
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36523.c b/drivers/gpu/drm/panel/panel-novatek-nt36523.c
new file mode 100644
index 000000000000..d30dbbfb67b1
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-novatek-nt36523.c
@@ -0,0 +1,777 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Novatek NT36523 DriverIC panels driver
+ *
+ * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+#define DSI_NUM_MIN 1
+
+#define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...) \
+ do { \
+ mipi_dsi_dcs_write_seq(dsi0, cmd, seq); \
+ mipi_dsi_dcs_write_seq(dsi1, cmd, seq); \
+ } while (0)
+
+struct panel_info {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi[2];
+ const struct panel_desc *desc;
+
+ struct gpio_desc *reset_gpio;
+ struct backlight_device *backlight;
+ struct regulator *vddio;
+
+ bool prepared;
+};
+
+struct panel_desc {
+ unsigned int width_mm;
+ unsigned int height_mm;
+
+ unsigned int bpc;
+ unsigned int lanes;
+ unsigned long mode_flags;
+ enum mipi_dsi_pixel_format format;
+
+ const struct drm_display_mode *modes;
+ unsigned int num_modes;
+ const struct mipi_dsi_device_info dsi_info;
+ int (*init_sequence)(struct panel_info *pinfo);
+
+ bool is_dual_dsi;
+};
+
+static inline struct panel_info *to_panel_info(struct drm_panel *panel)
+{
+ return container_of(panel, struct panel_info, panel);
+}
+
+static int elish_boe_init_sequence(struct panel_info *pinfo)
+{
+ struct mipi_dsi_device *dsi0 = pinfo->dsi[0];
+ struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
+ /* No datasheet, so write magic init sequence directly */
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2d);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xfe);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xfd);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xfb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xf8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xf5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xf3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0xef);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0xec);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3d, 0xe9);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3f, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x13);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xf4);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xe7);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xda);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xcd);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4a, 0xc0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4b, 0xb3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4c, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4d, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4e, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x99);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0x0e);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xfb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5a, 0xf7);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5b, 0xf3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5c, 0xef);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5d, 0xe3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5e, 0xda);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5f, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xcb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xbf);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xb3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x47);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x47);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x47);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1a, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb0, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x1b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x24);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x27);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x31);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd1, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd2, 0x30);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xde, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdf, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9f, 0x50);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6f, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x76, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x77, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa0, 0x3f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa9, 0x50);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xaa, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xab, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xad, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xba, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbe, 0x04);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbf, 0x49);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc0, 0x04);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc1, 0x59);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc2, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc5, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc6, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc7, 0x48);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xca, 0x43);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcb, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xce, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcf, 0x43);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd3, 0x43);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd7, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdc, 0x43);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdd, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xe1, 0x43);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xe2, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf2, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf3, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xf4, 0x48);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x13, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x23);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbc, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbd, 0x23);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x97, 0x3c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x98, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x99, 0x95);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9a, 0x03);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9b, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9c, 0x0b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9d, 0x0a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9e, 0x90);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9f, 0x50);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa3, 0x50);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x60);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0xc0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xd0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xaf);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xee);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x99);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1d, 0x09);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0f, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x13);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11);
+ msleep(70);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29);
+
+ return 0;
+}
+
+static int elish_csot_init_sequence(struct panel_info *pinfo)
+{
+ struct mipi_dsi_device *dsi0 = pinfo->dsi[0];
+ struct mipi_dsi_device *dsi1 = pinfo->dsi[1];
+ /* No datasheet, so write magic init sequence directly */
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xd0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xaf);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x30);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xee);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x99);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1d, 0x09);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x23);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2d);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xfe);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xfd);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xfb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xf8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xf5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xf3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xf2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3a, 0xef);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0xec);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3d, 0xe9);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3f, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xe5);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x13);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xf4);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xe7);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xda);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xcd);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4a, 0xc0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4b, 0xb3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4c, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4d, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4e, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4f, 0x99);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0x0e);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xfb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5a, 0xf7);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5b, 0xf3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5c, 0xef);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5d, 0xe3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5e, 0xda);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5f, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xd8);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xcb);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xbf);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xb3);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xb2);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0f, 0xff);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x55, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x13);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3b, 0x03, 0xac, 0x1a, 0x04, 0x04);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x46);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x46);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x46);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1a, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1c, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2a, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2b, 0xe0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0xf0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb0, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1b, 0x1b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x24);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x27);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x31);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd1, 0x20);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xde, 0x80);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xdf, 0x02);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x26);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xb0);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x22);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6f, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x4d);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa0, 0x3f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xa9, 0x50);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xaa, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xab, 0x28);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xad, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb8, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x4b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xba, 0x96);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbb, 0x4b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbe, 0x07);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbf, 0x4b);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc0, 0x07);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc1, 0x5c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc2, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc5, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc6, 0x3f);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xc7, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xca, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcb, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xce, 0x00);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xcf, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd0, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd3, 0x08);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xd4, 0x40);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x25);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbc, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xbd, 0x1c);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x2a);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9a, 0x03);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11);
+ msleep(70);
+ mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29);
+
+ return 0;
+}
+
+static const struct drm_display_mode elish_boe_modes[] = {
+ {
+ /* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz preferred */
+ .clock = (1600 + 60 + 8 + 60) * (2560 + 26 + 4 + 168) * 104 / 1000,
+ .hdisplay = 1600,
+ .hsync_start = 1600 + 60,
+ .hsync_end = 1600 + 60 + 8,
+ .htotal = 1600 + 60 + 8 + 60,
+ .vdisplay = 2560,
+ .vsync_start = 2560 + 26,
+ .vsync_end = 2560 + 26 + 4,
+ .vtotal = 2560 + 26 + 4 + 168,
+ },
+};
+
+static const struct drm_display_mode elish_csot_modes[] = {
+ {
+ /* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz preferred */
+ .clock = (1600 + 200 + 40 + 52) * (2560 + 26 + 4 + 168) * 104 / 1000,
+ .hdisplay = 1600,
+ .hsync_start = 1600 + 200,
+ .hsync_end = 1600 + 200 + 40,
+ .htotal = 1600 + 200 + 40 + 52,
+ .vdisplay = 2560,
+ .vsync_start = 2560 + 26,
+ .vsync_end = 2560 + 26 + 4,
+ .vtotal = 2560 + 26 + 4 + 168,
+ },
+};
+
+static const struct panel_desc elish_boe_desc = {
+ .modes = elish_boe_modes,
+ .num_modes = ARRAY_SIZE(elish_boe_modes),
+ .dsi_info = {
+ .type = "BOE-elish",
+ .channel = 0,
+ .node = NULL,
+ },
+ .width_mm = 127,
+ .height_mm = 203,
+ .bpc = 8,
+ .lanes = 3,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
+ .init_sequence = elish_boe_init_sequence,
+ .is_dual_dsi = true,
+};
+
+static const struct panel_desc elish_csot_desc = {
+ .modes = elish_csot_modes,
+ .num_modes = ARRAY_SIZE(elish_csot_modes),
+ .dsi_info = {
+ .type = "CSOT-elish",
+ .channel = 0,
+ .node = NULL,
+ },
+ .width_mm = 127,
+ .height_mm = 203,
+ .bpc = 8,
+ .lanes = 3,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM,
+ .init_sequence = elish_csot_init_sequence,
+ .is_dual_dsi = true,
+};
+
+static void nt36523_reset(struct panel_info *pinfo)
+{
+ gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
+ usleep_range(12000, 13000);
+ gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
+ usleep_range(12000, 13000);
+ gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
+ usleep_range(12000, 13000);
+ gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
+ usleep_range(12000, 13000);
+}
+
+static int nt36523_prepare(struct drm_panel *panel)
+{
+ struct panel_info *pinfo = to_panel_info(panel);
+ int ret;
+
+ if (pinfo->prepared)
+ return 0;
+
+ ret = regulator_enable(pinfo->vddio);
+ if (ret) {
+ dev_err(panel->dev, "failed to enable vddio regulator: %d\n", ret);
+ return ret;
+ }
+
+ nt36523_reset(pinfo);
+
+ ret = pinfo->desc->init_sequence(pinfo);
+ if (ret < 0) {
+ regulator_disable(pinfo->vddio);
+ dev_err(panel->dev, "failed to initialize panel: %d\n", ret);
+ return ret;
+ }
+
+ pinfo->prepared = true;
+
+ return 0;
+}
+
+static int nt36523_disable(struct drm_panel *panel)
+{
+ struct panel_info *pinfo = to_panel_info(panel);
+ int i, ret;
+
+ for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
+ ret = mipi_dsi_dcs_set_display_off(pinfo->dsi[i]);
+ if (ret < 0)
+ dev_err(&pinfo->dsi[i]->dev, "failed to set display off: %d\n", ret);
+ }
+
+ for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
+ ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->dsi[i]);
+ if (ret < 0)
+ dev_err(&pinfo->dsi[i]->dev, "failed to enter sleep mode: %d\n", ret);
+ }
+
+ msleep(70);
+
+ return 0;
+}
+
+static int nt36523_unprepare(struct drm_panel *panel)
+{
+ struct panel_info *pinfo = to_panel_info(panel);
+
+ if (!pinfo->prepared)
+ return 0;
+
+ gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
+ regulator_disable(pinfo->vddio);
+
+ pinfo->prepared = false;
+
+ return 0;
+}
+
+static void nt36523_remove(struct mipi_dsi_device *dsi)
+{
+ struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi);
+ int ret;
+
+ ret = mipi_dsi_detach(pinfo->dsi[0]);
+ if (ret < 0)
+ dev_err(&dsi->dev, "failed to detach from DSI0 host: %d\n", ret);
+
+ if (pinfo->desc->is_dual_dsi) {
+ ret = mipi_dsi_detach(pinfo->dsi[1]);
+ if (ret < 0)
+ dev_err(&pinfo->dsi[1]->dev, "failed to detach from DSI1 host: %d\n", ret);
+ mipi_dsi_device_unregister(pinfo->dsi[1]);
+ }
+
+ drm_panel_remove(&pinfo->panel);
+}
+
+static int nt36523_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct panel_info *pinfo = to_panel_info(panel);
+ int i;
+
+ for (i = 0; i < pinfo->desc->num_modes; i++) {
+ const struct drm_display_mode *m = &pinfo->desc->modes[i];
+ struct drm_display_mode *mode;
+
+ mode = drm_mode_duplicate(connector->dev, m);
+ if (!mode) {
+ dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+ m->hdisplay, m->vdisplay, drm_mode_vrefresh(m));
+ return -ENOMEM;
+ }
+
+ mode->type = DRM_MODE_TYPE_DRIVER;
+ if (i == 0)
+ mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
+ }
+
+ connector->display_info.width_mm = pinfo->desc->width_mm;
+ connector->display_info.height_mm = pinfo->desc->height_mm;
+ connector->display_info.bpc = pinfo->desc->bpc;
+
+ return pinfo->desc->num_modes;
+}
+
+static const struct drm_panel_funcs nt36523_panel_funcs = {
+ .disable = nt36523_disable,
+ .prepare = nt36523_prepare,
+ .unprepare = nt36523_unprepare,
+ .get_modes = nt36523_get_modes,
+};
+
+static int nt36523_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct device_node *dsi1;
+ struct mipi_dsi_host *dsi1_host;
+ struct panel_info *pinfo;
+ const struct mipi_dsi_device_info *info;
+ int i, ret;
+
+ pinfo = devm_kzalloc(dev, sizeof(*pinfo), GFP_KERNEL);
+ if (!pinfo)
+ return -ENOMEM;
+
+ pinfo->vddio = devm_regulator_get(dev, "vddio");
+ if (IS_ERR(pinfo->vddio))
+ return dev_err_probe(dev, PTR_ERR(pinfo->vddio), "failed to get vddio regulator\n");
+
+ pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(pinfo->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio), "failed to get reset gpio\n");
+
+ pinfo->desc = of_device_get_match_data(dev);
+ if (!pinfo->desc)
+ return -ENODEV;
+
+ /* If the panel is dual dsi, register DSI1 */
+ if (pinfo->desc->is_dual_dsi) {
+ info = &pinfo->desc->dsi_info;
+
+ dsi1 = of_graph_get_remote_node(dsi->dev.of_node, 1, -1);
+ if (!dsi1) {
+ dev_err(dev, "cannot get secondary DSI node.\n");
+ return -ENODEV;
+ }
+
+ dsi1_host = of_find_mipi_dsi_host_by_node(dsi1);
+ of_node_put(dsi1);
+ if (!dsi1_host)
+ return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n");
+
+ pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info);
+ if (!pinfo->dsi[1]) {
+ dev_err(dev, "cannot get secondary DSI device\n");
+ return -ENODEV;
+ }
+ }
+
+ pinfo->dsi[0] = dsi;
+ mipi_dsi_set_drvdata(dsi, pinfo);
+ drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI);
+
+ ret = drm_panel_of_backlight(&pinfo->panel);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get backlight\n");
+
+ drm_panel_add(&pinfo->panel);
+
+ for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) {
+ pinfo->dsi[i]->lanes = pinfo->desc->lanes;
+ pinfo->dsi[i]->format = pinfo->desc->format;
+ pinfo->dsi[i]->mode_flags = pinfo->desc->mode_flags;
+
+ ret = mipi_dsi_attach(pinfo->dsi[i]);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "cannot attach to DSI%d host.\n", i);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id nt36523_of_match[] = {
+ {
+ .compatible = "xiaomi,elish-boe-nt36523",
+ .data = &elish_boe_desc,
+ },
+ {
+ .compatible = "xiaomi,elish-csot-nt36523",
+ .data = &elish_csot_desc,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, nt36523_of_match);
+
+static struct mipi_dsi_driver nt36523_driver = {
+ .probe = nt36523_probe,
+ .remove = nt36523_remove,
+ .driver = {
+ .name = "panel-novatek-nt36523",
+ .of_match_table = nt36523_of_match,
+ },
+};
+module_mipi_dsi_driver(nt36523_driver);
+
+MODULE_AUTHOR("Jianhua Lu <lujianhua000@gmail.com>");
+MODULE_DESCRIPTION("DRM driver for Novatek NT36523 based MIPI DSI panels");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index b4729a94c34a..898b892f1143 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -471,7 +471,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
DRM_MODE_CONNECTOR_DSI);
ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev),
- dsi->host->dev, ctx,
+ dev, ctx,
&otm8009a_backlight_ops,
NULL);
if (IS_ERR(ctx->bl_dev)) {
diff --git a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
index 76160e5d43bd..c250ca36a5b3 100644
--- a/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
+++ b/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c
@@ -7,6 +7,7 @@
*/
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -48,6 +49,7 @@ struct seiko_panel {
const struct seiko_panel_desc *desc;
struct regulator *dvdd;
struct regulator *avdd;
+ struct gpio_desc *enable_gpio;
};
static inline struct seiko_panel *to_seiko_panel(struct drm_panel *panel)
@@ -139,6 +141,8 @@ static int seiko_panel_unprepare(struct drm_panel *panel)
if (!p->prepared)
return 0;
+ gpiod_set_value_cansleep(p->enable_gpio, 0);
+
regulator_disable(p->avdd);
/* Add a 100ms delay as per the panel datasheet */
@@ -174,6 +178,8 @@ static int seiko_panel_prepare(struct drm_panel *panel)
goto disable_dvdd;
}
+ gpiod_set_value_cansleep(p->enable_gpio, 1);
+
p->prepared = true;
return 0;
@@ -252,6 +258,12 @@ static int seiko_panel_probe(struct device *dev,
if (IS_ERR(panel->avdd))
return PTR_ERR(panel->avdd);
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(panel->enable_gpio))
+ return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
+ "failed to request GPIO\n");
+
drm_panel_init(&panel->base, dev, &seiko_panel_funcs,
DRM_MODE_CONNECTOR_DPI);
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 0b8cf65172ff..7eae83aa0ea1 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -135,6 +135,7 @@ struct st7701 {
struct regulator_bulk_data supplies[2];
struct gpio_desc *reset;
unsigned int sleep_delay;
+ enum drm_panel_orientation orientation;
};
static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
@@ -397,6 +398,31 @@ static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701)
ST7701_DSI(st7701, 0x3A, 0x70);
}
+static void kd50t048a_gip_sequence(struct st7701 *st7701)
+{
+ /**
+ * ST7701_SPEC_V1.2 is unable to provide enough information above this
+ * specific command sequence, so grab the same from vendor BSP driver.
+ */
+ ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
+ ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
+ 0x00, 0x00, 0x33, 0x33);
+ ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+ ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
+ ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
+ ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
+ 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);
+ ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
+ ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
+ ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
+ 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);
+ ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
+ ST7701_DSI(st7701, 0xEC, 0x02, 0x01);
+ ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);
+}
+
static int st7701_prepare(struct drm_panel *panel)
{
struct st7701 *st7701 = panel_to_st7701(panel);
@@ -489,15 +515,29 @@ static int st7701_get_modes(struct drm_panel *panel,
connector->display_info.width_mm = desc_mode->width_mm;
connector->display_info.height_mm = desc_mode->height_mm;
+ /*
+ * TODO: Remove once all drm drivers call
+ * drm_connector_set_orientation_from_panel()
+ */
+ drm_connector_set_panel_orientation(connector, st7701->orientation);
+
return 1;
}
+static enum drm_panel_orientation st7701_get_orientation(struct drm_panel *panel)
+{
+ struct st7701 *st7701 = panel_to_st7701(panel);
+
+ return st7701->orientation;
+}
+
static const struct drm_panel_funcs st7701_funcs = {
.disable = st7701_disable,
.unprepare = st7701_unprepare,
.prepare = st7701_prepare,
.enable = st7701_enable,
.get_modes = st7701_get_modes,
+ .get_orientation = st7701_get_orientation,
};
static const struct drm_display_mode ts8550b_mode = {
@@ -700,6 +740,105 @@ static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = {
.gip_sequence = dmt028vghmcmi_1a_gip_sequence,
};
+static const struct drm_display_mode kd50t048a_mode = {
+ .clock = 27500,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 2,
+ .hsync_end = 480 + 2 + 10,
+ .htotal = 480 + 2 + 10 + 2,
+
+ .vdisplay = 854,
+ .vsync_start = 854 + 2,
+ .vsync_end = 854 + 2 + 2,
+ .vtotal = 854 + 2 + 2 + 17,
+
+ .width_mm = 69,
+ .height_mm = 139,
+
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct st7701_panel_desc kd50t048a_desc = {
+ .mode = &kd50t048a_mode,
+ .lanes = 2,
+ .format = MIPI_DSI_FMT_RGB888,
+ .panel_sleep_delay = 0,
+
+ .pv_gamma = {
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
+ },
+ .nv_gamma = {
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
+
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
+ },
+ .nlinv = 1,
+ .vop_uv = 4887500,
+ .vcom_uv = 937500,
+ .vgh_mv = 15000,
+ .vgl_mv = -9510,
+ .avdd_mv = 6600,
+ .avcl_mv = -4400,
+ .gamma_op_bias = OP_BIAS_MIDDLE,
+ .input_op_bias = OP_BIAS_MIN,
+ .output_op_bias = OP_BIAS_MIN,
+ .t2d_ns = 1600,
+ .t3d_ns = 10400,
+ .eot_en = true,
+ .gip_sequence = kd50t048a_gip_sequence,
+};
+
static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
{
const struct st7701_panel_desc *desc;
@@ -730,6 +869,10 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
return PTR_ERR(st7701->reset);
}
+ ret = of_drm_get_panel_orientation(dsi->dev.of_node, &st7701->orientation);
+ if (ret < 0)
+ return dev_err_probe(&dsi->dev, ret, "Failed to get orientation\n");
+
drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
DRM_MODE_CONNECTOR_DSI);
@@ -775,6 +918,7 @@ static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
static const struct of_device_id st7701_of_match[] = {
{ .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },
+ { .compatible = "elida,kd50t048a", .data = &kd50t048a_desc },
{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
{ }
};
diff --git a/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c b/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c
new file mode 100644
index 000000000000..8d8813dbaa45
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-sony-td4353-jdi.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Konrad Dybcio <konrad.dybcio@somainline.org>
+ *
+ * Generated with linux-mdss-dsi-panel-driver-generator with a
+ * substantial amount of manual adjustments.
+ *
+ * SONY Downstream kernel calls this one:
+ * - "JDI ID3" for Akari (XZ2)
+ * - "JDI ID4" for Apollo (XZ2 Compact)
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+enum {
+ TYPE_TAMA_60HZ,
+ /*
+ * Leaving room for expansion - SONY very often uses
+ * *truly reliably* overclockable panels on their flagships!
+ */
+};
+
+struct sony_td4353_jdi {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct regulator_bulk_data supplies[3];
+ struct gpio_desc *panel_reset_gpio;
+ struct gpio_desc *touch_reset_gpio;
+ bool prepared;
+ int type;
+};
+
+static inline struct sony_td4353_jdi *to_sony_td4353_jdi(struct drm_panel *panel)
+{
+ return container_of(panel, struct sony_td4353_jdi, panel);
+}
+
+static int sony_td4353_jdi_on(struct sony_td4353_jdi *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = &dsi->dev;
+ int ret;
+
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+ ret = mipi_dsi_dcs_set_column_address(dsi, 0x0000, 1080 - 1);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set column address: %d\n", ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_page_address(dsi, 0x0000, 2160 - 1);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set page address: %d\n", ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set tear scanline: %d\n", ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set tear on: %d\n", ret);
+ return ret;
+ }
+
+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
+
+ ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set pixel format: %d\n", ret);
+ return ret;
+ }
+
+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS,
+ 0x00, 0x00, 0x08, 0x6f);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
+ return ret;
+ }
+ msleep(70);
+
+ mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START);
+
+ ret = mipi_dsi_dcs_set_display_on(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to turn display on: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int sony_td4353_jdi_off(struct sony_td4353_jdi *ctx)
+{
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct device *dev = &dsi->dev;
+ int ret;
+
+ dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+ ret = mipi_dsi_dcs_set_display_off(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set display off: %d\n", ret);
+ return ret;
+ }
+ msleep(22);
+
+ ret = mipi_dsi_dcs_set_tear_off(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set tear off: %d\n", ret);
+ return ret;
+ }
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
+ return ret;
+ }
+ msleep(80);
+
+ return 0;
+}
+
+static void sony_td4353_assert_reset_gpios(struct sony_td4353_jdi *ctx, int mode)
+{
+ gpiod_set_value_cansleep(ctx->touch_reset_gpio, mode);
+ gpiod_set_value_cansleep(ctx->panel_reset_gpio, mode);
+ usleep_range(5000, 5100);
+}
+
+static int sony_td4353_jdi_prepare(struct drm_panel *panel)
+{
+ struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ if (ctx->prepared)
+ return 0;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
+ msleep(100);
+
+ sony_td4353_assert_reset_gpios(ctx, 1);
+
+ ret = sony_td4353_jdi_on(ctx);
+ if (ret < 0) {
+ dev_err(dev, "Failed to power on panel: %d\n", ret);
+ sony_td4353_assert_reset_gpios(ctx, 0);
+ regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+ return ret;
+ }
+
+ ctx->prepared = true;
+ return 0;
+}
+
+static int sony_td4353_jdi_unprepare(struct drm_panel *panel)
+{
+ struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ if (!ctx->prepared)
+ return 0;
+
+ ret = sony_td4353_jdi_off(ctx);
+ if (ret < 0)
+ dev_err(dev, "Failed to power off panel: %d\n", ret);
+
+ sony_td4353_assert_reset_gpios(ctx, 0);
+ regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+
+ ctx->prepared = false;
+ return 0;
+}
+
+static const struct drm_display_mode sony_td4353_jdi_mode_tama_60hz = {
+ .clock = (1080 + 4 + 8 + 8) * (2160 + 259 + 8 + 8) * 60 / 1000,
+ .hdisplay = 1080,
+ .hsync_start = 1080 + 4,
+ .hsync_end = 1080 + 4 + 8,
+ .htotal = 1080 + 4 + 8 + 8,
+ .vdisplay = 2160,
+ .vsync_start = 2160 + 259,
+ .vsync_end = 2160 + 259 + 8,
+ .vtotal = 2160 + 259 + 8 + 8,
+ .width_mm = 64,
+ .height_mm = 128,
+};
+
+static int sony_td4353_jdi_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct sony_td4353_jdi *ctx = to_sony_td4353_jdi(panel);
+ struct drm_display_mode *mode = NULL;
+
+ if (ctx->type == TYPE_TAMA_60HZ)
+ mode = drm_mode_duplicate(connector->dev, &sony_td4353_jdi_mode_tama_60hz);
+ else
+ return -EINVAL;
+
+ if (!mode)
+ return -ENOMEM;
+
+ drm_mode_set_name(mode);
+
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+ drm_mode_probed_add(connector, mode);
+
+ return 1;
+}
+
+static const struct drm_panel_funcs sony_td4353_jdi_panel_funcs = {
+ .prepare = sony_td4353_jdi_prepare,
+ .unprepare = sony_td4353_jdi_unprepare,
+ .get_modes = sony_td4353_jdi_get_modes,
+};
+
+static int sony_td4353_jdi_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct sony_td4353_jdi *ctx;
+ int ret;
+
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->type = (uintptr_t)of_device_get_match_data(dev);
+
+ ctx->supplies[0].supply = "vddio";
+ ctx->supplies[1].supply = "vsp";
+ ctx->supplies[2].supply = "vsn";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
+ ctx->supplies);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to get regulators\n");
+
+ ctx->panel_reset_gpio = devm_gpiod_get(dev, "panel-reset", GPIOD_ASIS);
+ if (IS_ERR(ctx->panel_reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(ctx->panel_reset_gpio),
+ "Failed to get panel-reset-gpios\n");
+
+ ctx->touch_reset_gpio = devm_gpiod_get(dev, "touch-reset", GPIOD_ASIS);
+ if (IS_ERR(ctx->touch_reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(ctx->touch_reset_gpio),
+ "Failed to get touch-reset-gpios\n");
+
+ ctx->dsi = dsi;
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS;
+
+ drm_panel_init(&ctx->panel, dev, &sony_td4353_jdi_panel_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
+
+ drm_panel_add(&ctx->panel);
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
+ drm_panel_remove(&ctx->panel);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void sony_td4353_jdi_remove(struct mipi_dsi_device *dsi)
+{
+ struct sony_td4353_jdi *ctx = mipi_dsi_get_drvdata(dsi);
+ int ret;
+
+ ret = mipi_dsi_detach(dsi);
+ if (ret < 0)
+ dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
+
+ drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id sony_td4353_jdi_of_match[] = {
+ { .compatible = "sony,td4353-jdi-tama", .data = (void *)TYPE_TAMA_60HZ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sony_td4353_jdi_of_match);
+
+static struct mipi_dsi_driver sony_td4353_jdi_driver = {
+ .probe = sony_td4353_jdi_probe,
+ .remove = sony_td4353_jdi_remove,
+ .driver = {
+ .name = "panel-sony-td4353-jdi",
+ .of_match_table = sony_td4353_jdi_of_match,
+ },
+};
+module_mipi_dsi_driver(sony_td4353_jdi_driver);
+
+MODULE_AUTHOR("Konrad Dybcio <konrad.dybcio@somainline.org>");
+MODULE_DESCRIPTION("DRM panel driver for SONY Xperia XZ2/XZ2c JDI panel");
+MODULE_LICENSE("GPL");
generated by cgit v1.2.3-70-g09d2 (git 2.51.1) at 2025-11-03 19:12:21 +0000