diff options
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/Makefile | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-lvds.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 21 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-raydium-rm68200.c | 448 | ||||
| -rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 82 |
7 files changed, 547 insertions, 20 deletions
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 988048ebcc22..25682ff3449a 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -108,6 +108,15 @@ config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN Pi 7" Touchscreen. To compile this driver as a module, choose M here. +config DRM_PANEL_RAYDIUM_RM68200 + tristate "Raydium RM68200 720x1280 DSI video mode panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. + config DRM_PANEL_SAMSUNG_S6E3HA2 tristate "Samsung S6E3HA2 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 3d2a88d0e965..f26efc11d746 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o +obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c index b4ec0ecff807..bd38bf4f1ba6 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c @@ -179,7 +179,7 @@ enum ili9322_input { ILI9322_INPUT_UNKNOWN = 0xc, }; -const char *ili9322_inputs[] = { +static const char * const ili9322_inputs[] = { "8 bit serial RGB through", "8 bit serial RGB aligned", "8 bit serial RGB dummy 320x240", @@ -340,7 +340,7 @@ static bool ili9322_writeable_reg(struct device *dev, unsigned int reg) return true; } -const struct regmap_config ili9322_regmap_config = { +static const struct regmap_config ili9322_regmap_config = { .reg_bits = 8, .val_bits = 8, .max_register = 0x44, diff --git a/drivers/gpu/drm/panel/panel-lvds.c b/drivers/gpu/drm/panel/panel-lvds.c index b5e3994f0aa8..5185819c5b79 100644 --- a/drivers/gpu/drm/panel/panel-lvds.c +++ b/drivers/gpu/drm/panel/panel-lvds.c @@ -1,5 +1,5 @@ /* - * rcar_du_crtc.c -- R-Car Display Unit CRTCs + * Generic LVDS panel driver * * Copyright (C) 2016 Laurent Pinchart * Copyright (C) 2016 Renesas Electronics Corporation diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c index c189cd6329c8..90f1ae4af93c 100644 --- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c +++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c @@ -1,16 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) STMicroelectronics SA 2017 * * Authors: Philippe Cornu <philippe.cornu@st.com> * Yannick Fertre <yannick.fertre@st.com> - * - * License terms: GNU General Public License (GPL), version 2 */ + #include <drm/drmP.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_panel.h> #include <linux/backlight.h> #include <linux/gpio/consumer.h> +#include <linux/regulator/consumer.h> #include <video/mipi_display.h> #define DRV_NAME "orisetech_otm8009a" @@ -62,6 +63,7 @@ struct otm8009a { struct drm_panel panel; struct backlight_device *bl_dev; struct gpio_desc *reset_gpio; + struct regulator *supply; bool prepared; bool enabled; }; @@ -279,6 +281,8 @@ static int otm8009a_unprepare(struct drm_panel *panel) msleep(20); } + regulator_disable(ctx->supply); + ctx->prepared = false; return 0; @@ -292,6 +296,12 @@ static int otm8009a_prepare(struct drm_panel *panel) if (ctx->prepared) return 0; + ret = regulator_enable(ctx->supply); + if (ret < 0) { + DRM_ERROR("failed to enable supply: %d\n", ret); + return ret; + } + if (ctx->reset_gpio) { gpiod_set_value_cansleep(ctx->reset_gpio, 0); gpiod_set_value_cansleep(ctx->reset_gpio, 1); @@ -414,6 +424,13 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi) return PTR_ERR(ctx->reset_gpio); } + ctx->supply = devm_regulator_get(dev, "power"); + if (IS_ERR(ctx->supply)) { + ret = PTR_ERR(ctx->supply); + dev_err(dev, "failed to request regulator: %d\n", ret); + return ret; + } + mipi_dsi_set_drvdata(dsi, ctx); ctx->dev = dev; diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c new file mode 100644 index 000000000000..77593533abcd --- /dev/null +++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics SA 2017 + * + * Authors: Philippe Cornu <philippe.cornu@st.com> + * Yannick Fertre <yannick.fertre@st.com> + */ + +#include <linux/backlight.h> +#include <linux/gpio/consumer.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drmP.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_panel.h> + +/*** Manufacturer Command Set ***/ +#define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */ +#define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */ +#define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */ +#define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */ +#define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */ +#define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */ + +/* CMD2 P0 commands (Display Options and Power) */ +#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */ +#define MCS_SGOPCTR 0x16 /* Source Bias Current */ +#define MCS_SDCTR 0x1A /* Source Output Delay Time */ +#define MCS_INVCTR 0x1B /* Inversion Type */ +#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */ +#define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */ +#define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */ +#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */ +#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */ +#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */ +#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */ +#define MCS_SETVGN 0x52 /* VG M/S N Control */ +#define MCS_SETVGP 0x54 /* VG M/S P Control */ +#define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */ + +/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */ +#define GOA_VSTV1 0x00 +#define GOA_VSTV2 0x07 +#define GOA_VCLK1 0x0E +#define GOA_VCLK2 0x17 +#define GOA_VCLK_OPT1 0x20 +#define GOA_BICLK1 0x2A +#define GOA_BICLK2 0x37 +#define GOA_BICLK3 0x44 +#define GOA_BICLK4 0x4F +#define GOA_BICLK_OPT1 0x5B +#define GOA_BICLK_OPT2 0x60 +#define MCS_GOA_GPO1 0x6D +#define MCS_GOA_GPO2 0x71 +#define MCS_GOA_EQ 0x74 +#define MCS_GOA_CLK_GALLON 0x7C +#define MCS_GOA_FS_SEL0 0x7E +#define MCS_GOA_FS_SEL1 0x87 +#define MCS_GOA_FS_SEL2 0x91 +#define MCS_GOA_FS_SEL3 0x9B +#define MCS_GOA_BS_SEL0 0xAC +#define MCS_GOA_BS_SEL1 0xB5 +#define MCS_GOA_BS_SEL2 0xBF +#define MCS_GOA_BS_SEL3 0xC9 +#define MCS_GOA_BS_SEL4 0xD3 + +/* CMD2 P3 commands (Gamma) */ +#define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */ +#define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */ + +struct rm68200 { + struct device *dev; + struct drm_panel panel; + struct gpio_desc *reset_gpio; + struct regulator *supply; + struct backlight_device *backlight; + bool prepared; + bool enabled; +}; + +static const struct drm_display_mode default_mode = { + .clock = 52582, + .hdisplay = 720, + .hsync_start = 720 + 38, + .hsync_end = 720 + 38 + 8, + .htotal = 720 + 38 + 8 + 38, + .vdisplay = 1280, + .vsync_start = 1280 + 12, + .vsync_end = 1280 + 12 + 4, + .vtotal = 1280 + 12 + 4 + 12, + .vrefresh = 50, + .flags = 0, + .width_mm = 68, + .height_mm = 122, +}; + +static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel) +{ + return container_of(panel, struct rm68200, panel); +} + +static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data, + size_t len) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int err; + + err = mipi_dsi_dcs_write_buffer(dsi, data, len); + if (err < 0) + DRM_ERROR_RATELIMITED("MIPI DSI DCS write buffer failed: %d\n", + err); +} + +static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int err; + + err = mipi_dsi_dcs_write(dsi, cmd, &value, 1); + if (err < 0) + DRM_ERROR_RATELIMITED("MIPI DSI DCS write failed: %d\n", err); +} + +#define dcs_write_seq(ctx, seq...) \ +({ \ + static const u8 d[] = { seq }; \ + \ + rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ +}) + +/* + * This panel is not able to auto-increment all cmd addresses so for some of + * them, we need to send them one by one... + */ +#define dcs_write_cmd_seq(ctx, cmd, seq...) \ +({ \ + static const u8 d[] = { seq }; \ + unsigned int i; \ + \ + for (i = 0; i < ARRAY_SIZE(d) ; i++) \ + rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \ +}) + +static void rm68200_init_sequence(struct rm68200 *ctx) +{ + /* Enter CMD2 with page 0 */ + dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0); + dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00); + dcs_write_seq(ctx, MCS_BT2CTR, 0xE5); + dcs_write_seq(ctx, MCS_SETAVDD, 0x0A); + dcs_write_seq(ctx, MCS_SETAVEE, 0x0A); + dcs_write_seq(ctx, MCS_SGOPCTR, 0x52); + dcs_write_seq(ctx, MCS_BT3CTR, 0x53); + dcs_write_seq(ctx, MCS_BT4CTR, 0x5A); + dcs_write_seq(ctx, MCS_INVCTR, 0x00); + dcs_write_seq(ctx, MCS_STBCTR, 0x0A); + dcs_write_seq(ctx, MCS_SDCTR, 0x06); + dcs_write_seq(ctx, MCS_VCMCTR, 0x56); + dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00); + dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00); + dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ + + dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2); + dcs_write_seq(ctx, GOA_VSTV1, 0x05); + dcs_write_seq(ctx, 0x02, 0x0B); + dcs_write_seq(ctx, 0x03, 0x0F); + dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50); + dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00, + 0x50); + dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D, + 0x00, 0x85, 0x08); + dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D, + 0x00, 0x85, 0x08); + dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00); + dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08); + dcs_write_seq(ctx, 0x2D, 0x01); + dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D, + 0x00); + dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00); + dcs_write_seq(ctx, 0x3D, 0x40); + dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00); + dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00); + dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00); + dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00); + dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00); + dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00); + dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00); + dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, + 0x00, 0x00); + dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00); + dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10, + 0x16, 0x12, 0x08, 0x3F); + dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C, + 0x0A, 0x0E, 0x3F, 0x3F, 0x00); + dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, + 0x05, 0x01, 0x3F, 0x3F, 0x0F); + dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F, + 0x3F); + dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15); + dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F); + dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13, + 0x15, 0x11, 0x0F, 0x3F); + dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B, + 0x0D, 0x09, 0x3F, 0x3F, 0x07); + dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F, + 0x02, 0x06, 0x3F, 0x3F, 0x08); + dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x0E, 0x10, 0x14); + dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F); + dcs_write_seq(ctx, 0xDC, 0x02); + dcs_write_seq(ctx, 0xDE, 0x12); + + dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */ + dcs_write_seq(ctx, 0x01, 0x75); + + dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3); + dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06, + 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, + 0x12, 0x0C, 0x00); + dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06, + 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, + 0x12, 0x0C, 0x00); + + /* Exit CMD2 */ + dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS); +} + +static int rm68200_disable(struct drm_panel *panel) +{ + struct rm68200 *ctx = panel_to_rm68200(panel); + + if (!ctx->enabled) + return 0; + + backlight_disable(ctx->backlight); + + ctx->enabled = false; + + return 0; +} + +static int rm68200_unprepare(struct drm_panel *panel) +{ + struct rm68200 *ctx = panel_to_rm68200(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int ret; + + if (!ctx->prepared) + return 0; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret) + DRM_WARN("failed to set display off: %d\n", ret); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret) + DRM_WARN("failed to enter sleep mode: %d\n", ret); + + msleep(120); + + if (ctx->reset_gpio) { + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(20); + } + + regulator_disable(ctx->supply); + + ctx->prepared = false; + + return 0; +} + +static int rm68200_prepare(struct drm_panel *panel) +{ + struct rm68200 *ctx = panel_to_rm68200(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int ret; + + if (ctx->prepared) + return 0; + + ret = regulator_enable(ctx->supply); + if (ret < 0) { + DRM_ERROR("failed to enable supply: %d\n", ret); + return ret; + } + + if (ctx->reset_gpio) { + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + msleep(20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + msleep(100); + } + + rm68200_init_sequence(ctx); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret) + return ret; + + msleep(125); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret) + return ret; + + msleep(20); + + ctx->prepared = true; + + return 0; +} + +static int rm68200_enable(struct drm_panel *panel) +{ + struct rm68200 *ctx = panel_to_rm68200(panel); + + if (ctx->enabled) + return 0; + + backlight_enable(ctx->backlight); + + ctx->enabled = true; + + return 0; +} + +static int rm68200_get_modes(struct drm_panel *panel) +{ + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(panel->drm, &default_mode); + if (!mode) { + DRM_ERROR("failed to add mode %ux%ux@%u\n", + default_mode.hdisplay, default_mode.vdisplay, + default_mode.vrefresh); + return -ENOMEM; + } + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(panel->connector, mode); + + panel->connector->display_info.width_mm = mode->width_mm; + panel->connector->display_info.height_mm = mode->height_mm; + + return 1; +} + +static const struct drm_panel_funcs rm68200_drm_funcs = { + .disable = rm68200_disable, + .unprepare = rm68200_unprepare, + .prepare = rm68200_prepare, + .enable = rm68200_enable, + .get_modes = rm68200_get_modes, +}; + +static int rm68200_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct rm68200 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) { + ret = PTR_ERR(ctx->reset_gpio); + dev_err(dev, "cannot get reset GPIO: %d\n", ret); + return ret; + } + + ctx->supply = devm_regulator_get(dev, "power"); + if (IS_ERR(ctx->supply)) { + ret = PTR_ERR(ctx->supply); + dev_err(dev, "cannot get regulator: %d\n", ret); + return ret; + } + + ctx->backlight = devm_of_find_backlight(dev); + if (IS_ERR(ctx->backlight)) + return PTR_ERR(ctx->backlight); + + mipi_dsi_set_drvdata(dsi, ctx); + + ctx->dev = dev; + + dsi->lanes = 2; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + + drm_panel_init(&ctx->panel); + ctx->panel.dev = dev; + ctx->panel.funcs = &rm68200_drm_funcs; + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static int rm68200_remove(struct mipi_dsi_device *dsi) +{ + struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id raydium_rm68200_of_match[] = { + { .compatible = "raydium,rm68200" }, + { } +}; +MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match); + +static struct mipi_dsi_driver raydium_rm68200_driver = { + .probe = rm68200_probe, + .remove = rm68200_remove, + .driver = { + .name = "panel-raydium-rm68200", + .of_match_table = raydium_rm68200_of_match, + }, +}; +module_mipi_dsi_driver(raydium_rm68200_driver); + +MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); +MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 5591984a392b..cbf1ab404ee7 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -581,6 +581,29 @@ static const struct panel_desc auo_b133htn01 = { }, }; +static const struct drm_display_mode auo_g104sn02_mode = { + .clock = 40000, + .hdisplay = 800, + .hsync_start = 800 + 40, + .hsync_end = 800 + 40 + 216, + .htotal = 800 + 40 + 216 + 128, + .vdisplay = 600, + .vsync_start = 600 + 10, + .vsync_end = 600 + 10 + 35, + .vtotal = 600 + 10 + 35 + 2, + .vrefresh = 60, +}; + +static const struct panel_desc auo_g104sn02 = { + .modes = &auo_g104sn02_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 211, + .height = 158, + }, +}; + static const struct display_timing auo_g133han01_timings = { .pixelclock = { 134000000, 141200000, 149000000 }, .hactive = { 1920, 1920, 1920 }, @@ -1217,6 +1240,30 @@ static const struct panel_desc innolux_zj070na_01p = { }, }; +static const struct display_timing koe_tx31d200vm0baa_timing = { + .pixelclock = { 39600000, 43200000, 48000000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 16, 36, 56 }, + .hback_porch = { 16, 36, 56 }, + .hsync_len = { 8, 8, 8 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 6, 21, 33.5 }, + .vback_porch = { 6, 21, 33.5 }, + .vsync_len = { 8, 8, 8 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc koe_tx31d200vm0baa = { + .timings = &koe_tx31d200vm0baa_timing, + .num_timings = 1, + .bpc = 6, + .size = { + .width = 292, + .height = 109, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, +}; + static const struct display_timing kyo_tcg121xglp_timing = { .pixelclock = { 52000000, 65000000, 71000000 }, .hactive = { 1024, 1024, 1024 }, @@ -1597,7 +1644,7 @@ static const struct panel_desc ontat_yx700wv03 = { .width = 154, .height = 83, }, - .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, }; static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { @@ -1741,23 +1788,22 @@ static const struct panel_desc sharp_lq101k1ly04 = { .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, }; -static const struct drm_display_mode sharp_lq123p1jx31_mode = { - .clock = 252750, - .hdisplay = 2400, - .hsync_start = 2400 + 48, - .hsync_end = 2400 + 48 + 32, - .htotal = 2400 + 48 + 32 + 80, - .vdisplay = 1600, - .vsync_start = 1600 + 3, - .vsync_end = 1600 + 3 + 10, - .vtotal = 1600 + 3 + 10 + 33, - .vrefresh = 60, - .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +static const struct display_timing sharp_lq123p1jx31_timing = { + .pixelclock = { 252750000, 252750000, 266604720 }, + .hactive = { 2400, 2400, 2400 }, + .hfront_porch = { 48, 48, 48 }, + .hback_porch = { 80, 80, 84 }, + .hsync_len = { 32, 32, 32 }, + .vactive = { 1600, 1600, 1600 }, + .vfront_porch = { 3, 3, 3 }, + .vback_porch = { 33, 33, 120 }, + .vsync_len = { 10, 10, 10 }, + .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, }; static const struct panel_desc sharp_lq123p1jx31 = { - .modes = &sharp_lq123p1jx31_mode, - .num_modes = 1, + .timings = &sharp_lq123p1jx31_timing, + .num_timings = 1, .bpc = 8, .size = { .width = 259, @@ -2049,6 +2095,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "auo,b133xtn01", .data = &auo_b133xtn01, }, { + .compatible = "auo,g104sn02", + .data = &auo_g104sn02, + }, { .compatible = "auo,g133han01", .data = &auo_g133han01, }, { @@ -2124,6 +2173,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "innolux,zj070na-01p", .data = &innolux_zj070na_01p, }, { + .compatible = "koe,tx31d200vm0baa", + .data = &koe_tx31d200vm0baa, + }, { .compatible = "kyo,tcg121xglp", .data = &kyo_tcg121xglp, }, { |