diff options
Diffstat (limited to 'drivers/net/ipa/reg/ipa_reg-v3.1.c')
-rw-r--r-- | drivers/net/ipa/reg/ipa_reg-v3.1.c | 283 |
1 files changed, 141 insertions, 142 deletions
diff --git a/drivers/net/ipa/reg/ipa_reg-v3.1.c b/drivers/net/ipa/reg/ipa_reg-v3.1.c index 677ece3bce9e..648dbfe1fce3 100644 --- a/drivers/net/ipa/reg/ipa_reg-v3.1.c +++ b/drivers/net/ipa/reg/ipa_reg-v3.1.c @@ -7,7 +7,7 @@ #include "../ipa.h" #include "../ipa_reg.h" -static const u32 ipa_reg_comp_cfg_fmask[] = { +static const u32 reg_comp_cfg_fmask[] = { [COMP_CFG_ENABLE] = BIT(0), [GSI_SNOC_BYPASS_DIS] = BIT(1), [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), @@ -16,9 +16,9 @@ static const u32 ipa_reg_comp_cfg_fmask[] = { /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); +REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); -static const u32 ipa_reg_clkon_cfg_fmask[] = { +static const u32 reg_clkon_cfg_fmask[] = { [CLKON_RX] = BIT(0), [CLKON_PROC] = BIT(1), [TX_WRAPPER] = BIT(2), @@ -39,9 +39,9 @@ static const u32 ipa_reg_clkon_cfg_fmask[] = { /* Bits 17-31 reserved */ }; -IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); +REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); -static const u32 ipa_reg_route_fmask[] = { +static const u32 reg_route_fmask[] = { [ROUTE_DIS] = BIT(0), [ROUTE_DEF_PIPE] = GENMASK(5, 1), [ROUTE_DEF_HDR_TABLE] = BIT(6), @@ -52,31 +52,31 @@ static const u32 ipa_reg_route_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_FIELDS(ROUTE, route, 0x00000048); +REG_FIELDS(ROUTE, route, 0x00000048); -static const u32 ipa_reg_shared_mem_size_fmask[] = { +static const u32 reg_shared_mem_size_fmask[] = { [MEM_SIZE] = GENMASK(15, 0), [MEM_BADDR] = GENMASK(31, 16), }; -IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); +REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); -static const u32 ipa_reg_qsb_max_writes_fmask[] = { +static const u32 reg_qsb_max_writes_fmask[] = { [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), /* Bits 8-31 reserved */ }; -IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); +REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); -static const u32 ipa_reg_qsb_max_reads_fmask[] = { +static const u32 reg_qsb_max_reads_fmask[] = { [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), }; -IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); +REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); -static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { +static const u32 reg_filt_rout_hash_en_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -87,9 +87,9 @@ static const u32 ipa_reg_filt_rout_hash_en_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); +REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); -static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { +static const u32 reg_filt_rout_hash_flush_fmask[] = { [IPV6_ROUTER_HASH] = BIT(0), /* Bits 1-3 reserved */ [IPV6_FILTER_HASH] = BIT(4), @@ -100,121 +100,121 @@ static const u32 ipa_reg_filt_rout_hash_flush_fmask[] = { /* Bits 13-31 reserved */ }; -IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); +REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); /* Valid bits defined by ipa->available */ -IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); +REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); -IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0); +REG(IPA_BCR, ipa_bcr, 0x000001d0); -static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = { +static const u32 reg_local_pkt_proc_cntxt_fmask[] = { [IPA_BASE_ADDR] = GENMASK(16, 0), /* Bits 17-31 reserved */ }; /* Offset must be a multiple of 8 */ -IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); +REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); /* Valid bits defined by ipa->available */ -IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); +REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); -static const u32 ipa_reg_counter_cfg_fmask[] = { +static const u32 reg_counter_cfg_fmask[] = { [EOT_COAL_GRANULARITY] = GENMASK(3, 0), [AGGR_GRANULARITY] = GENMASK(8, 4), /* Bits 5-31 reserved */ }; -IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); +REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); -static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, - 0x00000400, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, + 0x00000400, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, - 0x00000404, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, + 0x00000404, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, - 0x00000408, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, + 0x00000408, 0x0020); -static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { +static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, - 0x0000040c, 0x0020); +REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, + 0x0000040c, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, - 0x00000500, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, + 0x00000500, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, - 0x00000504, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, + 0x00000504, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, - 0x00000508, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, + 0x00000508, 0x0020); -static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { +static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { [X_MIN_LIM] = GENMASK(7, 0), [X_MAX_LIM] = GENMASK(15, 8), [Y_MIN_LIM] = GENMASK(23, 16), [Y_MAX_LIM] = GENMASK(31, 24), }; -IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, - 0x0000050c, 0x0020); +REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, + 0x0000050c, 0x0020); -static const u32 ipa_reg_endp_init_ctrl_fmask[] = { +static const u32 reg_endp_init_ctrl_fmask[] = { [ENDP_SUSPEND] = BIT(0), [ENDP_DELAY] = BIT(1), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); -static const u32 ipa_reg_endp_init_cfg_fmask[] = { +static const u32 reg_endp_init_cfg_fmask[] = { [FRAG_OFFLOAD_EN] = BIT(0), [CS_OFFLOAD_EN] = GENMASK(2, 1), [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), @@ -223,16 +223,16 @@ static const u32 ipa_reg_endp_init_cfg_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); -static const u32 ipa_reg_endp_init_nat_fmask[] = { +static const u32 reg_endp_init_nat_fmask[] = { [NAT_EN] = GENMASK(1, 0), /* Bits 2-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); -static const u32 ipa_reg_endp_init_hdr_fmask[] = { +static const u32 reg_endp_init_hdr_fmask[] = { [HDR_LEN] = GENMASK(5, 0), [HDR_OFST_METADATA_VALID] = BIT(6), [HDR_OFST_METADATA] = GENMASK(12, 7), @@ -245,9 +245,9 @@ static const u32 ipa_reg_endp_init_hdr_fmask[] = { /* Bits 29-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); -static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { +static const u32 reg_endp_init_hdr_ext_fmask[] = { [HDR_ENDIANNESS] = BIT(0), [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), [HDR_TOTAL_LEN_OR_PAD] = BIT(2), @@ -257,12 +257,12 @@ static const u32 ipa_reg_endp_init_hdr_ext_fmask[] = { /* Bits 14-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); -IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, - 0x00000818, 0x0070); +REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, + 0x00000818, 0x0070); -static const u32 ipa_reg_endp_init_mode_fmask[] = { +static const u32 reg_endp_init_mode_fmask[] = { [ENDP_MODE] = GENMASK(2, 0), /* Bit 3 reserved */ [DEST_PIPE_INDEX] = GENMASK(8, 4), @@ -274,9 +274,9 @@ static const u32 ipa_reg_endp_init_mode_fmask[] = { /* Bit 31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); -static const u32 ipa_reg_endp_init_aggr_fmask[] = { +static const u32 reg_endp_init_aggr_fmask[] = { [AGGR_EN] = GENMASK(1, 0), [AGGR_TYPE] = GENMASK(4, 2), [BYTE_LIMIT] = GENMASK(9, 5), @@ -289,25 +289,25 @@ static const u32 ipa_reg_endp_init_aggr_fmask[] = { /* Bits 25-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); -static const u32 ipa_reg_endp_init_hol_block_en_fmask[] = { +static const u32 reg_endp_init_hol_block_en_fmask[] = { [HOL_BLOCK_EN] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, - 0x0000082c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, + 0x0000082c, 0x0070); /* Entire register is a tick count */ -static const u32 ipa_reg_endp_init_hol_block_timer_fmask[] = { +static const u32 reg_endp_init_hol_block_timer_fmask[] = { [TIMER_BASE_VALUE] = GENMASK(31, 0), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, - 0x00000830, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, + 0x00000830, 0x0070); -static const u32 ipa_reg_endp_init_deaggr_fmask[] = { +static const u32 reg_endp_init_deaggr_fmask[] = { [DEAGGR_HDR_LEN] = GENMASK(5, 0), [SYSPIPE_ERR_DETECTION] = BIT(6), [PACKET_OFFSET_VALID] = BIT(7), @@ -317,25 +317,24 @@ static const u32 ipa_reg_endp_init_deaggr_fmask[] = { [MAX_PACKET_LEN] = GENMASK(31, 16), }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); -static const u32 ipa_reg_endp_init_rsrc_grp_fmask[] = { +static const u32 reg_endp_init_rsrc_grp_fmask[] = { [ENDP_RSRC_GRP] = GENMASK(2, 0), /* Bits 3-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, - 0x00000838, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); -static const u32 ipa_reg_endp_init_seq_fmask[] = { +static const u32 reg_endp_init_seq_fmask[] = { [SEQ_TYPE] = GENMASK(7, 0), [SEQ_REP_TYPE] = GENMASK(15, 8), /* Bits 16-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); +REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); -static const u32 ipa_reg_endp_status_fmask[] = { +static const u32 reg_endp_status_fmask[] = { [STATUS_EN] = BIT(0), [STATUS_ENDP] = GENMASK(5, 1), /* Bits 6-7 reserved */ @@ -343,9 +342,9 @@ static const u32 ipa_reg_endp_status_fmask[] = { /* Bits 9-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); +REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); -static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { +static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { [FILTER_HASH_MSK_SRC_ID] = BIT(0), [FILTER_HASH_MSK_SRC_IP] = BIT(1), [FILTER_HASH_MSK_DST_IP] = BIT(2), @@ -366,84 +365,84 @@ static const u32 ipa_reg_endp_filter_router_hsh_cfg_fmask[] = { /* Bits 23-31 reserved */ }; -IPA_REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, - 0x0000085c, 0x0070); +REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, + 0x0000085c, 0x0070); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ -IPA_REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); +REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); -static const u32 ipa_reg_ipa_irq_uc_fmask[] = { +static const u32 reg_ipa_irq_uc_fmask[] = { [UC_INTR] = BIT(0), /* Bits 1-31 reserved */ }; -IPA_REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); +REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); /* Valid bits defined by ipa->available */ -IPA_REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, - 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); +REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, + 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, - 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); +REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, + 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); /* Valid bits defined by ipa->available */ -IPA_REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, - 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); - -static const struct ipa_reg *ipa_reg_array[] = { - [COMP_CFG] = &ipa_reg_comp_cfg, - [CLKON_CFG] = &ipa_reg_clkon_cfg, - [ROUTE] = &ipa_reg_route, - [SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size, - [QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes, - [QSB_MAX_READS] = &ipa_reg_qsb_max_reads, - [FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en, - [FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush, - [STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active, - [IPA_BCR] = &ipa_reg_ipa_bcr, - [LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt, - [AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close, - [COUNTER_CFG] = &ipa_reg_counter_cfg, - [SRC_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_01_rsrc_type, - [SRC_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_23_rsrc_type, - [SRC_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_45_rsrc_type, - [SRC_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_src_rsrc_grp_67_rsrc_type, - [DST_RSRC_GRP_01_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_01_rsrc_type, - [DST_RSRC_GRP_23_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_23_rsrc_type, - [DST_RSRC_GRP_45_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_45_rsrc_type, - [DST_RSRC_GRP_67_RSRC_TYPE] = &ipa_reg_dst_rsrc_grp_67_rsrc_type, - [ENDP_INIT_CTRL] = &ipa_reg_endp_init_ctrl, - [ENDP_INIT_CFG] = &ipa_reg_endp_init_cfg, - [ENDP_INIT_NAT] = &ipa_reg_endp_init_nat, - [ENDP_INIT_HDR] = &ipa_reg_endp_init_hdr, - [ENDP_INIT_HDR_EXT] = &ipa_reg_endp_init_hdr_ext, - [ENDP_INIT_HDR_METADATA_MASK] = &ipa_reg_endp_init_hdr_metadata_mask, - [ENDP_INIT_MODE] = &ipa_reg_endp_init_mode, - [ENDP_INIT_AGGR] = &ipa_reg_endp_init_aggr, - [ENDP_INIT_HOL_BLOCK_EN] = &ipa_reg_endp_init_hol_block_en, - [ENDP_INIT_HOL_BLOCK_TIMER] = &ipa_reg_endp_init_hol_block_timer, - [ENDP_INIT_DEAGGR] = &ipa_reg_endp_init_deaggr, - [ENDP_INIT_RSRC_GRP] = &ipa_reg_endp_init_rsrc_grp, - [ENDP_INIT_SEQ] = &ipa_reg_endp_init_seq, - [ENDP_STATUS] = &ipa_reg_endp_status, - [ENDP_FILTER_ROUTER_HSH_CFG] = &ipa_reg_endp_filter_router_hsh_cfg, - [IPA_IRQ_STTS] = &ipa_reg_ipa_irq_stts, - [IPA_IRQ_EN] = &ipa_reg_ipa_irq_en, - [IPA_IRQ_CLR] = &ipa_reg_ipa_irq_clr, - [IPA_IRQ_UC] = &ipa_reg_ipa_irq_uc, - [IRQ_SUSPEND_INFO] = &ipa_reg_irq_suspend_info, - [IRQ_SUSPEND_EN] = &ipa_reg_irq_suspend_en, - [IRQ_SUSPEND_CLR] = &ipa_reg_irq_suspend_clr, -}; - -const struct ipa_regs ipa_regs_v3_1 = { - .reg_count = ARRAY_SIZE(ipa_reg_array), - .reg = ipa_reg_array, +REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, + 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); + +static const struct reg *reg_array[] = { + [COMP_CFG] = ®_comp_cfg, + [CLKON_CFG] = ®_clkon_cfg, + [ROUTE] = ®_route, + [SHARED_MEM_SIZE] = ®_shared_mem_size, + [QSB_MAX_WRITES] = ®_qsb_max_writes, + [QSB_MAX_READS] = ®_qsb_max_reads, + [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, + [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, + [STATE_AGGR_ACTIVE] = ®_state_aggr_active, + [IPA_BCR] = ®_ipa_bcr, + [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, + [AGGR_FORCE_CLOSE] = ®_aggr_force_close, + [COUNTER_CFG] = ®_counter_cfg, + [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, + [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, + [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, + [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type, + [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, + [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, + [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, + [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type, + [ENDP_INIT_CTRL] = ®_endp_init_ctrl, + [ENDP_INIT_CFG] = ®_endp_init_cfg, + [ENDP_INIT_NAT] = ®_endp_init_nat, + [ENDP_INIT_HDR] = ®_endp_init_hdr, + [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, + [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, + [ENDP_INIT_MODE] = ®_endp_init_mode, + [ENDP_INIT_AGGR] = ®_endp_init_aggr, + [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, + [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, + [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, + [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, + [ENDP_INIT_SEQ] = ®_endp_init_seq, + [ENDP_STATUS] = ®_endp_status, + [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, + [IPA_IRQ_STTS] = ®_ipa_irq_stts, + [IPA_IRQ_EN] = ®_ipa_irq_en, + [IPA_IRQ_CLR] = ®_ipa_irq_clr, + [IPA_IRQ_UC] = ®_ipa_irq_uc, + [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, + [IRQ_SUSPEND_EN] = ®_irq_suspend_en, + [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, +}; + +const struct regs ipa_regs_v3_1 = { + .reg_count = ARRAY_SIZE(reg_array), + .reg = reg_array, }; |