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2021-12-21Merge tag 'qcom-drivers-for-5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.17 This introduces RPM power-domain support for the SM8450, SM6125 and QCM2290 platforms. It them clean up the platform-based naming of the resources definitions throughout the RPMh PD driver. The last-level cache controller driver gains SM8350 support. The RPM sleep stats driver gains support for several older systems that had a slightly different memory layout for this information. The socinfo gains SM8450, SM6350 and SM7227 definitions. In addition to the DeviceTree binding updates related to these changes new compatibles was added to describe the SM8450 and the Kryo 780 CPU. Lastly a few typo and style fixes are introduced. * tag 'qcom-drivers-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ... Link: https://lore.kernel.org/r/20211221040452.3620633-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20soc: qcom: rpmh-rsc: Fix typo in a commentJason Wang
The double `for' in the comment in line 694 is repeated. Remove one of them from the comment. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211211090626.248801-1-wangborong@cdjrlc.com
2021-12-20soc: qcom: socinfo: Add SM6350 and SM7225Luca Weiss
Both SoCs are known as 'lagoon' downstream. Add their ids to the socinfo driver. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213081111.20217-1-luca.weiss@fairphone.com
2021-12-20dt-bindings: arm: msm: Don't mark LLCC interrupt as requiredLuca Weiss
Newer SoCs like SM6350 or SM8250 don't provide an interrupt for LLCC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082614.22651-9-luca.weiss@fairphone.com
2021-12-20dt-bindings: firmware: scm: Add SM6350 compatibleLuca Weiss
Add devicetree compatible for SCM on SM6350 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082614.22651-3-luca.weiss@fairphone.com
2021-12-20dt-bindings: arm: msm: Add LLCC for SM6350Konrad Dybcio
Add LLCC compatible for SM6350 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211213082614.22651-2-luca.weiss@fairphone.com
2021-12-20soc: qcom: rpmhpd: Sort power-domain definitions and listsRajendra Nayak
Sort all power-domain defines and the SoC specific lists in alphabetical order for better readability. No functional changes. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-5-git-send-email-quic_rjendra@quicinc.com
2021-12-20soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280Rajendra Nayak
The requirement to specify the active + sleep and active-only MX power-domains as the parents of the corresponding CX power domains is not applicable on sc7280. Fix it by using the cx/cx_ao structs for sc7280 instead of the _w_mx_parent ones. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-4-git-send-email-quic_rjendra@quicinc.com
2021-12-20soc: qcom: rpmhpd: Rename rpmhpd struct namesRajendra Nayak
The rpmhpd structs were named with a SoC-name prefix, but then they got reused across multiple SoC families making things confusing. Rename all the struct names to remove SoC-name prefixes. While we do this we end up with some power-domains without parents, and some with and at times different parents across SoCs. use a _w_<parent-name>_parent suffix for such cases. No functional change as part of this patch. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-3-git-send-email-quic_rjendra@quicinc.com
2021-12-20soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_aoRajendra Nayak
sm8450_cx and sm8450_cx_ao should be peers of each other, add the missing .peer entry for sm8450_cx_ao Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1639063917-9011-2-git-send-email-quic_rjendra@quicinc.com
2021-12-20soc: qcom: socinfo: add SM8450 IDDmitry Baryshkov
Add the ID for the Qualcomm SM8450 SoC. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-8-vkoul@kernel.org
2021-12-20soc: qcom: rpmhpd: Add SM8450 power domainsDmitry Baryshkov
Add the power domains exposed by RPMH in the Qualcomm SM8450 platform. Unlike previous generations CX domain is not a child of MX domain. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-7-vkoul@kernel.org
2021-12-20dt-bindings: power: rpmpd: Add SM8450 to rpmpd bindingDmitry Baryshkov
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-6-vkoul@kernel.org
2021-12-20soc: qcom: smem: Update max processor countDmitry Baryshkov
Update max processor count to reflect the number of co-processors on SM8450 SoCs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-5-vkoul@kernel.org
2021-12-20dt-bindings: arm: qcom: Document SM8450 SoC and boardsVinod Koul
Document the SM8450 SoC binding and also the boards using it. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-4-vkoul@kernel.org
2021-12-20dt-bindings: firmware: scm: Add SM8450 compatibleVinod Koul
Add compatible for SM8450 SoCs. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-3-vkoul@kernel.org
2021-12-20dt-bindings: arm: cpus: Add kryo780 compatibleVinod Koul
Kryo780 is found in SM8450, so add it to the list of cpu compatibles Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-2-vkoul@kernel.org
2021-12-20soc: qcom: rpmpd: Add support for sm6125Martin Botka
Add RPM power domains located in Qualcomm SM6125 SoC. Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211130212332.25401-2-martin.botka@somainline.org
2021-12-20dt-bindings: qcom-rpmpd: Add sm6125 power domainsMartin Botka
Add dt-bindings for sm6125 SoC RPM Power Domains Signed-off-by: Martin Botka <martin.botka@somainline.org> [bjorn: Added compatible to binding as well] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211130212332.25401-1-martin.botka@somainline.org
2021-12-20soc: qcom: aoss: constify static struct thermal_cooling_device_opsRikard Falkeborn
The only usage of qmp_cooling_device_ops is to pass its address to devm_thermal_of_cooling_device_register() which takes a pointer to const struct thermal_cooling_device_ops as argument. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211128210317.25504-1-rikard.falkeborn@gmail.com
2021-12-20PM: AVS: qcom-cpr: Use div64_ul instead of do_divChangcheng Deng
do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211125014311.45942-1-deng.changcheng@zte.com.cn
2021-12-20soc: qcom: llcc: Add configuration data for SM8350Konrad Dybcio
Add LLCC configuration data for SM8350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211121002050.36977-2-konrad.dybcio@somainline.org
2021-12-20soc: qcom: stats: Add fixed sleep stats offset for older RPM firmwaresStephan Gerhold
Not all RPM firmware versions have the dynamic sleep stats offset available. Most older versions use a fixed offset of 0xdba0. Add support for this using new SoC-specific compatibles for APQ8084, MSM8226, MSM8916 and MSM8974. Even older SoCs seem to use a different offset and stats format. If needed those could be supported in the future by adding separate compatibles for those with a different stats_config. Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211119213953.31970-3-stephan@gerhold.net
2021-12-20dt-bindings: soc: qcom: stats: Document compatibles with fixed offsetStephan Gerhold
Document additional compatibles that can be used similarly to qcom,rpm-stats for older RPM firmware versions that have the sleep stats at a fixed offset rather than a dynamic one. The exact offset might vary depending on the SoC so use SoC-specific compatible names to avoid confusion. Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211119213953.31970-2-stephan@gerhold.net
2021-12-20Merge tag 'samsung-drivers-5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung SoC drivers changes for v5.17 1. Exynos ChipID: add Exynos7885 support. 2. Exynos PMU: add Exynos850 support. 3. Minor bindings cleanup. 4. Add Exynos USIv2 (Universal Serial Interface) driver. The USI block is a shared IP block between I2C, UART/serial and SPI. Basically one has to choose which feature the USI block will support and later the regular I2C/serial/SPI driver will bind and work. This merges also one commit with dt-binding headers from my dts64 pull request. Together with a future serial driver change, this will break the ABI. Affected: Serial on ExynosAutov9 SADK and out-of-tree ExynosAutov9 boards Why: To properly and efficiently support the USI with new hierarchy of USI-{serial,SPI,I2C} devicetree nodes. Rationale: Recently added serial and USI support was short-sighted and did not allow to smooth support of other features (SPI and I2C). Adding support for USI-SPI and USI-I2C would effect in code duplication. Adding support for different USI versions (currently supported is USIv2 but support for v1 is planned) would cause even more code duplication and create a solution difficult to maintain. Since USI-serial and ExynosAutov9 have been added recently, are considered fresh development features and there are no supported products using them, the code/solution is being refactored in non-backwards compatible way. The compatibility is not broken yet. It will be when serial driver changes are accepted. The ABI break was discussed with only known users of ExynosAutov9 and received their permission. * tag 'samsung-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: soc: samsung: keep SoC driver bindings together soc: samsung: Add USI driver dt-bindings: soc: samsung: Add Exynos USI bindings soc: samsung: exynos-pmu: Add Exynos850 support dt-bindings: samsung: pmu: Document Exynos850 soc: samsung: exynos-chipid: add Exynos7885 SoC support soc: samsung: exynos-chipid: describe which SoCs go with compatibles Link: https://lore.kernel.org/r/20211220115405.30434-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'imx-drivers-5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.17: - A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add i.MX8MN display related domain support. - Add optional continuous burst clock support for imx-weim bus driver. - Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and MIX domain. * tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled bus: imx-weim: optionally enable continuous burst clock soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active soc: imx: gpcv2: Synchronously suspend MIX domains Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'at91-soc-5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 SoC #1 for 5.17: - one low priority fix about of_node_put() missing in PM code * tag 'at91-soc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: pm: Add of_node_put() before goto Link: https://lore.kernel.org/r/20211217164134.28566-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'tegra-for-5.17-soc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.17-rc1 This set of changes contains some preparatory work that is shared by several branches and trees to support DVFS via power domains. There's also a bit of cleanup and improvements to reboot on chips that use PSCI. * tag 'tegra-for-5.17-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Rename core power domain soc/tegra: pmc: Rename 3d power domains soc/tegra: regulators: Prepare for suspend soc/tegra: fuse: Use resource-managed helpers soc/tegra: fuse: Reset hardware soc/tegra: pmc: Add reboot notifier soc/tegra: Don't print error message when OPPs not available Link: https://lore.kernel.org/r/20211217162253.1801077-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'tegra-for-5.17-drivers' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers drivers: Changes for v5.17-rc1 This is an assortment of driver patches that rely on some of the changes in the for-5.17/soc branch. These have all been acked by the respective maintainers and go through the Tegra tree to more easily handle the build dependency. * tag 'tegra-for-5.17-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: staging: tegra-vde: Support generic power domain spi: tegra20-slink: Add OPP support mtd: rawnand: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support usb: chipidea: tegra: Add runtime PM and OPP support soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: Enable runtime PM during OPP state-syncing Link: https://lore.kernel.org/r/20211217162253.1801077-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'ti-driver-soc-fixes-for-v5.17' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers SoC: Keystone driver update for v5.17 * k3-socinfo: Add entry for J721S2 SoC family * Misc fixups for tisci, pruss, knav_dma * tag 'ti-driver-soc-fixes-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_init soc: ti: k3-socinfo: Add entry for J721S2 SoC family firmware: ti_sci: rm: remove unneeded semicolon soc: ti: pruss: fix referenced node in error message Link: https://lore.kernel.org/r/20211217154921.cagzppcensxx6wm4@pension Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-18dt-bindings: soc: samsung: keep SoC driver bindings togetherKrzysztof Kozlowski
Recently added Samsung Exynos USI driver devicetree bindings were added under ../bindings/soc/samsung/exynos-usi.yaml, so move there also two other bindings for Exynos SoC drivers: the PMU and ChipID. Update Samsung Exynos MAINTAINERS entry to include this new path. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211213112057.16709-1-krzysztof.kozlowski@canonical.com
2021-12-18soc: samsung: Add USI driverSam Protsenko
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204195757.8600-3-semen.protsenko@linaro.org Tested-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-17Merge tag 'renesas-drivers-for-v5.17-tag2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.17 (take two) - Core support for the R-Car S4-8 (R8A779F0) SoC, including System Controller (SYSC) and Reset (RST) support. * tag 'renesas-drivers-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-rst: Add support for R-Car S4-8 soc: renesas: Identify R-Car S4-8 soc: renesas: r8a779f0-sysc: Add r8a779f0 support soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions Link: https://lore.kernel.org/r/cover.1639736722.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-17soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrlAdam Ford
This adds the description for the i.MX8MN disp blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domainsAdam Ford
This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17soc: imx: gpcv2: Add dispmix and mipi domains to imx8mnAdam Ford
The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabledAdam Ford
Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16media: staging: tegra-vde: Support generic power domainDmitry Osipenko
Currently driver supports legacy power domain API, this patch adds generic power domain support. This allows us to utilize a modern GENPD API for newer device-trees. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16spi: tegra20-slink: Add OPP supportDmitry Osipenko
The SPI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SPI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state in accordance to the rate. Add OPP support to the driver. Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mtd: rawnand: tegra: Add runtime PM and OPP supportDmitry Osipenko
The NAND on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now NAND must be resumed using runtime PM API in order to initialize the NAND power state. Add runtime PM and OPP support to the NAND driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mmc: sdhci-tegra: Add runtime PM and OPP supportDmitry Osipenko
The SDHCI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SDHCI must be resumed using runtime PM API in order to initialize the SDHCI power state. The SDHCI clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the SDHCI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16pwm: tegra: Add runtime PM and OPP supportDmitry Osipenko
The PWM on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now PWM must be resumed using runtime PM API in order to initialize the PWM power state. The PWM clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the PWM driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16bus: tegra-gmi: Add runtime PM and OPP supportDmitry Osipenko
The GMI bus on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now GMI must be resumed using runtime PM API in order to initialize the GMI power state. Add runtime PM and OPP support to the GMI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16usb: chipidea: tegra: Add runtime PM and OPP supportDmitry Osipenko
The Tegra USB controller belongs to the core power domain and we're going to enable GENPD support for the core domain. Now USB controller must be resumed using runtime PM API in order to initialize the USB power state. We already support runtime PM for the CI device, but CI's PM is separated from the RPM managed by tegra-usb driver. Add runtime PM and OPP support to the driver. Acked-by: Peter Chen <peter.chen@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge branch 'tegra-for-5.17-soc-opp' of ↵Thierry Reding
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into for-5.17/drivers
2021-12-16soc/tegra: pmc: Rename core power domainDmitry Osipenko
CORE power domain uses name of device-tree node, which is inconsistent with the names of PMC domains. Set the name to "core" to make it consistent. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()Dmitry Osipenko
Only couple drivers need to get the -ENODEV error code and majority of drivers need to explicitly initialize the performance state. Add new common helper which sets up OPP table for these drivers. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: pmc: Rename 3d power domainsDmitry Osipenko
Device-tree schema doesn't allow domain name to start with a number. We don't use 3d domain yet in device-trees, so rename it to the name used by Tegra TRMs: TD, TD2. Reported-by: David Heidelberg <david@ixit.cz> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Enable runtime PM during OPP state-syncingDmitry Osipenko
GENPD core now can set up domain's performance state properly while device is RPM-suspended. Runtime PM of a device must be enabled during setup because GENPD checks whether device is suspended and check doesn't work while RPM is disabled. Instead of replicating the boilerplate RPM-enable code around OPP helper for each driver, let's make OPP helper to take care of enabling it. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: regulators: Prepare for suspendDmitry Osipenko
Depending on hardware version, Tegra SoC may require a higher voltages during resume from system suspend, otherwise hardware will crash. Set SoC voltages to a nominal levels during suspend. Link: https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf057@gmail.com/ Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-07-31 18:39:01 +0000