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2022-12-06arm64: dts: qcom: sm8350-sagami: Wire up SDHCI2Konrad Dybcio
Adjust regulators, add required pin setup and finally enable SDHCI2 to get the SD Card slot going on Sagami Xperias. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116123612.34302-4-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8350-sagami: Add GPIO line names for TLMMKonrad Dybcio
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Sagami-common / PDX215 DTSIs to better document the hardware. Diff between 215 and common: < "NC", < "NC", > "WLC_I2C_SDA", > "WLC_I2C_SCL", < "NC", > "WLC_INT_N", > "CAM_MCLK4", < "NC", < "NC", > "TOF_RST_N", < "NC", < "NC", < "NC", > "QLINK1_REQ", > "QLINK1_EN", > "QLINK1_WMSS_RESET_N", It's pretty logical as 1 III has WLC (WireLess Charging), and an additional 3D iToF sensor. As for QLINK, no idea. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116123612.34302-3-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8350: Add SDHCI2Konrad Dybcio
Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be broken). Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116123612.34302-2-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: clean up 'regulator-allowed-modes' indentationJohan Hovold
When recently adding the missing 'regulator-allowed-modes' properties it appears that the binding example with its four-spaces indentation (corresponding to a single tab, which is still to little) was copied verbatim. Drop the unnecessary first line break after 'regulator-allowed-modes' properties and indent the single remaining continuation line properly. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116102054.4673-3-johan+linaro@kernel.org
2022-12-06arm64: dts: qcom: sc7280: Remove unused sleep pin control nodesSrinivasa Rao Mandadapu
Remove unused and redundant sleep pin control entries as they are not referenced anywhere in sc7280 based platform's device tree variants. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reported-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1668591184-21099-1-git-send-email-quic_srivasam@quicinc.com
2022-12-06arm64: dts: qcom: pmk8350: Specify PBS register for PONKonrad Dybcio
PMK8350 is the first PMIC to require both HLOS and PBS registers for PON to function properly (at least in theory, sm8350 sees no change). The support for it on the driver side has been added long ago, but it has never been wired up. Do so. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115132626.7465-1-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8150: Use defines for power domain indicesKonrad Dybcio
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115130936.6830-2-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8450: Use defines for power domain indicesKonrad Dybcio
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115130936.6830-1-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Enable ADSP & CDSPKonrad Dybcio
Enable the newly added remote processors and assign them a firmware path. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114105913.37044-4-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add ADSP&CDSPKonrad Dybcio
Add ADSP & CDSP remote processors. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114105913.37044-3-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add SMP2P for ADSP&CDSPKonrad Dybcio
Add nodes for ADSP&CDSP SMP2P. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114105913.37044-2-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Enable SD card slotKonrad Dybcio
Set SDHCI VMMC/VQMMC to <=2v96 and allow load setting by the SDHCI driver, as required by this use case. Configure the SD Card Detect pin, enable the SDHCI2 controller and assign it the aforementioned regulators. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114105043.36698-4-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreenKonrad Dybcio
Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-10-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulatorsKonrad Dybcio
Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-9-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Add PMIC peripheralsKonrad Dybcio
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-8-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMAKonrad Dybcio
Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-7-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add SDHCI2Konrad Dybcio
Configure the second SDHCI bus controller, which usually the interface used for SD cards. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114105043.36698-3-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hostsKonrad Dybcio
Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-6-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add pin configs for some QUP configurationsKonrad Dybcio
Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-5-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm6375: Add GPI DMA nodesKonrad Dybcio
Add nodes for GPI DMA hosts on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-4-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: pmk8350: Allow specifying arbitrary SIDKonrad Dybcio
PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-3-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8450-nagara: Add Samsung touchscreenKonrad Dybcio
Add device node and required pinctrl settings (as well as a fixup for an existing one, whoops!) to support the Samsung Electronics touchscreen on Nagara devices. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114095654.34561-4-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8450: Add Xperia 5 IV supportKonrad Dybcio
Add a device tree for the Xperia 5 IV (pdx224). It's literally the 1 IV with a smaller body, different panel, one camera lens (not sensor afaict) swapped out and no 3D iToF sensor, hence the device-specific DT is tiny. Be sure to follow the vbmeta disablement steps (detailed in pdx223 introduction commit message), otherwise your phone will not boot and will reject anything and everything with just a non-descriptive "Your device is corrupted" followed by a sad reboot. This should not be the case, as vbmeta should be plainly ignored in unlocked state, but what can we do.. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114095654.34561-3-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8450-nagara: Separate out Nagara platform dtsiKonrad Dybcio
Turns out 1 IV is not the only Nagara device, reflect that in the DTS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114095654.34561-2-konrad.dybcio@linaro.org
2022-12-06arm64: dts: qcom: sm8250: Add coresight componentsMao Jinlong
Add coresight components for sm8250. STM/ETM are added. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221114091251.13939-1-quic_jinlmao@quicinc.com
2022-12-06arm64: dts: qcom: sagit: add initial device tree for sagitDzmitry Sankouski
New device support - Xiaomi Mi6 phone What works: - storage - usb - power regulators Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konra.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221112203300.536010-3-dsankouski@gmail.com
2022-12-06arm64: dts: qcom: Add support for SONY Xperia X/X CompactAngeloGioacchino Del Regno
This adds support for the Sony Xperia Loire/SmartLoire platform with a base configuration that is common across all of the devices that are based on this project. Also adds a base DT configuration for the Xperia X and Xperia X Compact (respectively, Suzu and Kugo) which is valid for both their RoW (single-sim), DSDS (dual-sim) and other regional variants of these two smartphones, that makes us able to boot to a UART console. Please note that, currently, the APC0/1 (cluster 0/1) vregs are set to a safe voltage in order to ensure boot stability until a proper solution for CPU DVFS scaling lands. Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-12-angelogioacchino.delregno@collabora.com
2022-12-06arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCsAngeloGioacchino Del Regno
This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-11-angelogioacchino.delregno@collabora.com
2022-12-06arm64: dts: qcom: Add configuration for PMI8950 peripheralAngeloGioacchino Del Regno
The PMI8950 features integrated peripherals like ADC, GPIO controller, MPPs and others. [luca@z3ntu.xyz: remove pm8950, style changes for 2022 standards, add wled] Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221101161801.1058969-2-luca@z3ntu.xyz
2022-12-06arm64: dts: qcom: Add configuration for PM8950 peripheralAngeloGioacchino Del Regno
The PM8950 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add them to DT files that will be imported on boards having this PMIC combo (or one of them, anyways). Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-10-angelogioacchino.delregno@collabora.com
2022-12-06arm64: dts: qcom: sm8250: fix USB-DP PHY registersJohan Hovold
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 5aa0d1becd5b ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode") Cc: stable@vger.kernel.org # 5.13 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111094729.11842-3-johan+linaro@kernel.org
2022-12-06arm64: dts: qcom: sm6350: fix USB-DP PHY registersJohan Hovold
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes") Cc: stable@vger.kernel.org # 5.16 Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111094729.11842-2-johan+linaro@kernel.org
2022-12-06arm64: dts: qcom: sc8280xp: drop reference-clock sourceJohan Hovold
The source clock for the reference clock should not be described by the devicetree binding and instead this relationship should be modelled in the clock driver. Update the USB PHY nodes to match the fixed binding. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111093857.11360-4-johan+linaro@kernel.org
2022-12-06arm64: dts: qcom: sc8280xp: Add bwmon instancesBjorn Andersson
Add the two bwmon instances and define votes for CPU -> LLCC and LLCC -> DDR, with bandwidth values based on the downstream DeviceTree. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-11-quic_bjorande@quicinc.com
2022-12-06arm64: dts: qcom: sc8280xp: Set up L3 scalingBjorn Andersson
Add the L3 interconnect path to all CPUs and define the bandwidth requirements for all opp entries across sc8280xp and sa8540p. The values are based on the tables reported by the hardware, distributed such that each value is the largest value, lower than the cluster frequency. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-9-quic_bjorande@quicinc.com
2022-12-06arm64: dts: qcom: sc8280xp: Add epss_l3 nodeBjorn Andersson
Add a device node for the EPSS L3 frequency domain. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-8-quic_bjorande@quicinc.com
2022-12-06arm64: dts: qcom: Align with generic osm-l3/epss-l3Bjorn Andersson
Update all references to OSM or EPSS L3 compatibles, to include the generic compatible, as defined by the updated binding. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111032515.3460-7-quic_bjorande@quicinc.com
2022-12-06arm64: dts: qcom: sc8280xp: update UFS PHY nodesJohan Hovold
Update the UFS PHY nodes to match the new binding. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104092045.17410-3-johan+linaro@kernel.org
2022-12-06arm64: dts: qcom: ipq6018: improve pcie phy pcs reg tableChristian Marangi
This is not a fix on its own but more a cleanup. Phy qmp pcie driver currently have a workaround to handle pcs_misc not declared and add 0x400 offset to the pcs reg if pcs_misc is not declared. Correctly declare pcs_misc reg and reduce PCS size to the common value of 0x1f0 as done for every other qmp based pcie phy device. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
2022-12-06arm64: dts: qcom: sc7180-trogdor: Remove VBAT supply from rt5682sNícolas F. R. A. Prado
These devicetrees override a rt5682 node to use the rt5682s compatible, however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the inexistent supply in the rt5682s nodes. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102182002.255282-9-nfraprado@collabora.com
2022-12-06arm64: dts: qcom: sc7180-trogdor: Add missing supplies for rt5682Nícolas F. R. A. Prado
The DBVDD and LDO1-IN supplies for rt5682 are required but are missing. They are supplied by the same power rail as AVDD. Add them. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102182002.255282-8-nfraprado@collabora.com
2022-12-06arm64: dts: qcom: sa8295p-adp: Add RTC nodeBjorn Andersson
The first PM8540 PMIC has an available RTC block, describe this in the SA8295P ADP. Mark it as wakeup-source to allow waking the system from sleep. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221205174309.16733-1-quic_bjorande@quicinc.com
2022-12-06NFS: avoid spurious warning of lost lock that is being unlocked.NeilBrown
When the NFSv4 state manager recovers state after a server restart, it reports that locks have been lost if it finds any lock state for which recovery hasn't been successful. i.e. any for which NFS_LOCK_INITIALIZED is not set. However it only tries to recover locks that are still linked to inode->i_flctx. So if a lock has been removed from inode->i_flctx, but the state for that lock has not yet been destroyed, then a spurious warning results. nfs4_proc_unlck() calls locks_lock_inode_wait() - which removes the lock from ->i_flctx - before sending the unlock request to the server and before the final nfs4_put_lock_state() is called. This allows a window in which a spurious warning can be produced. So add a new flag NFS_LOCK_UNLOCKING which is set once the decision has been made to unlock the lock. This will prevent it from triggering any warning. Signed-off-by: NeilBrown <neilb@suse.de> Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
2022-12-06nfs: fix possible null-ptr-deref when parsing paramHawkins Jiawei
According to commit "vfs: parse: deal with zero length string value", kernel will set the param->string to null pointer in vfs_parse_fs_string() if fs string has zero length. Yet the problem is that, nfs_fs_context_parse_param() will dereferences the param->string, without checking whether it is a null pointer, which may trigger a null-ptr-deref bug. This patch solves it by adding sanity check on param->string in nfs_fs_context_parse_param(). Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Reviewed-by: Jeff Layton <jlayton@kernel.org> Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
2022-12-06NFSv4: check FMODE_EXEC from open context mode in nfs4_opendata_access()ChenXiaoSong
After converting file f_flags to open context mode by flags_to_mode(), open context mode will have FMODE_EXEC when file open for exec, so we check FMODE_EXEC from open context mode. No functional change, just simplify the code. Signed-off-by: ChenXiaoSong <chenxiaosong2@huawei.com> Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
2022-12-06NFS: make sure open context mode have FMODE_EXEC when file open for execChenXiaoSong
Because file f_mode never have FMODE_EXEC, open context mode won't get FMODE_EXEC from file f_mode. Open context mode only care about FMODE_READ/ FMODE_WRITE/FMODE_EXEC, and all info about open context mode can be convert from file f_flags, so convert file f_flags to open context mode by flags_to_mode(). Signed-off-by: ChenXiaoSong <chenxiaosong2@huawei.com> Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
2022-12-06s390/nmi: get rid of private slab cacheHeiko Carstens
Get rid of private "nmi_save_areas" slab cache. The only reason this was introduced years ago was that with some slab debugging options allocations would only guarantee a minimum alignment of ARCH_KMALLOC_MINALIGN, which was eight bytes back then. This is not sufficient for the extended machine check save area. However since commit 59bb47985c1d ("mm, sl[aou]b: guarantee natural alignment for kmalloc(power-of-two)") kmalloc guarantees a power-of-two alignment even with debugging options enabled. Therefore the private slab cache can be removed. Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-06s390/nmi: move storage error checking back to C, enter with DAT onHeiko Carstens
Checking for storage errors in machine check entry code was done in order to handle also storage errors on kernel page tables. However this is extremely unlikely and some basic assumptions what works on machine check entry are necessary anyway. In order to simplify machine check handling delay checking for storage errors to C code. With this also change the machine check new PSW to have DAT on, which simplifies the entry code even further. Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-06s390/nmi: print machine check interruption code before stopping systemHeiko Carstens
In case a system will be stopped because of e.g. missing validity bits print the machine check interruption code before the system is stopped. This is helpful, since up to now no message was printed in such a case. Only a disabled wait PSW was loaded, which doesn't give a hint of what went wrong. Improve this by printing a message with debug information. Reviewed-by: Peter Oberparleiter <oberpar@linux.ibm.com> Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2022-12-06s390/sclp: introduce sclp_emergency_printk()Heiko Carstens
Introduce sclp_emergency_printk() which can be used to emit a message in emergency cases. sclp_emergency_printk() is only supposed to be used in cases where it can be assumed that regular console device drivers may not work anymore. For example this may be the case for unrecoverable machine checks. Reviewed-by: Peter Oberparleiter <oberpar@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
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