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Add entry for Nothing Technology Limited (https://nothing.tech/)
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-5-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The Qualcomm Snapdragon 778G/778G+/780G/782G uses CPUs named Kryo 670.
Add the compatible string in the documentation.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241020205615.211256-3-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document two supplies that are used by this model and the optional
xo-clk signal.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20241018-sc8280xp-pwrseq-v6-1-8da8310d9564@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Convert Linear Technology LTC3676 8-output I2C voltage regulator IC
DT bindings to DT schema. Add missing interrupts: property as this
IC does have interrupt line and it is used in existing DTs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://patch.msgid.link/20241016225235.114635-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
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BLK CTRL
Sort compatible entries by alphabetical order.
Then, add compatible string "nxp,imx95-hsio-blk-ctl" for i.MX95.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1728977644-8207-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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Document support for defining a partition table in the mmc-card node.
This is needed if the eMMC doesn't have a partition table written and
the bootloader of the device load data by using absolute offset of the
block device. This is common on embedded device that have eMMC installed
to save space and have non removable block devices.
If an OF partition table is detected, any partition table written in the
eMMC will be ignored and won't be parsed.
eMMC provide a generic disk for user data and if supported (JEDEC 4.4+)
also provide two additional disk ("boot1" and "boot2") for special usage
of boot operation where normally is stored the bootloader or boot info.
New JEDEC version also supports up to 4 GP partition for other usage
called "gp1", "gp2", "gp3", "gp4".
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241002221306.4403-7-ansuelsmth@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
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Add devicetree binding for FriendlyARM NanoPi R3S.
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241020173946.225960-1-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add device tree documentation for Radxa E20C board.
Link: https://docs.radxa.com/en/e/e20c
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20240829092705.6241-3-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add devicetree binding for the ArmSoM Sige 5 board.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240903152308.13565-2-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Document compatibles for Qualcomm SM8750 SoC macro digital codecs (RX,
TX, VA and WSA), compatible with previous generation (SM8550 and
SM8650).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20241022064155.22800-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add bindings for the pin controller (TLMM) present on the
Qualcomm SAR2130P platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-1-11a1d09a6e5f@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add DT bindings for the TLMM controller on QCS8300 platforms.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/20241018-qcs8300_tlmm-v3-1-8b8d3957cf1a@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The ES8328/ES8388 audio codec is currently used in conjunction with
audio-graph-card to provide an endpoint for binding with the other side
of the audio link.
This is achieved via the 'port' property, which is not supported by the
binding:
rk3588s-indiedroid-nova.dtb: audio-codec@11: 'port' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/sound/everest,es8328.yaml#
Document the missing property.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20241019-es8328-doc-port-v1-1-25c1d1b5c65c@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add DT binding for MediaTek MT6735 SCPSYS power controller.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogiaocchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017085136.68053-2-y.oudjana@protonmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document compatible for RPMh power domain controller on SAR2130P platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-rpmhpd-v1-1-f4bf7f6fd12e@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document QCS8300 BWMONs, which has two BWMONv4 instances for the CPU->LLCC
path and one BWMONv5 instance for LLCC->DDR path.
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240925-qcs8300_bwmon_binding-v1-1-a7bfd94b2854@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Add bindings for the Network of Connects (NoC) present on the
Qualcomm SAR2130P platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241018-sar2130p-icc-v2-1-c58c73dcd19d@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
per HW instance (so potentially up to six displays for multi-vdo SoCs).
The MMSYS or VDOSYS is always the first component in the DDP pipeline,
so it only supports an output port with multiple endpoints - where each
endpoint defines the starting point for one of the (currently three)
possible hardware paths.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200
Link: https://lore.kernel.org/r/20241017103809.156056-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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QCS615 SoC
Document the RPMh Network-On-Chip Interconnect of the QCS615 platform.
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240924143958.25-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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QCS8300 SoC
Document the RPMh Network-On-Chip Interconnect of the QCS8300 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20240910101013.3020-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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The ST M24256E behaves as a regular M24C256, except for the E variant
which uses up another I2C address for Additional Write lockable page.
This page is 64 Bytes long and can contain additional data. Add entry
for it, so users can describe that page in DT. Note that users still
have to describe the main M24C256 area separately as that is on separate
I2C address from this page.
Unlike M24C32-D and M24C64-D, this part is specifically ST and does not
have any comparable M24* counterparts from other vendors, hence the st,
vendor prefix. Furthermore, the part name is M24256E without C between
the 24 and 256, this is not a typo. Finally, there is M24C256-D part,
which does contain 32 Bytes long Additional Write lockable page, which
is a different part and not supported by this patch.
Datasheet: https://www.st.com/resource/en/datasheet/m24256e-f.pdf
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20241017184152.128395-1-marex@denx.de
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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Document the DH electronics i.MX6DL DHCOM SoM and a PDK2 evaluation board.
The evaluation board features three serial ports, USB OTG, USB host with
an USB hub, Fast or Gigabit ethernet, eMMC, uSD, SD, analog audio, PCIe
and HDMI video output.
All of the aforementioned features except for mSATA are supported, mSATA
is not available on i.MX6DL and is only available on DHCOM populated with
i.MX6Q SoC which is already supported upstream.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Merge series from Chris Packham <chris.packham@alliedtelesis.co.nz>:
This series adds support for the SPI-NAND flash controller on the RTL9300
family of SoCs.
There are 2 physical chip selects which are called SPI_MST_CS0 and SPI_MST_CS1
in the datasheet. Via some pin-strapping these can be assigned to either the
SPI-NOR controller or the SPI-NAND controller. Which means you can end up with
the following permutations
SPI-Flash
Boot Model SPI_MST_CS0 SPI_MST_CS1
---------- ----------- -----------
NOR x1 NOR-CS0 X
NOR x2 NOR-CS0 NOR-CS1
NAND x1 NAND-CS0 X
NAND x2 NAND-CS0 NAND-CS1
NOR+NAND NOR-CS0 NAND-CS0
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Lan969x is going to reuse the existing Sparx5 SERDES driver - document
that by adding compatible strings for the different SKU's that we
support, and a short description of the SERDES types and data rates
supported.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-8-d695bcb57b84@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The old binding variant (the one covering whole DMU block) was
deprecated 3 years ago. Linux kernel was warning when using it for
similar amount of time.
There aren't any known Northstar devices with bootloader providing DT to
operating system. Actually OpenWrt seems to be the only project using
this binding and it always appends DTB to kernel. It has switched to the
non-deprecated binding years ago.
Given there is close to zero chance this breaks anyone's setup it should
more than safe to drop this binding variant after 3 years.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240913044557.28315-1-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Add dt bindings for AD7779 8-channel, simultaneous sampling ADC
family with eight full Σ-Δ ADCs on chip and ultra-low input
current to allow direct sensor connection.
Signed-off-by: Ramona Alexandra Nechita <ramona.nechita@analog.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20241014143204.30195-2-ramona.nechita@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Add the required properties for iio-backend support, as well as an
example and the conditions to mutually exclude interruption and
conversion trigger with iio-backend.
The iio-backend's function is to controls the communication, and thus the
interruption pin won't be available anymore.
As a consequence, the conversion pin must be controlled externally since
we will miss information about when every single conversion cycle (i.e
conversion + data transfer) ends, hence a PWM is introduced to trigger
the conversions.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Guillaume Stols <gstols@baylibre.com>
Link: https://patch.msgid.link/20241015-ad7606_add_iio_backend_support-v5-2-654faf1ae08c@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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The documentation is erroneously stating that spi-cpha is required, and
the example is erroneously setting both spi-cpol and spi-cpha. According
to the datasheet, only cpol should be set.
On zedboard for instance, setting the devicetree as in the example will
simply not work.
Fixes: 416f882c3b40 ("dt-bindings: iio: adc: Migrate AD7606 documentation to yaml")
Fixes: 6e33a125df66 ("dt-bindings: iio: adc: Add docs for AD7606 ADC")
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Guillaume Stols <gstols@baylibre.com>
Link: https://patch.msgid.link/20241015-ad7606_add_iio_backend_support-v5-1-654faf1ae08c@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Add interrupt options for BMP3xx and BMP5xx devices as well.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Vasileios Amoiridis <vassilisamir@gmail.com>
Link: https://patch.msgid.link/20241017233022.238250-3-vassilisamir@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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add devicetree binding for Bosch imu smi240.
The smi240 is a combined three axis angular rate and
three axis acceleration sensor module.
* The smi240 requires VDD and VDDIO
* Provides only spi interface.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Shen Jianping <Jianping.Shen@de.bosch.com>
Link: https://patch.msgid.link/20241018135234.5446-2-Jianping.Shen@de.bosch.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Document the QMP UFS PHY compatible for Qualcomm QCS8300 to support
physical layer functionality for UFS found on the SoC. Use fallback to
indicate the compatibility of the QMP UFS PHY on the QCS8300 with that
on the SA8775P.
Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241018-qcs8300_ufs_phy_binding-v4-1-261c7c5fb8ff@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document the Synopsys eUSB2 PHY on the SAR2130P platform by using
the SM8550 as fallback.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-eusb2-v1-1-1cedd674ec64@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The PCIe 6a PHY is actually Gen4 4-lanes capable. So the gen4x4 compatible
describes it. But according to the schema, currently the gen4x4 compatible
doesn't require both PHY and PHY-nocsr resets, while the HW does. So fix
that by adding the gen4x4 compatible alongside the gen4x2 one for the
resets description.
Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241021-phy-qcom-qmp-pcie-fix-x1e80100-gen4x4-resets-v3-1-1918c46fc37c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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PIC64GX is compatible as out of order DMA capable, just like the MPFS
version, therefore we add it with microchip,mpfs-pdma as a fallback
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240930095449.1813195-10-pierre-henry.moussay@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Some devices require a single transfer. For example, reading FMC ECC status
registers does not support multiple transfers.
Add the possibility to prevent additional transfers, by setting bit 17 of
the 'DMA transfer requirements' bit mask.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-4-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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When source data width/burst and destination data width/burst are
different, data are packed or unpacked in DMA3 channel FIFO.
Data are pushed out from DMA3 channel FIFO when the destination burst
length (= data width * burst) is reached.
If the channel is stopped before the transfer end, and if some bytes are
packed/unpacked in the DMA3 channel FIFO, these bytes are lost.
Indeed, DMA3 channel FIFO has no flush capability, only reset.
To avoid potential bytes lost, pack/unpack must be prevented by setting
memory data width/burst equal to peripheral data width/burst.
Memory accesses will be penalized. But it is the only way to avoid bytes
lost.
Some devices (e.g. cyclic RX like UART) need this, so add the possibility
to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer
requirements' bit mask.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241016-dma3-mp25-updates-v3-1-8311fe6f228d@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Document compatible for GPI DMA controller on SAR2130P platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-dma-v1-1-e6aa6789f116@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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The usb2phy is accessible via a syscon registers on RK3576, similar
to RK3588.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241016073713.14133-2-frawang.cn@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add rockchip,rk3576-vo1-grf syscon compatible, the vo1-grf is
configured in usbdp phy driver.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20241017025230.28752-1-frawang.cn@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add bindings for the MediaTek Dynamic Voltage and Frequency Scaling
Resource Collector (DVFSRC), a hardware module used to collect all the
requests from both software and the various remote processors embedded
into the SoC and decide about a minimum operating voltage and a minimum
DRAM frequency to fulfill those requests in an effort to provide the
best achievable performance per watt.
This hardware IP is capable of transparently performing direct register
R/W on all of the DVFSRC-controlled regulators and SoC bandwidth knobs.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Add support for AGX Orin Industrial Module with AGX Orin Developer Kit.
Signed-off-by: Dara Stotland <dstotland@nvidia.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The SI9022 HDMI transmitter can be configured with a bus-width of 16,
18, or 24 bits. Introduce a bus-width property to the input endpoint,
specifying the number of parallel RGB input bits connected to the
transmitter.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017085556.3045686-2-w.egorov@phytec.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241017085556.3045686-2-w.egorov@phytec.de
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"data-lines" property is way too similar to "data-lanes". It is also
duplicating "bus-width" from video-interfaces.yaml schema. Deprecate
"data-lines" and use the common property.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241003133904.69244-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241003133904.69244-1-krzysztof.kozlowski@linaro.org
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The display IPs in MediaTek SoCs support being interconnected with
different instances of DDP IPs (for example, merge0 or merge1) and/or
with different DDP IPs (for example, rdma can be connected with either
color, dpi, dsi, merge, etc), forming a full Display Data Path that
ends with an actual display.
The final display pipeline is effectively board specific, as it does
depend on the display that is attached to it, and eventually on the
sensors supported by the board (for example, Adaptive Ambient Light
would need an Ambient Light Sensor, otherwise it's pointless!), other
than the output type.
Add support for OF graphs to most of the MediaTek DDP (display) bindings
to add flexibility to build custom hardware paths, hence enabling board
specific configuration of the display pipeline and allowing to finally
migrate away from using hardcoded paths.
Please note that - while this commit retains retro-compatibility with
old device trees - it will break the ABI for mediatek,dsi and for
mediatek,dpi for the sake of consistency between the `ports` in all
MediaTek DRM drivers versus DRM bridge drivers as in the previous
binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT,
while now the first port is an INPUT, and the second one is an OUTPUT,
which is consistent with other DRM drivers which can be chained to
drm/mediatek.
As for maintainability concerns, I am aware that the old device tree
will not be actively tested anymore, but retrocompatibility breakages
will *not* be more likely to happen in the future because any addition
to the graph (new drivers) will be done only for features present on
newer SoCs, keeping the old ones (and their default pipeline) untouched.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Tested-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
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According to the vendor kernel, the Exynos8895 SoC has an SPI
configuration that matches with the Exynos850 one.
SPI FIFO depth is 64 bytes for all SPI blocks. All blocks have DIV_4
as the default internal clock divider, and an internal loopback mode
to run a loopback test.
Reuse the samsung,exynos850-spi compatible.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20241020182121.377969-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add a dtschema for the SPI-NAND controller on the RTL9300 SoCs. The
controller supports
* Serial/Dual/Quad data with
* PIO and DMA data read/write operation
* Configurable flash access timing
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20241015225434.3970360-2-chris.packham@alliedtelesis.co.nz
Signed-off-by: Mark Brown <broonie@kernel.org>
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Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/620494/
Link: https://lore.kernel.org/r/20241019-patchv3_1-v5-2-d2fb72c9a845@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Document the MDSS hardware found on the Qualcomm SA8775P platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/620492/
Link: https://lore.kernel.org/r/20241019-patchv3_1-v5-1-d2fb72c9a845@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Split of the bindings was artificial and not helping - we end up with
multiple binding files for very similar devices thus increasing the
chances of using different order of reg and clocks entries.
Unify DPU bindings of SC7280 and SM8550, because they are the same.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/617874/
Link: https://lore.kernel.org/r/20241003-dt-binding-display-msm-merge-v1-5-91ab08fc76a2@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Split of the bindings was artificial and not helping - we end up with
multiple binding files for very similar devices thus increasing the
chances of using different order of reg and clocks entries.
Unify DPU bindings of SC7280 and SM8450, because they are the same.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/617873/
Link: https://lore.kernel.org/r/20241003-dt-binding-display-msm-merge-v1-4-91ab08fc76a2@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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