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path: root/arch/mips/pci/fixup-loongson3.c
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2017-09-21MIPS: PCI: fix pcibios_map_irq section mismatchManuel Lauss
Drop the __init from pcibios_map_irq() to make this section mis- match go away: WARNING: vmlinux.o(.text+0x56acd4): Section mismatch in reference from the function pcibios_scanbus() to the function .init.text:pcibios_map_irq() The function pcibios_scanbus() references the function __init pcibios_map_irq(). This is often because pcibios_scanbus lacks a __init annotation or the annotation of pcibios_map_irq is wrong. Run-Tested only on Alchemy. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17267/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-12MIPS: Loongson 3: Keep CPU physical (not virtual) addresses in shadow ROM ↵Bjorn Helgaas
resource Loongson 3 used the IORESOURCE_ROM_COPY flag for its ROM resource. There are two problems with this: - When IORESOURCE_ROM_COPY is set, pci_map_rom() assumes the resource contains virtual addresses, so it doesn't ioremap the resource. This implies loongson_sysconf.vgabios_addr is a virtual address. That's a problem because resources should contain CPU *physical* addresses not virtual addresses. - When IORESOURCE_ROM_COPY is set, pci_cleanup_rom() calls kfree() on the resource. We did not kmalloc() the loongson_sysconf.vgabios_addr area, so it is incorrect to kfree() it. If we're using a shadow copy in RAM for the Loongson 3 VGA BIOS area, disable the ROM BAR and release the address space it was consuming. Use IORESOURCE_ROM_SHADOW instead of IORESOURCE_ROM_COPY. This means the struct resource contains CPU physical addresses, and pci_map_rom() will ioremap() it as needed. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-03-12MIPS: Loongson 3: Use temporary struct resource * to avoid repetitionBjorn Helgaas
Use a temporary struct resource pointer to avoid needless repetition of "pdev->resource[PCI_ROM_RESOURCE]". No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-03-31MIPS: Loongson 3: Add HT-linked PCI supportHuacai Chen
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>