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path: root/drivers/clk/imx
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2022-06-03Merge tag 'driver-core-5.19-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is the set of driver core changes for 5.19-rc1. Lots of tiny driver core changes and cleanups happened this cycle, but the two major things are: - firmware_loader reorganization and additions including the ability to have XZ compressed firmware images and the ability for userspace to initiate the firmware load when it needs to, instead of being always initiated by the kernel. FPGA devices specifically want this ability to have their firmware changed over the lifetime of the system boot, and this allows them to work without having to come up with yet-another-custom-uapi interface for loading firmware for them. - physical location support added to sysfs so that devices that know this information, can tell userspace where they are located in a common way. Some ACPI devices already support this today, and more bus types should support this in the future. Smaller changes include: - driver_override api cleanups and fixes - error path cleanups and fixes - get_abi script fixes - deferred probe timeout changes. It's that last change that I'm the most worried about. It has been reported to cause boot problems for a number of systems, and I have a tested patch series that resolves this issue. But I didn't get it merged into my tree before 5.18-final came out, so it has not gotten any linux-next testing. I'll send the fixup patches (there are 2) as a follow-on series to this pull request. All have been tested in linux-next for weeks, with no reported issues other than the above-mentioned boot time-outs" * tag 'driver-core-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (55 commits) driver core: fix deadlock in __device_attach kernfs: Separate kernfs_pr_cont_buf and rename_lock. topology: Remove unused cpu_cluster_mask() driver core: Extend deferred probe timeout on driver registration MAINTAINERS: add Russ Weight as a firmware loader maintainer driver: base: fix UAF when driver_attach failed test_firmware: fix end of loop test in upload_read_show() driver core: location: Add "back" as a possible output for panel driver core: location: Free struct acpi_pld_info *pld driver core: Add "*" wildcard support to driver_async_probe cmdline param driver core: location: Check for allocations failure arch_topology: Trace the update thermal pressure kernfs: Rename kernfs_put_open_node to kernfs_unlink_open_file. export: fix string handling of namespace in EXPORT_SYMBOL_NS rpmsg: use local 'dev' variable rpmsg: Fix calling device_lock() on non-initialized device firmware_loader: describe 'module' parameter of firmware_upload_register() firmware_loader: Move definitions from sysfs_upload.h to sysfs.h firmware_loader: Fix configs for sysfs split selftests: firmware: Add firmware upload selftests ...
2022-05-17clk: imx8mp: fix usb_root_clk parentPeng Fan
According to reference mannual CCGR77(usb) sources from hsio_axi, fix it. Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220507125430.793287-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-05-02clk: imx8mp: add clkout1/2 supportLucas Stach
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220427162131.3127303-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-05-02clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usageMiaoqian Lin
If the device is already in a runtime PM enabled state pm_runtime_get_sync() will return 1. Also, we need to call pm_runtime_put_noidle() when pm_runtime_get_sync() fails, so use pm_runtime_resume_and_get() instead. this function will handle this. Fixes: 78edeb080330 ("clk: imx: scu: add runtime pm support") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220425011117.25093-1-linmq006@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-22clk: imx: scu: Fix kfree() of static memory on setting driver_overrideKrzysztof Kozlowski
The driver_override field from platform driver should not be initialized from static memory (string literal) because the core later kfree() it, for example when driver_override is set via sysfs. Use dedicated helper to set driver_override properly. Fixes: 77d8f3068c63 ("clk: imx: scu: add two cells binding support") Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220419113435.246203-10-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-18clk: imx8mp: Add DISP2 pixel clockMarek Vasut
Add pixel clock for second LCDIFv3 interface. Both LCDIFv3 interfaces use the same set of parent clock, so deduplicate imx8mp_media_disp1_pix_sels into common imx8mp_media_disp_pix_sels and use it for both. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220313123949.207284-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu()Xiaoke Wang
In __imx_clk_gpr_scu(), if imx_scu_clk_is_valid(rsrc_id) fails, then `clk_node` which is allocated by kzalloc() is not properly released, which may lead to memory leak. So this patch added kfree(clk_node) on the above error path before return ERR_PTR(-EINVAL). Signed-off-by: Xiaoke Wang <xkernel.wang@foxmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/tencent_27FF59903EE6AB5C0D0E6D0A8E7059A59007@qq.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx: Add check for kcallocJiasheng Jiang
As the potential failure of the kcalloc(), it should be better to check it in order to avoid the dereference of the NULL pointer. Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220310080257.1988412-1-jiasheng@iscas.ac.cn Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx8mn: add GPT supportAlvin Šipraga
Add support for the General Purpose Timer (GPT) clocks on the i.MX8MN. The i.MX8MN GPT IP block is the same as on the i.MX8MM, on which this patch is based. Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220317223600.175894-2-alvin@pqrs.dk Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx: Remove the snvs clockJacky Bai
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220310093404.236966-1-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx8m: check mcore_booted before register clkPeng Fan
If mcore_booted is true, ignore the clk root gate registration and this will simplify AMP clock management and avoid system hang unexpectly especially Linux shutdown clk used by mcore. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-2-peng.fan@oss.nxp.com [abelvesa@kernel.org: Removed if-case for when mcore_booted is true] Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-12clk: imx: add mcore_booted module paratemterPeng Fan
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX8M, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and CCGR (clock gating) to gate clocks to peripherals. As below: anatop->ccm->ccgr->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for CCGR and CCM, auxiliary core normally only use CCGR hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Per NXP hardware design, because CCGR already support gate to peripherals, and clk root gate power leakage is negligible. So when in AMP case, we could not register the clk root gate. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-04-07clk: imx8mq: add 27m phy pll ref clockPeng Fan
According to pll documentation, the 3rd pll ref clock should be hdmi phy 27m clock, not dummy clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225090002.2497057-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-15clk: imx: Select MXC_CLK for i.MX93 clock driverAbel Vesa
Most of the i.MX clock generic API is built by selecting MXC_CLK. Without it, the i.MX93 clock driver will fail to build: aarch64-linux-gnu-ld: drivers/clk/imx/clk-imx93.o: in function `imx93_clocks_probe': clk-imx93.c:(.text+0xa8): undefined reference to `imx_obtain_fixed_clk_hw' So fix this by selecting MXC_CLK for the CLK_IMX93. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20220315082446.3120850-1-abel.vesa@nxp.com Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-09clk: imx: remove redundant re-assignment of pll->baseColin Ian King
There are two identical assignments of pll->base to the same value, the second assignment is redundant and can be removed. Cleans up cppcheck warning: drivers/clk/imx/clk-sscg-pll.c:528:12: style: Variable 'pll->base' is reassigned a value before the old one has been used. [redundantAssignment] Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20220303090508.1125175-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-04clk: imx: pll14xx: Support dynamic ratesSascha Hauer
The pll1443x PLL so far only supports rates from a rate table passed during initialization. Calculating PLL settings dynamically helps audio applications to get their desired rates, so support for this is added in this patch. The strategy to get to the PLL setting for a rate is: - First try to only adjust kdiv which specifies the fractional part of the PLL. This setting can be changed without glitches on the output and is therefore preferred - When that isn't possible then the rate table is searched for suitable rates, so for standard rates the same settings are used as without this patch - As a last resort the best settings are calculated dynamically The code in this patch is based on patches from Adrian Alonso <adrian.alonso@nxp.com> and Mads Bligaard Nielsen <bli@bang-olufsen.dk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-9-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: Add pr_fmtSascha Hauer
Print all messages from within the pll14xx driver with a common prefix using pr_fmt. No need to print function names anymore, so drop them from the messages. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-8-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: explicitly return lowest rateSascha Hauer
clk_pll14xx_round_rate() returns the lowest rate by indexing into the rate table with the variable i. i is actually pll->rate_count as this is the value we come out of the loop with. Use pll->rate_count explicitly to make it a bit more clear what is being done. While at it fix a typo in the comment. No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-7-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: name variables after usageSascha Hauer
In clk_pll1443x_set_rate() 'tmp' is used for the content of different registers which makes it a bit hard to follow. Use different variables named after the registers to make it clearer. No functional change intended. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-6-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: consolidate rate calculationSascha Hauer
The PLL driver has support for two different PLLs: The pll1416x and the pll1443x. The latter has support for an additional kdiv value. recalc_rate can be the same calculation when kdiv is assumed to be zero for the PLL which doesn't support that value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-5-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: Use FIELD_GET/FIELD_PREPSascha Hauer
Linux has these marvelous FIELD_GET/FIELD_PREP macros for easy access to bitfields in registers. Use them and remove the now unused *_SHIFT defines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-4-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: Drop wrong shiftingSascha Hauer
The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK already contains the shifted value, so shifting it again is wrong. No functional change though as SDIV_SHIFT is zero. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-3-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: pll14xx: Use register defines consistentlySascha Hauer
The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220304125256.2125023-2-s.hauer@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx8mp: remove SYS PLL 1/2 clock gatesPeng Fan
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx8mn: remove SYS PLL 1/2 clock gatesPeng Fan
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx8mm: remove SYS PLL 1/2 clock gatesPeng Fan
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: add i.MX93 clkPeng Fan
Add i.MX93 clk driver. i.MX93 clk hardware design is different compared with i.MX8M. It supports 4 sources for each clk root and the sources are separated into a few groups, low speed/fast io/audio and etc. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-6-peng.fan@oss.nxp.com [abel.vesa@nxp.com: Added missing module license and description] Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: support fracn gppllPeng Fan
This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: add i.MX93 composite clkPeng Fan
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx: off by one in imx_lpcg_parse_clks_from_dt()Dan Carpenter
The > needs to be >= to prevent an off by one access. Fixes: d5f1e6a2bb61 ("clk: imx: imx8qxp-lpcg: add parsing clocks from device tree") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20220228075014.GD13685@kili Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-03-04clk: imx7d: Remove audio_mclk_root_clkAbel Vesa
The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), but according to the reference manual, there is no such gate. The CCGR121 belongs to ECSPI2 and it is not shared. Fixes: 8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support") Reported-by: David Wolfe <david.wolfe@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220127141052.1900174-2-abel.vesa@nxp.com
2022-02-21clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clockLaurent Pinchart
The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the media_mipi_phy1_ref clock and is gated by the shared media clock gate. Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its definition is missing from the driver. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Paul Elder <paul.elder@ideasonboard.com> Link: https://lore.kernel.org/r/20220211091311.28146-1-laurent.pinchart@ideasonboard.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-01-29clk: imx: Add imx8dxl clk driverJacky Bai
Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1639747533-9778-1-git-send-email-abel.vesa@nxp.com
2022-01-29clk: imx: Add initial support for i.MXRT1050 clock driverJesse Taube
Add clock driver support for i.MXRT1050. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Suggested-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220111215415.2075257-6-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2022-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have a couple patches in the framework core this time around but they're mostly minor cleanups and some debugfs stuff. The real work that's in here is the typical pile of clk driver updates and new SoC support. Per usual (or maybe just recent trends), Qualcomm gains a handful of SoC drivers additions and has the largest diffstat. After that there are quite a few updates to the Allwinner (sunxi) drivers to support modular drivers and Renesas is heavily updated to add more support for various clks. Overall it looks pretty normal. New Drivers: - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770 - MediaTek mt7986 SoC basic support - Clock and reset driver for Toshiba Visconti SoCs - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) - Allwinner D1 clks - Lan966x Generic Clock Controller driver and associated DT bindings - Qualcomm SDX65, SM8450, and MSM8976 GCC clks - Qualcomm SDX65 and SM8450 RPMh clks Updates: - Set suppress_bind_attrs to true for i.MX8ULP driver - Switch from do_div to div64_ul for throughout all i.MX drivers - Fix imx8mn_clko1_sels for i.MX8MN - Remove unused IPG_AUDIO_ROOT from i.MX8MP - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - Refactoring of the CPU clocks registration to use common interface - An update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - Prep for runtime PM and generic power domains on Tegra - Support modular Allwinner clk drivers via platform bus - Lan966x clock driver extended to support clock gating - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and thermal (TSU) clocks and resets on Renesas RZ/G2L - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock drivers, and in the Renesas SDHI driver - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC - Add GPU clock and resets on Renesas RZ/G2L - Add clk-provider.h to various Qualcomm clk drivers - devm version of clk_hw_register_gate() - kerneldoc fixes in a couple drivers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits) clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() clk: mediatek: add mt7986 clock support clk: mediatek: add mt7986 clock IDs dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper clk: x86: Fix clk_gate_flags for RV_CLK_GATE clk: x86: Use dynamic con_id string during clk registration ACPI: APD: Add a fmw property clk-name drivers: acpi: acpi_apd: Remove unused device property "is-rv" x86: clk: clk-fch: Add support for newer family of AMD's SOC clk: ingenic: Add MDMA and BDMA clocks dt-bindings: clk/ingenic: Add MDMA and BDMA clocks clk: bm1880: remove kfrees on static allocations clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent clk: Enable/Disable runtime PM for clk_summary MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver ...
2022-01-11Merge branches 'clk-nvidia', 'clk-imx', 'clk-samsung' and 'clk-qcom' into ↵Stephen Boyd
clk-next * clk-nvidia: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114 * clk-imx: clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true * clk-samsung: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks * clk-qcom: (25 commits) clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock ...
2021-12-02clk: imx: use module_platform_driverMiles Chen
Replace builtin_platform_driver_probe with module_platform_driver_probe because CONFIG_CLK_IMX8QXP can be set to =m (kernel module). Fixes: e0d0d4d86c766 ("clk: imx8qxp: Support building i.MX8QXP clock driver as module") Cc: Fabio Estevam <festevam@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210904235418.2442-1-miles.chen@mediatek.com Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-12-02clk: imx: pllv1: fix kernel-doc notation for struct clk_pllv1Randy Dunlap
Convert struct clk_pllv1 comments to kernel-doc notation and move them below the MFN_* macros. Fixes this kernel-doc warning: drivers/clk/imx/clk-pllv1.c:12: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * pll v1 Fixes: 2af9e6db14db ("ARM i.MX: Add common clock support for pllv1") Fixes: a594790368a8 ("ARM: imx: pllv1: Fix PLL calculation for i.MX27") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: linux-clk@vger.kernel.org Cc: linux-imx@nxp.com Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20211115032607.28970-1-rdunlap@infradead.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-11-22clk: imx8mp: Fix the parent clk of the audio_root_clkHui Wang
Having the parent of the audio_root_clk set to ipg_root in the clk-imx8mp.c, there is a hang happening when the audiomix IP regs are accessed. Switch parent to audio_ahb. And we could also refer to the section "5.1.4 System Clocks" of the IMX8MPRM.pdf, the parent clk of CCGR101 (Audiomix) is the AUDIO_AHB_CLK_ROOT. Signed-off-by: Hui Wang <hui.wang@canonical.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211109125657.63485-2-hui.wang@canonical.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx8mn: Fix imx8mn_clko1_selsAdam Ford
When attempting to use sys_pll1_80m as the parent for clko1, the system hangs. This is due to the fact that the source select for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which doesn't yet exist. According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly references an osc_27m which does not exist, nor does an entry for source select bits 010b. Fix both by inserting a dummy clock into the missing space in the table and renaming the incorrectly name clock with dummy. Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx: Use div64_ul instead of do_divChangcheng Deng
do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211118080634.165275-1-deng.changcheng@zte.com.cn Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-22clk: imx: imx8ulp: set suppress_bind_attrs to truePeng Fan
The clock driver is registered as platform devices and it is possible to reloading the driver at runtime. But actually the clocks should never be removed to make system work, attempting to bind again would result in a crash, because almost all devices depends on clock to function well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211022131513.17381-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-11-05clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein
Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-10-06clk: imx: Make CLK_IMX8ULP select MXC_CLKFabio Estevam
Building CLK_IMX8ULP without selecting MXC_CLK causes the following build errors: ld: drivers/clk/imx/clk-imx8ulp.o: in function `imx8ulp_clk_cgc2_init': clk-imx8ulp.c:(.text+0xd0): undefined reference to `imx_ccm_lock' ld: clk-imx8ulp.c:(.text+0x14f): undefined reference to `imx_clk_hw_pllv4' ld: clk-imx8ulp.c:(.text+0x15a): undefined reference to `imx_ccm_lock' Avoid this problem by making CLK_IMX8ULP select MXC_CLK. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211006190008.1935051-1-festevam@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-10-01clk: imx: imx6ul: Fix csi clk gate registerStefan Riedmueller
According to the imx6ul Reference Manual the csi clk gate register is CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the csi clk gate which is the current setting. Tests have shown though that the correct csi clk gate register for the imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct register for both platforms. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Tested-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-10-01clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller
The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-10-01clk: imx: Fix the build break when clk-imx8ulp build as moduleJacky Bai
Export the necessary symbols to fix the build break when clk-imx8ulp build as module Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210917061629.3798360-1-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Add the pcc reset controller support on imx8ulpJacky Bai
On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit resides in the same registers as the clock controller. So add this SW RST controller support alongs with the pcc clock initialization. the reset and clock shared the same register, to avoid accessing the same register by reset control and clock control concurrently, locking is necessary, so reuse the imx_ccm_lock spinlock to simplify the code. Suggested-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-10-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Add clock driver for imx8ulpJacky Bai
Add clock driver for i.MX8ULP. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-9-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
2021-09-30clk: imx: Update the pfdv2 for 8ulp specific supportJacky Bai
On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2024-12-29 10:56:59 +0000