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path: root/drivers/clk/renesas/r9a07g043-cpg.c
AgeCommit message (Expand)Author
2022-05-05clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy
2022-05-05clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy
2022-05-05clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy
2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das
2022-04-13clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das
2022-04-13clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das
2022-04-13clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das
2022-04-13clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das
2022-04-13clk: renesas: Add support for RZ/G2UL SoCBiju Das