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After som grep:ing it turns out nothing in the kernel is really calling
clk_[hw_]_register_gpio_[gate|mux](). All existing instances are just
created directly from the device tree probe functions at the bottom of
the clk-gpio.c clock provider file.
This means we can change the signature of the function without any
consequences! Everyone should be using GPIO descriptors now, so let's
just go in and enforce that.
This saves a bit of code since GPIO descriptors know inherently if they
are active low so no need for the code keeping track of that.
We leave it to the caller to come up with the GPIO descriptor. It is
nowadays possible to do that even without a corresponding device, so
no excuse not to pass them around. The one in-kernel user lifecycles
it using devm_gpiod_get() in gpio_clk_driver_probe().
Cc: Sergej Sawazki <ce3a@gmx.de>
Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add all supported clocks exported from every susbystem found on MT7622 SoC
such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys,
ethsys and audsys.
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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On gcc-4.6, we get a harmless link-time warning:
WARNING: vmlinux.o(.text.unlikely+0x196a0): Section mismatch in reference from the function mtk_infrasys_init_early() to the function .init.text:mtk_clk_register_cpumuxes()
The function mtk_infrasys_init_early() references
the function __init mtk_clk_register_cpumuxes().
This is often because mtk_infrasys_init_early lacks a __init
annotation or the annotation of mtk_clk_register_cpumuxes is wrong.
Newer compilers inline this function so they don't warn, but
marking it __init is the right solution for all versions.
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add MT2712 clock support, include topckgen, apmixedsys,
infracfg, pericfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
[sboyd@codeaurora.org: Static on top_clk_data]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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IMX7d does not have an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The parent of OCRAM_CLK should be axi_main_root_clk
and not axi_post_div.
before:
axi_src 1 1 332307692 0 0
axi_cg 1 1 332307692 0 0
axi_pre_div 1 1 332307692 0 0
axi_post_div 1 1 332307692 0 0
ocram_clk 0 0 332307692 0 0
main_axi_root_clk 1 1 332307692 0 0
after:
axi_src 1 1 332307692 0 0
axi_cg 1 1 332307692 0 0
axi_pre_div 1 1 332307692 0 0
axi_post_div 1 1 332307692 0 0
main_axi_root_clk 1 1 332307692 0 0
ocram_clk 0 0 332307692 0 0
Reference Doc: i.MX 7D Reference Manual - Chap 5, p 516
(https://www.nxp.com/docs/en/reference-manual/IMX7DRM.pdf)
Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support")
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Allowing the lcdif_pre_sel to propagate rate changes to its parent PLL
allows more fine grained control over the LCDIF pixel clock rate.
For example, the Innovision AT043TN24 LCD panel described in the
imx6ul-14x14-evk device tree requires a 9 MHz pixel clock.
Before this patch, the lcdif_pre_sel clock rate is fixed, and just
setting the lcdif_pred and lcdif_podf dividers only allows to get as
close as about 8.44 MHz:
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 1 1 480000000 0 0
pll3_pfd1_540m 1 1 540000000 0 0
lcdif_pre_sel 1 1 540000000 0 0
lcdif_pred 1 1 67500000 0 0
lcdif_podf 1 1 8437500 0 0
lcdif_pix 1 1 8437500 0 0
Once lcdif_pre_sel is allowed to propagate rate requests to its parent,
the actual pixel clock matches the requested value:
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 1 1 480000000 0 0
pll3_pfd1_540m 1 1 288000000 0 0
lcdif_pre_sel 1 1 288000000 0 0
lcdif_pred 1 1 36000000 0 0
lcdif_podf 1 1 9000000 0 0
lcdif_pix 1 1 9000000 0 0
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver
fails to probe:
[ 2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller
(0000:00:00)
[ 2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi
(ops dw_hdmi_imx_ops): -19
[ 2.557403] imx-drm display-subsystem: master bind failed: -19
That's because hdmi_isfr's parent, video_27m, is not correctly ungated.
As explained in commit 5ccc248cc537 ("ARM: imx6q: clk: Add support for
mipi_core_cfg clock as a shared clock gate"), video_27m is gated by
CCM_CCGR3[CG8].
On i.MX6 SoCs with VPU, the hdmi is working thanks to the
CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever
is in CCM_CCGR3[CG8]. The issue can be reproduced by setting
CCMEOR[mod_en_ov_vpu] to 0.
Make the HDMI work in every case by setting hdmi_isfr's parent to
mipi_core_cfg.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add all RPM controlled clocks on msm8996 platform
[srini: Fixed various issues with offsets and made names specific to msm8996]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The RPM clocks were missing for MSM8660/APQ8060. For this to be
completed we need to add a special fixed rate RPM clock that is used
for the PLL4 on these SoCs. The rest of the clocks are pretty
similar to the other supported platforms.
The "active" clock pattern is mirrored in all the clocks. I guess
that the PLL4 that clocks the LPASS is actually never used as
"active only" since the low-power audio subsystem should be left
on when the CPU goes to idle, so that it can be used as a stand-alone
MP3 player type of device.
The PLL4 seems to be enabled only on behalf of the booting LPASS
Hexagon - which will cast its own vote once its booted - and as
such we only configure the active state (meaning both states will
have same configuration). The result is that PLL4 will be on
from prepare() to unprepare() regardless of what the application
CPU does.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The RCGs ops for shared branches are not used now, so remove it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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By default, it is assumed that the UTMI clock is generated from a 12 MHz
reference clock (MAINCK). If it's not the case, the FREQ field of the
SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the
proper way.
The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target of
480 MHz.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Ingo van Lil <inguin@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Now that we have devm APIs for the reset controller and of clk hw
provider APIs we can remove the custom code here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Sometimes we only have one of_clk_del_provider() call in driver
error and remove paths, because we're missing a
devm_of_clk_add_hw_provider() API. Introduce the API so we can
convert drivers to use this and potentially reduce the amount of
code needed to remove providers in drivers.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the init field of a clk_hw
structure, which is const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make these const as they are either stored in the masks 'const' field
of a clk_aux structure or passed to the function clk_register_aux
having the argument as const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Make the masks field of clk_aux structure const as it do not modify the
fields of the aux_clk_masks structure it points to.
Make the struct aux_clk_masks *aux argument of the function
clk_register_aux as const as the argument is only stored in the masks
field of a clk_aux structure which is now made const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.
No functional changes.
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch fix the following build warning:
drivers/clk/sunxi/clk-factors.c:279:14: warning: variable 'name' set but not used [-Wunused-but-set-variable]
Fixes: 4cbeaebb8af1 ("clk: sunxi: factors: Add unregister function")
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.
Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org
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Below is the call trace of tegra210_init_pllu() function:
start_kernel()
-> time_init()
--> of_clk_init()
---> tegra210_clock_init()
----> tegra210_pll_init()
-----> tegra210_init_pllu()
Because the preemption is disabled in the start_kernel before calling
time_init, tegra210_init_pllu is actually in an atomic context while
it includes a readl_relaxed_poll_timeout that might sleep.
So this patch just changes this readl_relaxed_poll_timeout() to its
atomic version.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers for the drvdata. Once the drvdata has been overwritten
by tegra124-dfll, clk-dfll will never get its td pointer as it
expects.
Since tegra124-dfll merely needs its soc pointer in its remove
function, this patch fixes the bug by removing the overwriting
in the tegra124-dfll file and letting the tegra_dfll_unregister
return an soc pointer for it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.
Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The APBDMA clock is defined in the common clock gates table that is used
by Tegra30+. Tegra20 can use it too, let's remove the custom definition
and use the common one.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that
driver for the AHB DMA controller could be implemented.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Currently, the APB clock is registered with the CLK_IGNORE_UNUSED flag
to prevent the clock from being disabled if unused on boot. However,
even if it is used, it still needs to be always kept enabled so that it
doesn't get inadvertently disabled when all of its children are, and so
update the flag for the APB clock to be CLK_IS_CRITICAL.
Suggested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull Rockchip clk drivers updates from Heiko Stuebner:
- new clock ids for rk3188 and rk3368
- removal of a superfluous memory allocation error message
* tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: use new cif/vdpu clock ids on rk3188
clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
clk: rockchip: add more rk3188 graphics clock ids
clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the second display unit clock on RZ/G1E,
- Add git repository to MAINTAINERS,
- Add suspend/resume support for R-Car Gen3 CPG/MSSR,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Restore R clock during resume
clk: renesas: rcar-gen3: Restore SDHI clocks during resume
clk: renesas: div6: Restore clock state during resume
clk: renesas: cpg-mssr: Add support to restore core clocks during resume
clk: renesas: cpg-mssr: Restore module clocks during resume
MAINTAINERS: Add git repository to Renesas clock driver section
clk: renesas: cpg-mssr: Add du1 clock to R8A7745
clk: renesas: rz: clk-rz is meant for RZ/A1
clk: renesas: r8a77995: Correct parent clock of INTC-AP
clk: renesas: r8a7796: Correct parent clock of INTC-AP
clk: renesas: r8a7795: Correct parent clock of INTC-AP
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clk-next
Pull Amlogic clock driver updates from Neil Armstrong:
- Addition of Video Processing Unit VPU and VAPB clocks
* tag 'meson-clk-for-4.15' of git://github.com/baylibre/clk-meson:
clk: meson: gxbb: Add VPU and VAPB clocks data
clk: meson: gxbb: Add VPU and VAPB clockids
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock driver updates from Maxime Ripard:
- Addition of sigma/delta modulation for the audio PLLs on the newer SoCs
- A83t Display clocks supports
- minor fixes that didn't have any impact on current features
* tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun4i: Export video PLLs
clk: sunxi-ng: Add A83T display clocks
clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: nm: Add support for sigma-delta modulation
clk: sunxi-ng: Add sigma-delta modulation support
clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock
clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider
clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset
clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision
clk: sunxi-ng: sun6i: Export video PLLs
clk: sunxi-ng: Implement reset control status readback
clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
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git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
- An addition of separate driver for the Exynos 4412 ISP CMU, needed
to model and properly handle the clock controller's dependencies
on the ISP power domain.
- Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
resume} ops to suppress compiler warnings with CONFIG_PM disabled.
* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add a separate driver for Exynos4412 ISP clocks
clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
clk: samsung: Instantiate Exynos4412 ISP clocks only when available
clk: samsung: exynos5433: mark PM functions as __maybe_unused
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git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
Overall clk/samsung clean up and fixes. Removed remaining unused code
after removal of exynos4212 SoC support; dropped internal data structure
fields and related code for registering clkdev lookup entry for each
possible clock object, clkdev aliases could still be defined if needed
in a separate table; other minor fixes of the clock tree definitions.
* tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Remove obsolete clkdev alias support
clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver
clk: samsung: Rework clkdev alias handling in S3C2443 driver
clk: samsung: Rework clkdev alias handling in Exynos5440 driver
clk: samsung: Drop useless alias in Exynos5420 clk driver
clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver
clk: samsung: Remove clkdev alias support in Exynos4 clk driver
clk: samsung: Remove support for obsolete Exynos4212 CPU clock
clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver
clk: samsung: Properly propagate flags in __PLL macro
clk: samsung: Fix m2m scaler clock on Exynos542x
clk: samsung: Delete a memory allocation error message in clk-cpu.c
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the new R-Car V3M SoC,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen2: Delete error message for failed memory allocation
clk: renesas: mstp: Delete error messages for failed memory allocations
clk: renesas: cpg-mssr: Add R8A77970 support
dt-bindings: clock: Add R8A77970 CPG core clock definitions
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Fix reg offsets of USB clocks.
Fixes: 736de651a836 ("clk: uniphier: add PXs3 clock data")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
clock configuration. Register a notifier to save/restore the RCKCR
register during system suspend/resume.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
clock configuration. Register a notifier to save/restore SDHI clock
registers during system suspend/resume.
This is implemented using the cpg_simple_notifier abstraction, which can
be reused for others clocks that just need to save/restore a single
register.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
clock configuration. Register an (optional) notifier to restore the
DIV6 clock state during system resume.
As DIV6 clocks can be picky w.r.t. modifying multiple register fields at
once, restore is not implemented by blindly restoring the register
value, but by using the existing cpg_div6_clock_{en,dis}able() helpers.
Note that this does not yet support DIV6 clocks with multiple parents,
which do not exist on R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly
losing clock configuration. Hence add a notifier chain that can be used
by core clocks to save/restore clock state during system suspend/resume.
The implementation of the actual clock state save/restore operations is
clock-specific, and to be registered with the notifier chain in the SoC
or family-specific cpg_mssr_info.cpg_clk_register() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
clock register state is lost. Note that as the boot loader skips most
initialization after system resume, clock register state differs from
the state encountered during normal system boot, too.
Hence after s2ram, some operations may fail because module clocks are
disabled, while drivers expect them to be still enabled. E.g. EtherAVB
fails when Wake-on-LAN has been enabled using "ethtool -s eth0 wol g":
ravb e6800000.ethernet eth0: failed to switch device to config mode
ravb e6800000.ethernet eth0: device will be stopped after h/w processes are done.
ravb e6800000.ethernet eth0: failed to switch device to config
PM: Device e6800000.ethernet failed to resume: error -110
In addition, some module clocks that were disabled by
clk_disable_unused() may have been re-enabled, wasting power.
To fix this, restore all bits of the SMSTPCR registers that represent
clocks under control of Linux.
Notes:
- While this fixes EtherAVB operation after resume from s2ram,
EtherAVB cannot be used as an actual wake-up source from s2ram, only
from s2idle, due to PSCI limitations,
- To avoid overhead on platforms not needing it, the suspend/resume
code has a build time dependency on sleep and PSCI support, and a
runtime dependency on PSCI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT
bindings and clk-rz driver apply to RZ/A1 only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
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