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path: root/drivers/cxl/cxl.h
AgeCommit message (Expand)Author
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams
2021-06-15cxl/pmem: Add initial infrastructure for pmem supportDan Williams
2021-06-15cxl/core: Add cxl-bus driver infrastructureDan Williams
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky
2021-06-09cxl/acpi: Introduce cxl_decoder objectsDan Williams
2021-06-09cxl/acpi: Add downstream port data to cxl_port instancesDan Williams
2021-06-09cxl/acpi: Introduce the root of a cxl_port topologyDan Williams
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny
2021-05-14cxl/core: Refactor CXL register lookup for bridge reuseDan Williams
2021-05-14cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams
2021-05-14cxl/mem: Move some definitions to mem.hDan Williams
2021-02-16cxl/mem: Enable commands via CELBen Widawsky
2021-02-16cxl/mem: Register CXL memX devicesDan Williams
2021-02-16cxl/mem: Find device capabilitiesBen Widawsky
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2025-01-07 14:14:58 +0000