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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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2015-12-21drm/amd/amdgpu: add gfx clock gating support for Fiji.Eric Huang
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amdgpu: support per device powerplay enablement (v2)Jammy Zhou
The amdgu_powerplay variable is global for multiple GPU instances. v2: fold in Flora's module option change, protect adev reference in macros Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-21drm/amdgpu: disable legacy path of firmware check if powerplay is enabledRex Zhu
Powerplay will use a different interface once it's integrated. These legacy pathes will be removed once powerplay is enabled by default. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11drm/amdgpu/gfx8: update PA_SC_RASTER_CONFIG:PKR_MAP onlyFlora Cui
Use default value as a base. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-11drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3Flora Cui
Otherwise FW cannot see the RLC ACK for the memory clean request It's for Stoney. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-04amdgpu/gfxv8: Remove magic numbers from function ↵Tom St Denis
gfx_v8_0_tiling_mode_table_init() Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-04amdgpu/gfxv8: Simplification in gfx_v8_0_enable_gui_idle_interrupt()Tom St Denis
Simplified the function by folding the two paths into one. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-04amdgpu/gfxv8: Simplification of gfx_v8_0_create_bitmask()Tom St Denis
Simplification of the function gfx_v8_0_create_bitmask(). Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-04amdgpu/gfxv8: Cleanup of gfx_v8_0_tiling_mode_table_init() (v2)Tom St Denis
Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init() v2: remove spurious break bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236 Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-02amdgpu/gfxv8: Add missing break to switch statement from states init codeTom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-02drm/amdgpu: add EDC support for CZ (v3)Alex Deucher
This adds EDC support for CZ. EDC = Error Correction and Detection This code properly initializes the EDC hardware and resets the error counts. This is done in late_init since it requires the IB pool which is not initialized during hw_init. v2: fix the IB size as noted by Felix, fix shader pgm register programming v3: use the IB for the shaders as suggested by Christian Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-16drm/amdgpu: update Fiji's tiling mode tableFlora Cui
Change-Id: I925c15015390113f7e27746ec5751eaa6a92c2a7 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-16drm/amdgpu: update fiji_mgcg_cgcg_init tableFlora Cui
Change-Id: If44b8057741c78208f1976f60f31b535c944d0bd Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-11-16drm/amdgpu: update Fiji's mmPA_SC_RASTER_CONFIG valueFlora Cui
Change-Id: I6d138306a878450e5bf8a77a2f1aacc380a39fe5 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-03drm/amdgpu: update Fiji's Golden settingFlora Cui
Change-Id: Ic3f3bfce4767cc05d04f6eb24e22a0f3e7ceacaa Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-10-28drm/amdgpu: add some additional CZ revisionsAlex Deucher
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2015-10-21drm/amdgpu: add GFX support for Stoney (v2)Samuel Li
Stoney is GFX 8.1. v2: update to latest golden settings Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: remove old lockup detection infrastructureChristian König
It didn't worked to well anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2015-10-19drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packetAlex Deucher
This is the recommended setting from the hw team for newer versions of the firmware. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2015-10-07drm/amdgpu: split gfx8 gpu init into sw and hw partsAlex Deucher
Calculate the driver state in sw_init and program the registers in hw init. Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-23drm/amdgpu: sync ce and me with SWITCH_BUFFER(2)monk.liu
we used to adopt wait_reg_mem to let CE wait before DE finish page updating, but from Tonga+, CE doesn't support wait_reg_mem package so this logic no longer works. so here is another approach to do same thing: Insert two of SWITCH_BUFFER at both front and end of vm_flush can guarantee that CE not go further to process IB_const before vm_flush done. Insert two of SWITCH_BUFFER also works on CI, so remove legency method to sync CE and ME v2: Insert double SWITCH_BUFFER at front of vm flush as well. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-09-23drm/amdgpu: export reservation_object from dmabuf to ttm (v2)Christian König
Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c. Port of radeon commit 831b6966a60fe72d85ae3576056b4e4e0775b112. v2: fix up kfd. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-23drm/amdgpu: use write confirm for vm_flush()Christian König
Make sure the CP waits for the write to be confirmed before invalidating. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-23drm/amdgpu: execution barrier after fence v2Anatoli Antonovitch
Insert wait for reg mem after EOP to fix potential issue with vm context switch v2: move wait to vm_flush() use equal instead of greater than. Signed-off-by: Anatoli Antonovitch <anatoli.antonovitch@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-04drm/amdgpu: rename gmc_v8_0_init_compute_vmidAlex Deucher
It should be gfx_v8_0_init_compute_vmid since it's part of the gfx block. Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-02drm/amdgpu: set MEC doorbell range for FijiJammy Zhou
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-02drm/amdgpu: add insert_nop ring func and default implementationJammy Zhou
The insert_nop function is added to amdgpu_ring_funcs structure as well as the default implementation Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-20drm/amdgpu: fix zeroing all IB fields manually v2Christian König
The problem now is that we don't necessarily call amdgpu_ib_get() in some error paths and so work with uninitialized data. Better require that the memory is already zeroed. v2: better commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: add reference for **fenceChunming Zhou
fix fence is released when pass to **fence sometimes. add reference for it. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
2015-08-17drm/amdgpu: add kernel fence in ib_submit_kernel_helperChunming Zhou
every sbumission should be able to get a fence. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
2015-08-17drm/amdgpu: use kernel fence for gfx ib testChunming Zhou
Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
2015-08-17drm/amdgpu: Use gpu scheduler for gfx ring ib testChunming Zhou
Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
2015-08-17drm/amdgpu: Add Fiji support to the GFX 8.0 IP module (v2)David Zhang
v2: agd5f: fix the rb setup. Signed-off-by: David Zhang <david1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-17drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)Jammy Zhou
Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-12Revert "drm/amdgpu: Configure doorbell to maximum slots"Alex Deucher
This reverts commit 78ad5cdd21f0d614983fc397338944e797ec70b9. This commit breaks dpm and suspend/resume on CZ.
2015-08-05drm/amdgpu: set fw_version and feature_version for smu fw loadingJammy Zhou
The fw_version and feature_verion should be set correctly when the firmwares are loaded by SMU on Tonga/Carrzio/Iceland Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-05drm/amdgpu: add feature version for RLC and MEC v2Jammy Zhou
Expose feature version to user space for RLC/MEC/MEC2 ucode as well v2: fix coding style Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-05drm/amdgpu: fix rb setting for CZAlex Deucher
Always set num_rbs to 2 for CZ. The 1 RB parts are often harvest configs. The will get sorted out in mesa when we program PA_SC_RASTER_CONFIG[_1]. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-07-29drm/amdgpu: different emit_ib for gfx and computemonk.liu
compute ring didn't use const engine byfar, so ignore CE things in compute routine Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-07-16drm/amdgpu: remove bogus check in gfx8 rb setupAlex Deucher
Always respect the harvest configuration as is. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-29drm/amdgpu: reset wptr at cp compute resume (v2)Sonny Jiang
This patch is to resolve compute hang at resume time. v2: (agd5f) squash in second fix Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-29drm/amdgpu: Configure doorbell to maximum slotsBen Goz
Signed-off-by: Ben Goz <ben.goz@amd.com> Acked-by: Oded Gabbay <oded.gabbay@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-29drm/amdgpu: Initialize compute sdma and memory from kgdBen Goz
v2: add missing MTYPE_NONCACHED enum Signed-off-by: Ben Goz <ben.goz@amd.com> Acked-by: Oded Gabbay <oded.gabbay@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-10drm/amdgpu: update to latest gfx8 golden register settingsAlex Deucher
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-10drm/amdgpu: remove the VI hardware semaphore in ring syncDavid Zhang
Signed-off-by: David Zhang <david1.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-06-08drm/amdgpu: set the gfx config properly for all CZ variants (v2)Alex Deucher
Need to adjust the number of CUs and RBs. v2: get proper values Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-05drm/amdgpu: disable user fence interrupt (v2)Chunming Zhou
amdgpu submits both kernel and user fences, but just need one interrupt, disable user fence interrupt and don't effect user fence. v2: fix merge error Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-06-03drm/amdgpu: add me/ce/pfp_feature_version interface queryKen Wang
Provide this information to usermode drivers. We were previously missing this info. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-06-03drm/amdgpu add ce_ram_size for interface queryKen Wang
Add a query for the CE ram size. User mode drivers will want to use this to determine how much size of the cache on the CE. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-06-03drm/amdgpu: add hdp flush for gfx8 compute ringmonk.liu
We had forgotten to register the callback. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: jammy zhou <jammy.zhou@amd.com>
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