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path: root/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
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2022-02-17drm/amdgpu: Optimize xxx_ras_late_init function of each ras blockyipechai
1. Move calling ras block instance members from module internal function to the top calling xxx_ras_late_init. 2. Module internal function calls can only use parameter variables of xxx_ras_late_init instead of ras block instance members. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-14drm/amdgpu: Optimize amdgpu_sdma_ras_late_init/amdgpu_sdma_ras_fini function ↵yipechai
code Optimize amdgpu_sdma_ras_late_init/amdgpu_sdma_ras_fini function code. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-14drm/amdgpu: Optimize xxx_ras_late_init/xxx_ras_late_fini for each ras blockyipechai
1. Define amdgpu_ras_block_late_init to create sysfs nodes and interrupt handles. 2. Define amdgpu_ras_block_late_fini to remove sysfs nodes and interrupt handles. 3. Replace ras block variable members in struct amdgpu_ras_block_object with struct ras_common_if, which can make it easy to associate each ras block instance with each ras block functional interface. 4. Add .ras_cb to struct amdgpu_ras_block_object. 5. Change each ras block to fit for the changement of struct amdgpu_ras_block_object. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-02-11drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.Rajib Mahapatra
[Why] SDMA ring buffer test failed if suspend is aborted during S0i3 resume. [How] If suspend is aborted for some reason during S0i3 resume cycle, it follows SDMA ring test failing and errors in amdgpu resume. For RN/CZN/Picasso, SMU saves and restores SDMA registers during S0ix cycle. So, skipping SDMA suspend and resume from driver solves the issue. This time, the system is able to resume gracefully even the suspend is aborted. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rajib Mahapatra <rajib.mahapatra@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-18drm/amdgpu: Fix the code style warnings in sdmayipechai
Fix the code style warnings in sdma: 1. WARNING: Missing a blank line after declarations. 2. ERROR: that open brace { should be on the previous line. 3. WARNING: unnecessary whitespace before a quoted newline. 4. ERROR: space required after that ',' (ctx:VxV). Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-01-14drm/amdgpu: Modify sdma block to fit for the unified ras block data and opsyipechai
1.Modify sdma block to fit for the unified ras block data and ops. 2.Change amdgpu_sdma_ras_funcs to amdgpu_sdma_ras, and the corresponding variable name remove _funcs suffix. 3.Remove the const flag of sdma ras variable so that sdma ras block can be able to be inserted into amdgpu device ras block link list. 4.Invoke amdgpu_ras_register_ras_block function to register sdma ras block into amdgpu device ras block link list. 5.Remove the redundant code about sdma in amdgpu_ras.c after using the unified ras block. 6.Fill unified ras block .name .block .ras_late_init and .ras_fini for all of sdma versions. If .ras_late_init and .ras_fini had been defined by the selected sdma version, the defined functions will take effect; if not defined, default fill them with amdgpu_sdma_ras_late_init and amdgpu_sdma_ras_fini. v2: squash in warning fix (Alex) Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amdgpu: convert IP version array to include instancesAlex Deucher
Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amdgpu/sdma: remove manual instance settingAlex Deucher
Handled by IP discovery now. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amdgpu/sdma4.0: convert to IP version checkingAlex Deucher
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: Conditionally reset SDMA RAS error countsMukul Joshi
Reset SDMA RAS error counts during init only if persistent EDC harvesting is not supported. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)Aaron Liu
Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1 by default for all asic. On Raven/Renoir, the sdma goldsetting changes SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0. This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-05-21drm/amd/amdgpu/sdma_v4_0: Realign functions with their headersLee Jones
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:764: warning: expecting prototype for sdma_v4_0_page_ring_set_wptr(). Prototype was for sdma_v4_0_ring_set_wptr() instead drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:830: warning: expecting prototype for sdma_v4_0_ring_set_wptr(). Prototype was for sdma_v4_0_page_ring_set_wptr() instead Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-28drm/amdgpu: Correct and simplify sdma 4.x irq.num_typesFeifei Xu
Correct and init the sdma4.x irq.num_types. v2: squash in fix (Alex) Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-28drm/amdgpu: Change the sdma interrupt print levelFeifei Xu
Change the print level into debug. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-23drm/amdgpu: extend xnack limit page fault timeoutAlex Sierra
Extending this timeout will prevent IH from storm interrupts coming from SDMA while a page fault is active. Currently, on Aldebaran, handling that many interrupts can take a lot of CPU time (up to 4 seconds). This eventually causes timeouts in other tasks. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09drm/amdgpu: add the sched_score to amdgpu_ring_initChristian König
Allow separate ring to share the same scheduler score. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: UTLC1 RB SDMA timeout on AldebaranAlex Sierra
[Why] This causes infinite retries on the UTCL1 RB, preventing higher priority RB such as paging RB. [How] Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: add sdma v4_4 ras functionHawking Zhang
sdma ras function is the main structure to support sdma ras on aldebaran. the patch initializes late_init late_fini callbacks. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li<Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: apply sdma golden settings for aldebaranHawking Zhang
perform one-time initialization for sdma registers Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23drm/amdgpu: declare sdma firmware binary file for aldebaranKevin Wang
declare sdma firmware binary file for aldebaran Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add aldebaran sdma firmware support (v2)Kevin Wang
add sdma firmware load support for soc model v2: drop some emulator leftovers (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add sdma block support for aldebaranLe Ma
Add initial sdma support for aldebaran, and this asic has 5 sdma instances. v2: remove adundant condition check Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <Evan.Quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: add sdma 4_x interrupts printingFeifei Xu
Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE interrupt info printing. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.Feifei Xu
SDMA 4_x asics share the same MGCG/MGLS setting. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05drm/amdgpu: remove redundant logic related HDPLikun Gao
Remove hdp_flush function from amdgpu_nbio struct as it have been unified into hdp struct. Remove the include about hdp register which was not used. V2: Remove hdp golden setting which is unnecessary. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-01drm/amd/amdgpu/sdma_v4_0: Repair a bunch of kernel-doc problemsLee Jones
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:848: warning: Function parameter or member 'job' not described in 'sdma_v4_0_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:848: warning: Function parameter or member 'flags' not described in 'sdma_v4_0_ring_emit_ib' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:923: warning: Function parameter or member 'addr' not described in 'sdma_v4_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:923: warning: Function parameter or member 'seq' not described in 'sdma_v4_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:923: warning: Function parameter or member 'flags' not described in 'sdma_v4_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:923: warning: Excess function parameter 'fence' description in 'sdma_v4_0_ring_emit_fence' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1117: warning: Function parameter or member 'ring' not described in 'sdma_v4_0_rb_cntl' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1117: warning: Function parameter or member 'rb_cntl' not described in 'sdma_v4_0_rb_cntl' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1581: warning: Function parameter or member 'timeout' not described in 'sdma_v4_0_ring_test_ib' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1682: warning: Function parameter or member 'value' not described in 'sdma_v4_0_vm_write_pte' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1682: warning: Excess function parameter 'addr' description in 'sdma_v4_0_vm_write_pte' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1682: warning: Excess function parameter 'flags' description in 'sdma_v4_0_vm_write_pte' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1734: warning: Function parameter or member 'ring' not described in 'sdma_v4_0_ring_pad_ib' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1782: warning: Function parameter or member 'vmid' not described in 'sdma_v4_0_ring_emit_vm_flush' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1782: warning: Function parameter or member 'pd_addr' not described in 'sdma_v4_0_ring_emit_vm_flush' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1782: warning: Excess function parameter 'vm' description in 'sdma_v4_0_ring_emit_vm_flush' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2508: warning: Function parameter or member 'ib' not described in 'sdma_v4_0_emit_copy_buffer' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2508: warning: Function parameter or member 'tmz' not described in 'sdma_v4_0_emit_copy_buffer' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2508: warning: Excess function parameter 'ring' description in 'sdma_v4_0_emit_copy_buffer' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2534: warning: Function parameter or member 'ib' not described in 'sdma_v4_0_emit_fill_buffer' drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2534: warning: Excess function parameter 'ring' description in 'sdma_v4_0_emit_fill_buffer' Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org Cc: linaro-mm-sig@lists.linaro.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-01drm/amdgpu: only skip smc sdma sos ta and asd fw in SRIOV for navi12Stanley.Yang
The KFDTopologyTest.BasicTest will failed if skip smc, sdma, sos, ta and asd fw in SRIOV for vega10, so adjust above fw and skip load them in SRIOV only for navi12. v2: remove unnecessary asic type check. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amdgpu/sdma: use "*" adjacent to data nameDeepak R Varma
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-07drm/amdgpu/sdma: add sdma engine support for green_sardine (v2)Prike Liang
Initialize the SDMA IP for green_sardine. v2: use apu flags Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-25drm/amd: Skip not used microcode loading in SRIOVJingwen Chen
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Emily.Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amd/amdgpu: fix comparison pointer to bool warning in sdma_v4_0.cZheng Bin
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1003:4-9: WARNING: Comparison to bool drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:1083:5-11: WARNING: Comparison to bool Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-15drm/amdgpu: Enable SDMA utilization for ArcturusMukul Joshi
SDMA utilization calculations are enabled/disabled by writing to SDMAx_PUB_DUMMY_REG2 register. Currently, enable this only for Arcturus. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: call release_firmware() without a NULL checkNirmoy Das
The release_firmware() function is NULL tolerant so we do not need to check for NULL param before calling it. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: Reconfigure ULV for gfx9 server SKUsJoseph Greathouse
SDMA ULV can benefit low-power modes, but can sometimes cause latency increases in small SDMA transfers. Server SKUs have a different trade-off space in this domain, so this configures the server SKUs' ULV hysteresis times differently than consumer SKUs'. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amdgpu/sdma4: simplify the logic around powering up sdmaAlex Deucher
Just check if it's an APU. The checks for the ppfuncs are pointless because if we don't have them we can't power up sdma anyway so we shouldn't even be in this code in the first place. I'm not sure about the in_gpu_reset check. This probably needs to be double checked. The fini logic doesn't match the init logic however with that in_gpu_reset check in place which seems odd. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amdgpu: simplify raven and renoir checksAlex Deucher
Just check for APU. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-28drm/amdgpu/sdma4: add renoir to powergating setupAlex Deucher
Looks like renoir should be handled here as well. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-22drm/amdgpu: add apu flags (v2)Alex Deucher
Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-08Merge tag 'amd-drm-next-5.8-2020-04-30' of ↵Dave Airlie
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.8-2020-04-30: amdgpu: - SR-IOV fixes - SDMA fix for Navi - VCN 2.5 DPG fixes - Display fixes - Display stuttering fixes for pageflip and cursor - Add support for handling encrypted GPU memory - Add UAPI for encrypted GPU memory - Rework IB pool handling amdkfd: - Expose asic revision in topology - Add UAPI for GWS (Global Wave Sync) resource management UAPI: - Add amdgpu UAPI for encrypted GPU memory Used by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401 - Add amdkfd UAPI for GWS (Global Wave Sync) resource management Thunk usage of KFD ioctl: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/blob/roc-2.8.0/src/queues.c#L840 ROCr usage of Thunk API: https://github.com/RadeonOpenCompute/ROCR-Runtime/blob/roc-3.1.0/src/core/runtime/amd_gpu_agent.cpp#L597 HCC code using ROCr API: https://github.com/RadeonOpenCompute/hcc/blob/98ee9f34945d3b5f572d7a4c15cbffa506487734/lib/hsa/mcwamp_hsa.cpp#L2161 HIP code using HCC API: https://github.com/ROCm-Developer-Tools/HIP/blob/cf8589b8c8a40ddcc55fa3a51e23390a49824130/src/hip_module.cpp#L567 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430212951.3902-1-alexander.deucher@amd.com
2020-04-30Merge tag 'amd-drm-next-5.8-2020-04-24' of ↵Dave Airlie
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.8-2020-04-24: amdgpu: - Documentation improvements - Enable FRU chip access on boards that support it - RAS updates - SR-IOV updates - Powerplay locking fixes for older SMU versions - VCN DPG (dynamic powergating) cleanup - VCN 2.5 DPG enablement - Rework GPU scheduler handling - Improve scheduler priority handling - Add SPM (streaming performance monitor) golden settings for navi - GFX10 clockgating fixes - DC ABM (automatic backlight modulation) fixes - DC cursor and plane fixes - DC watermark fixes - DC clock handling fixes - DC color management fixes - GPU reset fixes - Clean up MMIO access macros - EEPROM access fixes - Misc code cleanups amdkfd: - Misc code cleanups radeon: - Clean up safe reg list generation - Misc code cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200424190827.4542-1-alexander.deucher@amd.com
2020-04-28drm/amdgpu: enable TMZ bit in sdma copy pkt for sdma v4Aaron Liu
Enable sdma TMZ mode via setting TMZ bit in sdma copy pkt for sdma v4 Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-28drm/amdgpu: expand sdma copy_buffer interface with tmz parameterAaron Liu
This patch expands sdma copy_buffer interface with tmz parameter. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-22drm/amdgpu: Adjust the SDMA doorbell info printingYong Zhao
Turn off the printing by default because it is not very useful, while adding more details. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-09drm/amdgpu: rework sched_list generationNirmoy Das
Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01Merge tag 'drm-next-2020-04-01' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm updates from Dave Airlie: "This is the main drm pull request for 5.7-rc1. Highlights: - i915 enables Tigerlake by default - i915 and amdgpu have initial OLED backlight support [ Jani Nikula pipes up and points out that we've had a bunch of "initial support" code for a long time already, but only now Lyude made it actually work on real world machines ] - vmwgfx add support to enable OpenGL 4 userspace - zero length arrays are mostly removed. Detailed summary: new driver: - tidss: TI Keystone platform display subsystem core: - new drm device warn macros - mode config valid for memory constrained devices - bridge bus format negotation - consolidated fake vblank event handling - dma_alloc related cleanups - drop get_crtc callback - dp: DP1.4 EDID corruption test - EDID CEA detailed timings improvements - relicense some code to dual GPL2/MIT - convert core vblank support to per-crtc support - rework drm_global_mutex - bridge rework to allow omap_dss custom driver removeal - remove drm_fb_helper connector interrfaces - zero-length array removal scheduler: - support for modifying the sched list - revert job distribution optimization - helper to pick least loaded scheduler - race condition fix mst: - various fixes - remove register_connector callback i915: - uapi to allows userspace specific CS ring buffer sizes - Tigerlake enablement patches + Tigerlake enabled by default - new sysfs entries for engine properties - display/logging refactors - eDP/DP fixes for DPCD - Gen7 back to aliasing-ppgtt - Gen8+ irq refactor - Avoid globals - GEM locking fixes and simplifications - Ice Lake and Elkhart Lake fixes and workarounds - Baytrail/Haswell instability fix - GVT - VFIO edid better support amdgpu: - Rework VM update handling in preparation for HMM support - drm load/unload removal fixups - USB-C PD firmware updates - HDCP srm support - Navi/renoir PM watermark fixes - OLED panel support - Optimize debugging vram access - Use BACO for runtime pm - DC clock programming optimizations and fixes - PSP fw loading sequence updates - Drop DRIVER_USE_AGP - Remove legacy drm load and unload callbacks - ACP Kconfig fix - Lots of fixes across the driver amdkfd: - runtime pm support - more gfx config details in amdgpu radeon: - drop DRIVER_USE_AGP vmwgfx: - Disable DMA when SEV encryption in use - Shader Model 5 support - needed for GL4 support msm: - DPU resource manager refactor - dpu using atomic global state mediatek: - MT8183 DPI support etnaviv: - out-of-bounds read fix - expose feature flags for GC400 STM32MP1 SoC - runtime suspend entry fix - dma32 zone fix hisilicon: - mode selection fixes meson: - YUV420 support lima: - add support for heap buffers tinydrm: - removal of owner field - explicit DT dependency removal - YAML schema conversion tegra: - misc cleanups tidss: - new driver virtio: - better batching of notifications to host - memory handling reworked - shmem + gpu context fixes hibmc: - add gamma_set support - improve DPMS support pl111: - Integrator IM-PD1 support sun4i: - LVDS support for A20 + A33 - DSI panel handling improvements" * tag 'drm-next-2020-04-01' of git://anongit.freedesktop.org/drm/drm: (1537 commits) drm/i915/display: Fix mode private_flags comparison at atomic_check drm/i915/gt: Stage the transfer of the virtual breadcrumb drm/i915/gt: Select the deepest available parking mode for rc6 drm/i915: Avoid live-lock with i915_vma_parked() drm/i915/gt: Treat idling as a RPS downclock event drm/i915/gt: Cancel a hung context if already closed drm/i915: Use explicit flag to mark unreachable intel_context drm/amdgpu: don't try to reserve training bo for sriov (v2) drm/amdgpu/smu11: add support for SMU AC/DC interrupts drm/amdgpu/swSMU: handle manual AC/DC notifications drm/amdgpu/swSMU: handle DC controlled by GPIO for navi1x drm/amdgpu/swSMU: set AC/DC mode based on the current system state (v2) drm/amdgpu/swSMU: correct the bootup power source for Navi1X (v2) drm/amdgpu/swSMU: use the smu11 power source helper for navi1x drm/amdgpu/smu11: add a helper to set the power source drm/amd/swSMU: add callback to set AC/DC power source (v2) drm/scheduler: fix rare NULL ptr race drm/amdgpu: fix the coverage issue to clear ArcVPGRs drm/amd/display: Fix pageflip event race condition for DCN. drm/[radeon|amdgpu]: Remove HAINAN board from max_sclk override check ...
2020-04-01drm/amdgpu: stop disable the scheduler during HW finiChristian König
When we stop the HW for example for GPU reset we should not stop the front-end scheduler. Otherwise we run into intermediate failures during command submission. The scheduler should only be stopped in very few cases: 1. We can't get the hardware working in ring or IB test after a GPU reset. 2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset. 3. In amdgpu_ring_fini() when the driver unloads. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Test-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu: infinite retries fix from UTLC1 RB SDMAAlex Sierra
[Why] Previously these registers were set to 0. This was causing an infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB. [How] Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Vega10, Vega12, Vega20 and Arcturus. Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-01drm/amdgpu: implement more ib pools (v2)xinhui pan
We have three ib pools, they are normal, VM, direct pools. Any jobs which schedule IBs without dependence on gpu scheduler should use DIRECT pool. Any jobs schedule direct VM update IBs should use VM pool. Any other jobs use NORMAL pool. v2: squash in coding style fix Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-17drm/amdgpu: fix two documentation mismatch issuesWang Xiayang
The function name mentioned in the documentational comments mismatches the actual one. The mismatch may make trouble for automatic documentation generation. One of the erronous name has seen to be misused and fixed in commit bc5ab2d29b8a ("drm/amdgpu: fix typo in function sdma_v4_0_page_resume"). There is apparently no functional change in the patch. Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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