| Age | Commit message (Collapse) | Author |
|---|
|
Introduce a flag to signal that access to a BO will be synchronized
through an external mechanism.
Currently all buffers shared between contexts are subject to implicit
synchronization. However, this is only required for protocols that
currently don't support an explicit synchronization mechanism (DRI2/3).
This patch introduces the AMDGPU_GEM_CREATE_EXPLICIT_SYNC, so that
users can specify when it is safe to disable implicit sync.
v2: only disable explicit sync in amdgpu_cs_ioctl
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Convert GTT mappings into linear ones for huge page handling.
v2: use fragment size as minimum for linear conversion
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
SR-IOV need to reserve a piece of shared VRAM at the exact place
to exchange data betweem PF and VF. The start address and size of
the shared mem are passed to guest through VBIOS structure
VRAM_UsageByFirmware.
VRAM_UsageByFirmware is a general feature in VBIOS, it indicates
that VBIOS need to reserve a piece of memory on the VRAM.
Because the mem address is specified. Reserve it early in
amdgpu_ttm_init to make sure that it can monoplize the space.
Signed-off-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Without the additional bits set in PDEs/PTEs, the ATC memory access
would have failed on Raven.
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
into drm-next
More new stuff for 4.15. Highlights:
- Add clock query interface for raven
- Add new FENCE_TO_HANDLE ioctl
- UVD video encode ring support on polaris
- transparent huge page DMA support
- deadlock fixes
- compute pipe lru tweaks
- powerplay cleanups and regression fixes
- fix duplicate symbol issue with radeon and amdgpu
- misc bug fixes
* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (72 commits)
drm/radeon/dp: make radeon_dp_get_dp_link_config static
drm/radeon: move ci_send_msg_to_smc to where it's used
drm/amd/sched: fix deadlock caused by unsignaled fences of deleted jobs
drm/amd/sched: NULL out the s_fence field after run_job
drm/amd/sched: move adding finish callback to amd_sched_job_begin
drm/amd/sched: fix an outdated comment
drm/amd/sched: rename amd_sched_entity_pop_job
drm/amdgpu: minor coding style fix
drm/ttm: add transparent huge page support for DMA allocations v2
drm/ttm: add support for different pool sizes
drm/ttm: remove unsued options from ttm_mem_global_alloc_page
drm/amdgpu: add uvd enc irq
drm/amdgpu: add uvd enc ib test
drm/amdgpu: add uvd enc ring test
drm/amdgpu: add uvd enc vm functions (v2)
drm/amdgpu: add uvd enc into run queue
drm/amdgpu: add uvd enc rings
drm/amdgpu: add new uvd enc ring methods
drm/amdgpu: add uvd enc command in header
drm/amdgpu: add uvd enc registers in header
...
|
|
Fix two minor 80 char issues.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Add UVD encode IRQ handle and enable the UVD encode trap
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Generate create/destroy messages to test UVD encode indirect buffer function.
And enable UVD encode IB test during device initialization.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Add UVD encode ring test functions. And enable UVD encode ring test
during UVD encode hardware initialization.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Add UVD encode ring vm functions to handle frame ecoding.
v2: squash in warning fix (James)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
UVD 6.3 has two UVD encode rings. Add the ring structures and initialize the hw ring buffers.
Currently only ASIC Polaris10/11/12 uses UVD6.3 encode engine on HEVC encoding.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Add new UVD encode ring methods get/set/emit/flush/sync to support uvd6.3 HEVC encoding
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Add UVD encode command interface definition for uvd6.3 HEVC encoding
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
The dead circular lock senario captured is as followed.
The idea of the fix is moving read_user_wptr outside of
acquire_queue...release_queue critical section
[ 63.477482] WARNING: possible circular locking dependency detected
[ 63.484091] 4.12.0-kfd-ozeng #3 Not tainted
[ 63.488531] ------------------------------------------------------
[ 63.495146] HelloWorldLoop/2526 is trying to acquire lock:
[ 63.501011] (&mm->mmap_sem){++++++}, at: [<ffffffff911898ce>] __might_fault+0x3e/0x90
[ 63.509472]
but task is already holding lock:
[ 63.515716] (&adev->srbm_mutex){+.+...}, at: [<ffffffffc0484feb>] lock_srbm+0x2b/0x50 [amdgpu]
[ 63.525099]
which lock already depends on the new lock.
[ 63.533841]
the existing dependency chain (in reverse order) is:
[ 63.541839]
-> #2 (&adev->srbm_mutex){+.+...}:
[ 63.548178] lock_acquire+0x6d/0x90
[ 63.552461] __mutex_lock+0x70/0x8c0
[ 63.556826] mutex_lock_nested+0x16/0x20
[ 63.561603] gfx_v8_0_kiq_resume+0x1039/0x14a0 [amdgpu]
[ 63.567817] gfx_v8_0_hw_init+0x204d/0x2210 [amdgpu]
[ 63.573675] amdgpu_device_init+0xdea/0x1790 [amdgpu]
[ 63.579640] amdgpu_driver_load_kms+0x63/0x220 [amdgpu]
[ 63.585743] drm_dev_register+0x145/0x1e0
[ 63.590605] amdgpu_pci_probe+0x11e/0x160 [amdgpu]
[ 63.596266] local_pci_probe+0x40/0xa0
[ 63.600803] pci_device_probe+0x134/0x150
[ 63.605650] driver_probe_device+0x2a1/0x460
[ 63.610785] __driver_attach+0xdc/0xe0
[ 63.615321] bus_for_each_dev+0x5f/0x90
[ 63.619984] driver_attach+0x19/0x20
[ 63.624337] bus_add_driver+0x40/0x270
[ 63.628908] driver_register+0x5b/0xe0
[ 63.633446] __pci_register_driver+0x5b/0x60
[ 63.638586] rtsx_pci_switch_output_voltage+0x1d/0x20 [rtsx_pci]
[ 63.645564] do_one_initcall+0x4c/0x1b0
[ 63.650205] do_init_module+0x56/0x1ea
[ 63.654767] load_module+0x208c/0x27d0
[ 63.659335] SYSC_finit_module+0x96/0xd0
[ 63.664058] SyS_finit_module+0x9/0x10
[ 63.668629] entry_SYSCALL_64_fastpath+0x1f/0xbe
[ 63.674088]
-> #1 (reservation_ww_class_mutex){+.+.+.}:
[ 63.681257] lock_acquire+0x6d/0x90
[ 63.685551] __ww_mutex_lock.constprop.11+0x8c/0xed0
[ 63.691426] ww_mutex_lock+0x67/0x70
[ 63.695802] amdgpu_verify_access+0x6d/0x100 [amdgpu]
[ 63.701743] ttm_bo_mmap+0x8e/0x100 [ttm]
[ 63.706615] amdgpu_bo_mmap+0xd/0x60 [amdgpu]
[ 63.711814] amdgpu_mmap+0x35/0x40 [amdgpu]
[ 63.716904] mmap_region+0x3b5/0x5a0
[ 63.721255] do_mmap+0x400/0x4d0
[ 63.725260] vm_mmap_pgoff+0xb0/0xf0
[ 63.729625] SyS_mmap_pgoff+0x19e/0x260
[ 63.734292] SyS_mmap+0x1d/0x20
[ 63.738199] entry_SYSCALL_64_fastpath+0x1f/0xbe
[ 63.743681]
-> #0 (&mm->mmap_sem){++++++}:
[ 63.749641] __lock_acquire+0x1401/0x1420
[ 63.754491] lock_acquire+0x6d/0x90
[ 63.758750] __might_fault+0x6b/0x90
[ 63.763176] kgd_hqd_load+0x24f/0x270 [amdgpu]
[ 63.768432] load_mqd+0x4b/0x50 [amdkfd]
[ 63.773192] create_queue_nocpsch+0x535/0x620 [amdkfd]
[ 63.779237] pqm_create_queue+0x34d/0x4f0 [amdkfd]
[ 63.784835] kfd_ioctl_create_queue+0x282/0x670 [amdkfd]
[ 63.790973] kfd_ioctl+0x310/0x4d0 [amdkfd]
[ 63.795944] do_vfs_ioctl+0x90/0x6e0
[ 63.800268] SyS_ioctl+0x74/0x80
[ 63.804207] entry_SYSCALL_64_fastpath+0x1f/0xbe
[ 63.809607]
other info that might help us debug this:
[ 63.818026] Chain exists of:
&mm->mmap_sem --> reservation_ww_class_mutex --> &adev->srbm_mutex
[ 63.830382] Possible unsafe locking scenario:
[ 63.836605] CPU0 CPU1
[ 63.841364] ---- ----
[ 63.846123] lock(&adev->srbm_mutex);
[ 63.850061] lock(reservation_ww_class_mutex);
[ 63.857475] lock(&adev->srbm_mutex);
[ 63.864084] lock(&mm->mmap_sem);
[ 63.867657]
*** DEADLOCK ***
[ 63.873884] 3 locks held by HelloWorldLoop/2526:
[ 63.878739] #0: (&process->mutex){+.+.+.}, at: [<ffffffffc06e1a9a>] kfd_ioctl_create_queue+0x24a/0x670 [amdkfd]
[ 63.889543] #1: (&dqm->lock){+.+...}, at: [<ffffffffc06eedeb>] create_queue_nocpsch+0x3b/0x620 [amdkfd]
[ 63.899684] #2: (&adev->srbm_mutex){+.+...}, at: [<ffffffffc0484feb>] lock_srbm+0x2b/0x50 [amdgpu]
[ 63.909500]
stack backtrace:
[ 63.914187] CPU: 3 PID: 2526 Comm: HelloWorldLoop Not tainted 4.12.0-kfd-ozeng #3
[ 63.922184] Hardware name: AMD Carrizo/Gardenia, BIOS WGA5819N_Weekly_15_08_1 08/19/2015
[ 63.930865] Call Trace:
[ 63.933464] dump_stack+0x85/0xc9
[ 63.936999] print_circular_bug+0x1f9/0x207
[ 63.941442] __lock_acquire+0x1401/0x1420
[ 63.945745] ? lock_srbm+0x2b/0x50 [amdgpu]
[ 63.950185] lock_acquire+0x6d/0x90
[ 63.953885] ? __might_fault+0x3e/0x90
[ 63.957899] __might_fault+0x6b/0x90
[ 63.961699] ? __might_fault+0x3e/0x90
[ 63.965755] kgd_hqd_load+0x24f/0x270 [amdgpu]
[ 63.970577] load_mqd+0x4b/0x50 [amdkfd]
[ 63.974745] create_queue_nocpsch+0x535/0x620 [amdkfd]
[ 63.980242] pqm_create_queue+0x34d/0x4f0 [amdkfd]
[ 63.985320] kfd_ioctl_create_queue+0x282/0x670 [amdkfd]
[ 63.991021] kfd_ioctl+0x310/0x4d0 [amdkfd]
[ 63.995499] ? kfd_ioctl_destroy_queue+0x70/0x70 [amdkfd]
[ 64.001234] do_vfs_ioctl+0x90/0x6e0
[ 64.005065] ? up_read+0x1a/0x40
[ 64.008496] SyS_ioctl+0x74/0x80
[ 64.011955] entry_SYSCALL_64_fastpath+0x1f/0xbe
[ 64.016863] RIP: 0033:0x7f4b3bd35f07
[ 64.020696] RSP: 002b:00007ffe7689ec38 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
[ 64.028786] RAX: ffffffffffffffda RBX: 00000000002a2000 RCX: 00007f4b3bd35f07
[ 64.036414] RDX: 00007ffe7689ecb0 RSI: 00000000c0584b02 RDI: 0000000000000005
[ 64.044045] RBP: 00007f4a3212d000 R08: 00007f4b3c919000 R09: 0000000000080000
[ 64.051674] R10: 00007f4b376b64b8 R11: 0000000000000246 R12: 00007f4a3212d000
[ 64.059324] R13: 0000000000000015 R14: 0000000000000064 R15: 00007ffe7689ef50
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
for being able to convert an amdgpu fence into one of the handles.
Mesa will use this.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Linux 4.14-rc3
Requested by Daniel for the tracing build fix in fixes.
|
|
1. use flag PP_DPM_DISABLED within powerplay
notify amdgpu dpm state by cgs interface.
2. delete redundant virtualization check in
powerplay
v2: squash in fix for hwmgr_init (Rex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
This removes the init path as well, since the init path
just did some constant init of some structs.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
These don't seem to change at runtime, and the initialisers
are constant data. This could be improved by not selecting
the apu/non-apu path on each pcie read/write access.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
This isn't safe if we have multiple GPUs plugged in, since
there is only one copy of this struct in the bss, just allocate
on stack, it's 40/108 bytes which should be safe.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
amdgpu not care powerplay or dpm is enabled.
just check ip functions and pp functions
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
cgs device not free.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
When many wavefronts cause VM faults at the same time, it can
overwhelm the interrupt handler and cause IH ring overflows before
the driver can notify or kill the faulting application.
As a workaround I'm introducing limited per-VM fault credit. After
that number of VM faults have occurred, further VM faults are
filtered out at the prescreen stage of processing.
This depends on the PASID in the interrupt packet, so it currently
only works for KFD contexts.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
This patch provides a guarantee that the first n queues allocated by
an application will be on different pipes. Where n is the number of
pipes available from the hardware.
This helps avoid ring aliasing which can result in work executing in
time-sliced mode instead of truly parallel mode.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Useful for testing the effects of multipipe compute without recompiling.
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
A performance regression for OpenCL tests on Polaris11 had this feature
disabled for all asics.
Instead, disable it selectively on the affected asics.
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
The error handling for virtual functions assumed a single
vf per VM and didn't properly account for bare metal. Make
the error arrays per device and add locking.
Reviewed-by: Gavin Wan <gavin.wan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
into drm-next
First feature pull for 4.15. Highlights:
- Per VM BO support
- Lots of powerplay cleanups
- Powerplay support for CI
- pasid mgr for kfd
- interrupt infrastructure for recoverable page faults
- SR-IOV fixes
- initial GPU reset for vega10
- prime mmap support
- ttm page table debugging improvements
- lots of bug fixes
* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux: (232 commits)
drm/amdgpu: clarify license in amdgpu_trace_points.c
drm/amdgpu: Add gem_prime_mmap support
drm/amd/powerplay: delete dead code in smumgr
drm/amd/powerplay: delete SMUM_FIELD_MASK
drm/amd/powerplay: delete SMUM_WAIT_INDIRECT_FIELD
drm/amd/powerplay: delete SMUM_READ_FIELD
drm/amd/powerplay: delete SMUM_SET_FIELD
drm/amd/powerplay: delete SMUM_READ_VFPF_INDIRECT_FIELD
drm/amd/powerplay: delete SMUM_WRITE_VFPF_INDIRECT_FIELD
drm/amd/powerplay: delete SMUM_WRITE_FIELD
drm/amd/powerplay: delete SMU_WRITE_INDIRECT_FIELD
drm/amd/powerplay: move macros to hwmgr.h
drm/amd/powerplay: move PHM_WAIT_VFPF_INDIRECT_FIELD to hwmgr.h
drm/amd/powerplay: move SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL to hwmgr.h
drm/amd/powerplay: move SMUM_WAIT_INDIRECT_FIELD_UNEQUAL to hwmgr.h
drm/amd/powerplay: add new helper functions in hwmgr.h
drm/amd/powerplay: use SMU_IND_INDEX/DATA_11 pair
drm/amd/powerplay: refine powerplay code.
drm/amd/powerplay: delete dead code in hwmgr.h
drm/amd/powerplay: refine interface in struct pp_smumgr_func
...
|
|
into drm-fixes
A few fixes for 4.14. Nothing too major.
* 'drm-fixes-4.14' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: disable hard reset in hibernate for APUs
drm/amdgpu: revert tile table update for oland
|
|
It was not clear. The rest of the driver is MIT/X11.
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
v2: drop hdp invalidate/flush.
v3: honor pgoff during prime mmap. Add a barrier after cpu access.
v4: drop begin/end_cpu_access() for now, revisit later.
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Just set the CPU access required flag when we pin it.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
this fix memory leak due to request_firmware after driver
unloaded
v2:
release gmc firmware for gmc6/7/8 as well
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
this way after KIQ MQD released in drv unloading, CPC
can still let KIQ access this MQD thus RLCV SAVE_VF
will not fail
v2:
always use VRAM domain for KIQ MQD no matter BM or SRIOV
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
v2:
move kcq_disable out of SRIOV, make it genearal
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
only with this way we can debug the VMC page fault issue
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping().
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
When max_bytes is not 8 bytes aligned and bo size is larger than
max_bytes, the last 8 bytes in a ttm node may be left unchanged.
For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size
is 0x200000, the problem will happen.
In order to fix the problem, we separately store the max nums of
PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs
structure, rather than inferring it from bytes limit of SDMA
constant fill, i.e. fill_max_bytes.
Together with the fix, we replace the hard code value "10" in
amdgpu_vm_bo_update_mapping() with the corresponding values from
structure amdgpu_vm_pte_funcs.
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
Use 2MB fragment size by default for older hardware generations as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: John Bridgman <john.bridgman@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
SRIOV doesn't implement PMC capability of PCIe, so it can't update
power state by reading PMC register.
Currently, amdgpu driver doesn't disable pci device when removing
driver, the enable_cnt of pci device will not be decrease to 0.
When reloading driver, pci_enable_device will do nothing as
enable_cnt is not zero. And power state will not be updated as PMC
is not support.
So current_state of pci device is not D0 state and pci_enable_msi
return fail.
Add pci_disable_device when remmoving driver to fix the issue.
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
