summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/amdgpu
AgeCommit message (Collapse)Author
2021-03-10drm/amdgpu: add mmhub support for aldebaran (v3)Le Ma
v1: dupilcate mmhub_v1_7.c from mmhub_v1_0.c because mmhub register address for aldebaran is different from existing asics (Le) v2: switch to latest mmhub_v9_4_2 register headers (Hawking) v3: squash in init VM_L2_CNTL3 default value for mmhub v1_7 Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add soc15 common ip block support for aldebaranLe Ma
Initialize aldebaran common ip block Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add gpu_info fw parse support for aldebaranLe Ma
Parses asic configurations stored in gpu_info firmware and make them available for driver to use. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add register base init for aldebaran (v2)Le Ma
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-10drm/amdgpu: add aldebaran asic typeLe Ma
Add aldebaran in amdgpu_asic_name array and amdgpu_asic_type enum Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/display: Add a backlight module optionTakashi Iwai
There seem devices that don't work with the aux channel backlight control. For allowing such users to test with the other backlight control method, provide a new module option, aux_backlight, to specify enabling or disabling the aux backport support explicitly. As default, the aux support is detected by the hardware capability. v2: make the backlight option generic in case we add future backlight types (Alex) BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1180749 BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: enable TMZ by default on Raven asicsAlex Deucher
This has been stable for a while. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: Fix some unload driver issuesEmily Deng
If have memory leak, maybe it will have issue in ttm_bo_force_list_clean-> ttm_mem_evict_first. Set adev->gart.ptr to null to avoid to call amdgpu_gmc_set_pte_pde to cause ptr issue pointer when calling amdgpu_gart_unbind in amdgpu_bo_fini which is after gart_fini. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: Fix some unload driver issuesEmily Deng
When unloading driver after killing some applications, it will hit sdma flush tlb job timeout which is called by ttm_bo_delay_delete. So to avoid the job submit after fence driver fini, call ttm_bo_lock_delayed_workqueue before fence driver fini. And also put drm_sched_fini before waiting fence. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amd/amdgpu: add fini virt data exchange to ip_suspendJingwen Chen
[Why] when try to shutdown guest vm in sriov mode, virt data exchange is not fini. After vram lost, trying to write vram could hang cpu. [How] add fini virt data exchange in ip_suspend Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Jack Zhang <Jack.Zhang1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: add sdma 4_x interrupts printingFeifei Xu
Add VM_HOLE/DOORBELL_INVALID_BE/POLL_TIMEOUT/SRBMWRITE interrupt info printing. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.Feifei Xu
SDMA 4_x asics share the same MGCG/MGLS setting. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: add DMUB trace event IRQ source defineLeo (Hanghong) Ma
[Why & How] We use DMCUB outbox0 interrupt to log DMCUB trace buffer events as Linux kernel traces, so need to add some irq source related defination in the header files; Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05drm/amdgpu: enable one vf mode on sienna cichlid vfHorace Chen
sienna cichlid needs one vf mode which allows vf to set and get clock status from guest vm. So now expose the required interface and allow some smu request on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send SMU request under sriov vf. OD use same command as getting pp table which is not allowed for sienna cichlid, so remove OD feature under sriov vf. Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: correct DRM_ERROR for kvmalloc_arrayChen Li
This may avoid debug confusion. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Li <chenli@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: Use kvmalloc for CS chunksChen Li
The number of chunks/chunks_array may be passed in by userspace and can be large. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Li <chenli@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcieKevin Wang
the register offset isn't needed division by 4 to pass RREG32_PCIE() Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: add SECURE DISPLAY TA firmware info in debugfsKevin Wang
add SECUREDISPLAY TA firmware info in amdgpu_fimrware_info() Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-03drm/amdgpu: refine PSP TA firmware info print in debugfsKevin Wang
refine PSP TA firmware info print in amdgpu_firmware_info(). Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy flounderAlex Deucher
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: Only check for S0ix if AMD_PMC is configuredAlex Deucher
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: add missing df counter disable writeJonathan Kim
Request to stop DF performance counters is missing the actual write to the controller register. Reported-by: Chris Freehill <chris.freehill@amd.com> Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02drm/amdgpu: correct TA RAP firmware information print errorKevin Wang
miss RAP TA in loop. (when i == 4) Fix: drm/amdgpu: add RAP TA version print in amdgpu_firmware_info Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reported-by: Candice Li <candice.li@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: remove unnecessary reading for epprom headerDennis Li
If the number of badpage records exceed the threshold, driver has updated both epprom header and control->tbl_hdr.header before gpu reset, therefore GPU recovery thread no need to read epprom header directly. v2: merge amdgpu_ras_check_err_threshold into amdgpu_ras_eeprom_check_err_threshold Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: add RAP TA version print in amdgpu_firmware_infoKevin Wang
add RAP TA version print in amdgpu_firmware_info. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTEYang Li
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1589:0-23: WARNING: fops_ib_preempt should be defined with DEFINE_DEBUGFS_ATTRIBUTE ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1592:0-23: WARNING: fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu/codec: drop the internal codec indexAlex Deucher
And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: bump driver version for new video codec INFO ioctl queryAlex Deucher
So mesa can check when to query the kernel vs use hardcoded codec bandwidth data. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: add INFO ioctl support for querying video caps (v4)Alex Deucher
We currently hardcode these in mesa, but querying them from the kernel makes more sense since there may be board specific limitations that the kernel driver is better suited to determining. Userpace patches that use this interface: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case, squash in memory leak fix v4: drop extra break Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3)Alex Deucher
For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: add asic callback for querying video codec info (v3)Alex Deucher
This will be used by a new INFO ioctl query to fetch the decode and encode capabilities from the kernel driver rather than hardcoding them in mesa. This gives us more fine grained control of capabilities using information that is only availabl in the kernel (e.g., platform limitations or bandwidth restrictions). v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amd/display: Add module parameter for freesync video modeAurabindo Pillai
[Why] This option shall be opt-in by default since it is a temporary solution until long term solution is agreed upon which may require userspace interface changes. This feature give the user a seamless experience when freesync aware programs (media players for instance) switches to a compatible freesync mode when playing videos. Enabling this feature also have the potential side effect of causing higher power consumption due to running a mode with lower resolution and base clock frequency with the highest base clock supported on the monitor as per its advertised modes. There has been precedent of manufacturing modes in the kernel. In AMDGPU, the existing usage are for common modes and scaling modes. Other driver have a similar approach as well. [How] Adds a module parameter to enable freesync video mode modeset optimization. Enabling this mode allows the driver to skip a full modeset when a freesync compatible mode is requested by the userspace. This parameter will also add some additional modes that are within the connected monitor's VRR range corresponding to common video modes, which media players can use for a seamless experience while making use of freesync. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: Remove amdgpu_device arg from free_sgt api (v2)Ramesh Errabolu
Currently callers have to provide handle of amdgpu_device, which is not used by the implementation. It is unlikely this parameter will become useful in future, thus removing it v2: squash in unused variable fix Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amd/amdgpu: move inc gpu_reset_counter after drm_sched_stopJingwen Chen
Move gpu_reset_counter after drm_sched_stop to avoid race condition caused by job submitted between reset_count +1 and drm_sched_stop. Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: decline max_me for mec2_fw remove in renoir/arcturusChangfeng
The value of max_me in amdgpu_gfx_rlc_setup_cp_table should reduce to 4 when mec2_fw is removed on asic renoir/arcturus. Or it will cause kernel NULL pointer when modprobe driver. Signed-off-by: Changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu:disable VCN for Navi12 SKUAsher.Song
Navi12 0x7360/C7 SKU has no video support, so remove it. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Asher.Song <Asher.Song@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-26drm/amdgpu: reserve backup pages for bad page retirmentDennis Li
To ensure user has a constant of VRAM accessible in run-time, driver reserves limit backup pages when init, and return ones when bad pages retired, to keep no change of unused memory size. v2: refine codes to calculate badpags threshold Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:79:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:81:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/vcn3.0: add wptr/rptr reset/update for share memorySonny Jiang
Because of dpg, the rptr/wptr need to be saved on fw shared memory, and restore them back in RBC_RB_RPTR/WPTR in kernel at power up. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: disable mec2 fw bin loadingJohn Clements
disable mec2 fw bin loading and reference on unsupported ASIC Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: fix wrong executable setting for dimgrey_cavefish_reg_init.cTao Zhou
Remove executable configuration for the file. Reported-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: fix shutdown and poweroff process failed with s0ixPrike Liang
In the shutdown and poweroff opt on the s0i3 system we still need un-gate the gfx clock gating and power gating before destory amdgpu device. Fixes: 628c36d7b238e2 ("drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1499 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/sdma5.2: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1621:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1619:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amdgpu: remove unused variable from struct amdgpu_boNirmoy Das
Fixes: 62914a99dee5a ("drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amdgpu: mark local function as staticNirmoy Das
Mark amdgpu_ras_debugfs_create_ctrl_node() as static. Fixes: eb14235668777b ("drm/amdgpu: do not keep debugfs dentry") Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amdgpu: do not use drm middle layer for debugfsNirmoy Das
Use debugfs API directly instead of drm middle layer. This also includes following debugfs file output changes: 1 amdgpu_evict_vram/amdgpu_evict_gtt output will not contain any braces. e.g. (0) --> 0 2 amdgpu_gpu_recover output will print return value of amdgpu_device_gpu_recover() instead of not so important "gpu recover" message. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: do not use drm middle layer for debugfsNirmoy Das
Use debugfs API directly instead of drm middle layer. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: do not use drm middle layer for debugfsNirmoy Das
Use debugfs API directly instead of drm middle layer. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amdgpu: remove CONFIG_DRM_AMDGPU_GART_DEBUGFSNirmoy Das
Removed unused CONFIG_DRM_AMDGPU_GART_DEBUGFS code. We can use umr instead of this gart debugfs. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-07-30 02:00:11 +0000