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path: root/drivers/gpu/drm/amd/powerplay
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2019-10-25drm/amd/powerplay: Add EEPROM I2C read/write support to Arcturus.Andrey Grodzovsky
The communication is done through SMU table and hence the code is in powerplay. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: Add interface for I2C transactions to SMU.Andrey Grodzovsky
Will be used by Arcturus support for RAS page retirement. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: clear the swSMU code layerEvan Quan
With this cleanup, the APIs from amdgpu_smu.c will map to ASIC specific ones directly. Those can be shared around all SMU V11/V12 ASICs will be put in smu_v11_0.c and smu_v12_0.c respectively. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: split out those internal used swSMU APIs V2Evan Quan
Those swSMU APIs used internally are moved to smu_internal.h while others are kept in amdgpu_smu.h. V2: give a better name smu_internal.h for the place to hold those internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: add lock protection for swSMU APIs V2Evan Quan
This is a quick and low risk fix. Those APIs which are exposed to other IPs or to support sysfs/hwmon interfaces or DAL will have lock protection. Meanwhile no lock protection is enforced for swSMU internal used APIs. Future optimization is needed. V2: strip the lock protection for all swSMU internal APIs Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: update Arcturus driver smu interface XGMI link partEvan Quan
To fit the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/powerplay: use local renoir array sizes for clock fetchingAlex Deucher
To avoid walking past the end of the arrays since the PP_SMU defines don't match the renoir defines. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/vi: silence an uninitialized variable warningDan Carpenter
Smatch complains that we need to initialized "*cap" otherwise it can lead to an uninitialized variable bug in the caller. This seems like a reasonable warning and it doesn't hurt to silence it at least. drivers/gpu/drm/amd/amdgpu/vi.c:767 vi_asic_reset_method() error: uninitialized symbol 'baco_reset'. Fixes: 425db2553e43 ("drm/amdgpu: expose BACO interfaces to upper level from PP") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17drm/amdgpu/powerplay: implement interface pp_power_profile_modePrike Liang
implement get_power_profile_mode for getting power profile mode status. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17drm/amdgpu: No need to check gfxoff status after enable gfxoff featurechen gong
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17drm/amd/powerplay: bug fix for memory clock request from displayKenneth Feng
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-17drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acqPrike Liang
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. The patch can fix VCN IB test failed and DAL get dispaly count failed issue. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: wire up BACO to powerplay API for smu7Alex Deucher
Wire up the powerplay callbacks for for BACO for smu7 devices. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: split out common smu7 BACO codeAlex Deucher
Several of the BACO functions are common across smu7-based asics. Split the common code out. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on CIAlex Deucher
This adds BACO support for CI asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on FijiAlex Deucher
This adds BACO support for Fiji asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on VegaMAlex Deucher
This adds BACO support for VegaM asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on polarisAlex Deucher
This adds BACO support for Polaris asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on IcelandAlex Deucher
This adds BACO support for Iceland asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add support for BACO on tongaAlex Deucher
This adds BACO support for Tonga. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add core support for pre-SOC15 bacoAlex Deucher
This adds core support for BACO on pre-vega asics. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu: remove in_baco_reset hackAlex Deucher
It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/powerplay: add renoir funcs to support dcHersen Wu
there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: enable Arcturus runtime VCN dpm on/offEvan Quan
Enable runtime VCN DPM on/off on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: bug fix for pcie parameters overrideKenneth Feng
Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: add BACO platformCaps for VEGA20Le Ma
BACO reset is needed for RAS recovery. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: send EnterBaco msg with argument as RAS recovery flagLe Ma
1 indicates RAS recovery flag in SMU FW. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20Le Ma
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting for ECC supported SKU. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: re-enable FW_DSTATE feature bitXiaojie Yuan
SMU firmware has fix the bug, so remove this workaround. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14Kevin Wang
add navi14 umd pstate peak clock support. NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: enable df cstate control on swSMU routineEvan Quan
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-15drm/amd/powerplay: enable df cstate control on powerplay routineEvan Quan
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/swSMU/navi: add feature toggles for more thingsAlex Deucher
Add toggles for more power features. Helpful in debugging. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/powerplay: Use swap() where appropriateVille Syrjälä
@swap@ identifier TEMP; expression A,B; @@ - TEMP = A; - A = B; - B = TEMP; + swap(A, B); @@ type T; identifier swap.TEMP; @@ ( - T TEMP; | - T TEMP = {...}; ) ... when != TEMP Cc: Rex Zhu <rex.zhu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amd/powerplay: add more feature bitsXiaojie Yuan
Additional features that can be enabled in the SMU. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-10drm/amdgpu/powerplay: fix typo in mvdd table setupAlex Deucher
Polaris and vegam use count for the value rather than level. This looks like a copy paste typo from when the code was adapted from previous asics. I'm not sure that the SMU actually uses this value, so I don't know that it actually is a bug per se. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609 Reported-by: Robert Strube <rstrube@gmail.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07drm/amd/powerplay: Fix error handling in smu_init_fb_allocations()Dan Carpenter
The error handling is off by one. We should not free the first "tables[i].bo" without decrementing "i" because that might result in a double free. The second problem is that when an error occurs, then the zeroth element "tables[0].bo" isn't freed. I had make "i" signed int for the error handling to work, so I just updated "ret" as well as a clean up. Fixes: f96357a991b9 ("drm/amd/powerplay: implement smu_init(fini)_fb_allocations function") Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-07drm/amd/powerplay: unlock on error in smu_resume()Dan Carpenter
This function needs to drop the mutex before returning. Fixes: f7e3a5776fa6 ("drm/amd/powerplay: check SMU engine readiness before proceeding on S3 resume") Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amdgpu: Drop unused variable and statementAustin Kim
Even though 'smu8_smu' is declared, it is not used after below statement. smu8_smu = hwmgr->smu_backend; So 'unused variable' could be safely removed to stop warning message as below: drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/smu8_smumgr.c:180:22: warning: variable ‘smu8_smu’ set but not used [-Wunused-but-set-variable] struct smu8_smumgr *smu8_smu; ^ Signed-off-by: Austin Kim <austindh.kim@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: initlialize smu->is_apu is false by defaultKevin Wang
the member of is_apu in smu_context need to initlialize by default. set default value is false (dGPU) for patch: drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu series Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: update the interface for getting dpm full scale clock ↵Prike Liang
frequency Update get_dpm_uclk_limited to get more clock type full scale dpm frequency. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: implement the interface for setting sclk/uclk ↵Prike Liang
profile_peak level Add the interface for setting sclk and uclk peak frequency. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: implement interface set_power_profile_mode() (v2)Prike Liang
v1: Add set_power_profile_mode() for none manual dpm level case setting power profile mode. v2: After input power profile update successfully need can update the smu profile mode. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: add the interfaces for getting and setting profiling dpm ↵Prike Liang
clock level implement get_profiling_clk_mask and force_clk_levels for forcing dpm clk to limit value. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: add interface for getting workload typePrike Liang
The workload type was got from the input of power profile mode. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: add interface for forcing and unforcing dpm limit valuePrike Liang
That's base function for forcing and unforcing dpm limit value. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: implement the interface for setting soft freq rangePrike Liang
The APU soft freq range set by different way from DGPU, thus need implement the function respectively base on each common SMU part. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: bypass dpm_context null pointer check guard for some smu ↵Prike Liang
series For now APU has no smu_dpm_context structure for containing default/current related dpm tables, thus will needn't initialize smu_dpm_context to aviod APU null pointer issue. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: add sensor lock support for smuKevin Wang
when multithreading access sysfs of amdgpu_pm_info at the sametime. the swsmu driver cause smu firmware hang. eg: single thread access: Message A + Param A ==> right Message B + Param B ==> right Message C + Param C ==> right multithreading access: Message A + Param B ==> error Message B + Param A ==> error Message C + Param C ==> right the patch will add sensor lock(mutex) to avoid this error. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/powerplay: change metrics update period from 1ms to 100msKevin Wang
v2: change period from 10ms to 100ms (typo error) too high frequence to update mertrics table will cause smu firmware error,so change mertrics table update period from 1ms to 100ms (navi10, 12, 14) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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