summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_display.c
AgeCommit message (Collapse)Author
2024-06-20drm/i915: Pass the whole atomic state to intel_color_prepare_commit()Ville Syrjälä
We'll have need to examine both the old and new crtc states in intel_color_prepare_commit(), so let's just pass in the whole atomic state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-20drm/i915: Add async flip tracepointVille Syrjälä
Add a separate tracepoint for async flips vs. sync plane updates to make it a bit easier to figure out what is happening. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611133344.30673-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-06-13drm/i915: Factor out function to modeset commit a set of pipesImre Deak
Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-6-imre.deak@intel.com
2024-06-12drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondaryStanislav Lisovskiy
According to BSpec we now should call "master" pipes, "primary" pipes and "slave" pipes, should be "secondary" pipes. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Don't rename port sync stuff, catch a few more things] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240603112551.6481-3-stanislav.lisovskiy@intel.com
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, because in future we might have multiple configurations, involving multiple bigjoiners, ultrajoiner, however it is possible to use same api for handling both. v2: - Renamed back some bigjoiner specific parts for now(Ville) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Catch a few more cases] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607075457.15700-1-stanislav.lisovskiy@intel.com
2024-06-11drm/i915/display: Skip Panel Replay on pipe comparison if no active planesJouni Högander
Panel Replay is not enabled if there are no active planes. Do not compare it on pipe comparison. Otherwise we get pipe mismatch. Fixes: ac9ef327327b ("drm/i915/psr: Panel replay has to be enabled before link training") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-5-jouni.hogander@intel.com
2024-06-11drm/i915: Compute CMRR and calculate vtotalMitul Golani
Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Variable refresh mode with VRR timing generator or not. Make CMRR as small subset of FAVT mode, when Panel is running on Fixed refresh rate and on VRR framework then only enable CMRR to match with actual refresh rate. --v2: - Update is_cmrr_frac_required function return as bool, not int. [Jani] - Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani] - Fix typo and usage of camel case in cmrr_get_vtotal. [Jani] - Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani] - Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani] - Correct valiable name usage in is_cmrr_frac_required. [Ville] --v3: - Removing RFC tag. --v4: - Added edp check to address edp usecase for now. (ville) - Updated is_cmrr_fraction_required to more simplified calculation. - on longterm goal to be worked upon uapi as suggestion from ville. --v5: - Correct vtotal paramas accuracy and add 2 digit precision. - Avoid using DIV_ROUND_UP and improve scanline precision. --v6: - Make CMRR a small subset of FAVT mode. --v7: - Update commit message to avoid confusion with Legacy VRR (Ankit). - Add cmrr.enable in last, so remove from this patch. --v8: - Set cmrr.enable in current patch instead of separate patch (Ankit). - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly (Ankit). - is_edp is not required inside is_cmrr_frac_required function (Ankit). - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. --v9: - Move patch to last and set other bits before computing cmrr.enable.(Ankit) - Add TODO: for to address target refresh rate precision as future enhancement. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-10-mitulkumar.ajitkumar.golani@intel.com
2024-06-11drm/i915: Define and compute Transcoder CMRR registersMitul Golani
Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. --v2: - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] - Fix indent and order based on register offset. [Jani] --v3: - Removing RFC tag. --v4: - Update place holder for CMRR register definition. (Jani) --v5: - Add CMRR register definitions to a separate file intel_vrr_reg.h. --v6: - Fixed indentation. (Jani) - Add dependency header intel_display_reg_defs.h. (Jani) - Rename file name to intel_vrr_regs.h instead of reg.h (Jani) --v7: - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing, as it is already being done during intel_vrr_enable. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-4-mitulkumar.ajitkumar.golani@intel.com
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_SET_CONTEXT_LATENCY register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/989f89994edae0829e3b6d5d6e3d8a521f0eda00.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_DDI_FUNC_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4ccf75561aa0fb209fd71c85e9089b0350570fd6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5267c167414fb46a25277c1c9a802f6ccf8de3c9.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_M2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/31337adcaca1333724600b0afe6e3880f0948d5e.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N1Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N1 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0960c3726a36999b38084dce6c3824882921c475.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M1Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_M1 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bf25d447d98009f56f2c5b2205719ab2d9a70c93.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_N2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6eeb0c74d6e566f04a193b2a3f1272e58df66f20.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M2Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_M2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1fda9b8cd446727845089844a1c8eeb5c8ae7b5a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N1Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_N1 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/80759c6efdfdb59c4bd624af85b9db38ebe06f65.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_M1Jani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_M1 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/aa87444d7b2c0c695729c15730bb11aa922b7561.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to CHV_CANVASJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CHV_CANVAS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a48c7984a14412ef74af250d5bc2ea9097aa2222.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to CHV_BLENDJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CHV_BLEND register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a2c5064ee3a985f7b7b5c7e672737df447d3af29.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_ARB_CTLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_ARB_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e75e80bd96e05ece6b82c0bdb509527ab2dd0e6d.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANSCONFJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANSCONF register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9afc96be1cbe4514cdca701ab434b4c7aa3a55ba.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOSJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_PGM_RATIOS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8453205c9619bb8453bf4904d0c5bb868f614fc4.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PFIT_CONTROLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_CONTROL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/fad44d3d987d914c83844cdf172adaa19772e035.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MULTJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_MULT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7ea79208a81fd5c3b021bcd8e1f9f90607716d82.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to PIPESRCJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPESRC register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ac1959b7038d6fedb4777dcf2b961de901fb8880.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFTJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VSYNCSHIFT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8103a31fbf6da725e6aed3bb86c15bbd581164fb.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to BCLRPATJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the BCLRPAT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f04d0313032d5820a14cc504af390b4b1006fae6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VSYNCJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VSYNC register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eed30cb59cc45955a88cdf951023b0e695095760.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VBLANKJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VBLANK register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c33739ac6f26105fd1ad79b0027b6626e241c7bc.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_VTOTALJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VTOTAL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/751bc7046f5e2c5fc6a4fe5ade2e836c641abdb7.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HSYNCJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HSYNC register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d387281470c9b677adb659b80fa3385df2faca99.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HBLANKJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HBLANK register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/19d3d11d522be1787db89bdc254ae826ca4fb50a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_HTOTALJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HTOTAL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4bdba7417341782b74b89753b7db7fdc3edf932c.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-07drm/i915: pass dev_priv explicitly to DPLLJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DPLL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7deea1d86c2706994450ec938f8f174a2ac54d27.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-31drm/i915: Plumb the full atomic state into icl_check_nv12_planes()Ville Syrjälä
icl_check_nv12_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-30drm/i915/display: Add compare config for MTL+ platformsMika Kahola
Currently, we may bump into pll mismatch errors during the state verification stage. This happens when we try to use fastset instead of full modeset. Hence, we would need to add a check for pipe configuration to ensure that the sw and the hw configuration will match. In case of hw and sw mismatch, we would need to disable fastset and use full modeset instead. v2: Fix C10 error on PLL comparison (BAT) Use memcmp instead of fixed loops for pll config comparison (Jani) Clean up and use intel_cx0pll_dump_hw_state() to dump pll information (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com
2024-05-27drm/i915: Bury c8_planes_changed() in intel_color_check()Ville Syrjälä
The c8_planes_changed() check in the high level atomic code is a bit of an eyesore. Push it inside intel_color_check() so the high level code doesn't have to care about this stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-27drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()Ville Syrjälä
Move the intel_crtc_needs_color_update() into intel_color_check() so that the caller doesn't have to care about this. This will also enable us to hide the c8_planes_changed() thing better. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-27drm/i915: Plumb the entire atomic state into intel_color_check()Ville Syrjälä
Bunch of stuff in intel_color_check() needs to look at both the old and new crtc states. Currently we do that by digging the full atomic state via the crtc_state->state pointer. That thing is a total footgun if I ever saw one, as it's only valid during specific parts of the atomic flow. A lot of people have been bitten by this thing in the past when trying to use it after it's no longer valid. Take a small step towards elimination of the footgun by not using it in the inte_color_check(). Instead we plumb in the entire atomic state all the way from the top. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-24drm/i915: pass dev_priv explicitly to DSPCNTRJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPCNTR register macro. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d9434a718658d7dc6dba1e8a54f80cd1503d0b33.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-22drm/i915: Extract i9xx_plane_regs.hVille Syrjälä
Relocate all pre-skl primary plane register definitions into their own declutter i915_reg.h. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-22drm/i915: Add skl+ plane name aliases to enum plane_idVille Syrjälä
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch of unnecessary head scratching. Add aliases using the skl+ plane names. And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1 as we only ever have 0-2 sprites per pipe on those platforms. v2: Don't break icl_nv12_y_plane_mask() (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-16drm/i915: pass dev_priv explicitly to CURCNTRJani Nikula
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURCNTR register macro. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/06bc681558c86f351ae596e9600133bb10ae4bdd.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915: Extract intel_cursor_regs.hVille Syrjälä
Move most cursor register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915: Extract skl_universal_plane_regs.hVille Syrjälä
Move most of the SKL+ universal plane register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915/psr: Rename has_psr2 as has_sel_updateJouni Högander
We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
2024-05-03drm/i915/display: perform transient flushMatthew Auld
Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-19-radhakrishna.sripada@intel.com
2024-05-03drm/i915/bmg: Extend DG2 tc check to futureRadhakrishna Sripada
Discrete cards use the Port numbers TC1-4 for the offsets. The regular flow for type-c subsystem port initialization can be skipped. This check is present in DG2. Extend this to future discrete products. Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-5-radhakrishna.sripada@intel.com
2024-05-03drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/Ville Syrjälä
Rename need_async_flip_disable_wa to need_async_flip_toggle_wa to better reflect the fact that we need to deal with the bad PLANE_CTL_ASYNC_FLIP double buffering behaviour going both ways. Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-6-ville.syrjala@linux.intel.com
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-07-22 16:38:32 +0000