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path: root/drivers/pci/dwc
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2017-11-14Merge branch 'pci/host-layerscape' into nextBjorn Helgaas
* pci/host-layerscape: PCI: layerscape: Change default error response behavior PCI: Disable MSI for Freescale Layerscape PCIe RC mode arm64: dts: ls1046a: Add PCIe controller DT nodes arm64: dts: ls1012a: Add PCIe controller DT node PCI: layerscape: Add support for ls1012a arm64: dts: ls1012a: Add MSI controller DT node irqchip/ls-scfg-msi: Add LS1012a MSI support
2017-11-14Merge branch 'pci/host-hisi' into nextBjorn Helgaas
* pci/host-hisi: PCI: hisi: Add HiSilicon STB SoC PCIe controller driver
2017-10-24PCI: hisi: Add HiSilicon STB SoC PCIe controller driverJianguo Sun
Add a HiSilicon STB SoC PCIe controller driver. This controller is based on the DesignWare PCIe core. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-10-20PCI: layerscape: Change default error response behaviorMinghuan Lian
By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it sends an OKAY response to the device's internal AXI slave system interface. However, this default system error response behavior cannot be used for other types of outbound non-posted requests. For example, the outbound memory read transaction requires an actual ERROR response, like UR completion or completion timeout. Fix this by forwarding the error response of the non-posted request. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-10-12PCI: layerscape: Add support for ls1012aHou Zhiqiang
Add support for ls1012a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Acked-by: Thomas Gleixner <tglx@linutronix.de>
2017-10-11PCI: dra7xx: Add shutdown handler to cleanly turn off clocksKeerthy
Add shutdown handler to cleanly turn off clocks. This will help in cases of kexec where in a new kernel can boot abruptly. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-07Merge branch 'pci/trivial' into nextBjorn Helgaas
* pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
2017-09-07Merge branch 'pci/endpoint' into nextBjorn Helgaas
* pci/endpoint: tools: PCI: Add a missing option help line misc: pci_endpoint_test: Enable/Disable MSI using module param misc: pci_endpoint_test: Avoid using hard-coded BAR sizes misc: pci_endpoint_test: Add support to not enable MSI interrupts misc: pci_endpoint_test: Add support to provide aligned buffer addresses misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR PCI: designware-ep: Do not disable BARs during initialization PCI: dra7xx: Reset all BARs during initialization PCI: dwc: designware: Provide page_size to pci_epc_mem PCI: endpoint: Remove the ->remove() callback PCI: endpoint: Add support to poll early for host commands PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs PCI: endpoint: Do not reset *command* inadvertently PCI: endpoint: Add "volatile" to pci_epf_test_reg PCI: endpoint: Add support for configurable page size PCI: endpoint: Make ->remove() callback optional PCI: endpoint: Add an API to get matching "pci_epf_device_id" PCI: endpoint: Use of_dma_configure() to set initial DMA mask
2017-09-07Merge branch 'pci/host-spear13xx' into nextBjorn Helgaas
* pci/host-spear13xx: PCI: spear13xx: Fix platform_get_irq() error handling
2017-09-07Merge branch 'pci/host-qcom' into nextBjorn Helgaas
* pci/host-qcom: PCI: qcom: Add support for IPQ8074 PCIe controller dt-bindings: PCI: qcom: Add support for IPQ8074 PCI: qcom: Use block IP version for operations PCI: qcom: Explicitly request exclusive reset control PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expanders
2017-09-07Merge branch 'pci/host-layerscape' into nextBjorn Helgaas
* pci/host-layerscape: PCI: layerscape: Add support for ls1088a PCI: layerscape: Add support for ls2088a PCI: artpec6: Stop enabling writes to DBI read-only registers PCI: layerscape: Remove unnecessary class code fixup PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates PCI: dwc: Add accessors for write permission of DBI read-only registers PCI: layerscape: Disable outbound windows configured by bootloader PCI: layerscape: Refactor ls1021_pcie_host_init() PCI: layerscape: Move generic init functions earlier in file PCI: layerscape: Add class code and multifunction fixups for ls1021a PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()
2017-09-07Merge branch 'pci/host-kirin' into nextBjorn Helgaas
* pci/host-kirin: PCI: kirin: Constify dw_pcie_host_ops structure
2017-09-07Merge branch 'pci/host-keystone' into nextBjorn Helgaas
* pci/host-keystone: PCI: keystone: Use PCI_NUM_INTX PCI: keystone: Remove duplicate MAX_*_IRQS defs PCI: keystone-dw: Remove unused ks_pcie, pci variables
2017-09-07Merge branch 'pci/host-imx6' into nextBjorn Helgaas
* pci/host-imx6: PCI: imx6: Explicitly request exclusive reset control
2017-09-07Merge branch 'pci/host-hisi' into nextBjorn Helgaas
* pci/host-hisi: PCI: hisi: Constify dw_pcie_host_ops structure PCI: hisi: Remove unused variable driver
2017-09-07Merge branch 'pci/host-exynos' into nextBjorn Helgaas
* pci/host-exynos: PCI: exynos: Fix platform_get_irq() error handling
2017-09-07Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas
* pci/host-dra7xx: PCI: dra7xx: Fix platform_get_irq() error handling PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe() PCI: dra7xx: Use PCI_NUM_INTX
2017-09-07Merge branch 'pci/host-designware' into nextBjorn Helgaas
* pci/host-designware: PCI: dwc: Clear MSI interrupt status after it is handled, not before PCI: qcom: Allow ->post_init() to fail PCI: qcom: Don't unroll init if ->init() fails PCI: dwc: designware: Handle ->host_init() failures PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static
2017-09-07Merge branch 'pci/host-artpec6' into nextBjorn Helgaas
* pci/host-artpec6: PCI: artpec6: Fix platform_get_irq() error handling
2017-09-05PCI: spear13xx: Fix platform_get_irq() error handlingFabio Estevam
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
2017-09-05PCI: artpec6: Fix platform_get_irq() error handlingFabio Estevam
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com>
2017-09-05PCI: armada8k: Fix platform_get_irq() error handlingFabio Estevam
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-09-05PCI: dra7xx: Fix platform_get_irq() error handlingFabio Estevam
When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-05PCI: exynos: Fix platform_get_irq() error handlingFabio Estevam
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
2017-09-01PCI: Fix typos and whitespace errorsBjorn Helgaas
Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: layerscape: Add support for ls1088aHou Zhiqiang
Add support for ls1088a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
2017-08-29PCI: layerscape: Add support for ls2088aHou Zhiqiang
The ls2088a PCIe controller's register addresses are different from ls2080a, so add a match entry to identify ls2088a PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
2017-08-29PCI: artpec6: Stop enabling writes to DBI read-only registersHou Zhiqiang
Previously we enabled writes to the DBI read-only registers so the Class Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc() enables write permission itself, so we don't need to do it here. Stop enabling writes to the DBI read-only registers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Remove unnecessary class code fixupHou Zhiqiang
Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup from the Layerscape driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: dwc: Enable write permission for Class Code, Interrupt Pin updatesHou Zhiqiang
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt Pin registers, but the fixes don't actually work because these registers are read-only. Enable write permission before updating the Class Code and Interrupt Pin. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: dwc: Add accessors for write permission of DBI read-only registersHou Zhiqiang
The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Disable outbound windows configured by bootloaderHou Zhiqiang
Disable all the outbound windows to avoid one transaction hitting multiple outbound windows. dw_pcie_setup_rc() will reconfigure the outbound windows, which may conflict with windows configured by the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Refactor ls1021_pcie_host_init()Hou Zhiqiang
ls1021_pcie_host_init() duplicated the code in the generic ls_pcie_host_init(). Call ls_pcie_host_init() instead of duplicating the code. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: designware-ep: Do not disable BARs during initializationKishon Vijay Abraham I
Some platforms like K2G has reserved use of BAR_0 which shouldn't be disabled by software. Avoid disabling all BARs during initialization. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: dra7xx: Reset all BARs during initializationKishon Vijay Abraham I
dra7xx has all base address registers (BAR) enabled by default. Reset all BARs during initialization and so that BARs are enabled only if they are actually used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: dwc: designware: Provide page_size to pci_epc_memKishon Vijay Abraham I
Use the newly introduced __pci_epc_mem_init() instead of pci_epc_mem_init() to provide page_size to pci_epc_mem. This is in preparation for adding EP support to K2G which has a restriction that the address region should be either divided into 1MB/2MB/4MB or 8MB sizes (Ref: 11.14.4.9.1 Outbound Address Translation in K2G TRM SPRUHY8F January 2016 – Revised May 2017). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-29PCI: layerscape: Move generic init functions earlier in fileHou Zhiqiang
We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from device-specific routines. Move the generic functions earlier in the file so we won't need forward declarations. This is strictly a code move with no functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Add class code and multifunction fixups for ls1021aHou Zhiqiang
The current code depends on class code and multifunction fixups done by the bootloader. Perform these fixups in ls1021_pcie_host_init() to remove this dependency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracketHou Zhiqiang
The STRFMR1 is not a DBI read-only register, so move it out from the write-enable bracket. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()Hou Zhiqiang
We called dw_pcie_setup_rc() from the ls1021a host init function, but not from the common ls_pcie_host_init() function, so platforms other than ls1021a still depended on initialization by the bootloader. Call dw_pcie_setup_rc() from ls_pcie_host_init() to reduce dependencies on the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-24PCI: qcom: Add support for IPQ8074 PCIe controllerVaradarajan Narayanan
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the similar to the existing SoC, however the clocks and reset lines differ. Signed-off-by: smuthayy <smuthayy@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> [bhelgaas: fix capitalization and "dev" usage to match existing style] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24PCI: qcom: Use block IP version for operationsVaradarajan Narayanan
Presently, when support for a new SoC is added, the driver ops structures and functions are versioned with plain 1, 2, 3 etc. Instead use the block IP version number. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24PCI: qcom: Explicitly request exclusive reset controlPhilipp Zabel
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-24PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam
The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2017-08-22PCI: dwc: Clear MSI interrupt status after it is handled, not beforeFaiz Abbas
If the interrupt status is cleared before it is handled, it is possible that another interrupt will trigger while servicing the previous one. This is causing timeouts in some wireless lan cards which use PCIe. Clear MSI interrupt status after it gets serviced instead of before calling generic_handler. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com>
2017-08-22PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe()Gustavo A. R. Silva
platform_get_irq() returns an error code, but the pci-dra7xx driver ignores it and always returns -EINVAL. This is not correct and prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq() on failure. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-08-19PCI: kirin: Constify dw_pcie_host_ops structureBhumika Goyal
Make this structure const as it is only stored in the ops field of a pcie_port structure, which is of type const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-19PCI: hisi: Constify dw_pcie_host_ops structureBhumika Goyal
Make this structure const as it is only stored in the ops field of a pcie_port structure, which is of type const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-16PCI: keystone: Use PCI_NUM_INTXBjorn Helgaas
Switch from using custom MAX_LEGACY_IRQS and MAX_LEGACY_HOST_IRQS macros to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Based-on-similar-patches-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
2017-08-16PCI: keystone: Remove duplicate MAX_*_IRQS defsBjorn Helgaas
MAX_MSI_HOST_IRQS and MAX_LEGACY_HOST_IRQS are defined in both pci-keystone.h (which is included by pci-keystone.c) and in pci-keystone.c itself. Remove the duplicate definitions from pci-keystone.c. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
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