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2024-08-05phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resumePiyush Mehta
On a few Kria KR260 Robotics Starter Kit the PS-GEM SGMII linkup is not happening after the resume. This is because serdes registers are reset when FPD is off (in suspend state) and needs to be reprogrammed in the resume path with the same default initialization as done in the first stage bootloader psu_init routine. To address the failure introduce a set of serdes registers to be saved in the suspend path and then restore it on resume. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/1722837547-2578381-1-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-04phy: exynos5-usbdrd: fix error code in probe()Dan Carpenter
Return negative -ENOMEM instead of positive ENOMEM. Fixes: 497ddafe915e ("phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/a956a3e2-c6ce-4f07-ad80-ec8a96e00d16@stanley.mountain Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-04phy: fsl-imx8mq-usb: fix tuning parameter nameXu Yang
According to fsl,imx8mq-usb-phy.yaml, this tuning parameter should be fsl,phy-pcs-tx-deemph-3p5db-attenuation-db. Fixes: 63c85ad0cd81 ("phy: fsl-imx8mp-usb: add support for phy tuning") Cc: stable@vger.kernel.org Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20240801124642.1152838-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-04phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisationAbel Vesa
Update the PCIe Gen4 PHY init sequence with the latest based on internal Qualcomm documentation. Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240801-x1e80100-phy-qmp-pcie-fix-config-v2-1-cdc0f22b4169@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-24Merge tag 'phy-for-6.11' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New Support - Samsung Exynos gs101 drd combo phy - Qualcomm SC8180x USB uniphy, IPQ9574 QMP PCIe phy - Airoha EN7581 PCIe phy - Freescale i.MX8Q HSIO SerDes phy - Starfive jh7110 dphy tx Updates: - Resume support for j721e-wiz driver - Updates to Exynos usbdrd driver - Support for optional power domains in g12a usb2-phy driver - Debugfs support and updates to zynqmp driver" * tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (56 commits) phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema dt-bindings: phy: qcom,qmp-usb: fix spelling error phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk phy: exynos5-usbdrd: convert core clocks to clk_bulk phy: exynos5-usbdrd: support isolating HS and SS ports independently dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible phy: core: Fix documentation of of_phy_get phy: starfive: Correct the dphy configure process phy: zynqmp: Add debugfs support phy: zynqmp: Take the phy mutex in xlate phy: zynqmp: Only wait for PLL lock "primary" instances phy: zynqmp: Store instance instead of type phy: zynqmp: Enable reference clock correctly phy: cadence-torrent: Check return value on register read phy: Fix the cacography in phy-exynos5250-usb2.c phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON ...
2024-07-19Merge tag 'usb-6.11-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB / Thunderbolt updates from Greg KH: "Here is the big set of USB and Thunderbolt changes for 6.11-rc1. Nothing earth-shattering in here, just constant forward progress in adding support for new hardware and better debugging functionalities for thunderbolt devices and the subsystem. Included in here are: - thunderbolt debugging update and driver additions - xhci driver updates - typec driver updates - kselftest device driver changes (acked by the relevant maintainers, depended on other changes in this tree.) - cdns3 driver updates - gadget driver updates - MODULE_DESCRIPTION() additions - dwc3 driver updates and fixes All of these have been in linux-next for a while with no reported issues" * tag 'usb-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (112 commits) kselftest: devices: Add test to detect device error logs kselftest: Move ksft helper module to common directory kselftest: devices: Move discoverable devices test to subdirectory usb: gadget: f_uac2: fix non-newline-terminated function name USB: uas: Implement the new shutdown callback USB: core: add 'shutdown' callback to usb_driver usb: typec: Drop explicit initialization of struct i2c_device_id::driver_data to 0 usb: dwc3: enable CCI support for AMD-xilinx DWC3 controller usb: dwc2: add support for other Lantiq SoCs usb: gadget: Use u16 types for 16-bit fields usb: gadget: midi2: Fix incorrect default MIDI2 protocol setup usb: dwc3: core: Check all ports when set phy suspend usb: typec: tcpci: add support to set connector orientation dt-bindings: usb: Convert fsl-usb to yaml usb: typec: ucsi: reorder operations in ucsi_run_command() usb: typec: ucsi: extract common code for command handling usb: typec: ucsi: inline ucsi_read_message_in usb: typec: ucsi: rework command execution functions usb: typec: ucsi: split read operation usb: typec: ucsi: simplify command sending API ...
2024-07-03phy: renesas: phy-rcar-gen3-usb2: Control VBUS for RZ/G2L SoCsBiju Das
Use regulator_hardware_enable() for controlling VBUS enable for RZ/G2L alike SoCs in interrupt context. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20240702180032.207275-4-biju.das.jz@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-07-02phy: airoha: Add dtime and Rx AEQ IO registersLorenzo Bianconi
Introduce Tx-Rx detection Time and Rx AEQ training mappings to phy-airoha-pcie driver. This is a preliminary patch to introduce PCIe support to En7581 SoC through the mediatek-gen3 PCIe driver. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/edf3b28926177166c65256604d69f2f576cb6fb3.1719682943.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)André Draszik
Add support for the Exynos USB 3.1 DRD combo phy, as found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and DisplayPort. In terms of UTMI+, this is very similar to the existing Exynos850 support in this driver. The difference is that this combo phy supports both UTMI+ (HS) and PIPE3 (SS). It also supports DP alt mode. The number of ports for UTMI+ and PIPE3 can be determined using the LINKPORT register (which also exists on Exynos E850). For SuperSpeed (SS) a new SS phy is in use and its PIPE3 interface is new compared to Exynos E850, and also very different from the existing support for older Exynos SoCs in this driver. The SS phy needs a bit more configuration work and register tuning for signal quality to work reliably, presumably due to the higher frequency, e.g. to account for different board layouts. Additionally, power needs to be enabled before writing to the SS phy registers. This commit adds the necessary changes for USB HS and SS to work. DisplayPort is out of scope in this commit. Notes: * For the register tuning, exynos5_usbdrd_apply_phy_tunes() has been added with the appropriate data structures to support tuning at various stages during initialisation. Since these are hardware specific, the platform data is supposed to be populated accordingly. The implementation is loosely modelled after the Samsung UFS PHY driver. There is one tuning state for UTMI+, PTS_UTMI_POSTINIT, to execute after init and generally intended for HS signal tuning, as done in this commit. PTS_PIPE3_PREINIT PTS_PIPE3_INIT PTS_PIPE3_POSTINIT PTS_PIPE3_POSTLOCK are tuning states for PIPE3. In the downstream driver, preinit differs by Exynos SoC, and postinit and postlock are different per board. The latter haven't been implemented for gs101 here, because downstream doesn't use them on gs101 either. * Signal lock acquisition for SS depends on the orientation of the USB-C plug. Since there currently is no infrastructure to chain connector events to both the USB DWC3 driver and this phy driver, a work-around has been added in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock() to check both registers if it failed in one of the orientations. * Equally, we can only establish SS speed in one of the connector orientations due to programming differences when selecting the lane mux in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(), which really needs to be dynamic, based on the orientation of the connector. * As is, we can establish a HS link using any cable, and an SS link in one orientation of the plug, falling back to HS if the orientation is reversed to the expectation. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-6-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulkAndré Draszik
Using the regulator_bulk APIs, the handling of power supplies becomes much simpler. There is no need anymore to check if regulators have been acquired or not, the bulk APIs will do all the work for us. We can also drop the various handles to the individual power supplies in the driver runtime data and instead simply treat them all as one thing. Error cleanup also becomes much simpler. Converting to the regulator_bulk APIs also makes it easier to add support for those SoCs that have additional power supplies for the PHY. Google Tensor gs101 is one example of such a SoC. Otherwise we'd have to add all additional supplies individually via individual calls to regulator_get() and enable/disable handle them all individually, including complicated error handling. That doesn't scale and clutters the code. Just update the code to use the regulator_bulk APIs. Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-5-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulkAndré Draszik
In preparation for support for additional platforms, convert the phy register access clock to using the clk_bulk interfaces. Newer SoCs like Google Tensor gs101 require additional clocks for access to additional (different) register areas (PHY, PMA, PCS), and converting to clk_bulk simplifies addition of those extra clocks. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: exynos5-usbdrd: convert core clocks to clk_bulkAndré Draszik
Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. No need to check any flags whether or not certain clocks exist or not. Further, we can drop the various handles to the individual clocks in the driver data and instead simply treat them all as one thing. So far, this driver assumes that all platforms have a clock "ref". It also assumes that the clocks "phy_pipe", "phy_utmi", and "itp" exist if the platform data "has_common_clk_gate" is set to true. It then goes and individually tries to acquire and enable and disable all the individual clocks one by one. Rather than relying on these implicit clocks and open-coding the clock handling, we can just explicitly spell out the clock names in the different device data and use that information to populate clk_bulk_data, allowing us to use the clk_bulk APIs for managing the clocks. As a side-effect, this change highlighted the fact that exynos5_usbdrd_phy_power_on() forgot to check the result of the clock enable calls. Using the clk_bulk APIs, the compiler now warns when return values are not checked - therefore add the necessary check instead of silently ignoring failures and continuing as if all is OK when it isn't. For consistency, also change a related dev_err() to dev_err_probe() in exynos5_usbdrd_phy_clk_handle() to get consistent error message formatting. Finally, exynos5_usbdrd_phy_clk_handle() prints an error message in all cases as necessary (except for -ENOMEM). There is no need to print another message in its caller (the probe() function), and printing errors during OOM conditions is usually discouraged. Drop the duplicated message in exynos5_usbdrd_phy_probe(). Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-3-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: exynos5-usbdrd: support isolating HS and SS ports independentlyAndré Draszik
Some versions of this IP have been integrated using separate PMU power control registers for the HS and SS parts. One example is the Google Tensor gs101 SoC. Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value. The existing 'usbdrdphy' alias can not be used in this case because that is meant for determining the correct PMU offset if multiple distinct PHYs exist in the system (as opposed to one PHY with multiple isolators). Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-2-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: core: Fix documentation of of_phy_getMiaoqian Lin
of_phy_put is used for of_phy_get to release the reference count. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20240626080911.203630-1-linmq006@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: starfive: Correct the dphy configure processChanghuang Liang
We actually want to calculate the alignment values first, then use the alignment value to look up the data from reg_configs[]. Fixes: d3ab79553308 ("phy: starfive: Add mipi dphy tx support") Reviewed-by: Shengyang Chen <shengyang.chen@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240627020059.163535-1-changhuang.liang@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Add debugfs supportSean Anderson
Add support for printing some basic status information to debugfs. This is helpful when debugging phy consumers to make sure they are configuring the phy appropriately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-6-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Take the phy mutex in xlateSean Anderson
Take the phy mutex in xlate to protect against concurrent modification/access to gtr_phy. This does not typically cause any issues, since in most systems the phys are only xlated once and thereafter accessed with the phy API (which takes the locks). However, we are about to allow userspace to access phys for debugging, so it's important to avoid any data races. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-5-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Only wait for PLL lock "primary" instancesSean Anderson
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Store instance instead of typeSean Anderson
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: zynqmp: Enable reference clock correctlySean Anderson
Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save") Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: cadence-torrent: Check return value on register readMa Ke
cdns_torrent_dp_set_power_state() does not consider that ret might be overwritten. Add return value check of regmap_read_poll_timeout() after register read in cdns_torrent_dp_set_power_state(). Fixes: 5b16a790f18d ("phy: cadence-torrent: Reorder few functions to remove function declarations") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: Fix the cacography in phy-exynos5250-usb2.cLiu Jing
The word 'swtich' is wrong, so fix it. Signed-off-by: Liu Jing <liujing@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20240701112517.6597-1-liujing@cmss.chinamobile.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-02phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCONCristian Ciocaltea
Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-01Merge 6.10-rc6 into usb-nextGreg Kroah-Hartman
We need the USB fixes in here as well for some follow-on patches. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-06-20phy: airoha: Add PCIe PHY driver for EN7581 SoC.Lorenzo Bianconi
Introduce support for Airoha PCIe PHY controller available in EN7581 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20ac99aa8628d97778594f606681db7f868f24fe.1718485860.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-20phy: freescale: imx8qm-hsio: Include bitfield.h for FIELD_PREPNathan Chancellor
In various configurations/architectures, bitfield.h may not be transitively included, which results in a compiler error because FIELD_PREP is an unexpanded macro: drivers/phy/freescale/phy-fsl-imx8qm-hsio.c:459:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 459 | val = FIELD_PREP(HSIO_MODE_MASK, val); | ^ 1 error generated. Include bitfield.h explicitly to fix the build. Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406170340.7mk3WU3Q-lkp@intel.com/ Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240620-phy-fsl-imx8qm-hsio-add-bitfield-include-v1-1-5c7c09ed87e6@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver supportRichard Zhu
Add i.MX8QM HSIO PHY driver support. i.MX8QM HSIO has three lane PHY instances, and can be bound to the following controllers in the different use cases listed in below table. - two lanes capable PCIEA controller. - one lane PCIEB controller. - AHCI SATA controller. i.MX8QM HSIO PHYs support the following use cases. +----------------------------------------------------+ | | Lane0| Lane1| Lane2| |-------------------------------|------|------|------| | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA | |-------------------------------|------|------|------| | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| |-------------------------------|------|------|------| | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | +----------------------------------------------------+ Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/1716962565-2084-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15phy: starfive: Add mipi dphy tx supportShengyang Chen
Add mipi dphy tx support for the StarFive JH7110 SoC. It is a module which is used to receive data from DSI driver and transfer data to DSI interface like mipi screen. Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240418035020.47876-3-shengyang.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15phy: qcom: qmp-pcie: restore compatibility with existing DTsDmitry Baryshkov
Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: broadcom: add missing MODULE_DESCRIPTION() macrosJeff Johnson
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb3.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240608-md-drivers-phy-broadcom-v1-1-f070f84cc3f0@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: ti: am654-serdes: Remove duplicate defineJan Kiszka
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/60089a71-dad2-4a87-a304-a738e3334d4a@siemens.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()André Draszik
While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZAndré Draszik
Using 0x82 seems odd, where everything else is just a sequence. On E850, this macro isn't used (as a register value), only to assign its value to the 'extrefclk' variable, which is otherwise unused on that platform. Older platforms don't appear to support 26MHz in the first place (since this macro was added for E850). Furthermore, the downstream driver uses 0x82 to denote USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the other values we match downstream's non-DIFF macros. Update to avoid confusion. No functional change intended. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-4-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: exynos5-usbdrd: make phy_isol() take a bool for clarityAndré Draszik
on / not on is just a boolean flag and is a bit misleading as currently on==1 means to turn off the power, and on==0 to turn power on. Rename the flag and make it a bool to avoid confusion of future readers of this code. No functional change. While at it, fix a whitespace issue in nearby comment. No functional change. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-3-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: exynos5-usbdrd: convert udelay() to fsleep()André Draszik
The timers-howto recommends using usleep_range() and friends anytime waiting for >= ~10us is required. Doing so can help the timer subsystem a lot to coalesce wakeups. Additionally, fsleep() exists as a convenient wrapper so we do not have to think about which exact sleeping function is required in which case. Convert all udelay() calls in this driver to use fsleep() to follow the recommendataion. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-12phy: exynos5-usbdrd: uniform order of register bit macrosAndré Draszik
Most of the macros are ordered high -> low, but there are some outliers. Order them all uniformly from high to low. This will allow adding additional register (field) definitions in a consistent way. While at it, also remove some extra empty lines to group register bit field definitions together with the relevant register. This makes the registers easier to distinguish visually. No functional change. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-1-4ccba5afa7cc@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-04phy: ti: phy-da8xx-usb: Add runtime PM supportBastien Curutchet
Runtime PM is not supported while USB PHY can be turned off from register accesses. Add runtime PM for the USB2.0 PHY. The PHY is entirely shut down to save as much power as possible. This means that gadgets will not be discovered once suspend state is entered, and suspend state can not be left without an explicit user intervention (through sysfs). That's why runtime PM is disabled by default. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> Link: https://lore.kernel.org/r/20240528102026.40136-2-bastien.curutchet@bootlin.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-06-03phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEsdevi priya
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp: Add missing register definitions for PCS V5devi priya
Add missing register offsets for PCS V5 registers. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp: Add missing offsets for Qserdes PLL registers.devi priya
Add missing register offsets for Qserdes PLL. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsetsAbel Vesa
Currently, none of the X1E80100 supported boards upstream have enabled DP. As for USB, the reason it is not broken when it's obvious that the offsets are wrong is because the only difference with respect to USB is the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to work, the DP serdes tables need to be added as they have different values for V6 N4 when compared to V6 ones, even though they use the same V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as well. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp: pcs: Add missing v6 N4 register offsetsAbel Vesa
The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS register offsets, which are different. Add the offsets so the mentioned platform can be fixed later on. Add the new PCS offsets in a dedicated header file. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp: qserdes-txrx: Add missing registers offsetsAbel Vesa
Currently, the x1e80100 uses pure V6 register offsets for DP part of the combo PHY. This hasn't been an issue because external DP is not yet enabled on any of the boards yet. But in order to enabled it, all these new V6 N4 register offsets are needed. So add them. Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: miphy28lp: remove unused struct 'miphy_initval'Dr. David Alan Gilbert
'miphy_initval' is unused since the original commit 2c14e9be0c60 ("phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY"). Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Link: https://lore.kernel.org/r/20240527205844.165279-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: starfive: remove unused struct 'regval'Dr. David Alan Gilbert
'regval' is unused since the original commit f8aa660841bc ("phy: starfive: Add mipi dphy rx support"). Remove it. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240527205937.165325-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp-usb: Add sc8180x USB UNIPHYBjorn Andersson
The SC8180X platform has two UNIPHY blocks, add support for these in the QMP driver. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-2-60a904392438@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: cadence-torrent: add suspend and resume supportThomas Richard
Add suspend and resume support. The already_configured flag is cleared during the suspend stage to force the PHY initialization during the resume stage. Co-developed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-8-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: cadence-torrent: remove noop_ops phy operationsThomas Richard
Even if a PHY is already configured, the PHY operations are needed during resume stage, as the PHY is in reset state. The noop_ops PHY operations is removed to always have PHY operations. The already_configured flag is checked at the begening of init, configure and poweron operations to keep the already_configured behaviour. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-7-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: cadence-torrent: add already_configured to struct cdns_torrent_phyThomas Richard
Add already_configured to struct cdns_torrent_phy, so it can be used at differents stages. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-6-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: cadence-torrent: register resets even if the phy is already configuredThomas Richard
Resets are needed during suspend and resume stages. So they shall be registered during the probe even the phy is already initialized. The function cdns_torrent_reset is renamed cdns_torrent_of_get_reset() to make it clear. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-5-f15815833974@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2024-12-27 04:25:58 +0000