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path: root/drivers/pinctrl/renesas
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2023-01-26pinctrl: renesas: r8a77950: Add VIN[45] pins, groups, and functionsGeert Uytterhoeven
Add pins, groups, and functions for channels 4 and 5 of the Video Input Module (VIN) on the Renesas R-Car H3 ES1.x (R8A77950) SoC, based on the version for the R-Car H3 ES2.0+ (R8A77951) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/92c9b3b535d27ea7fcc0aa73d298783d710c214a.1673425207.git.geert+renesas@glider.be
2023-01-26pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checksLad Prabhakar
Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each supported SoC. While at it, for readability set n_port_pins based on the GPIO pin configs and not on GPIO names for r9a07g044_data as done for r9a07g043_data. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230102221815.273719-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interruptsLad Prabhakar
On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also the pin configs are completely different. This patch makes sure we use the appropriate pin configs for each SoC (which is passed as part of the OF data) while configuring the GPIO pin as interrupts instead of using rzg2l_gpio_configs[] for all the SoCs. Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230102221815.273719-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-01-26pinctrl: renesas: r8a779g0: Fix alignment in GPSR[678]_* macrosGeert Uytterhoeven
The alignment of the second column in the definitions of the GPSR[678]_* macros does not match the alignment used in other definitions. Fix this to improve uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/9424a0e7f6d66a94d333df9fdc5cdf3b7defb8f5.1669036423.git.geert+renesas@glider.be
2022-11-20Merge tag 'renesas-pinctrl-for-v6.2-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.2 - Use dynamic GPIO base on combined pincctrl/gpio controllers on SH/R-Mobile SoCs, - Miscellaneous improvements.
2022-11-17pinctrl: renesas: gpio: Use dynamic GPIO base if no function GPIOsGeert Uytterhoeven
Since commit 502df79b860563d7 ("gpiolib: Warn on drivers still using static gpiobase allocation") in gpio/for-next, one or more warnings are printed during boot on systems where the pin controller also provides GPIO functionality: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Fix this for ARM-based SH/R-Mobile SoCs by: 1. Taking into account a non-zero GPIO base in the various GPIO chip callbacks, 2. Switching to dynamic allocation of the GPIO base when support for legacy function GPIOs is not enabled. On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO controller and the GPIO function controller must not be changed, as all board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided by the various <cpu/sh*.h> header files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be
2022-11-15pinctrl: renesas: rzg2l: remove unnecessary check from rzg2l_dt_node_to_map()Biju Das
This patch removes the unnecessary check from rzg2l_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108191309.3908415-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-15pinctrl: renesas: rzv2m: remove unnecessary check from rzv2m_dt_node_to_map()Biju Das
This patch removes the unnecessary check from rzv2m_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108183223.3902097-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-24pinctrl: renesas: Add missing header(s)Andy Shevchenko
Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-10Merge tag 'pinctrl-v6.0-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Outside the pinctrl driver and DT bindings we hit some Arm DT files, patched by the maintainers. Other than that it is business as usual. Core changes: - Add PINCTRL_PINGROUP() helper macro (and use it in the AMD driver). New drivers: - Intel Meteor Lake support. - Reneasas RZ/V2M and r8a779g0 (R-Car V4H). - AXP209 variants AXP221, AXP223 and AXP809. - Qualcomm MSM8909, PM8226, PMP8074 and SM6375. - Allwinner D1. Improvements: - Proper pin multiplexing in the AMD driver. - Mediatek MT8192 can use generic drive strength and pin bias, then fixes on top plus some I2C pin group fixes. - Have the Allwinner Sunplus SP7021 use the generic DT schema and make interrupts optional. - Handle Qualcomm SC7280 ADSP. - Handle Qualcomm MSM8916 CAMSS GP clock muxing. - High impedance bias on ZynqMP. - Serialize StarFive access to MMIO. - Immutable gpiochip for BCM2835, Ingenic, Qualcomm SPMI GPIO" * tag 'pinctrl-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (117 commits) dt-bindings: pinctrl: qcom,pmic-gpio: add PM8226 constraints pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM pinctrl: qcom: sm8250: Fix PDC map pinctrl: amd: Fix an unused variable dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp dt-bindings: pinctrl: mt8186: Add gpio-line-names property ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header pinctrl: amd: Use unicode for debugfs output pinctrl: amd: Fix newline declaration in debugfs output pinctrl: at91: Fix typo 'the the' in comment dt-bindings: pinctrl: st,stm32: Correct 'resets' property name pinctrl: mvebu: Missing a blank line after declarations. pinctrl: qcom: Add SM6375 TLMM driver dt-bindings: pinctrl: Add DT schema for SM6375 TLMM dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable" pinctrl: imx93: Add MODULE_DEVICE_TABLE() pinctrl: sunxi: Add driver for Allwinner D1 pinctrl: sunxi: Make some layout parameters dynamic pinctrl: sunxi: Refactor register/offset calculation ...
2022-07-10pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interruptLad Prabhakar
Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220707182314.66610-7-prabhakar.mahadev-lad.rj@bp.renesas.com
2022-07-05pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBxKuninori Morimoto
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0Kuninori Morimoto
TSN0 needs MODSEL4 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87letdsj8e.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing ERROROUTC_AKuninori Morimoto
This patch adds missing ERROROUTC_A settings. Current existing ERROROUTC should be _B, this patch tidies it up. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing PWMKuninori Morimoto
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed. This patch adds missing PWM settings, and tidies these up. According to Document, GP3_14 Function4 is PWM2_A, but we can't select it at P1SR3[27:24]. This patch just ignore it for now. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing FlexRayKuninori Morimoto
This patch adds missing FlexRay pins. Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B), this patch names them as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing TPU0TOx_AKuninori Morimoto
This patch adds missing TPU0TOx_A. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing CANFD5_BKuninori Morimoto
This patch adds missing CANFD5_B. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87sfnlsj9t.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing SCIF1_XKuninori Morimoto
This patch adds missing SCIF1_X. Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing SCIF3Kuninori Morimoto
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed. This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing HSCIF1_XKuninori Morimoto
This patch adds missing HSCIF1. Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing HSCIF3_AKuninori Morimoto
This patch adds missing HSCIF3_A. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87y1xdsjar.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_BKuninori Morimoto
This patch adds missing IRQx_A/IRQx_B, and tidies up existing IRQs. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87zghtsjb4.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_XKuninori Morimoto
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X. Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B), this patch names them as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Tidyup POC1 voltageKuninori Morimoto
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx, GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28. According to the HW team, there are no bits assigned. This patch follows HW team's comment. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Tidy up ioctrl_regsKuninori Morimoto
Remove POC2 which is not documented, and remove TD0SEL3 which is not needed. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/874k01txy9.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Remove unused MOD_SELx definitionsKuninori Morimoto
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0. But these have no meaning. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitionsKuninori Morimoto
Current R-Car V4H PFC code has many IPxSRx definitions with all 0. But these have no meaning. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Remove unused NOGP definitionsKuninori Morimoto
Current R-Car V4H PFC code has many NOGP definitions. But these are not used, and they are different from original usage. This patch removes them. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Fixup MODSEL8Kuninori Morimoto
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is indicating that I2C needs 1. But we should use 0 for all cases in reality. New Datasheet should be updated. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: r8a779g0: Add pins, groups and functionsPhong Hoang
This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, MSIOF, PWM, CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> Signed-off-by: CongDang <cong.dang.xn@renesas.com> Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> [Morimoto: merged above patches into one, cleanup white space, sort modules alphabetically, fixup comments] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87bku9ty0b.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC supportLUU HOAI
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0) SoC, including bias, drive strength and voltage control. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: Add PORT_GP_CFG_13 macrosKuninori Morimoto
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the r8a779g0 subdriver. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: Add RZ/V2M pin and gpio controller driverPhil Edworthy
Add support for pin and gpio controller driver for RZ/V2M SoC. Based on the RZ/G2L driver. Note that the DETDO and DETMS dedicated pins are currently not documented in the HW manual as to which pin group they are in. HW team has since said that the output level of 1.8V I/O group 4 (for MD0-7, and debugger) is the same as the 1.8V I/O group 3. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-29pinctrl: renesas: r8a779f0: Remove unused POC2Geert Uytterhoeven
The POWER Condition Control Register 2 (POC2) is unused, and the documentation does not define any valid bits. Remove it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d8a9ea39b49d24e39f4da3f00b64bce34016887d.1655301529.git.geert+renesas@glider.be
2022-06-06pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabledLad Prabhakar
Pin status reported by pinconf-pins file always reported pin status as "input enabled" even for pins which had input disabled. Fix this by returning -EINVAL for the pins which have input disabled. Fixes: c4c4637eb57f2 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Reported-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220511094057.3151-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-14Merge tag 'renesas-pinctrl-for-v5.19-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.19 (take two) - Reserved field optimizations, - Miscellaneous fixes and improvements.
2022-05-05pinctrl: renesas: checker: Add reserved field checksGeert Uytterhoeven
Add checks for discovering registers with reserved fields that could benefit from being described using variable-width reserved field shorthands, reducing kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7786: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 79 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7785: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 150 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7757: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 115 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7734: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 161 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7724: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 8 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7723: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 105 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7722: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 396 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7720: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh73a0: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 154 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7269: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 406 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7264: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 572 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7203: Optimize fixed-width reserved fieldsGeert Uytterhoeven
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 281 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2025-01-11 18:47:01 +0000