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2020-03-02spi: spidev: fix speed setting messageOleksandr Suvorov
The message of max device speed setting is shown when an error in spi_setup() occurs. Instead, it should be shown when the setup call succeeds. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Link: https://lore.kernel.org/r/20200229161841.89144-3-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-03-02spi: spidev: fix a debug message valueOleksandr Suvorov
The debug message in spidev_message() can show wrong xfer speed. It happens if the initial (came from DT) and set with ioctl call spidev speeds are different (spidev->speed_hz != spi->max_speed_hz) and one sends a message with ioctl call and the field of speed is uninitialized (u_tmp->speed_hz == 0). In this case the kernel shows the spi->max_speed_hz value instead of correct spidev->speed_hz. ... set the max speed with an ioctl call: [ 1227.702714] spidev spi0.0: setup mode 0, 32 bits/w, 20000000 Hz max --> 0 (real speed sets to 20000000Hz) send a message with an ioctl call: [ 1227.731801] spidev spi0.0: xfer len 4096 tx 32bits 0 usec 10000000Hz (debug message shows 10000000Hz that is the original max speed of this spidev came from DT) ... Fix the data source for the debug message. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Link: https://lore.kernel.org/r/20200229161841.89144-2-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-03-02spi: bcm63xx-hsspi: Really keep pll clk enabledChristophe JAILLET
The purpose of commit 0fd85869c2a9 ("spi/bcm63xx-hsspi: keep pll clk enabled") was to keep the pll clk enabled through the lifetime of the device. In order to do that, some 'clk_prepare_enable()'/'clk_disable_unprepare()' calls have been added in the error handling path of the probe function, in the remove function and in the suspend and resume functions. However, a 'clk_disable_unprepare()' call has been unfortunately left in the probe function. So the commit seems to be more or less a no-op. Axe it now, so that the pll clk is left enabled through the lifetime of the device, as described in the commit. Fixes: 0fd85869c2a9 ("spi/bcm63xx-hsspi: keep pll clk enabled") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Jonas Gorski <jonas.gorski@gmail.com> Link: https://lore.kernel.org/r/20200228213838.7124-1-christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: pxa2xx: Introduce is_mmp2_ssp() helperAndy Shevchenko
Introduce is_mmp2_ssp() helper to be consistent with the rest helper function to distinguish SSP type. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200227162556.3152-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28Merge series "spi/HiSilicon v3xx: Support dual and quad mode through DMI ↵Mark Brown
quirks" from John Garry <john.garry@huawei.com>: As discussed during the original HiSilicon v3xx SPI driver upstreaming, currently there is no method for the ACPI SPI Serial Bus Connection Resource Descriptor to define the data buswidth [0], [1]. So we can look to get the ACPI spec updated for this, and I have submitted a proposal for a new feature here: https://bugzilla.tianocore.org/show_bug.cgi?id=2557 However I am not sure how successful that will be. In the meantime, as an alternate approach, this RFC proposes to allow the SPI controller driver override the device buswidth. In this example, the driver uses DMI quirks to discover the host machine and set the buswidth override accordingly when the machine is known to support dual or quad mode of operation. I also have included a fix for dual and quad modes in the driver. Comments welcome. thanks. [0] https://lore.kernel.org/linux-mtd/20200109212842.GK3702@sirena.org.uk/ [1] https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf, 19.6.126 John Garry (3): spi: Allow SPI controller override device buswidth spi: HiSilicon v3xx: Properly set CMD_CONFIG for Dual/Quad modes spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits drivers/spi/spi-hisi-sfc-v3xx.c | 99 ++++++++++++++++++++++++++++++++- drivers/spi/spi.c | 4 +- include/linux/spi/spi.h | 3 + 3 files changed, 104 insertions(+), 2 deletions(-) -- 2.17.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
2020-02-28spi: spi-mem: Compute length only when neededTudor Ambarus
When adjust_op_size is defined, len is never used. Move the len computation where it's actually used. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200228160735.1565047-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bitsJohn Garry
The Huawei D06 board (and variants) can support Quad mode of operation. Since we have no current method in ACPI SPI bus device resource description to describe this information, use DMI to detect the board, and set the controller buswidth override bits. Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1582903131-160033-4-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: HiSilicon v3xx: Properly set CMD_CONFIG for Dual/Quad modesJohn Garry
The CMD_CONFIG register memory interface type field is not set configured for Dual and Quad modes, so set appropriately. This was not detected previously as we only ever operated in standard SPI mode. Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1582903131-160033-3-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: Allow SPI controller override device buswidthJohn Garry
Currently ACPI firmware description for a SPI device does not have any method to describe the data buswidth on the board. So even through the controller and device may support higher modes than standard SPI, it cannot be assumed that the board does - as such, that device is limited to standard SPI in such a circumstance. As a workaround, allow the controller driver supply buswidth override bits, which are used inform the core code that the controller driver knows the buswidth supported on that board for that device. A host controller driver might know this info from DMI tables, for example. Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1582903131-160033-2-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: atmel-quadspi: fix possible MMIO window size overrunTudor Ambarus
The QSPI controller memory space is limited to 128MB: 0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000. There are nor flashes that are bigger in size than the memory size supported by the controller: Micron MT25QL02G (256 MB). Check if the address exceeds the MMIO window size. An improvement would be to add support for regular SPI mode and fall back to it when the flash memories overrun the controller's memory space. Fixes: 0e6aae08e9ae ("spi: Add QuadSPI driver for Atmel SAMA5D2") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200228155437.1558219-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-27spi/zynqmp: remove entry that causes a cs glitchThommy Jakobsson
In the public interface for chipselect, there is always an entry commented as "Dummy generic FIFO entry" pushed down to the fifo right after the activate/deactivate command. The dummy entry is 0x0, irregardless if the intention was to activate or deactive the cs. This causes the cs line to glitch rather than beeing activated in the case when there was an activate command. This has been observed on oscilloscope, and have caused problems for at least one specific flash device type connected to the qspi port. After the change the glitch is gone and cs goes active when intended. The reason why this worked before (except for the glitch) was because when sending the actual data, the CS bits are once again set. Since most flashes uses mode 0, there is always a half clk period anyway for cs to clk active setup time. If someone would rely on timing from a chip_select call to a transfer_one, it would fail though. It is unknown why the dummy entry was there in the first place, git log seems to be of no help in this case. The reference manual gives no indication of the necessity of this. In fact the lower 8 bits are a setup (or hold in case of deactivate) time expressed in cycles. So this should not be needed to fulfill any setup/hold timings. Signed-off-by: Thommy Jakobsson <thommyj@gmail.com> Reviewed-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Link: https://lore.kernel.org/r/20200224162643.29102-1-thommyj@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-26spi: pxa2xx: Add CS control clock quirkEvan Green
In some circumstances on Intel LPSS controllers, toggling the LPSS CS control register doesn't actually cause the CS line to toggle. This seems to be failure of dynamic clock gating that occurs after going through a suspend/resume transition, where the controller is sent through a reset transition. This ruins SPI transactions that either rely on delay_usecs, or toggle the CS line without sending data. Whenever CS is toggled, momentarily set the clock gating register to "Force On" to poke the controller into acting on CS. Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/20200211223700.110252-1-rajatja@google.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-24spi: pxa2xx: drv_data can't be NULL in ->remove()Andy Shevchenko
There is no need for drv_data check against NULL, since it won't happen. Remove useless check. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200224154556.11627-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-24spi: pxa2xx: Return error codes from pxa2xx_spi_init_pdata()Andy Shevchenko
For better understanding what's going on on error path, return distinguished error codes instead of NULL pointer. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200224154556.11627-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-21spi: spidev: Fix CS polarity if GPIO descriptors are usedLukas Wunner
Commit f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs") amended of_spi_parse_dt() to always set SPI_CS_HIGH for SPI slaves whose Chip Select is defined by a "cs-gpios" devicetree property. This change broke userspace applications which issue an SPI_IOC_WR_MODE ioctl() to an spidev: Chip Select polarity will be incorrect unless the application is changed to set SPI_CS_HIGH. And once changed, it will be incompatible with kernels not containing the commit. Fix by setting SPI_CS_HIGH in spidev_ioctl() (under the same conditions as in of_spi_parse_dt()). Fixes: f3186dd87669 ("spi: Optionally use GPIO descriptors for CS GPIOs") Reported-by: Simon Han <z.han@kunbus.com> Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/fca3ba7cdc930cd36854666ceac4fbcf01b89028.1582027457.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org # v5.1+
2020-02-21spi: qup: call spi_qup_pm_resume_runtime before suspendingYuji Sasaki
spi_qup_suspend() will cause synchronous external abort when runtime suspend is enabled and applied, as it tries to access SPI controller register while clock is already disabled in spi_qup_pm_suspend_runtime(). Signed-off-by: Yuji sasaki <sasakiy@chromium.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200214074340.2286170-1-vkoul@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-19spi: rspi: Add support for LSB-first word orderGeert Uytterhoeven
All RSPI variants support selecting the word order. Advertize support for LSB-first order, and act upon the flag being set. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200218105810.902-3-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-19spi: rspi: Factor out handling of common mode bitsGeert Uytterhoeven
Basic SPI features like clock phase/polarity and loopback mode are common to all RSPI variants. Factor them out to reduce duplication. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200218105810.902-2-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-17spi: spi-mem: Fix typo, s/fallback/falls backTudor Ambarus
"Fallback" in one word is a noun. "Fall back" is two separate words, a verb and an adverb. Use the latter. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200216214012.1106658-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-14drivers: spi: Call cpu_latency_qos_*() instead of pm_qos_*()Rafael J. Wysocki
Call cpu_latency_qos_add/remove_request() instead of pm_qos_add/remove_request(), respectively, because the latter are going to be dropped. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
2020-02-12spi: Add generic SPI multiplexerChris Packham
Add a SPI device driver that sits in-band and provides a SPI controller which supports chip selects via a mux-control. This enables extra SPI devices to be connected with limited native chip selects. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20200204032838.20739-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: add driver for ar934x spi controllerChuanhong Guo
This patch adds driver for SPI controller found in Qualcomm Atheros AR934x/QCA95xx SoCs. This controller is a superset of the already supported qca,ar7100-spi. Besides the bit-bang mode in spi-ath79.c, this new controller added a new "shift register" mode, allowing faster spi operations. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Link: https://lore.kernel.org/r/20200210034152.49063-2-gch981213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: stm32-qspi: properly manage probe errorsLionel Debieve
Fix resource release issues when driver probe operation fails. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Link: https://lore.kernel.org/r/20200203135048.1299-3-patrice.chotard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: spi-geni-qcom: Drop of.h includeStephen Boyd
This driver doesn't call any DT functions like of_get_property(). Remove the of.h include as it isn't used. Cc: Girish Mahadevan <girishm@codeaurora.org> Cc: Dilip Kota <dkota@codeaurora.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200204191206.97036-4-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: stm32-qspi: defer probe for reset controllerEtienne Carriere
Changes stm32 QSPI driver to defer its probe operation when a reset controller device have not yet probed but is registered in the system. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Link: https://lore.kernel.org/r/20200203135048.1299-2-patrice.chotard@st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: spi-geni-qcom: Grow a dev pointer to simplify codeStephen Boyd
Some lines are long here. Use a struct dev pointer to shorten lines and simplify code. The clk_get() call can fail because of EPROBE_DEFER problems too, so just remove the error print message because it isn't useful. Cc: Girish Mahadevan <girishm@codeaurora.org> Cc: Dilip Kota <dkota@codeaurora.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200204191206.97036-3-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: spi-geni-qcom: Let firmware specify irq trigger flagsStephen Boyd
We don't need to force IRQF_TRIGGER_HIGH here as the DT or ACPI tables should take care of this for us. Just use 0 instead so that we use the flags from the firmware. Cc: Girish Mahadevan <girishm@codeaurora.org> Cc: Dilip Kota <dkota@codeaurora.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200204191206.97036-2-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-11spi: pxa2xx: Enable support for compile-testingGeert Uytterhoeven
m68k/allmodconfig: WARNING: unmet direct dependencies detected for SPI_PXA2XX Depends on [n]: SPI [=y] && SPI_MASTER [=y] && (ARCH_PXA || ARCH_MMP || PCI [=n] || ACPI) Selected by [m]: - SND_SOC_INTEL_BDW_RT5677_MACH [=m] && SOUND [=m] && !UML && SND [=m] && SND_SOC [=m] && SND_SOC_INTEL_MACH [=y] && (SND_SOC_INTEL_HASWELL [=n] || SND_SOC_SOF_BROADWELL [=m]) && I2C [=m] && (I2C_DESIGNWARE_PLATFORM [=m] || COMPILE_TEST [=y]) && (GPIOLIB [=y] || COMPILE_TEST [=y]) && (X86_INTEL_LPSS || COMPILE_TEST [=y]) && SPI_MASTER [=y] This happens because SND_SOC_INTEL_BDW_RT5677_MACH selects SPI_PXA2XX, and the former depends on COMPILE_TEST, while the latter does not. Fix this by enabling compile-testing for SPI_PXA2XX. Fixes: 630db1549356f644 ("ASoC: Intel: bdw-rt5677: fix Kconfig dependencies") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20200210093027.6672-1-geert@linux-m68k.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-06spi: spi-omap2-mcspi: Support probe deferral for DMA channelsVignesh Raghavendra
dma_request_channel() can return -EPROBE_DEFER, if DMA driver is not ready. Currently driver just falls back to PIO mode on probe deferral. Fix this by requesting all required channels during probe and propagating EPROBE_DEFER error code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200204124816.16735-3-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-06spi: spi-omap2-mcspi: Handle DMA size restriction on AM65xVignesh Raghavendra
On AM654, McSPI can only support 4K - 1 bytes per transfer when DMA is enabled. Therefore populate master->max_transfer_size callback to inform client drivers of this restriction when DMA channels are available. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200204124816.16735-2-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-04treewide: remove redundant IS_ERR() before error code checkMasahiro Yamada
'PTR_ERR(p) == -E*' is a stronger condition than IS_ERR(p). Hence, IS_ERR(p) is unneeded. The semantic patch that generates this commit is as follows: // <smpl> @@ expression ptr; constant error_code; @@ -IS_ERR(ptr) && (PTR_ERR(ptr) == - error_code) +PTR_ERR(ptr) == - error_code // </smpl> Link: http://lkml.kernel.org/r/20200106045833.1725-1-masahiroy@kernel.org Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Cc: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Stephen Boyd <sboyd@kernel.org> [drivers/clk/clk.c] Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [GPIO] Acked-by: Wolfram Sang <wsa@the-dreams.de> [drivers/i2c] Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [acpi/scan.c] Acked-by: Rob Herring <robh@kernel.org> Cc: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2020-01-27Merge tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremapLinus Torvalds
Pull ioremap updates from Christoph Hellwig: "Remove the ioremap_nocache API (plus wrappers) that are always identical to ioremap" * tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap: remove ioremap_nocache and devm_ioremap_nocache MIPS: define ioremap_nocache to ioremap
2020-01-23Merge branch 'spi-5.6' into spi-nextMark Brown
2020-01-23Merge branch 'spi-5.5' into spi-linusMark Brown
2020-01-21spi: pxa2xx: Avoid touching SSCR0_SSE on MMP2Lubomir Rintel
A read from a Winbond W25Q32FV SPI NOR memory chip on my MMP2 returns wrong data. It seems like SSE doesn't do the right thing on MMP2 at all. After enabling the SPI port back again, the FIFO reads return garbage. Things can be brought back to order by telling the PMU to reset the block. Here's a good transaction with said chip: # busybox devmem 0xd4035000 32 0x00001987 # SSCR0 # echo 0 >/sys/class/gpio/gpio46/value # (assert CS) # busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command) # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 # SSDR 0x000000ff # busybox devmem 0xd4035010 # SSDR 0x000000ef # Correct response # busybox devmem 0xd4035010 # SSDR 0x00000040 # busybox devmem 0xd4035010 # SSDR 0x00000016 # busybox devmem 0xd4035010 # SSDR 0x00000000 # busybox devmem 0xd4035010 # SSDR 0x00000000 # busybox devmem 0xd4035010 # SSDR 0x00000000 # echo 1 >/sys/class/gpio/gpio46/value # (deassert CS) # Flipping off an on SSE, then running another transaction: # busybox devmem 0xd4035000 32 0x00001907 # SSCR0, SSE off # busybox devmem 0xd4035000 32 0x00001987 # SSCR0, SSE on # echo 0 >/sys/class/gpio/gpio46/value # (assert CS) # busybox devmem 0xd4035010 32 0x0000009f # SSDR (read ID command) # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 32 0x00000000 # SSDR # busybox devmem 0xd4035010 # SSDR 0x000000ff # busybox devmem 0xd4035010 # SSDR 0x000000ff # Garbage! # busybox devmem 0xd4035010 # SSDR 0x000000ff # Oh no # busybox devmem 0xd4035010 # SSDR 0x000000ff # busybox devmem 0xd4035010 # SSDR 0x000000ff # busybox devmem 0xd4035010 # SSDR 0x000000ff # busybox devmem 0xd4035010 # SSDR 0x000000ff # echo 1 >/sys/class/gpio/gpio46/value # (deassert CS) # Sometimes the response is not just ones, but something that looks like bits of a response from a previous transaction. I can't see a fix other than not touching the SSE altogether after the device is first brought up. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200118094031.327373-1-lkundrak@v3.sk Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-21spi: spi-fsl-qspi: Ensure width is respected in spi-mem operationsMichael Walle
Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-17spi: npcm-pspi: modify reset supportTomer Maimon
Modify NPCM perphiral SPI reset support from direct register access to reset controller support. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20200115162301.235926-5-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-17spi: npcm-pspi: improve spi transfer performanceTomer Maimon
Improving spi 8 bit per word mode transfer performance by using 16 bit per word transfer and receive when the data length is even and larger than one. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20200115162301.235926-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-17spi: spi-ti-qspi: fix warningJean Pihet
drivers/spi/spi-ti-qspi.c: In function ‘ti_qspi_start_transfer_one’: drivers/spi/spi-ti-qspi.c:392:8: warning: ‘rx_wlen’ may be used uninitialized in this function [-Wmaybe-uninitialized] 392 | if (rx_wlen >= 32) | ^ drivers/spi/spi-ti-qspi.c:318:12: note: ‘rx_wlen’ was declared here 318 | u8 rxlen, rx_wlen; | ^~~~~~~ The warning is a false positive; it is not thrown by all compiler versions, e.g. Red Hat Cross 9.2.1-1 but not Linaro GCC 7.5-2019.12. Signed-off-by: Jean Pihet <jean.pihet@newoldbits.com> Link: https://lore.kernel.org/r/20200115100700.3357-1-jean.pihet@newoldbits.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-17spi: npcm-pspi: fix 16 bit send and receive supportTomer Maimon
Fixing NPCM BMC Peripheral SPI controller 16 bit send and receive support by writing and reading the SPI data in the right order. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20200115162301.235926-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-17spi: pxa2xx: Add support for Intel Comet Lake PCH-VJarkko Nikula
Add support for Intel Comet Lake PCH-V which has the same LPSS than on Intel Kaby lake unlike other Intel Comet Lake PCH variants that are based on Intel Cannon Lake PCH LPSS. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20200116091035.575175-1-jarkko.nikula@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-14spi: fsl: simplify error path in of_fsl_spi_probe()Christophe Leroy
No need to 'goto err;' for just doing a return. return directly from where the error happens. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Link: https://lore.kernel.org/r/2a4a7e11b37cfa0558d68f0d35e90d6da858b059.1579017697.git.christophe.leroy@c-s.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-14spi: fsl-lpspi: fix only one cs-gpio workingPhilippe Schenker
Why it does not work at the moment: - num_chipselect sets the number of cs-gpios that are in the DT. This comes from drivers/spi/spi.c - num_chipselect gets set with devm_spi_register_controller, that is called in drivers/spi/spi.c - devm_spi_register_controller got called after num_chipselect has been used. How this commit fixes the issue: - devm_spi_register_controller gets called before num_chipselect is being used. Fixes: c7a402599504 ("spi: lpspi: use the core way to implement cs-gpio function") Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Link: https://lore.kernel.org/r/20191204141312.1411251-1-philippe.schenker@toradex.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-14spi: spi-ti-qspi: optimize byte-transfersJean Pihet
Optimize the 8-bit based transfers, as used by the SPI flash devices, by reading the data registers by 32 and 128 bits when possible and copy the contents to the receive buffer. The speed improvement is 4.9x using quad read. Signed-off-by: Jean Pihet <jean.pihet@newoldbits.com> Cc: Ryan Barnett <ryan.barnett@rockwellcollins.com> Cc: Conrad Ratschan <conrad.ratschan@rockwellcollins.com> Cc: Arnout Vandecappelle <arnout.vandecappelle@essensium.com> Link: https://lore.kernel.org/r/20200114124125.361429-3-jean.pihet@newoldbits.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-14spi: spi-ti-qspi: support large flash devicesJean Pihet
The TI QSPI IP has limitations: - the MMIO region is 64MB in size - in non-MMIO mode, the transfer can handle 4096 words max. Add support for bigger devices. Use MMIO and DMA transfers below the 64MB boundary, use software generated transfers above. Signed-off-by: Jean Pihet <jean.pihet@newoldbits.com> Cc: Ryan Barnett <ryan.barnett@rockwellcollins.com> Cc: Conrad Ratschan <conrad.ratschan@rockwellcollins.com> Cc: Arnout Vandecappelle <arnout.vandecappelle@essensium.com> Link: https://lore.kernel.org/r/20200114124125.361429-2-jean.pihet@newoldbits.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-13spi: spi-qcom-qspi: Use device managed memory for clk_bulk_dataMatthias Kaehlcke
Currrently the memory for the clk_bulk_data of the QSPI controller is allocated with spi_alloc_master(). The bulk data pointer is passed to devm_clk_bulk_get() which saves it in clk_bulk_devres->clks. When the device is removed later devm_clk_bulk_release() is called and uses the bulk data referenced by the pointer to release the clocks. For this driver this results in accessing memory that has already been freed, since the memory allocated with spi_alloc_master() is released by spi_controller_release(), which is called before the managed resources are released. Use device managed memory for the clock bulk data to fix the issue described above. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200108133948.1.I35ceb4db3ad8cfab78f7cd51494aeff4891339f5@changeid Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-10spi: Add HiSilicon v3xx SPI NOR flash controller driverJohn Garry
Add the driver for the HiSilicon v3xx SPI NOR flash controller, commonly found in hi16xx chipsets. This is a different controller than that in drivers/mtd/spi-nor/hisi-sfc.c; indeed, the naming for that driver is poor, since it is really known as FMC, and can support other memory technologies. The driver module name is "hisi-sfc-v3xx", as recommended by HW designer, being an attempt to provide a distinct name - v3xx being the unique controller versioning. Only ACPI firmware is supported. DMA is not supported, and we just use polling mode for operation completion notification. The driver uses the SPI MEM OPs. Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1575900490-74467-3-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-09spi: bcm2835: Raise maximum number of slaves to 4Lukas Wunner
The "RevPi Connect Flat" PLC offered by KUNBUS has 4 slaves attached to the BCM2835 SPI master. Raise the maximum number of slaves in the driver accordingly. Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/01453fd062de2d49bd74a847e13a0781cbf8143d.1578572268.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-09spi: sh-msiof: Do not redefine STR while compile testingKrzysztof Kozlowski
STR is a well-known stringify macro so it should be avoided in drivers to avoid warnings like this (MIPS architecture while compile testing): drivers/spi/spi-sh-msiof.c:76:0: warning: "STR" redefined #define STR 0x40 /* Status Register */ arch/mips/include/asm/mipsregs.h:30:0: note: this is the location of the previous definition #define STR(x) __STR(x) To maintain consistency between all register names add a SI prefix to all of them. This also matches register names in datasheet. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200108194319.3171-1-krzk@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-01-07spi: rspi: Add support for GPIO chip selectsGeert Uytterhoeven
Add support for GPIO chip selects using GPIO descriptors. As the RSPI controller always drives a native chip select when performing a transfer, at least one native chip select must be left unused. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200102133822.29346-7-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-07-29 10:36:33 +0000