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Misc cleanup. No functional changes.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We will only have event status of IOC when IOC bit is set in
TRB. There's no need to check both bits.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We know that only OUT endpoints can trigger SHORT. We also know that
count MUST be > 0 whenever SHORT triggers.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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This will make it easier to figure out the reason for the event. That
information really helps debugging certain problems.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We can just call reclaim_trb_linear instead of reimplementing it.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Minor cleanup, no functional changes.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We are trying to kick transfers on Isochronous endpoints in a more
controlled manner now. And this ended up rendering this piece of code
unnecessary.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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instead of having one big loop, let's split it down into two smaller
handlers: one for linear buffers and one for scatterlist.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Just a minor simplification, no functional changes.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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After all the previous changes, it's now a lot clearer how isoc
transfers should be managed. We don't need to try to End Transfers
from ep_queue since that's already done by cleanup_requests.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Now, this part of the code is duplicated and brings no extra value to
the driver. Let's remove it.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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In case we get an event with status set to Missed Isoc, this means we
have missed an isochronous interval and should issue End Transfer
command and wait for the following XferNotReady.
Let's do that early, rather than late.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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It's only written to, never read. We can remove it now.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We don't need to return a value anymore here. Let's remove it.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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It has no use anymore.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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By now, it has the same semantics as DWC3_EP_TRANSFER_STARTED, but
that has a much more descriptive name.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We will need an up-to-date frame_number from XferInProgress too when
future patches improve our handling of Isoc endpoints.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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The core requires the extra two bits of information for properly
scheduling Isochronous transfers. This means that we can't rely on
__dwc3_gadget_get_frame(). Let's always cache uFrame number from
XferNotReady instead.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Endpoint handlers need to know about endpoints, not dwc. If they
really need access to dwc (e.g. for printing error messages) we have a
reference to it tucked inside the endpoint.
This patch has no functional changes, it's simply moving things around.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Cleanup only, no functional changes. Just making code easier to
follow.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Cleanup only, no functional changes. This just matches the event name
with its handler.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We *KNOW* which events we enable for which endpoint types and
we *KNOW* when they'll trigger. The endpoint type checks are
pointless.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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That has never proven useful in any way. Just remove it.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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This patch simply renames two functions to more descriptive names so
that it's easier to understand what they're doing.
Cleanup only, no functional changes.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Instead of constantly calling kick transfer everything some event
shows up, let's just rely on the fact that we send Update Transfer
every time a new request is queued.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Now that we're making sure we don't have XferComplete events, we can
rename this function to what it actually handles:
dwc3_gadget_endpoint_transfer_in_progress()
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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XferComplete is enabled only for the default control pipe, let's make
that clear in the code.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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We don't use XferNotReady for anything other than Default Control
Pipe, which is handled in ep0.c, and Isochronous endpoints. Let's make
that clear in the code.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Interrupt endpoints behave much like Bulk endpoints with the exception
that they are periodic. We can pre-issue Start Transfer exactly as we
do for Bulk endpoints.
While at that, remove one trailing blank line which is unnecessary.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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The present code correctly fetches the req which were previously not
queued from the started_list but fails to continue queuing from the sg
where it previously stopped queuing (because of the unavailable TRB's).
This patch correct's the code to continue queuing from the correct sg
present in the sglist.
For example, consider 5 sgs in req. Because of limited TRB's among the
5 sgs only 3 got queued. This patch corrects the code to start queuing
from correct sg i.e 4th sg when the TRBs are available.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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The code logic in dwc3_prepare_one_trb() incorrectly uses the address
and length fields present in req packet for mapping TRB's instead of
using the address and length fields of scattergather lists. This patch
correct's the code to use sg->address and sg->length when scattergather
lists are present.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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extcon device is used to detect host/device connection. Since extcon
OF property is deprecated, alternative method should be added.
This method uses OF graph bindings to locate extcon.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Historically, the clocks and resets are handled on the glue layer
side instead of the DWC3 core. For simple cases, dwc3-of-simple.c
takes care of arbitrary number of clocks and resets. The DT node
structure typically looks like as follows:
dwc3-glue {
compatible = "foo,dwc3";
clocks = ...;
resets = ...;
...
dwc3 {
compatible = "snps,dwc3";
...
};
}
By supporting the clocks and the reset in the dwc3/core.c, it will
be turned into a single node:
dwc3 {
compatible = "foo,dwc3", "snps,dwc3";
clocks = ...;
resets = ...;
...
}
This commit adds the binding of clocks and resets specific to this IP.
The number of clocks should generally be the same across SoCs, it is
just some SoCs either tie clocks together or do not provide software
control of some of the clocks.
I took the clock names from the Synopsys datasheet: "ref" (ref_clk),
"bus_early" (bus_clk_early), and "suspend" (suspend_clk).
I found only one reset line in the datasheet, hence the reset-names
property is omitted.
Those clocks are required for new platforms. Enforcing the new
binding breaks existing platforms since they specify clocks (and
resets) in their glue layer node, but nothing in the core node.
I listed such exceptional cases in the DT binding. The driver
code has been relaxed to accept no clock. This change is based
on the discussion [1].
I inserted reset_control_deassert() and clk_bulk_enable() before the
first register access, i.e. dwc3_cache_hwparams().
[1] https://patchwork.kernel.org/patch/10284265/
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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It is not a good idea to directly modify the resource of a platform
device. Modify its local copy, and pass it to devm_ioremap_resource()
so that we do not need to restore it in the failure path and the remove
hook.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Some PHY drivers (e.g. for Qualcomm QUSB2 and QMP PHYs) support
runtime PM to reduce PHY power consumption during bus_suspend.
Add changes to let core auto-suspend PHYs on host bus-suspend
using GUSB2PHYCFG register if needed for a platform. Also perform
PHYs runtime suspend/resume and let platform glue drivers e.g.
dwc3-qcom handle remote wakeup during bus suspend by waking up
devices on receiving wakeup event from PHY.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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DWC3 controller on Qualcomm SOCs has a Qscratch wrapper.
Some of its uses are described below resulting in need to
have a separate glue driver instead of using dwc3-of-simple:
- It exposes register interface to override vbus-override
and lane0-pwr-present signals going to hardware. These
must be updated in peripheral mode for DWC3 if vbus lines
are not connected to hardware block. Otherwise RX termination
in SS mode or DP pull-up is not applied by device controller.
- pwr_events_irq_stat support to check if USB2 PHY is in L2 state
before glue driver proceeds with suspend.
- Support for wakeup interrupts lines that are asserted whenever
there is any wakeup event on USB3 or USB2 bus.
- Support to replace pip3 clock going to DWC3 with utmi clock
for hardware configuration where SSPHY is not used with DWC3.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Add compatible string to use this generic glue layer to support
Allwinner H6 platform's dwc3 controller.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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This is a requirement which has always existed but, somehow, wasn't
reflected in the documentation and problems weren't found until now
when Tuba Yavuz found a possible deadlock happening between dwc3 and
f_hid. She described the situation as follows:
spin_lock_irqsave(&hidg->write_spinlock, flags); // first acquire
/* we our function has been disabled by host */
if (!hidg->req) {
free_ep_req(hidg->in_ep, hidg->req);
goto try_again;
}
[...]
status = usb_ep_queue(hidg->in_ep, hidg->req, GFP_ATOMIC);
=>
[...]
=> usb_gadget_giveback_request
=>
f_hidg_req_complete
=>
spin_lock_irqsave(&hidg->write_spinlock, flags); // second acquire
Note that this happens because dwc3 would call ->complete() on a
failed usb_ep_queue() due to failed Start Transfer command. This is,
anyway, a theoretical situation because dwc3 currently uses "No
Response Update Transfer" command for Bulk and Interrupt endpoints.
It's still good to make this case impossible to happen even if the "No
Reponse Update Transfer" command is changed.
Reported-by: Tuba Yavuz <tuba@ece.ufl.edu>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing
Felipe writes:
usb: changes for v4.17 merge window
Quite a lot happened in this cycle, with a total of 95 non-merge
commits. The most interesting parts are listed below:
Synopsys has been adding better support for USB 3.1 to dwc3. The same
series also sets g_mass_storage's max speed to SSP.
Roger Quadros (TI) added support for dual-role using the OTG block
available in some dwc3 implementations, this makes sure that AM437x
can swap roles in runtime.
We have a new SoC supported in dwc3 now - Amlogic Meson GX - thanks to
the work of Martin Blumenstingl.
We also have a ton of changes in dwc2 (51% of all changes, in
fact). The most interesting part there is the support for
Hibernation (a Synopsys PM feature).
Apart from these, we have our regular set of non-critical fixes all
over the place.
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On TI's AM437x, the DWC3 controller looses state after a
system suspend/resume. We are re-initializing the controller
but we miss restoring the PRTCAP register. This causes
USB host to break on AM437x after a system suspend/resume.
Fix this by restoring the PRTCAP register on system resume.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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DWC_usb3 speed can only be set up to SuperSpeed. Limit the setting to
SuperSpeed only should the value be higher. Otherwise, the controller
will read an invalid speed value and set the device to an incorrect
speed.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Dump LSP and BMU debug info.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new fields to store these threshold configurations.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register
fields for DWC_usb31 is as follows:
+-------+--------------------------+-----------------------------------+
| BITS | Name | Description |
+=======+==========================+===================================+
| 31:27 | reserved | |
| 26 | UsbTxPktCntSel | Async ESS transmit packet |
| | | threshold enable |
| 25:21 | UsbTxPktCnt | Async ESS transmit packet |
| | | threshold count |
| 20:16 | UsbMaxTxBurstSize | Async ESS Max transmit burst size |
| 15 | UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic |
| | | transmit packet threshold enable |
| 14:13 | UsbTxThrNumPkt_HS_Prd | HS high bandwidth periodic |
| | | transmit packet threshold count |
| 12:11 | reserved | |
| 10 | UsbTxThrNumPktSel_Prd | Periodic ESS transmit packet |
| | | threshold enable |
| 9:5 | UsbTxThrNumPkt_Prd | Periodic ESS transmit packet |
| | | threshold count |
| 4:0 | UsbMaxTxBurstSize_Prd | Max periodic ESS TX burst size |
+-------+--------------------------+-----------------------------------+
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register
fields for DWC_usb31 is as follows:
+-------+--------------------------+----------------------------------+
| BITS | Name | Description |
+=======+==========================+==================================+
| 31:27 | reserved | |
| 26 | UsbRxPktCntSel | Async ESS receive packet |
| | | threshold enable |
| 25:21 | UsbRxPktCnt | Async ESS receive packet |
| | | threshold count |
| 20:16 | UsbMaxRxBurstSize | Async ESS Max receive burst size |
| 15 | UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic |
| | | receive packet threshold enable |
| 14:13 | UsbRxThrNumPkt_HS_Prd | HS high bandwidth periodic |
| | | receive packet threshold count |
| 12:11 | reserved | |
| 10 | UsbRxThrNumPktSel_Prd | Periodic ESS receive packet |
| | | threshold enable |
| 9:5 | UsbRxThrNumPkt_Prd | Periodic ESS receive packet |
| | | threshold count |
| 4:0 | UsbMaxRxBurstSize_Prd | Max periodic ESS RX burst size |
+-------+--------------------------+----------------------------------+
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.
The GTXFIFOSIZ register for DWC_usb31 is as follows:
+-------+-----------+----------------------------------+
| BITS | Name | Description |
+=======+===========+==================================+
| 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address |
| 15 | TXFRAMNUM | Asynchronous/Periodic TXFIFO |
| 14:0 | TXFDEP | TXFIFO Depth |
+-------+-----------+----------------------------------+
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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Platform device is allocated before adding resources. Make sure to
properly cleanup on error case.
Cc: <stable@vger.kernel.org>
Fixes: f1c7e7108109 ("usb: dwc3: convert to pcim_enable_device()")
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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