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2023-03-14mailbox: zynqmp: Fix typo in IPI documentationTanmay Shah
Xilinx IPI message buffers allows 32-byte data transfer. Fix documentation that says 12 bytes Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230311012407.1292118-4-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
2022-08-02mailbox: mtk-cmdq: Remove proprietary cmdq_task_cbChun-Kuang Hu
rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. Client driver has changed to use standard rx_callback, so remove proprietary cmdq_task_cb. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_dataChun-Kuang Hu
Current client use 'struct cmdq_pkt' as callback data, so change 'void *data' to 'struct cmdq_pkt *pkt'. Keep data until client use pkt instead of data. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Remove cmdq_cb_statusChun-Kuang Hu
cmdq_cb_status is an error status. Use the standard error number instead of cmdq_cb_status to prevent status duplication. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-09mailbox: arm_mhuv2: Add driverViresh Kumar
This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Tested-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-10-29mailbox: zynqmp-ipi-message: Replace zero-length array with flexible-array ↵Gustavo A. R. Silva
member There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/v5.9-rc1/process/deprecated.html#zero-length-and-one-element-arrays Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
2020-09-25soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe apiDennis YC Hsieh
Add clear parameter to let client decide if event should be clear to 0 after GCE receive it. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/1594136714-11650-9-git-send-email-dennis-yc.hsieh@mediatek.com [mb: fix commit message] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add read_s functionDennis YC Hsieh
Add read_s function in cmdq helper functions which support read value from register or dma physical address into gce internal register. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-5-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s_mask functionDennis YC Hsieh
add write_s_mask function in cmdq helper functions which writes value contains in internal register to address with mask and large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-4-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25soc: mediatek: cmdq: add write_s functionDennis YC Hsieh
add write_s function in cmdq helper functions which writes value contains in internal register to address with large dma access support. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1594136714-11650-3-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-08-07Merge tag 'mailbox-v5.9' of ↵Linus Torvalds
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: "mediatek: - add support for mt6779 gce - shutdown cleanup and address shift support qcom: - add msm8994 apcs and sdm660 hmss compatibility imx: - mark PM funcs __maybe pcc: - put acpi table before bailout misc: - replace http with https links" * tag 'mailbox-v5.9' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: mediatek: cmdq: clear task in channel before shutdown mailbox: cmdq: support mt6779 gce platform definition mailbox: cmdq: variablize address shift in platform dt-binding: gce: add gce header file for mt6779 mailbox: qcom: Add msm8994 apcs compatible mailbox: qcom: Add sdm660 hmss compatible mailbox: imx: Mark PM functions as __maybe_unused mailbox: pcc: Put the PCCT table for error path mailbox: Replace HTTP links with HTTPS ones
2020-08-03mailbox: cmdq: variablize address shift in platformDennis YC Hsieh
Some gce hardware shift pc and end address in register to support large dram addressing. Implement gce address shift when write or read pc and end register. And add shift bit in platform definition. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-22soc: mediatek: cmdq: add set event functionDennis YC Hsieh
Add set event function in cmdq helper functions to set specific event. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1592749115-24158-12-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-06-22soc: mediatek: cmdq: add assign functionDennis YC Hsieh
Add assign function in cmdq helper which assign constant value into internal register by index. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Link: https://lore.kernel.org/r/1592749115-24158-3-git-send-email-dennis-yc.hsieh@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-01-08soc: mediatek: cmdq: add polling functionBibby Hsieh
add polling function in cmdq helper functions Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-01-08soc: mediatek: cmdq: define the instruction structBibby Hsieh
Define an instruction structure for gce driver to append command. This structure can make the client's code more readability. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-09-17mailbox: mediatek: cmdq: clear the event in cmdq initial flowBibby Hsieh
GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-03-06mailbox: ZynqMP IPI mailbox controllerWendy Liang
This patch is to introduce ZynqMP IPI mailbox controller driver to use the ZynqMP IPI block as mailboxes. Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-08-03mailbox: mediatek: Add Mediatek CMDQ driverHoulong Wei
This patch is first version of Mediatek Command Queue(CMDQ) driver. The CMDQ is used to help write registers with critical time limitation, such as updating display configuration during the vblank. It controls Global Command Engine (GCE) hardware to achieve this requirement. Currently, CMDQ only supports display related hardwares, but we expect it can be extended to other hardwares for future requirements. Signed-off-by: Houlong Wei <houlong.wei@mediatek.com> Signed-off-by: HS Liao <hs.liao@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2017-03-28mailbox: Add driver for Broadcom FlexRM ring managerAnup Patel
Some of the Broadcom iProc SoCs have FlexRM ring manager which provides a ring-based programming interface to various offload engines (e.g. RAID, Crypto, etc). This patch adds a common mailbox driver for Broadcom FlexRM ring manager which can be shared by various offload engine drivers (implemented as mailbox clients). Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Pramod KUMAR <pramod.kumar@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-07-28mailbox: Add Broadcom PDC mailbox driverRob Rice
The Broadcom PDC mailbox driver is a mailbox controller that manages data transfers to and from one or more offload engines. Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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