From 6c1bfbd9df8c42a1156b9f4769ca78dfc5e89045 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 13 Oct 2020 13:55:01 +0800 Subject: MIPS: Loongson64: Add /sys/firmware/lefi/boardinfo Add /sys/firmware/lefi/boardinfo to get mainboard and BIOS info easily on the Loongson platform, this is useful to point out the current used mainboard type and BIOS version when there exists problems related with hardware or firmware. The related structures are already defined in the interface specification about firmware and kernel which are common requirement and specific for Loongson64, so only add a new boardinfo.c file in arch/mips/loongson64. E.g. with this patch: [loongson@linux ~]$ cat /sys/firmware/lefi/boardinfo Board Info Manufacturer : LEMOTE Board Name : LEMOTE-LS3A4000-7A1000-1w-V01-pc Family : LOONGSON3 BIOS Info Vendor : Kunlun Version : Kunlun-A1901-V4.1.3-20200414093938 ROM Size : 4 KB Release Date : 2020-04-14 By the way, using dmidecode command can get the similar info if there exists SMBIOS in firmware, but the fact is that there is no SMBIOS on some machines, we can see nothing when execute dmidecode, like this: [root@linux loongson]# dmidecode # dmidecode 2.12 # No SMBIOS nor DMI entry point found, sorry. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-loongson64/boot_param.h | 4 ++ arch/mips/loongson64/Makefile | 1 + arch/mips/loongson64/boardinfo.c | 48 ++++++++++++++++++++++ arch/mips/loongson64/env.c | 10 +++++ 4 files changed, 63 insertions(+) create mode 100644 arch/mips/loongson64/boardinfo.c diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h index afc92b7a61c6..4592841b6b0c 100644 --- a/arch/mips/include/asm/mach-loongson64/boot_param.h +++ b/arch/mips/include/asm/mach-loongson64/boot_param.h @@ -228,6 +228,10 @@ struct loongson_system_configuration { extern struct efi_memory_map_loongson *loongson_memmap; extern struct loongson_system_configuration loongson_sysconf; +extern struct board_devices *eboard; +extern struct interface_info *einter; +extern struct loongson_special_attribute *especial; + extern u32 node_id_offset; extern void ls7a_early_config(void); extern void rs780e_early_config(void); diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile index 39c06f52b08f..cc76944b1a9d 100644 --- a/arch/mips/loongson64/Makefile +++ b/arch/mips/loongson64/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_RS780_HPET) += hpet.o obj-$(CONFIG_SUSPEND) += pm.o obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o obj-$(CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION) += cpucfg-emul.o +obj-$(CONFIG_SYSFS) += boardinfo.o diff --git a/arch/mips/loongson64/boardinfo.c b/arch/mips/loongson64/boardinfo.c new file mode 100644 index 000000000000..280989c5a137 --- /dev/null +++ b/arch/mips/loongson64/boardinfo.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +static ssize_t boardinfo_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + char board_manufacturer[64] = {0}; + char *tmp_board_manufacturer = board_manufacturer; + char bios_vendor[64] = {0}; + char *tmp_bios_vendor = bios_vendor; + + strcpy(board_manufacturer, eboard->name); + strcpy(bios_vendor, einter->description); + + return sprintf(buf, + "Board Info\n" + "Manufacturer\t\t: %s\n" + "Board Name\t\t: %s\n" + "Family\t\t\t: LOONGSON3\n\n" + "BIOS Info\n" + "Vendor\t\t\t: %s\n" + "Version\t\t\t: %s\n" + "ROM Size\t\t: %d KB\n" + "Release Date\t\t: %s\n", + strsep(&tmp_board_manufacturer, "-"), + eboard->name, + strsep(&tmp_bios_vendor, "-"), + einter->description, + einter->size, + especial->special_name); +} +static struct kobj_attribute boardinfo_attr = __ATTR(boardinfo, 0444, + boardinfo_show, NULL); + +static int __init boardinfo_init(void) +{ + struct kobject *lefi_kobj; + + lefi_kobj = kobject_create_and_add("lefi", firmware_kobj); + if (!lefi_kobj) { + pr_err("lefi: Firmware registration failed.\n"); + return -ENOMEM; + } + + return sysfs_create_file(lefi_kobj, &boardinfo_attr.attr); +} +late_initcall(boardinfo_init); diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index 134cb8e9efc2..51a5d050a94c 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -28,6 +28,10 @@ EXPORT_SYMBOL(cpu_clock_freq); struct efi_memory_map_loongson *loongson_memmap; struct loongson_system_configuration loongson_sysconf; +struct board_devices *eboard; +struct interface_info *einter; +struct loongson_special_attribute *especial; + u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180}; u64 loongson_chiptemp[MAX_PACKAGES]; u64 loongson_freqctrl[MAX_PACKAGES]; @@ -57,6 +61,12 @@ void __init prom_init_env(void) ((u64)loongson_p + loongson_p->system_offset); ecpu = (struct efi_cpuinfo_loongson *) ((u64)loongson_p + loongson_p->cpu_offset); + eboard = (struct board_devices *) + ((u64)loongson_p + loongson_p->boarddev_table_offset); + einter = (struct interface_info *) + ((u64)loongson_p + loongson_p->interface_offset); + especial = (struct loongson_special_attribute *) + ((u64)loongson_p + loongson_p->special_offset); eirq_source = (struct irq_source_routing_table *) ((u64)loongson_p + loongson_p->irq_offset); loongson_memmap = (struct efi_memory_map_loongson *) -- cgit v1.2.3-70-g09d2 From 673a8c4f8517ea624cd838f7f2246b6990190770 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 13 Oct 2020 13:55:02 +0800 Subject: Documentation: ABI: Add /sys/firmware/lefi/boardinfo description for Loongson64 Add a description for /sys/firmware/lefi/boardinfo on the Loongson platform. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- .../ABI/testing/sysfs-firmware-lefi-boardinfo | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo diff --git a/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo new file mode 100644 index 000000000000..5e3f6148c52e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-firmware-lefi-boardinfo @@ -0,0 +1,35 @@ +What: /sys/firmware/lefi/boardinfo +Date: October 2020 +Contact: Tiezhu Yang +Description: + Get mainboard and BIOS info easily on the Loongson platform, + this is useful to point out the current used mainboard type + and BIOS version when there exists problems related with + hardware or firmware. + + The related structures are already defined in the interface + specification about firmware and kernel which are common + requirement and specific for Loongson64, so only add a new + boardinfo.c file in arch/mips/loongson64. + + For example: + + [loongson@linux ~]$ cat /sys/firmware/lefi/boardinfo + Board Info + Manufacturer : LEMOTE + Board Name : LEMOTE-LS3A4000-7A1000-1w-V01-pc + Family : LOONGSON3 + + BIOS Info + Vendor : Kunlun + Version : Kunlun-A1901-V4.1.3-20200414093938 + ROM Size : 4 KB + Release Date : 2020-04-14 + + By the way, using dmidecode command can get the similar info if there + exists SMBIOS in firmware, but the fact is that there is no SMBIOS on + some machines, we can see nothing when execute dmidecode, like this: + + [root@linux loongson]# dmidecode + # dmidecode 2.12 + # No SMBIOS nor DMI entry point found, sorry. -- cgit v1.2.3-70-g09d2 From ab7cffb8d2367e5b088c7c14452724e719a10eba Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Mon, 26 Oct 2020 20:20:40 +0100 Subject: MIPS: ingenic: remove unused platform_data header file There are no users of this headers file in the kernel. All users are likely migrated to device tree which is a good thing. Signed-off-by: Sam Ravnborg Cc: Thomas Bogendoerfer Cc: Paul Cercueil Cc: Harvey Hunt Cc: linux-mips@vger.kernel.org Reviewed-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer --- include/linux/platform_data/jz4740/jz4740_nand.h | 25 ------------------------ 1 file changed, 25 deletions(-) delete mode 100644 include/linux/platform_data/jz4740/jz4740_nand.h diff --git a/include/linux/platform_data/jz4740/jz4740_nand.h b/include/linux/platform_data/jz4740/jz4740_nand.h deleted file mode 100644 index b3f066d63059..000000000000 --- a/include/linux/platform_data/jz4740/jz4740_nand.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009-2010, Lars-Peter Clausen - * JZ4740 SoC NAND controller driver - */ - -#ifndef __JZ4740_NAND_H__ -#define __JZ4740_NAND_H__ - -#include -#include - -#define JZ_NAND_NUM_BANKS 4 - -struct jz_nand_platform_data { - int num_partitions; - struct mtd_partition *partitions; - - unsigned char banks[JZ_NAND_NUM_BANKS]; - - void (*ident_callback)(struct platform_device *, struct mtd_info *, - struct mtd_partition **, int *num_partitions); -}; - -#endif -- cgit v1.2.3-70-g09d2 From d2e850e961835825492f37346ae76670bf4758f5 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Mon, 26 Oct 2020 20:29:25 +0800 Subject: MIPS: zboot: put appended dtb into a section This will make a separated section for dtb appear in ELF, and we can then use objcopy to patch a dtb into vmlinuz when RAW_APPENDED_DTB is set in kernel config. command to patch a dtb: objcopy --set-section-flags=.appended_dtb=alloc,contents \ --update-section=.appended_dtb=.dtb vmlinuz Signed-off-by: Chuanhong Guo Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/compressed/ld.script | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script index 2ed08fbef8e7..0ebb667274d6 100644 --- a/arch/mips/boot/compressed/ld.script +++ b/arch/mips/boot/compressed/ld.script @@ -31,9 +31,12 @@ SECTIONS CONSTRUCTORS . = ALIGN(16); } - __appended_dtb = .; - /* leave space for appended DTB */ - . += 0x100000; + + .appended_dtb : { + __appended_dtb = .; + /* leave space for appended DTB */ + . += 0x100000; + } _edata = .; /* End of data section */ -- cgit v1.2.3-70-g09d2 From 18ff14c87d904f7968a143a6202740c27b4d8e7f Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 27 Oct 2020 18:34:30 +0000 Subject: MIPS: Kconfig: fix a few trivial spelling mistakes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are a few spelling mistakes in the Kconfig, fix these. Signed-off-by: Colin Ian King Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2000bb2b0220..ddaff19a9580 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2645,7 +2645,7 @@ config WAR_R4600_V1_INDEX_ICACHEOP # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, # Hit_Invalidate_D and Create_Dirty_Excl_D should only be # executed if there is no other dcache activity. If the dcache is -# accessed for another instruction immeidately preceding when these +# accessed for another instruction immediately preceding when these # cache instructions are executing, it is possible that the dcache # tag match outputs used by these cache instructions will be # incorrect. These cache instructions should be preceded by at least @@ -3086,7 +3086,7 @@ config MIPS_O32_FP64_SUPPORT Although binutils currently supports use of this flag the details concerning its effect upon the O32 ABI in userland are still being - worked on. In order to avoid userland becoming dependant upon current + worked on. In order to avoid userland becoming dependent upon current behaviour before the details have been finalised, this option should be considered experimental and only enabled by those working upon said details. @@ -3124,7 +3124,7 @@ choice objcopy --update-section .appended_dtb=.dtb vmlinux - This is meant as a backward compatiblity convenience for those + This is meant as a backward compatibility convenience for those systems with a bootloader that can't be upgraded to accommodate the documented boot protocol using a device tree. -- cgit v1.2.3-70-g09d2 From 5a5aa912f687204d50455d0db36f94dd8de601c2 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Wed, 28 Oct 2020 17:15:45 +0800 Subject: mips: ar7: add missing iounmap() on error in ar7_gpio_init Add the missing iounmap() of gpch->regs before return from ar7_gpio_init() in the error handling case. Signed-off-by: Qinglang Miao Signed-off-by: Thomas Bogendoerfer --- arch/mips/ar7/gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c index 8b006addd6ba..ae0e01b9438f 100644 --- a/arch/mips/ar7/gpio.c +++ b/arch/mips/ar7/gpio.c @@ -319,6 +319,7 @@ int __init ar7_gpio_init(void) if (ret) { printk(KERN_ERR "%s: failed to add gpiochip\n", gpch->chip.label); + iounmap(gpch->regs); return ret; } printk(KERN_INFO "%s: registered %d GPIOs\n", -- cgit v1.2.3-70-g09d2 From 2673ecf9586551c5bcee499c1cc1949f6f7cc9a1 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Wed, 28 Oct 2020 17:15:46 +0800 Subject: mips: cm: add missing iounmap() on error in mips_cm_probe() Add the missing iounmap() of iounmap(mips_gcr_base) before return from mips_cm_probe() in the error handling case. Signed-off-by: Qinglang Miao Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/mips-cm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index f60af512c877..90f1c3df1f0e 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -266,6 +266,7 @@ int mips_cm_probe(void) if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) { pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n", (unsigned long)addr); + iounmap(mips_gcr_base); mips_gcr_base = NULL; return -ENODEV; } -- cgit v1.2.3-70-g09d2 From c424dc4cd1809e181a161723f770b7bc1e0f9927 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Wed, 28 Oct 2020 17:15:48 +0800 Subject: mips: Vr41xx: add missing iounmap() on error in vr41xx_pciu_init() add missing iounmap() of pciu_base on error when failed to init io_map_base. Signed-off-by: Qinglang Miao Signed-off-by: Thomas Bogendoerfer --- arch/mips/pci/pci-vr41xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index 1fa4e101470c..4f250c55b6e6 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c @@ -293,8 +293,10 @@ static int __init vr41xx_pciu_init(void) master = setup->master_io; io_map_base = ioremap(master->bus_base_address, resource_size(res)); - if (!io_map_base) + if (!io_map_base) { + iounmap(pciu_base); return -EBUSY; + } vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base; } -- cgit v1.2.3-70-g09d2 From e1717283250aa426cd5f3ba9a1fc9faba3a2e529 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 10 Nov 2020 17:36:31 +0100 Subject: mips: Remove #include from Everything in arch/mips/include/uapi/asm/types.h is protected by "#ifndef __KERNEL__", so it's unused for kernelspace. Signed-off-by: Geert Uytterhoeven Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/types.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index 148d42a17f30..638ef88e2f8e 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -12,6 +12,5 @@ #define _ASM_TYPES_H #include -#include #endif /* _ASM_TYPES_H */ -- cgit v1.2.3-70-g09d2 From 4abaacc704729ec93a6ca23f6b3a92532337959b Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Tue, 10 Nov 2020 19:21:05 -0800 Subject: MIPS: remove GCC < 4.9 support Remove a tautology; since commit 0bddd227f3dc ("Documentation: update for gcc 4.9 requirement") which raised the minimally supported version of GCC to 4.9, this case is always true. Link: https://github.com/ClangBuiltLinux/linux/issues/427 Signed-off-by: Nick Desaulniers Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/compiler.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h index a2cb2d2b1c07..2b06090a78b2 100644 --- a/arch/mips/include/asm/compiler.h +++ b/arch/mips/include/asm/compiler.h @@ -43,14 +43,7 @@ #undef barrier_before_unreachable #define barrier_before_unreachable() asm volatile(".insn") -#if !defined(CONFIG_CC_IS_GCC) || \ - (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9) -# define GCC_OFF_SMALL_ASM() "ZC" -#elif defined(CONFIG_CPU_MICROMIPS) -# error "microMIPS compilation unsupported with GCC older than 4.9" -#else -# define GCC_OFF_SMALL_ASM() "R" -#endif +#define GCC_OFF_SMALL_ASM() "ZC" #ifdef CONFIG_CPU_MIPSR6 #define MIPS_ISA_LEVEL "mips64r6" -- cgit v1.2.3-70-g09d2 From 4d1b3ac886b5c03e966199edcc7e0efddd5c4cb2 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 3 Nov 2020 15:12:00 +0800 Subject: MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the write operations are meaningless, remove them. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 -------- arch/mips/loongson64/numa.c | 3 --- 2 files changed, 11 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h index 87a5bfbf8cfe..e4d77f4f0fe3 100644 --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h @@ -19,10 +19,6 @@ .macro kernel_entry_setup .set push .set mips64 - /* Set LPA on LOONGSON3 config3 */ - mfc0 t0, CP0_CONFIG3 - or t0, (0x1 << 7) - mtc0 t0, CP0_CONFIG3 /* Set ELPA on LOONGSON3 pagegrain */ mfc0 t0, CP0_PAGEGRAIN or t0, (0x1 << 29) @@ -54,10 +50,6 @@ .macro smp_slave_setup .set push .set mips64 - /* Set LPA on LOONGSON3 config3 */ - mfc0 t0, CP0_CONFIG3 - or t0, (0x1 << 7) - mtc0 t0, CP0_CONFIG3 /* Set ELPA on LOONGSON3 pagegrain */ mfc0 t0, CP0_PAGEGRAIN or t0, (0x1 << 29) diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index cf9459f79f9b..c7e3ccedc74f 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -39,9 +39,6 @@ static void enable_lpa(void) { unsigned long value; - value = __read_32bit_c0_register($16, 3); - value |= 0x00000080; - __write_32bit_c0_register($16, 3, value); value = __read_32bit_c0_register($16, 3); pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value); -- cgit v1.2.3-70-g09d2 From fe9863a19a5a73af8227548603fb521050769611 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 3 Nov 2020 15:12:01 +0800 Subject: MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once The field ELPA of CP0_PAGEGRAIN register is set at the beginning of the kernel entry point in kernel-entry-init.h, no need to set it again in numa.c, we can remove enable_lpa() and only print the related information. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/numa.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index c7e3ccedc74f..509b360e4d28 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -35,20 +35,6 @@ EXPORT_SYMBOL(__node_data); cpumask_t __node_cpumask[MAX_NUMNODES]; EXPORT_SYMBOL(__node_cpumask); -static void enable_lpa(void) -{ - unsigned long value; - - value = __read_32bit_c0_register($16, 3); - pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value); - - value = __read_32bit_c0_register($5, 1); - value |= 0x20000000; - __write_32bit_c0_register($5, 1, value); - value = __read_32bit_c0_register($5, 1); - pr_info("CP0_PageGrain: CP0 5.1 (0x%lx)\n", value); -} - static void cpu_node_probe(void) { int i; @@ -240,7 +226,8 @@ EXPORT_SYMBOL(pcibus_to_node); void __init prom_init_numa_memory(void) { - enable_lpa(); + pr_info("CP0_Config3: CP0 16.3 (0x%x)\n", read_c0_config3()); + pr_info("CP0_PageGrain: CP0 5.1 (0x%x)\n", read_c0_pagegrain()); prom_meminit(); } EXPORT_SYMBOL(prom_init_numa_memory); -- cgit v1.2.3-70-g09d2 From 42831cd70805211c240a5bba5b4fb6be9470c91d Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 3 Nov 2020 15:12:02 +0800 Subject: MIPS: Loongson64: Set IPI_Enable register per core by itself In the current code, for example, core 1 sets Core[0, 1, 2, 3]_IPI_Enalbe register and core 2, 3 do the same thing on the 1-way Loongson64 platform, this is not necessary. Set IPI_Enable register per core by itself to avoid duplicate operations and make the logic more clear. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index e744e1bee49e..7d58853a0631 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -348,8 +348,7 @@ static void loongson3_init_secondary(void) /* Set interrupt mask, but don't enable */ change_c0_status(ST0_IM, imask); - for (i = 0; i < num_possible_cpus(); i++) - loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]); + loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); per_cpu(cpu_state, cpu) = CPU_ONLINE; cpu_set_core(&cpu_data[cpu], @@ -420,6 +419,7 @@ static void __init loongson3_smp_setup(void) ipi_status0_regs_init(); ipi_en0_regs_init(); ipi_mailbox_buf_init(); + loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(0)]); cpu_set_core(&cpu_data[0], cpu_logical_map(0) % loongson_sysconf.cores_per_package); cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; -- cgit v1.2.3-70-g09d2 From fed4955f304eb62acfdf86ecf05ea164856e09d8 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 3 Nov 2020 15:12:03 +0800 Subject: MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Loongson 3A4000+ CPU has per-core Mail_Send register to send mail, there is no need to maintain register address of each core and node, just simply specify cpu number. Signed-off-by: Lu Zeng Signed-off-by: Jianmin Lv Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- .../include/asm/mach-loongson64/loongson_regs.h | 10 ++ arch/mips/loongson64/smp.c | 120 +++++++++++++++++---- 2 files changed, 107 insertions(+), 23 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h index 83dbb9fdf9c2..165993514762 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -227,6 +227,16 @@ static inline void csr_writeq(u64 val, u32 reg) #define CSR_IPI_SEND_CPU_SHIFT 16 #define CSR_IPI_SEND_BLOCK BIT(31) +#define LOONGSON_CSR_MAIL_BUF0 0x1020 +#define LOONGSON_CSR_MAIL_SEND 0x1048 +#define CSR_MAIL_SEND_BLOCK BIT_ULL(31) +#define CSR_MAIL_SEND_BOX_LOW(box) (box << 1) +#define CSR_MAIL_SEND_BOX_HIGH(box) ((box << 1) + 1) +#define CSR_MAIL_SEND_BOX_SHIFT 2 +#define CSR_MAIL_SEND_CPU_SHIFT 16 +#define CSR_MAIL_SEND_BUF_SHIFT 32 +#define CSR_MAIL_SEND_H32_MASK 0xFFFFFFFF00000000ULL + static inline u64 drdtime(void) { int rID = 0; diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 7d58853a0631..736e98ddd596 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -53,6 +53,29 @@ static uint32_t core0_c0count[NR_CPUS]; u32 (*ipi_read_clear)(int cpu); void (*ipi_write_action)(int cpu, u32 action); +void (*ipi_write_enable)(int cpu); +void (*ipi_clear_buf)(int cpu); +void (*ipi_write_buf)(int cpu, struct task_struct *idle); + +/* send mail via Mail_Send register for 3A4000+ CPU */ +static void csr_mail_send(uint64_t data, int cpu, int mailbox) +{ + uint64_t val; + + /* send high 32 bits */ + val = CSR_MAIL_SEND_BLOCK; + val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); + val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); + val |= (data & CSR_MAIL_SEND_H32_MASK); + csr_writeq(val, LOONGSON_CSR_MAIL_SEND); + + /* send low 32 bits */ + val = CSR_MAIL_SEND_BLOCK; + val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); + val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); + val |= (data << CSR_MAIL_SEND_BUF_SHIFT); + csr_writeq(val, LOONGSON_CSR_MAIL_SEND); +}; static u32 csr_ipi_read_clear(int cpu) { @@ -79,6 +102,35 @@ static void csr_ipi_write_action(int cpu, u32 action) } } +static void csr_ipi_write_enable(int cpu) +{ + csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN); +} + +static void csr_ipi_clear_buf(int cpu) +{ + csr_writeq(0, LOONGSON_CSR_MAIL_BUF0); +} + +static void csr_ipi_write_buf(int cpu, struct task_struct *idle) +{ + unsigned long startargs[4]; + + /* startargs[] are initial PC, SP and GP for secondary CPU */ + startargs[0] = (unsigned long)&smp_bootstrap; + startargs[1] = (unsigned long)__KSTK_TOS(idle); + startargs[2] = (unsigned long)task_thread_info(idle); + startargs[3] = 0; + + pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", + cpu, startargs[0], startargs[1], startargs[2]); + + csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); + csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); + csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); + csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); +} + static u32 legacy_ipi_read_clear(int cpu) { u32 action; @@ -96,14 +148,53 @@ static void legacy_ipi_write_action(int cpu, u32 action) loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); } +static void legacy_ipi_write_enable(int cpu) +{ + loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); +} + +static void legacy_ipi_clear_buf(int cpu) +{ + loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); +} + +static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) +{ + unsigned long startargs[4]; + + /* startargs[] are initial PC, SP and GP for secondary CPU */ + startargs[0] = (unsigned long)&smp_bootstrap; + startargs[1] = (unsigned long)__KSTK_TOS(idle); + startargs[2] = (unsigned long)task_thread_info(idle); + startargs[3] = 0; + + pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", + cpu, startargs[0], startargs[1], startargs[2]); + + loongson3_ipi_write64(startargs[3], + ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); + loongson3_ipi_write64(startargs[2], + ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); + loongson3_ipi_write64(startargs[1], + ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); + loongson3_ipi_write64(startargs[0], + ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); +} + static void csr_ipi_probe(void) { if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) { ipi_read_clear = csr_ipi_read_clear; ipi_write_action = csr_ipi_write_action; + ipi_write_enable = csr_ipi_write_enable; + ipi_clear_buf = csr_ipi_clear_buf; + ipi_write_buf = csr_ipi_write_buf; } else { ipi_read_clear = legacy_ipi_read_clear; ipi_write_action = legacy_ipi_write_action; + ipi_write_enable = legacy_ipi_write_enable; + ipi_clear_buf = legacy_ipi_clear_buf; + ipi_write_buf = legacy_ipi_write_buf; } } @@ -347,8 +438,7 @@ static void loongson3_init_secondary(void) /* Set interrupt mask, but don't enable */ change_c0_status(ST0_IM, imask); - - loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); + ipi_write_enable(cpu); per_cpu(cpu_state, cpu) = CPU_ONLINE; cpu_set_core(&cpu_data[cpu], @@ -380,8 +470,8 @@ static void loongson3_smp_finish(void) write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); local_irq_enable(); - loongson3_ipi_write64(0, - ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); + ipi_clear_buf(cpu); + pr_info("CPU#%d finished, CP0_ST=%x\n", smp_processor_id(), read_c0_status()); } @@ -419,7 +509,8 @@ static void __init loongson3_smp_setup(void) ipi_status0_regs_init(); ipi_en0_regs_init(); ipi_mailbox_buf_init(); - loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(0)]); + ipi_write_enable(0); + cpu_set_core(&cpu_data[0], cpu_logical_map(0) % loongson_sysconf.cores_per_package); cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; @@ -439,27 +530,10 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus) */ static int loongson3_boot_secondary(int cpu, struct task_struct *idle) { - unsigned long startargs[4]; - pr_info("Booting CPU#%d...\n", cpu); - /* startargs[] are initial PC, SP and GP for secondary CPU */ - startargs[0] = (unsigned long)&smp_bootstrap; - startargs[1] = (unsigned long)__KSTK_TOS(idle); - startargs[2] = (unsigned long)task_thread_info(idle); - startargs[3] = 0; - - pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", - cpu, startargs[0], startargs[1], startargs[2]); + ipi_write_buf(cpu, idle); - loongson3_ipi_write64(startargs[3], - ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); - loongson3_ipi_write64(startargs[2], - ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); - loongson3_ipi_write64(startargs[1], - ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); - loongson3_ipi_write64(startargs[0], - ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); return 0; } -- cgit v1.2.3-70-g09d2 From 381ad3843b26ec9b461e7973729ef64b36ed4627 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 3 Nov 2020 15:12:04 +0800 Subject: MIPS: Loongson64: SMP: Fix up play_dead jump indicator In play_dead function, the whole 64-bit PC mailbox was used as a indicator to determine if the master core had written boot jump information. However, after we introduced CSR mailsend, the hardware will not guarante an atomic write for the 64-bit PC mailbox. Thus we have to use the lower 32-bit which is written at the last as the jump indicator instead. Signed-off-by: Lu Zeng Signed-off-by: Jun Yi Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 736e98ddd596..aa0cd723e61d 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int *state_addr) "1: li %[count], 0x100 \n" /* wait for init loop */ "2: bnez %[count], 2b \n" /* limit mailbox access */ " addiu %[count], -1 \n" - " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ + " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */ " beqz %[initfunc], 1b \n" " nop \n" + " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */ " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ " ld $a1, 0x38(%[base]) \n" -- cgit v1.2.3-70-g09d2 From 877f2382c487eb22dc50a805a7def819b9911313 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:41 +0300 Subject: mips: dts: jz47x: Harmonize EHCI/OHCI DT nodes name In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Paul Cercueil Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ingenic/jz4740.dtsi | 2 +- arch/mips/boot/dts/ingenic/jz4770.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index eee523678ce5..c1afdfdaa8a3 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -295,7 +295,7 @@ clocks = <&cgu JZ4740_CLK_DMA>; }; - uhc: uhc@13030000 { + uhc: usb@13030000 { compatible = "ingenic,jz4740-ohci", "generic-ohci"; reg = <0x13030000 0x1000>; diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi index 018721a9eea9..05c00b93088e 100644 --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi @@ -430,7 +430,7 @@ interrupts = <23>; }; - uhc: uhc@13430000 { + uhc: usb@13430000 { compatible = "generic-ohci"; reg = <0x13430000 0x1000>; -- cgit v1.2.3-70-g09d2 From f4fc91af93924994348a88ff886129cc0322d282 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:42 +0300 Subject: mips: dts: sead3: Harmonize EHCI/OHCI DT nodes name In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mti/sead3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts index 192c26ff1d3d..1cf6728af8fe 100644 --- a/arch/mips/boot/dts/mti/sead3.dts +++ b/arch/mips/boot/dts/mti/sead3.dts @@ -56,7 +56,7 @@ interrupt-parent = <&cpu_intc>; }; - ehci@1b200000 { + usb@1b200000 { compatible = "generic-ehci"; reg = <0x1b200000 0x1000>; -- cgit v1.2.3-70-g09d2 From 3180b64aa9f1f25e0a6a743091d5c786a1a85cbd Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:43 +0300 Subject: mips: dts: ralink: mt7628a: Harmonize EHCI/OHCI DT nodes name In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7628a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi index 892e8ab863c5..45bf96a3d17a 100644 --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi @@ -275,7 +275,7 @@ reset-names = "host", "device"; }; - ehci@101c0000 { + usb@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; -- cgit v1.2.3-70-g09d2 From 09a48cbcd7af9203296938044f1100bb113ce01a Mon Sep 17 00:00:00 2001 From: Necip Fazil Yildiran Date: Wed, 4 Nov 2020 19:41:27 +0300 Subject: MIPS: BMC47xx: fix kconfig dependency bug for BCM47XX_SSB When BCM47XX_SSB is enabled and SSB_PCIHOST is disabled, it results in the following Kbuild warning: WARNING: unmet direct dependencies detected for SSB_B43_PCI_BRIDGE Depends on [n]: SSB [=y] && SSB_PCIHOST [=n] Selected by [y]: - BCM47XX_SSB [=y] && BCM47XX [=y] && PCI [=y] The reason is that BCM47XX_SSB selects SSB_B43_PCI_BRIDGE without depending on or selecting SSB_PCIHOST while SSB_B43_PCI_BRIDGE depends on SSB_PCIHOST. This can also fail building the kernel as demonstrated in a bug report. Honor the kconfig dependency to remove unmet direct dependency warnings and avoid any potential build failures. Link: https://bugzilla.kernel.org/show_bug.cgi?id=210051 Signed-off-by: Necip Fazil Yildiran Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index 6889f74e06f5..40876654423c 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -9,6 +9,7 @@ config BCM47XX_SSB select SSB_DRIVER_MIPS select SSB_DRIVER_EXTIF select SSB_EMBEDDED + select SSB_PCIHOST if PCI select SSB_B43_PCI_BRIDGE if PCI select SSB_DRIVER_PCICORE if PCI select SSB_PCICORE_HOSTMODE if PCI -- cgit v1.2.3-70-g09d2 From 3a5fe2fb9635c43359c9729352f45044f3c8df6b Mon Sep 17 00:00:00 2001 From: Necip Fazil Yildiran Date: Tue, 3 Nov 2020 00:34:01 +0300 Subject: MIPS: BCM47XX: fix kconfig dependency bug for BCM47XX_BCMA When BCM47XX_BCMA is enabled and BCMA_DRIVER_PCI is disabled, it results in the following Kbuild warning: WARNING: unmet direct dependencies detected for BCMA_DRIVER_PCI_HOSTMODE Depends on [n]: MIPS [=y] && BCMA_DRIVER_PCI [=n] && PCI_DRIVERS_LEGACY [=y] && BCMA [=y]=y Selected by [y]: - BCM47XX_BCMA [=y] && BCM47XX [=y] && PCI [=y] The reason is that BCM47XX_BCMA selects BCMA_DRIVER_PCI_HOSTMODE without depending on or selecting BCMA_DRIVER_PCI while BCMA_DRIVER_PCI_HOSTMODE depends on BCMA_DRIVER_PCI. This can also fail building the kernel. Honor the kconfig dependency to remove unmet direct dependency warnings and avoid any potential build failures. Fixes: c1d1c5d4213e ("bcm47xx: add support for bcma bus") Link: https://bugzilla.kernel.org/show_bug.cgi?id=209879 Signed-off-by: Necip Fazil Yildiran Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index 40876654423c..13d315ee676b 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -28,6 +28,7 @@ config BCM47XX_BCMA select BCMA select BCMA_HOST_SOC select BCMA_DRIVER_MIPS + select BCMA_DRIVER_PCI if PCI select BCMA_DRIVER_PCI_HOSTMODE if PCI select BCMA_DRIVER_GPIO default y -- cgit v1.2.3-70-g09d2 From fc3553cb9fc5fee18299b599040d2cc2eb17666d Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:00 +0100 Subject: dt-bindings: mips: Add Luton Luton SoC belongs to the same family as Ocelot. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT Reviewed-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/mscc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt index bc817e984628..cc93fd302553 100644 --- a/Documentation/devicetree/bindings/mips/mscc.txt +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following properties: Required properties: -- compatible: "mscc,ocelot" +- compatible: "mscc,ocelot" or "mscc,luton" * Other peripherals: -- cgit v1.2.3-70-g09d2 From 597fa616c49ae06a1a307750a7df9b59205f462f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:01 +0100 Subject: dt-bindings: mips: Add Serval and Jaguar2 Serval and Jaguar2 SoCs belong to the same family as Ocelot and Luton. Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT Reviewed-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/mscc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt index cc93fd302553..cc916eaeed0a 100644 --- a/Documentation/devicetree/bindings/mips/mscc.txt +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following properties: Required properties: -- compatible: "mscc,ocelot" or "mscc,luton" +- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2" * Other peripherals: -- cgit v1.2.3-70-g09d2 From 700364dadceb8d60ca1bb6ccd3da619a36ecdcde Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:02 +0100 Subject: MIPS: mscc: Prepare configuration to handle more SoCs Ocelot belongs to a family of SoC named the VCore III. In order to add these new Soc, use the new symbol SOC_VCOREIII instead of a one dedicated to Ocelot. In order to avoid regression on driver building, the MSCC_OCELOT configuration symbol is kept until the driver will be converted. Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/Makefile | 2 +- arch/mips/boot/dts/mscc/Makefile | 2 +- arch/mips/generic/Kconfig | 11 ++++++++--- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 19027129add8..0259238d7a2e 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -6,7 +6,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img subdir-$(CONFIG_MACH_INGENIC) += ingenic subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson -subdir-$(CONFIG_MSCC_OCELOT) += mscc +subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index eb71515871f6..5015ccbbfb23 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb +dtb-$(CONFIG_SOC_VCOREIII) += ocelot_pcb123.dtb ocelot_pcb120.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index 55d9aed7ced9..45431b88dded 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -34,14 +34,19 @@ config LEGACY_BOARD_OCELOT bool "Support MSCC Ocelot boards" depends on LEGACY_BOARD_SEAD3=n select LEGACY_BOARDS - select MSCC_OCELOT + select SOC_VCOREIII select SYS_HAS_EARLY_PRINTK select USE_GENERIC_EARLY_PRINTK_8250 -config MSCC_OCELOT +config SOC_VCOREIII bool select GPIOLIB select MSCC_OCELOT_IRQ + select MSCC_OCELOT #will be removed when driver no more use it + +#Will be removed when the driver using it will be converted to SOC_VCOREIII +config MSCC_OCELOT + bool comment "FIT/UHI Boards" @@ -67,7 +72,7 @@ config FIT_IMAGE_FDT_XILFPGA config FIT_IMAGE_FDT_OCELOT bool "Include FDT for Microsemi Ocelot development platforms" - select MSCC_OCELOT + select SOC_VCOREIII help Enable this to include the FDT for the Ocelot development platforms from Microsemi in the FIT kernel image. -- cgit v1.2.3-70-g09d2 From 2825f4c0ffcdf6e519e30ecdae4cd8c1c89a1cb9 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:03 +0100 Subject: MIPS: mscc: Fix configuration name for ocelot legacy boards Ocelots is supported by the generic MIPS build so make it clears that LEGACY_BOARD_OCELOT is only needed for legacy boards which didn't have bootloader supporting device tree. Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/generic/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index 45431b88dded..eb2a3fa9fcd7 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -31,7 +31,7 @@ comment "MSCC Ocelot doesn't work with SEAD3 enabled" depends on LEGACY_BOARD_SEAD3 config LEGACY_BOARD_OCELOT - bool "Support MSCC Ocelot boards" + bool "Legacy support for Ocelot based boards" depends on LEGACY_BOARD_SEAD3=n select LEGACY_BOARDS select SOC_VCOREIII -- cgit v1.2.3-70-g09d2 From 93b834e6cf0e6bbb16f9bd678106648442960aba Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:04 +0100 Subject: MIPS: mscc: Add luton dtsi Add a device tree include file for the Microsemi Luton SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mscc/luton.dtsi | 116 +++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 arch/mips/boot/dts/mscc/luton.dtsi diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi new file mode 100644 index 000000000000..2a170b84c5a9 --- /dev/null +++ b/arch/mips/boot/dts/mscc/luton.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microsemi Corporation */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,luton"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416666666>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&cpu_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + + ahb@60000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x60000000 0x20000000>; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@10000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x10000000 0x2c>; + }; + + intc: interrupt-controller@10000084 { + compatible = "mscc,luton-icpu-intr"; + reg = <0x10000084 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@10100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x10100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + i2c0: i2c@10100400 { + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + reg = <0x10100400 0x100>, <0x100002a4 0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clocks = <&ahb_clk>; + + status = "disabled"; + }; + + gpio: pinctrl@70068 { + compatible = "mscc,luton-pinctrl"; + reg = <0x70068 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 32>; + interrupt-controller; + interrupts = <13>; + #interrupt-cells = <2>; + + i2c_pins: i2c-pins { + pins = "GPIO_5", "GPIO_6"; + function = "twi"; + }; + + uart_pins: uart-pins { + pins = "GPIO_30", "GPIO_31"; + function = "uart"; + }; + + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 72bc5e8b25a0031354a27c1da2b89104e2bf32e3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:05 +0100 Subject: MIPS: mscc: Add luton PC0B91 device tree Add a device tree for the Microsemi Luton PCB091 evaluation board. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mscc/Makefile | 5 ++++- arch/mips/boot/dts/mscc/luton_pcb091.dts | 30 ++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 arch/mips/boot/dts/mscc/luton_pcb091.dts diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index 5015ccbbfb23..40699b44ed50 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_SOC_VCOREIII) += ocelot_pcb123.dtb ocelot_pcb120.dtb +dtb-$(CONFIG_SOC_VCOREIII) += \ + luton_pcb091.dtb \ + ocelot_pcb120.dtb \ + ocelot_pcb123.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mscc/luton_pcb091.dts b/arch/mips/boot/dts/mscc/luton_pcb091.dts new file mode 100644 index 000000000000..26ef6285d71d --- /dev/null +++ b/arch/mips/boot/dts/mscc/luton_pcb091.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microsemi Corporation + */ + +/dts-v1/; + +#include "luton.dtsi" + +/ { + model = "Luton10 PCB091 Reference Board"; + compatible = "mscc,luton-pcb091", "mscc,luton"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-sda-hold-time-ns = <300>; +}; -- cgit v1.2.3-70-g09d2 From 378e413fe97e8d66ff4dc90b0b5b6ef3bbc15252 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:06 +0100 Subject: MIPS: mscc: build FIT image for Luton Luton now has already an u-boot port so let's build FIT images. Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/generic/Kconfig | 8 ++++++++ arch/mips/generic/Platform | 1 + arch/mips/generic/board-luton.its.S | 23 +++++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 arch/mips/generic/board-luton.its.S diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index eb2a3fa9fcd7..e5a7a1314e71 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -78,6 +78,14 @@ config FIT_IMAGE_FDT_OCELOT from Microsemi in the FIT kernel image. This requires u-boot on the platform. +config FIT_IMAGE_FDT_LUTON + bool "Include FDT for Microsemi Luton development platforms" + select SOC_VCOREIII + help + Enable this to include the FDT for the Luton development platforms + from Microsemi in the FIT kernel image. + This requires u-boot on the platform. + config BOARD_INGENIC bool "Support boards based on Ingenic SoCs" select MACH_INGENIC_GENERIC diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index f8ef2f9d107e..4b6905daa39c 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -20,4 +20,5 @@ its-y := vmlinux.its.S its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S +its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S diff --git a/arch/mips/generic/board-luton.its.S b/arch/mips/generic/board-luton.its.S new file mode 100644 index 000000000000..39a543f62f25 --- /dev/null +++ b/arch/mips/generic/board-luton.its.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt@luton_pcb091 { + description = "MSCC Luton PCB091 Device Tree"; + data = /incbin/("boot/dts/mscc/luton_pcb091.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash@0 { + algo = "sha1"; + }; + }; + }; + + configurations { + pcb091 { + description = "Luton Linux kernel"; + kernel = "kernel@0"; + fdt = "fdt@luton_pcb091"; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From f84778f7d8c3b867d6aaca9361d7b43b222f9f6a Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:07 +0100 Subject: MIPS: mscc: Add jaguar2 support Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mscc/Makefile | 3 + arch/mips/boot/dts/mscc/jaguar2.dtsi | 167 +++++++++++++++++ arch/mips/boot/dts/mscc/jaguar2_common.dtsi | 25 +++ arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 267 ++++++++++++++++++++++++++++ arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 107 +++++++++++ arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 57 ++++++ arch/mips/generic/Kconfig | 8 + arch/mips/generic/Platform | 1 + arch/mips/generic/board-jaguar2.its.S | 40 +++++ 9 files changed, 675 insertions(+) create mode 100644 arch/mips/boot/dts/mscc/jaguar2.dtsi create mode 100644 arch/mips/boot/dts/mscc/jaguar2_common.dtsi create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts create mode 100644 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts create mode 100644 arch/mips/generic/board-jaguar2.its.S diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index 40699b44ed50..befda72ceb26 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_SOC_VCOREIII) += \ + jaguar2_pcb110.dtb \ + jaguar2_pcb111.dtb \ + jaguar2_pcb118.dtb \ luton_pcb091.dtb \ ocelot_pcb120.dtb \ ocelot_pcb123.dtb diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi new file mode 100644 index 000000000000..42b2b0a51ddc --- /dev/null +++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,jr2"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + gpio0 = &gpio; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&cpu_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + + ahb: ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + }; + + intc: interrupt-controller@70000070 { + compatible = "mscc,jaguar2-icpu-intr"; + reg = <0x70000070 0x94>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@70100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@70100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + gpio: pinctrl@71010038 { + compatible = "mscc,jaguar2-pinctrl"; + reg = <0x71010038 0x90>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_24", "GPIO_25"; + function = "uart2"; + }; + + cs1_pins: cs1-pins { + pins = "GPIO_16"; + function = "si"; + }; + + cs2_pins: cs2-pins { + pins = "GPIO_17"; + function = "si"; + }; + + cs3_pins: cs3-pins { + pins = "GPIO_18"; + function = "si"; + }; + + i2c_pins: i2c-pins { + pins = "GPIO_14", "GPIO_15"; + function = "twi"; + }; + + i2c2_pins: i2c2-pins { + pins = "GPIO_28", "GPIO_29"; + function = "twi2"; + }; + }; + + i2c0: i2c@70100400 { + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + reg = <0x70100400 0x100>, <0x700001b8 0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <8>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; + }; + + i2c2: i2c@70100c00 { + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + reg = <0x70100c00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <8>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; + }; + }; +}; diff --git a/arch/mips/boot/dts/mscc/jaguar2_common.dtsi b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi new file mode 100644 index 000000000000..679ff0d8eda8 --- /dev/null +++ b/arch/mips/boot/dts/mscc/jaguar2_common.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microsemi Corporation + */ + +#include "jaguar2.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-sda-hold-time-ns = <300>; +}; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts new file mode 100644 index 000000000000..d80cd6842b2a --- /dev/null +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microsemi Corporation + */ + +/dts-v1/; +#include "jaguar2_common.dtsi" +#include + +/ { + model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board"; + compatible = "mscc,jr2-pcb110", "mscc,jr2"; + + aliases { + i2c0 = &i2c0; + i2c108 = &i2c108; + i2c109 = &i2c109; + i2c110 = &i2c110; + i2c111 = &i2c111; + i2c112 = &i2c112; + i2c113 = &i2c113; + i2c114 = &i2c114; + i2c115 = &i2c115; + i2c116 = &i2c116; + i2c117 = &i2c117; + i2c118 = &i2c118; + i2c119 = &i2c119; + i2c120 = &i2c120; + i2c121 = &i2c121; + i2c122 = &i2c122; + i2c123 = &i2c123; + i2c124 = &i2c124; + i2c125 = &i2c125; + i2c126 = &i2c126; + i2c127 = &i2c127; + i2c128 = &i2c128; + i2c129 = &i2c129; + i2c130 = &i2c130; + i2c131 = &i2c131; + i2c149 = &i2c149; + i2c150 = &i2c150; + i2c151 = &i2c151; + i2c152 = &i2c152; + }; + i2c0_imux: i2c0-imux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + pinctrl-names = + "i2c149", "i2c150", "i2c151", "i2c152", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_2>; + pinctrl-3 = <&i2cmux_3>; + pinctrl-4 = <&i2cmux_pins_i>; + i2c149: i2c@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c150: i2c@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c151: i2c@2 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c152: i2c@3 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2c0_emux: i2c0-emux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH + &gpio 52 GPIO_ACTIVE_HIGH + &gpio 53 GPIO_ACTIVE_HIGH + &gpio 58 GPIO_ACTIVE_HIGH + &gpio 59 GPIO_ACTIVE_HIGH>; + idle-state = <0x0>; + i2c108: i2c@10 { + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c109: i2c@11 { + reg = <0x11>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c110: i2c@12 { + reg = <0x12>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c111: i2c@13 { + reg = <0x13>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c112: i2c@14 { + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c113: i2c@15 { + reg = <0x15>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c114: i2c@16 { + reg = <0x16>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c115: i2c@17 { + reg = <0x17>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c116: i2c@8 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c117: i2c@9 { + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c118: i2c@a { + reg = <0xa>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c119: i2c@b { + reg = <0xb>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c120: i2c@c { + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c121: i2c@d { + reg = <0xd>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c122: i2c@e { + reg = <0xe>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c123: i2c@f { + reg = <0xf>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&gpio { + synce_pins: synce-pins { + // GPIO 16 == SI_nCS1 + pins = "GPIO_16"; + function = "si"; + }; + synce_builtin_pins: synce-builtin-pins { + // GPIO 49 == SI_nCS13 + pins = "GPIO_49"; + function = "si"; + }; + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_17"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_18"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_2: i2cmux-2 { + pins = "GPIO_20"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_3: i2cmux-3 { + pins = "GPIO_21"; + function = "twi_scl_m"; + output-high; + }; +}; + +&i2c0 { + pca9545@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + i2c124: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c125: i2c@1 { + /* FMC B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c126: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c127: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + pca9545@71 { + compatible = "nxp,pca9545"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + i2c128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c129: i2c@1 { + /* FMC B */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts new file mode 100644 index 000000000000..813c5e16013c --- /dev/null +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "jaguar2_common.dtsi" + +/ { + model = "Jaguar2 Cu48 PCB111 Reference Board"; + compatible = "mscc,jr2-pcb111", "mscc,jr2"; + + aliases { + i2c0 = &i2c0; + i2c149 = &i2c149; + i2c150 = &i2c150; + i2c151 = &i2c151; + i2c152 = &i2c152; + i2c203 = &i2c203; + }; + + i2c0_imux: i2c0-imux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + pinctrl-names = + "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_2>; + pinctrl-3 = <&i2cmux_3>; + pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE + pinctrl-5 = <&i2cmux_pins_i>; + i2c149: i2c@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c150: i2c@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c151: i2c@2 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c152: i2c@3 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c203: i2c@4 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&gpio { + synce_builtin_pins: synce-builtin-pins { + // GPIO 49 == SI_nCS13 + pins = "GPIO_49"; + function = "si"; + }; + cpld_pins: cpld-pins { + // GPIO 50 == SI_nCS14 + pins = "GPIO_50"; + function = "si"; + }; + cpld_fifo_pins: synce-builtin-pins { + // GPIO 51 == SI_nCS15 + pins = "GPIO_51"; + function = "si"; + }; +}; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_17", "GPIO_18"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_17"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_18"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_2: i2cmux-2 { + pins = "GPIO_20"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_3: i2cmux-3 { + pins = "GPIO_21"; + function = "twi_scl_m"; + output-high; + }; +}; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts new file mode 100644 index 000000000000..27c644f2d17f --- /dev/null +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "jaguar2_common.dtsi" + +/ { + model = "Jaguar2/Aquantia PCB118 Reference Board"; + compatible = "mscc,jr2-pcb118", "mscc,jr2"; + + aliases { + i2c150 = &i2c150; + i2c151 = &i2c151; + }; + + i2c0_imux: i2c0-imux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + pinctrl-names = + "i2c150", "i2c151", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_pins_i>; + i2c150: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c151: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&gpio { + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_17", "GPIO_16"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_17"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_16"; + function = "twi_scl_m"; + output-high; + }; +}; diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index e5a7a1314e71..c7a840b8eaa6 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -86,6 +86,14 @@ config FIT_IMAGE_FDT_LUTON from Microsemi in the FIT kernel image. This requires u-boot on the platform. +config FIT_IMAGE_FDT_JAGUAR2 + bool "Include FDT for Microsemi Jaguar2 development platforms" + select SOC_VCOREIII + help + Enable this to include the FDT for the Jaguar2 development platforms + from Microsemi in the FIT kernel image. + This requires u-boot on the platform. + config BOARD_INGENIC bool "Support boards based on Ingenic SoCs" select MACH_INGENIC_GENERIC diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index 4b6905daa39c..3f2055bea596 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -21,4 +21,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S +its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S diff --git a/arch/mips/generic/board-jaguar2.its.S b/arch/mips/generic/board-jaguar2.its.S new file mode 100644 index 000000000000..fb0e589eeff7 --- /dev/null +++ b/arch/mips/generic/board-jaguar2.its.S @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt@jaguar2_pcb110 { + description = "MSCC Jaguar2 PCB110 Device Tree"; + data = /incbin/("boot/dts/mscc/jaguar2_pcb110.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash@0 { + algo = "sha1"; + }; + }; + fdt@jaguar2_pcb111 { + description = "MSCC Jaguar2 PCB111 Device Tree"; + data = /incbin/("boot/dts/mscc/jaguar2_pcb111.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash@0 { + algo = "sha1"; + }; + }; + }; + + configurations { + pcb110 { + description = "Jaguar2 Linux kernel"; + kernel = "kernel@0"; + fdt = "fdt@jaguar2_pcb110"; + ramdisk = "ramdisk"; + }; + pcb111 { + description = "Jaguar2 Linux kernel"; + kernel = "kernel@0"; + fdt = "fdt@jaguar2_pcb111"; + ramdisk = "ramdisk"; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From fe0052018a84d50be034449b4175177f569fbf5c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 10 Nov 2020 12:45:08 +0100 Subject: MIPS: mscc: Add serval support Add a device trees and FIT image support for the Microsemi Serval SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen . Signed-off-by: Gregory CLEMENT Acked-by: Alexandre Belloni Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/mscc/Makefile | 5 +- arch/mips/boot/dts/mscc/serval.dtsi | 153 +++++++++++++++++++++++++++++ arch/mips/boot/dts/mscc/serval_common.dtsi | 127 ++++++++++++++++++++++++ arch/mips/boot/dts/mscc/serval_pcb105.dts | 17 ++++ arch/mips/boot/dts/mscc/serval_pcb106.dts | 17 ++++ arch/mips/generic/Kconfig | 8 ++ arch/mips/generic/Platform | 1 + arch/mips/generic/board-serval.its.S | 24 +++++ 8 files changed, 351 insertions(+), 1 deletion(-) create mode 100644 arch/mips/boot/dts/mscc/serval.dtsi create mode 100644 arch/mips/boot/dts/mscc/serval_common.dtsi create mode 100644 arch/mips/boot/dts/mscc/serval_pcb105.dts create mode 100644 arch/mips/boot/dts/mscc/serval_pcb106.dts create mode 100644 arch/mips/generic/board-serval.its.S diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index befda72ceb26..eeb6b7aae83b 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -5,6 +5,9 @@ dtb-$(CONFIG_SOC_VCOREIII) += \ jaguar2_pcb118.dtb \ luton_pcb091.dtb \ ocelot_pcb120.dtb \ - ocelot_pcb123.dtb + ocelot_pcb123.dtb \ + serval_pcb105.dtb \ + serval_pcb106.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mscc/serval.dtsi b/arch/mips/boot/dts/mscc/serval.dtsi new file mode 100644 index 000000000000..089ce89df190 --- /dev/null +++ b/arch/mips/boot/dts/mscc/serval.dtsi @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mscc,serval"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips24KEc"; + device_type = "cpu"; + clocks = <&cpu_clk>; + reg = <0>; + }; + }; + + aliases { + serial0 = &uart0; + gpio0 = &gpio; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + cpu_clk: cpu-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416666666>; + }; + + ahb_clk: ahb-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&cpu_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + + ahb: ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupt-parent = <&intc>; + + cpu_ctrl: syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + }; + + intc: interrupt-controller@70000070 { + compatible = "mscc,serval-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + uart0: serial@70100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100000 0x20>; + interrupts = <6>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + uart2: serial@70100800 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + compatible = "ns16550a"; + reg = <0x70100800 0x20>; + interrupts = <7>; + clocks = <&ahb_clk>; + reg-io-width = <4>; + reg-shift = <2>; + + status = "disabled"; + }; + + gpio: pinctrl@71070034 { + compatible = "mscc,serval-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1"; + function = "sg0"; + }; + + i2c_pins: i2c-pins { + pins = "GPIO_6", "GPIO_7"; + function = "twi"; + }; + + uart_pins: uart-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_13", "GPIO_14"; + function = "uart2"; + }; + + cs1_pins: cs1-pins { + pins = "GPIO_8"; + function = "si"; + }; + + irqext0_pins: irqext0-pins { + pins = "GPIO_28"; + function = "irq0"; + }; + + irqext1_pins: irqext1-pins { + pins = "GPIO_29"; + function = "irq1"; + }; + }; + + i2c0: i2c@70100400 { + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; + status = "disabled"; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + reg = <0x70100400 0x100>, <0x70000190 0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <8>; + clock-frequency = <100000>; + clocks = <&ahb_clk>; + }; + }; +}; diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi new file mode 100644 index 000000000000..5b404836db5e --- /dev/null +++ b/arch/mips/boot/dts/mscc/serval_common.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microsemi Corporation + */ + +#include "serval.dtsi" + +/ { + aliases { + serial0 = &uart0; + i2c104 = &i2c104; + i2c105 = &i2c105; + i2c106 = &i2c106; + i2c107 = &i2c107; + i2c108 = &i2c108; + i2c109 = &i2c109; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2c0_imux: i2c0-imux{ + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c0>; + pinctrl-names = + "i2c104", "i2c105", "i2c106", "i2c107", + "i2c108", "i2c109", "idle"; + pinctrl-0 = <&i2cmux_0>; + pinctrl-1 = <&i2cmux_1>; + pinctrl-2 = <&i2cmux_2>; + pinctrl-3 = <&i2cmux_3>; + pinctrl-4 = <&i2cmux_4>; + pinctrl-5 = <&i2cmux_5>; + pinctrl-6 = <&i2cmux_pins_i>; + i2c104: i2c_sfp0@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c105: i2c_sfp1@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c106: i2c_sfp2@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c107: i2c_sfp3@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c108: i2c_sfp4@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c109: i2c_sfp5@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&gpio { + i2c_pins: i2c-pins { + pins = "GPIO_7"; /* No "default" scl for i2c0 */ + function = "twi"; + }; + i2cmux_pins_i: i2cmux-pins-i { + pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19", + "GPIO_20", "GPIO_21"; + function = "twi_scl_m"; + output-low; + }; + i2cmux_0: i2cmux-0 { + pins = "GPIO_11"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_1: i2cmux-1 { + pins = "GPIO_12"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_2: i2cmux-2 { + pins = "GPIO_18"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_3: i2cmux-3 { + pins = "GPIO_19"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_4: i2cmux-4 { + pins = "GPIO_20"; + function = "twi_scl_m"; + output-high; + }; + i2cmux_5: i2cmux-5 { + pins = "GPIO_21"; + function = "twi_scl_m"; + output-high; + }; +}; + +&i2c0 { + status = "okay"; + i2c-sda-hold-time-ns = <300>; +}; + diff --git a/arch/mips/boot/dts/mscc/serval_pcb105.dts b/arch/mips/boot/dts/mscc/serval_pcb105.dts new file mode 100644 index 000000000000..a1b0012b79d3 --- /dev/null +++ b/arch/mips/boot/dts/mscc/serval_pcb105.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "serval_common.dtsi" + +/ { + model = "Serval PCB105 Reference Board"; + compatible = "mscc,serval-pcb105", "mscc,serval"; + + aliases { + }; + +}; + diff --git a/arch/mips/boot/dts/mscc/serval_pcb106.dts b/arch/mips/boot/dts/mscc/serval_pcb106.dts new file mode 100644 index 000000000000..237be7c8da57 --- /dev/null +++ b/arch/mips/boot/dts/mscc/serval_pcb106.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +/dts-v1/; +#include "serval_common.dtsi" + +/ { + model = "Serval PCB106 Reference Board"; + compatible = "mscc,serval-pcb106", "mscc,serval"; + + aliases { + }; + +}; + diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index c7a840b8eaa6..657dd93c5e76 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -94,6 +94,14 @@ config FIT_IMAGE_FDT_JAGUAR2 from Microsemi in the FIT kernel image. This requires u-boot on the platform. +config FIT_IMAGE_FDT_SERVAL + bool "Include FDT for Microsemi Serval development platforms" + select SOC_VCOREIII + help + Enable this to include the FDT for the Serval development platforms + from Microsemi in the FIT kernel image. + This requires u-boot on the platform. + config BOARD_INGENIC bool "Support boards based on Ingenic SoCs" select MACH_INGENIC_GENERIC diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index 3f2055bea596..b871af16b5b6 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -22,4 +22,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S +its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S diff --git a/arch/mips/generic/board-serval.its.S b/arch/mips/generic/board-serval.its.S new file mode 100644 index 000000000000..4ea4fc9d757f --- /dev/null +++ b/arch/mips/generic/board-serval.its.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt@serval_pcb105 { + description = "MSCC Serval PCB105 Device Tree"; + data = /incbin/("boot/dts/mscc/serval_pcb105.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash@0 { + algo = "sha1"; + }; + }; + }; + + configurations { + pcb105 { + description = "Serval Linux kernel"; + kernel = "kernel@0"; + fdt = "fdt@serval_pcb105"; + ramdisk = "ramdisk"; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 9d63bcb87157c90899525d9db25b37106cd0afe3 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 1 Nov 2020 15:12:52 +0000 Subject: mips: boot: clean up self-extracting targets scenarios 1. All final targets like vmlinuz.{bin,ecoff,srec} etc. should reside in $(objtree)/arch/mips/boot, not in the root $(objtree) directory. The only file that should be left there is vmlinuz, similar to other architectures. 2. Add all the targets to $(targets) variable, so they'll be properly accounted by Kbuild. This also allows to remove redundant $(clean-files) (which were missing uzImage BTW). 3. Prefix all targets with $(obj)/$(objtree), depending on their locations. Misc: fix the identation of the 'STRIP' quiet message. Signed-off-by: Alexander Lobakin Acked-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 2 +- arch/mips/boot/.gitignore | 1 + arch/mips/boot/compressed/Makefile | 50 ++++++++++++++++++++++++++------------ 3 files changed, 37 insertions(+), 16 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0d0f29d662c9..622ee83dbb9b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -378,7 +378,7 @@ ifdef CONFIG_SYS_SUPPORTS_ZBOOT # boot/compressed $(bootz-y): $(vmlinux-32) FORCE $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ - $(bootvars-y) 32bit-bfd=$(32bit-bfd) $@ + $(bootvars-y) 32bit-bfd=$(32bit-bfd) arch/mips/boot/$@ else vmlinuz: FORCE @echo ' CONFIG_SYS_SUPPORTS_ZBOOT is not enabled' diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore index 2adc8581a175..1c7adddf2e60 100644 --- a/arch/mips/boot/.gitignore +++ b/arch/mips/boot/.gitignore @@ -2,6 +2,7 @@ mkboot elf2ecoff vmlinux.* +vmlinuz.* zImage zImage.tmp calc_vmlinuz_load_addr diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index d66511825fe1..fa2c1e1b303f 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -65,7 +65,9 @@ $(obj)/bswapsi.c: $(obj)/%.c: $(srctree)/arch/mips/lib/%.c FORCE targets := $(notdir $(vmlinuzobjs-y)) targets += vmlinux.bin + OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S + $(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE $(call if_changed,objcopy) @@ -78,12 +80,15 @@ tool_$(CONFIG_KERNEL_XZ) = xzkern tool_$(CONFIG_KERNEL_ZSTD) = zstd22 targets += vmlinux.bin.z + $(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE $(call if_changed,$(tool_y)) targets += piggy.o dummy.o + OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \ --set-section-flags=.image=contents,alloc,load,readonly,data + $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE $(call if_changed,objcopy) @@ -102,14 +107,21 @@ UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS) vmlinuzobjs-y += $(obj)/piggy.o +targets += ../../../../vmlinuz + quiet_cmd_zld = LD $@ cmd_zld = $(LD) $(KBUILD_LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@ -quiet_cmd_strip = STRIP $@ +quiet_cmd_strip = STRIP $@ cmd_strip = $(STRIP) -s $@ -vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr + +$(objtree)/vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr $(call cmd,zld) $(call cmd,strip) +objboot := $(objtree)/arch/mips/boot + +$(objboot)/vmlinuz: $(objtree)/vmlinuz FORCE + # # Some DECstations need all possible sections of an ECOFF executable # @@ -121,34 +133,42 @@ endif hostprogs += ../elf2ecoff ifdef CONFIG_32BIT - VMLINUZ = vmlinuz + VMLINUZ = $(objtree)/vmlinuz else - VMLINUZ = vmlinuz.32 + VMLINUZ = $(objboot)/vmlinuz.32 endif +targets += ../vmlinuz.32 + quiet_cmd_32 = OBJCOPY $@ cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ -vmlinuz.32: vmlinuz + +$(objboot)/vmlinuz.32: $(objtree)/vmlinuz $(call cmd,32) +targets += ../vmlinuz.ecoff + quiet_cmd_ecoff = ECOFF $@ cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag) -vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ) + +$(objboot)/vmlinuz.ecoff: $(objboot)/elf2ecoff $(VMLINUZ) $(call cmd,ecoff) +targets += ../vmlinuz.bin + OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary -vmlinuz.bin: vmlinuz + +$(objboot)/vmlinuz.bin: $(objtree)/vmlinuz $(call cmd,objcopy) +targets += ../vmlinuz.srec + OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec -vmlinuz.srec: vmlinuz + +$(objboot)/vmlinuz.srec: $(objtree)/vmlinuz $(call cmd,objcopy) -uzImage.bin: vmlinuz.bin FORCE - $(call if_changed,uimage,none) +targets += ../uzImage.bin -clean-files += $(objtree)/vmlinuz -clean-files += $(objtree)/vmlinuz.32 -clean-files += $(objtree)/vmlinuz.ecoff -clean-files += $(objtree)/vmlinuz.bin -clean-files += $(objtree)/vmlinuz.srec +$(objboot)/uzImage.bin: $(objboot)/vmlinuz.bin FORCE + $(call if_changed,uimage,none) -- cgit v1.2.3-70-g09d2 From a3fb655027c33a9281d3b813798b15bdf1e75d43 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 1 Nov 2020 15:13:01 +0000 Subject: mips: boot: add support for self-extracting FIT images (vmlinuz.itb) Commit c3e2ee657418 ("MIPS: generic: Add support for zboot") added support for self-extracting images to Generic MIPS. However, the intended way to boot Generic MIPS kernels is using FIT Images and UHI boot protocol, but currently there's no way to make self-extracting FIT Image (only legacy uzImages). Add a target for this named "vmlinuz.itb", which will consist of vmlinuz.bin and selected DT blobs. It will allow to have the advantages of both UHI and self-extracting images. Signed-off-by: Alexander Lobakin Acked-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 1 + arch/mips/boot/compressed/Makefile | 48 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 622ee83dbb9b..cd4343edeb11 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -347,6 +347,7 @@ bootz-y += vmlinuz.srec ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0) bootz-y += uzImage.bin endif +bootz-y += vmlinuz.itb # # Some machines like the Indy need 32-bit ELF binaries for booting purposes. diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index fa2c1e1b303f..4c3bc7e3d56d 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -172,3 +172,51 @@ targets += ../uzImage.bin $(objboot)/uzImage.bin: $(objboot)/vmlinuz.bin FORCE $(call if_changed,uimage,none) + +# +# Flattened Image Tree (.itb) image +# + +ifeq ($(ADDR_BITS),32) +itb_addr_cells = 1 +endif +ifeq ($(ADDR_BITS),64) +itb_addr_cells = 2 +endif + +targets += ../vmlinuz.its.S + +quiet_cmd_its_cat = CAT $@ + cmd_its_cat = cat $(real-prereqs) >$@ + +$(objboot)/vmlinuz.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS)) FORCE + $(call if_changed,its_cat) + +targets += ../vmlinuz.its + +quiet_cmd_cpp_its_S = ITS $@ + cmd_cpp_its_S = $(CPP) -P -C -o $@ $< \ + -DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \ + -DVMLINUX_BINARY="\"$(2)\"" \ + -DVMLINUX_COMPRESSION="\"none\"" \ + -DVMLINUX_LOAD_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) \ + -DVMLINUX_ENTRY_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) \ + -DADDR_BITS=$(ADDR_BITS) \ + -DADDR_CELLS=$(itb_addr_cells) + +$(objboot)/vmlinuz.its: $(objboot)/vmlinuz.its.S FORCE + $(call if_changed,cpp_its_S,vmlinuz.bin) + +targets += ../vmlinuz.itb + +quiet_cmd_itb-image = ITB $@ + cmd_itb-image = \ + env PATH="$(objtree)/scripts/dtc:$(PATH)" \ + $(BASH) $(MKIMAGE) \ + -D "-I dts -O dtb -p 500 \ + --include $(objtree)/arch/mips \ + --warning no-unit_address_vs_reg" \ + -f $(2) $@ + +$(objboot)/vmlinuz.itb: $(objboot)/vmlinuz.its $(objboot)/vmlinuz.bin FORCE + $(call if_changed,itb-image,$<) -- cgit v1.2.3-70-g09d2 From 158c774d3c64859e84dd20e04d5fb18c8d3d318e Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Tue, 17 Nov 2020 01:55:07 +0800 Subject: MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20. 2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1000-Neo. 3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752 nodes for CU1830-Neo. Tested-by: 周正 (Zhou Zheng) Tested by: H. Nikolaus Schaller # CI20/jz4780 Signed-off-by: 周琰杰 (Zhou Yanjie) Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ingenic/ci20.dts | 45 +++++++++++++++++++-- arch/mips/boot/dts/ingenic/cu1000-neo.dts | 62 ++++++++++++++++++++++++++--- arch/mips/boot/dts/ingenic/cu1830-neo.dts | 66 ++++++++++++++++++++++++++++--- arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++++++++++++++++++++- arch/mips/boot/dts/ingenic/x1000.dtsi | 56 +++++++++++++++++++++++++- arch/mips/boot/dts/ingenic/x1830.dtsi | 58 ++++++++++++++++++++++++++- 6 files changed, 313 insertions(+), 19 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 75f5bfbf2c37..8877c62609de 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -69,9 +69,11 @@ eth0_power: fixedregulator@0 { compatible = "regulator-fixed"; + regulator-name = "eth0_power"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpb 25 GPIO_ACTIVE_LOW>; enable-active-high; }; @@ -83,16 +85,39 @@ wlan0_power: fixedregulator@1 { compatible = "regulator-fixed"; + regulator-name = "wlan0_power"; + gpio = <&gpb 19 GPIO_ACTIVE_LOW>; enable-active-high; }; + + otg_power: fixedregulator@2 { + compatible = "regulator-fixed"; + + regulator-name = "otg_power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpf 14 GPIO_ACTIVE_LOW>; + enable-active-high; + }; }; &ext { clock-frequency = <48000000>; }; +&cgu { + /* + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher + * precision. + */ + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; + assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; + assigned-clock-rates = <48000000>; +}; + &mmc0 { status = "okay"; @@ -396,6 +421,16 @@ status = "okay"; }; +&otg_phy { + status = "okay"; + + vcc-supply = <&otg_power>; +}; + +&otg { + status = "okay"; +}; + &pinctrl { pins_uart0: uart0 { function = "uart0"; @@ -489,7 +524,11 @@ }; &tcu { - /* 3 MHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; - assigned-clock-rates = <3000000>, <3000000>; + /* + * 750 kHz for the system timer and 3 MHz for the clocksource, + * use channel #0 for the system timer, #1 for the clocksource. + */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_OST>; + assigned-clock-rates = <750000>, <3000000>, <3000000>; }; diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts index 22a1066d637b..f98cf029efc3 100644 --- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts +++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts @@ -3,7 +3,7 @@ #include "x1000.dtsi" #include -#include +#include #include / { @@ -31,6 +31,42 @@ }; }; + ssi: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + num-chipselects = <1>; + + mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>; + + status = "okay"; + + spi-max-frequency = <50000000>; + + sc16is752: expander@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + spi-max-frequency = <4000000>; + + clocks = <&exclk_sc16is752>; + + interrupt-parent = <&gpc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + exclk_sc16is752: sc16is752 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; + }; + wlan_pwrseq: msc1-pwrseq { compatible = "mmc-pwrseq-simple"; @@ -43,13 +79,19 @@ clock-frequency = <24000000>; }; -&tcu { +&cgu { + /* + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher + * precision. + */ + assigned-clocks = <&cgu X1000_CLK_RTC>; + assigned-clock-parents = <&cgu X1000_CLK_RTCLK>; +}; + +&ost { /* 1500 kHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>; + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; assigned-clock-rates = <1500000>, <1500000>; - - /* Use channel #0 for the system timer channel #2 for the clocksource */ - ingenic,pwm-channels-mask = <0xfa>; }; &uart2 { @@ -135,6 +177,14 @@ }; }; +&otg_phy { + status = "okay"; +}; + +&otg { + status = "okay"; +}; + &pinctrl { pins_uart2: uart2 { function = "uart2"; diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts index 640f96c00d63..cfcb40edb7d9 100644 --- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts +++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts @@ -3,7 +3,7 @@ #include "x1830.dtsi" #include -#include +#include #include / { @@ -31,6 +31,42 @@ }; }; + ssi0: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + num-chipselects = <1>; + + mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>; + + status = "okay"; + + spi-max-frequency = <50000000>; + + sc16is752: expander@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + spi-max-frequency = <4000000>; + + clocks = <&exclk_sc16is752>; + + interrupt-parent = <&gpb>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + + exclk_sc16is752: sc16is752 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + }; + }; + wlan_pwrseq: msc1-pwrseq { compatible = "mmc-pwrseq-simple"; @@ -43,13 +79,19 @@ clock-frequency = <24000000>; }; -&tcu { +&cgu { + /* + * Use the 32.768 kHz oscillator as the parent of the RTC for a higher + * precision. + */ + assigned-clocks = <&cgu X1830_CLK_RTC>; + assigned-clock-parents = <&cgu X1830_CLK_RTCLK>; +}; + +&ost { /* 1500 kHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>; + assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>; assigned-clock-rates = <1500000>, <1500000>; - - /* Use channel #0 for the system timer channel #2 for the clocksource */ - ingenic,pwm-channels-mask = <0xfa>; }; &uart1 { @@ -73,6 +115,10 @@ }; }; +&dtrng { + status = "okay"; +}; + &msc0 { status = "okay"; @@ -135,6 +181,14 @@ }; }; +&otg_phy { + status = "okay"; +}; + +&otg { + status = "okay"; +}; + &pinctrl { pins_uart1: uart1 { function = "uart1"; diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index dfb5a7e1bb21..8d01feef7ff5 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -61,13 +61,34 @@ }; cgu: jz4780-cgu@10000000 { - compatible = "ingenic,jz4780-cgu"; + compatible = "ingenic,jz4780-cgu", "simple-mfd"; reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; + + #clock-cells = <1>; clocks = <&ext>, <&rtc>; clock-names = "ext", "rtc"; - #clock-cells = <1>; + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4780-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu JZ4780_CLK_OTG1>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + rng: rng@d8 { + compatible = "ingenic,jz4780-rng"; + reg = <0xd8 0x8>; + + status = "disabled"; + }; }; tcu: timer@10002000 { @@ -494,4 +515,24 @@ status = "disabled"; }; + + otg: usb@13500000 { + compatible = "ingenic,jz4780-otg", "snps,dwc2"; + reg = <0x13500000 0x40000>; + + interrupt-parent = <&intc>; + interrupts = <21>; + + clocks = <&cgu JZ4780_CLK_UHC>; + clock-names = "otg"; + + phys = <&otg_phy>; + phy-names = "usb2-phy"; + + g-rx-fifo-size = <768>; + g-np-tx-fifo-size = <256>; + g-tx-fifo-size = <256 256 256 256 256 256 256 512>; + + status = "disabled"; + }; }; diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi index 1f1f896dd1f7..aac9dedaf334 100644 --- a/arch/mips/boot/dts/ingenic/x1000.dtsi +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi @@ -52,13 +52,47 @@ }; cgu: x1000-cgu@10000000 { - compatible = "ingenic,x1000-cgu"; + compatible = "ingenic,x1000-cgu", "simple-mfd"; reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; #clock-cells = <1>; clocks = <&exclk>, <&rtclk>; clock-names = "ext", "rtc"; + + otg_phy: usb-phy@3c { + compatible = "ingenic,x1000-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu X1000_CLK_OTGPHY>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + rng: rng@d8 { + compatible = "ingenic,x1000-rng"; + reg = <0xd8 0x8>; + + status = "disabled"; + }; + }; + + ost: timer@12000000 { + compatible = "ingenic,x1000-ost"; + reg = <0x12000000 0x3c>; + + #clock-cells = <1>; + + clocks = <&cgu X1000_CLK_OST>; + clock-names = "ost"; + + interrupt-parent = <&cpuintc>; + interrupts = <3>; }; tcu: timer@10002000 { @@ -323,4 +357,24 @@ status = "disabled"; }; }; + + otg: usb@13500000 { + compatible = "ingenic,x1000-otg", "snps,dwc2"; + reg = <0x13500000 0x40000>; + + interrupt-parent = <&intc>; + interrupts = <21>; + + clocks = <&cgu X1000_CLK_OTG>; + clock-names = "otg"; + + phys = <&otg_phy>; + phy-names = "usb2-phy"; + + g-rx-fifo-size = <768>; + g-np-tx-fifo-size = <256>; + g-tx-fifo-size = <256 256 256 256 256 256 256 512>; + + status = "disabled"; + }; }; diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi index b05dac3ae308..b21c93057356 100644 --- a/arch/mips/boot/dts/ingenic/x1830.dtsi +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi @@ -52,13 +52,40 @@ }; cgu: x1830-cgu@10000000 { - compatible = "ingenic,x1830-cgu"; + compatible = "ingenic,x1830-cgu", "simple-mfd"; reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; #clock-cells = <1>; clocks = <&exclk>, <&rtclk>; clock-names = "ext", "rtc"; + + otg_phy: usb-phy@3c { + compatible = "ingenic,x1830-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu X1830_CLK_OTGPHY>; + + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + ost: timer@12000000 { + compatible = "ingenic,x1830-ost", "ingenic,x1000-ost"; + reg = <0x12000000 0x3c>; + + #clock-cells = <1>; + + clocks = <&cgu X1830_CLK_OST>; + clock-names = "ost"; + + interrupt-parent = <&cpuintc>; + interrupts = <4>; }; tcu: timer@10002000 { @@ -236,6 +263,15 @@ status = "disabled"; }; + dtrng: trng@10072000 { + compatible = "ingenic,x1830-dtrng"; + reg = <0x10072000 0xc>; + + clocks = <&cgu X1830_CLK_DTRNG>; + + status = "disabled"; + }; + pdma: dma-controller@13420000 { compatible = "ingenic,x1830-dma"; reg = <0x13420000 0x400 @@ -311,4 +347,24 @@ status = "disabled"; }; }; + + otg: usb@13500000 { + compatible = "ingenic,x1830-otg", "snps,dwc2"; + reg = <0x13500000 0x40000>; + + interrupt-parent = <&intc>; + interrupts = <21>; + + clocks = <&cgu X1830_CLK_OTG>; + clock-names = "otg"; + + phys = <&otg_phy>; + phy-names = "usb2-phy"; + + g-rx-fifo-size = <768>; + g-np-tx-fifo-size = <256>; + g-tx-fifo-size = <256 256 256 256 256 256 256 512>; + + status = "disabled"; + }; }; -- cgit v1.2.3-70-g09d2 From e5dab78f1f3c8d6cd1f0717c27580ddab5176bc4 Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Tue, 17 Nov 2020 01:55:08 +0800 Subject: MIPS: Ingenic: Refresh defconfig for Ingenic SoCs based boards. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Refresh defconfig of CI20 to support OTG and RNG. 2.Refresh defconfig of CU1000-Neo to support OTG/RNG/OST/SC16IS752. 3.Refresh defconfig of CU1830-Neo to support OTG/DTRNG/OST/SC16IS752. Tested-by: 周正 (Zhou Zheng) Tested by: H. Nikolaus Schaller # CI20/jz4780 Signed-off-by: 周琰杰 (Zhou Yanjie) Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/ci20_defconfig | 15 +++++++++++++-- arch/mips/configs/cu1000-neo_defconfig | 28 +++++++++++++++++++++++----- arch/mips/configs/cu1830-neo_defconfig | 32 +++++++++++++++++++++++++------- 3 files changed, 61 insertions(+), 14 deletions(-) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index 052c5ad0f2b1..ab7ebb066834 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -49,6 +49,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MTD_NAND_JZ4780=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_ARC is not set # CONFIG_NET_VENDOR_BROADCOM is not set @@ -77,7 +79,6 @@ CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_INGENIC=y CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_JZ4780=y CONFIG_SPI=y @@ -99,7 +100,12 @@ CONFIG_IR_GPIO_TX=m CONFIG_MEDIA_SUPPORT=m # CONFIG_VGA_CONSOLE is not set # CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC2=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_JZ4740=y CONFIG_NEW_LEDS=y @@ -131,8 +137,13 @@ CONFIG_MEMORY=y CONFIG_JZ4780_NEMC=y CONFIG_PWM=y CONFIG_PWM_JZ4740=m +CONFIG_JZ4780_EFUSE=y +CONFIG_JZ4770_PHY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set +CONFIG_AUTOFS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y CONFIG_PROC_KCORE=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y diff --git a/arch/mips/configs/cu1000-neo_defconfig b/arch/mips/configs/cu1000-neo_defconfig index 55d0690a3ffe..9d75f5b77d5d 100644 --- a/arch/mips/configs/cu1000-neo_defconfig +++ b/arch/mips/configs/cu1000-neo_defconfig @@ -25,6 +25,7 @@ CONFIG_HIGHMEM=y CONFIG_HZ_100=y # CONFIG_SECCOMP is not set # CONFIG_SUSPEND is not set +CONFIG_MODULES=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPACTION is not set CONFIG_CMA=y @@ -32,15 +33,17 @@ CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y -CONFIG_CFG80211=y +CONFIG_CFG80211=m CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_NETDEVICES=y CONFIG_STMMAC_ETH=y CONFIG_SMSC_PHY=y -CONFIG_BRCMFMAC=y +CONFIG_BRCMFMAC=m # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set @@ -52,16 +55,25 @@ CONFIG_SERIAL_8250_NR_UARTS=3 CONFIG_SERIAL_8250_RUNTIME_UARTS=3 CONFIG_SERIAL_8250_INGENIC=y CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_SC16IS7XX=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_I2C=y CONFIG_I2C_JZ4780=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_ADS7828=y +CONFIG_SENSORS_ADS7828=m CONFIG_WATCHDOG=y CONFIG_JZ4740_WDT=y # CONFIG_VGA_CONSOLE is not set # CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC2=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_JZ4740=y CONFIG_NEW_LEDS=y @@ -72,16 +84,22 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_JZ4740=y CONFIG_DMADEVICES=y CONFIG_DMA_JZ4780=y +# CONFIG_INGENIC_TIMER is not set +CONFIG_INGENIC_SYSOST=y # CONFIG_IOMMU_SUPPORT is not set +CONFIG_JZ4770_PHY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_AUTOFS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y CONFIG_PROC_KCORE=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y CONFIG_NFS_FS=y CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=y CONFIG_NLS_ASCII=y diff --git a/arch/mips/configs/cu1830-neo_defconfig b/arch/mips/configs/cu1830-neo_defconfig index e7064851a47a..29decd0003c6 100644 --- a/arch/mips/configs/cu1830-neo_defconfig +++ b/arch/mips/configs/cu1830-neo_defconfig @@ -25,6 +25,7 @@ CONFIG_HIGHMEM=y CONFIG_HZ_100=y # CONFIG_SECCOMP is not set # CONFIG_SUSPEND is not set +CONFIG_MODULES=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_COMPACTION is not set CONFIG_CMA=y @@ -32,18 +33,20 @@ CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_INET=y -CONFIG_CFG80211=y +CONFIG_CFG80211=m CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y # CONFIG_ALLOW_DEV_COREDUMP is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_BLK_DEV_DM=y +CONFIG_BLK_DEV_MD=m +CONFIG_BLK_DEV_DM=m CONFIG_NETDEVICES=y CONFIG_STMMAC_ETH=y CONFIG_ICPLUS_PHY=y -CONFIG_BRCMFMAC=y +CONFIG_BRCMFMAC=m # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_SERIO is not set @@ -55,16 +58,25 @@ CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 CONFIG_SERIAL_8250_INGENIC=y CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_SC16IS7XX=y +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_I2C=y CONFIG_I2C_JZ4780=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_ADS7828=y +CONFIG_SENSORS_ADS7828=m CONFIG_WATCHDOG=y CONFIG_JZ4740_WDT=y # CONFIG_VGA_CONSOLE is not set # CONFIG_HID is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC2=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CH341=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_JZ4740=y CONFIG_NEW_LEDS=y @@ -75,16 +87,22 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_JZ4740=y CONFIG_DMADEVICES=y CONFIG_DMA_JZ4780=y +# CONFIG_INGENIC_TIMER is not set +CONFIG_INGENIC_SYSOST=y # CONFIG_IOMMU_SUPPORT is not set +CONFIG_JZ4770_PHY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_AUTOFS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y CONFIG_PROC_KCORE=y # CONFIG_PROC_PAGE_MONITOR is not set CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=y CONFIG_NFS_FS=y CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=y CONFIG_NLS_ASCII=y -- cgit v1.2.3-70-g09d2 From 29906e1aac11bf9907e26608216dc7970e73a70e Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:33 +0200 Subject: mips: bmips: select ARCH_HAS_RESET_CONTROLLER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows to add reset controllers support. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ddaff19a9580..0f638bfaf63a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -249,6 +249,7 @@ config ATH79 config BMIPS_GENERIC bool "Broadcom Generic BMIPS kernel" + select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL select ARCH_HAS_PHYS_TO_DMA select BOOT_RAW -- cgit v1.2.3-70-g09d2 From 10c1e714a68b45b124157aa02d80abe244a2a61a Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:34 +0200 Subject: dt-bindings: reset: add BCM6345 reset controller bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device tree binding documentation for BCM6345 reset controller. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- .../bindings/reset/brcm,bcm6345-reset.yaml | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml new file mode 100644 index 000000000000..560cf6522cb8 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: BCM6345 reset controller + +description: This document describes the BCM6345 reset controller. + +maintainers: + - Álvaro Fernández Rojas + +properties: + compatible: + const: brcm,bcm6345-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; -- cgit v1.2.3-70-g09d2 From aac025437f14c1647dc6054b95daeebed34f6971 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:35 +0200 Subject: reset: add BCM6345 reset controller driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for resetting blocks through the Linux reset controller subsystem for BCM63xx SoCs. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Florian Fainelli Reviewed-by: Philipp Zabel Signed-off-by: Thomas Bogendoerfer --- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-bcm6345.c | 135 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-bcm6345.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 07d162b179fc..dceec715e745 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -35,6 +35,13 @@ config RESET_AXS10X help This enables the reset controller driver for AXS10x. +config RESET_BCM6345 + bool "BCM6345 Reset Controller" + depends on BMIPS_GENERIC || COMPILE_TEST + default BMIPS_GENERIC + help + This enables the reset controller driver for BCM6345 SoCs. + config RESET_BERLIN bool "Berlin Reset Driver" if COMPILE_TEST default ARCH_BERLIN diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 16947610cc3b..1054123fd187 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o +obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c new file mode 100644 index 000000000000..737e4e81f6b7 --- /dev/null +++ b/drivers/reset/reset-bcm6345.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * BCM6345 Reset Controller Driver + * + * Copyright (C) 2020 Álvaro Fernández Rojas + */ + +#include +#include +#include +#include +#include +#include + +#define BCM6345_RESET_NUM 32 +#define BCM6345_RESET_SLEEP_MIN_US 10000 +#define BCM6345_RESET_SLEEP_MAX_US 20000 + +struct bcm6345_reset { + struct reset_controller_dev rcdev; + void __iomem *base; + spinlock_t lock; +}; + +static inline struct bcm6345_reset * +to_bcm6345_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct bcm6345_reset, rcdev); +} + +static int bcm6345_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); + unsigned long flags; + uint32_t val; + + spin_lock_irqsave(&bcm6345_reset->lock, flags); + val = __raw_readl(bcm6345_reset->base); + if (assert) + val &= ~BIT(id); + else + val |= BIT(id); + __raw_writel(val, bcm6345_reset->base); + spin_unlock_irqrestore(&bcm6345_reset->lock, flags); + + return 0; +} + +static int bcm6345_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return bcm6345_reset_update(rcdev, id, true); +} + +static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return bcm6345_reset_update(rcdev, id, false); +} + +static int bcm6345_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + bcm6345_reset_update(rcdev, id, true); + usleep_range(BCM6345_RESET_SLEEP_MIN_US, + BCM6345_RESET_SLEEP_MAX_US); + + bcm6345_reset_update(rcdev, id, false); + /* + * Ensure component is taken out reset state by sleeping also after + * deasserting the reset. Otherwise, the component may not be ready + * for operation. + */ + usleep_range(BCM6345_RESET_SLEEP_MIN_US, + BCM6345_RESET_SLEEP_MAX_US); + + return 0; +} + +static int bcm6345_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); + + return !(__raw_readl(bcm6345_reset->base) & BIT(id)); +} + +static struct reset_control_ops bcm6345_reset_ops = { + .assert = bcm6345_reset_assert, + .deassert = bcm6345_reset_deassert, + .reset = bcm6345_reset_reset, + .status = bcm6345_reset_status, +}; + +static int bcm6345_reset_probe(struct platform_device *pdev) +{ + struct bcm6345_reset *bcm6345_reset; + + bcm6345_reset = devm_kzalloc(&pdev->dev, + sizeof(*bcm6345_reset), GFP_KERNEL); + if (!bcm6345_reset) + return -ENOMEM; + + platform_set_drvdata(pdev, bcm6345_reset); + + bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bcm6345_reset->base)) + return PTR_ERR(bcm6345_reset->base); + + spin_lock_init(&bcm6345_reset->lock); + bcm6345_reset->rcdev.ops = &bcm6345_reset_ops; + bcm6345_reset->rcdev.owner = THIS_MODULE; + bcm6345_reset->rcdev.of_node = pdev->dev.of_node; + bcm6345_reset->rcdev.of_reset_n_cells = 1; + bcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM; + + return devm_reset_controller_register(&pdev->dev, + &bcm6345_reset->rcdev); +} + +static const struct of_device_id bcm6345_reset_of_match[] = { + { .compatible = "brcm,bcm6345-reset" }, + { /* sentinel */ }, +}; + +static struct platform_driver bcm6345_reset_driver = { + .probe = bcm6345_reset_probe, + .driver = { + .name = "bcm6345-reset", + .of_match_table = bcm6345_reset_of_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(bcm6345_reset_driver); -- cgit v1.2.3-70-g09d2 From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:36 +0200 Subject: mips: bmips: dts: add BCM6328 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6328 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6328-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi index 1f9edd710392..9dc558763c46 100644 --- a/arch/mips/boot/dts/brcm/bcm6328.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi @@ -57,6 +57,12 @@ #clock-cells = <1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h new file mode 100644 index 000000000000..0f3df87d47af --- /dev/null +++ b/include/dt-bindings/reset/bcm6328-reset.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6328_H +#define __DT_BINDINGS_RESET_BCM6328_H + +#define BCM6328_RST_SPI 0 +#define BCM6328_RST_EPHY 1 +#define BCM6328_RST_SAR 2 +#define BCM6328_RST_ENETSW 3 +#define BCM6328_RST_USBS 4 +#define BCM6328_RST_USBH 5 +#define BCM6328_RST_PCM 6 +#define BCM6328_RST_PCIE_CORE 7 +#define BCM6328_RST_PCIE 8 +#define BCM6328_RST_PCIE_EXT 9 +#define BCM6328_RST_PCIE_HARD 10 + +#endif /* __DT_BINDINGS_RESET_BCM6328_H */ -- cgit v1.2.3-70-g09d2 From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:37 +0200 Subject: mips: bmips: dts: add BCM6358 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6358 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6358-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm6358.dtsi b/arch/mips/boot/dts/brcm/bcm6358.dtsi index f21176cac038..9d93e7f5e6fc 100644 --- a/arch/mips/boot/dts/brcm/bcm6358.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi @@ -82,6 +82,12 @@ interrupts = <2>, <3>; }; + periph_rst: reset-controller@fffe0034 { + compatible = "brcm,bcm6345-reset"; + reg = <0xfffe0034 0x4>; + #reset-cells = <1>; + }; + leds0: led-controller@fffe00d0 { #address-cells = <1>; #size-cells = <0>; diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h new file mode 100644 index 000000000000..bda62ef84f5a --- /dev/null +++ b/include/dt-bindings/reset/bcm6358-reset.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6358_H +#define __DT_BINDINGS_RESET_BCM6358_H + +#define BCM6358_RST_SPI 0 +#define BCM6358_RST_ENET 2 +#define BCM6358_RST_MPI 3 +#define BCM6358_RST_EPHY 6 +#define BCM6358_RST_SAR 7 +#define BCM6358_RST_USBH 12 +#define BCM6358_RST_PCM 13 +#define BCM6358_RST_ADSL 14 + +#endif /* __DT_BINDINGS_RESET_BCM6358_H */ -- cgit v1.2.3-70-g09d2 From 226383600be58dcf2e070e4ac8a371640024fe54 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:38 +0200 Subject: mips: bmips: dts: add BCM6362 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6362 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6362.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6362-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm6362.dtsi b/arch/mips/boot/dts/brcm/bcm6362.dtsi index c98f9111e3c8..eb10341b75ba 100644 --- a/arch/mips/boot/dts/brcm/bcm6362.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi @@ -70,6 +70,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 000000000000..7ebb0546e0ab --- /dev/null +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */ -- cgit v1.2.3-70-g09d2 From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:39 +0200 Subject: mips: bmips: dts: add BCM6368 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6368-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi index 449c167dd892..52c19f40b9cc 100644 --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi @@ -70,6 +70,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h new file mode 100644 index 000000000000..c81d8eb6d173 --- /dev/null +++ b/include/dt-bindings/reset/bcm6368-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6368_H +#define __DT_BINDINGS_RESET_BCM6368_H + +#define BCM6368_RST_SPI 0 +#define BCM6368_RST_MPI 3 +#define BCM6368_RST_IPSEC 4 +#define BCM6368_RST_EPHY 6 +#define BCM6368_RST_SAR 7 +#define BCM6368_RST_SWITCH 10 +#define BCM6368_RST_USBD 11 +#define BCM6368_RST_USBH 12 +#define BCM6368_RST_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM6368_H */ -- cgit v1.2.3-70-g09d2 From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:40 +0200 Subject: mips: bmips: dts: add BCM63268 reset controller support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM63268 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 ++++++ include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset/bcm63268-reset.h diff --git a/arch/mips/boot/dts/brcm/bcm63268.dtsi b/arch/mips/boot/dts/brcm/bcm63268.dtsi index 5acb49b61867..e0021ff9f144 100644 --- a/arch/mips/boot/dts/brcm/bcm63268.dtsi +++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi @@ -70,6 +70,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x20>, diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h new file mode 100644 index 000000000000..6a6403a4c2d5 --- /dev/null +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM63268_H +#define __DT_BINDINGS_RESET_BCM63268_H + +#define BCM63268_RST_SPI 0 +#define BCM63268_RST_IPSEC 1 +#define BCM63268_RST_EPHY 2 +#define BCM63268_RST_SAR 3 +#define BCM63268_RST_ENETSW 4 +#define BCM63268_RST_USBS 5 +#define BCM63268_RST_USBH 6 +#define BCM63268_RST_PCM 7 +#define BCM63268_RST_PCIE_CORE 8 +#define BCM63268_RST_PCIE 9 +#define BCM63268_RST_PCIE_EXT 10 +#define BCM63268_RST_WLAN_SHIM 11 +#define BCM63268_RST_DDR_PHY 12 +#define BCM63268_RST_FAP0 13 +#define BCM63268_RST_WLAN_UBUS 14 +#define BCM63268_RST_DECT 15 +#define BCM63268_RST_FAP1 16 +#define BCM63268_RST_PCIE_HARD 17 +#define BCM63268_RST_GPHY 18 + +#endif /* __DT_BINDINGS_RESET_BCM63268_H */ -- cgit v1.2.3-70-g09d2 From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001 From: Álvaro Fernández Rojas Date: Wed, 17 Jun 2020 12:50:41 +0200 Subject: mips: bmips: add BCM6318 reset controller definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM6318 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/dt-bindings/reset/bcm6318-reset.h diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h new file mode 100644 index 000000000000..f882662505ea --- /dev/null +++ b/include/dt-bindings/reset/bcm6318-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __DT_BINDINGS_RESET_BCM6318_H +#define __DT_BINDINGS_RESET_BCM6318_H + +#define BCM6318_RST_SPI 0 +#define BCM6318_RST_EPHY 1 +#define BCM6318_RST_SAR 2 +#define BCM6318_RST_ENETSW 3 +#define BCM6318_RST_USBD 4 +#define BCM6318_RST_USBH 5 +#define BCM6318_RST_PCIE_CORE 6 +#define BCM6318_RST_PCIE 7 +#define BCM6318_RST_PCIE_EXT 8 +#define BCM6318_RST_PCIE_HARD 9 +#define BCM6318_RST_ADSL 10 +#define BCM6318_RST_PHYMIPS 11 +#define BCM6318_RST_HOSTMIPS 12 + +#endif /* __DT_BINDINGS_RESET_BCM6318_H */ -- cgit v1.2.3-70-g09d2 From 724d554a117a0552c2c982f0b5cd1d685274d678 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 13 Nov 2020 12:09:49 +0100 Subject: MIPS: vdso: Use vma page protection for remapping MIPS protection bits are setup during runtime so using defines like PAGE_READONLY ignores these runtime changes. To fix this we simply use the page protection of the setup vma. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vdso.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c index 242dc5e83847..7d0b91ad2581 100644 --- a/arch/mips/kernel/vdso.c +++ b/arch/mips/kernel/vdso.c @@ -161,7 +161,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) gic_pfn = virt_to_phys(mips_gic_base + MIPS_GIC_USER_OFS) >> PAGE_SHIFT; ret = io_remap_pfn_range(vma, base, gic_pfn, gic_size, - pgprot_noncached(PAGE_READONLY)); + pgprot_noncached(vma->vm_page_prot)); if (ret) goto out; } @@ -169,7 +169,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) /* Map data page. */ ret = remap_pfn_range(vma, data_addr, virt_to_phys(vdso_data) >> PAGE_SHIFT, - PAGE_SIZE, PAGE_READONLY); + PAGE_SIZE, vma->vm_page_prot); if (ret) goto out; -- cgit v1.2.3-70-g09d2 From 411406a8c758d9ad6f908fab3a6cf1d3d89e1d08 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 13 Nov 2020 12:09:50 +0100 Subject: MIPS: kvm: Use vm_get_page_prot to get protection bits MIPS protection bits are setup during runtime so using defines like PAGE_SHARED ignores this runtime changes. Using vm_get_page_prot to get correct page protection fixes this. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kvm/mmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/kvm/mmu.c b/arch/mips/kvm/mmu.c index 28c366d307e7..3dabeda82458 100644 --- a/arch/mips/kvm/mmu.c +++ b/arch/mips/kvm/mmu.c @@ -1074,6 +1074,7 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, { kvm_pfn_t pfn; pte_t *ptep; + pgprot_t prot; ptep = kvm_trap_emul_pte_for_gva(vcpu, badvaddr); if (!ptep) { @@ -1083,7 +1084,8 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, pfn = PFN_DOWN(virt_to_phys(vcpu->arch.kseg0_commpage)); /* Also set valid and dirty, so refill handler doesn't have to */ - *ptep = pte_mkyoung(pte_mkdirty(pfn_pte(pfn, PAGE_SHARED))); + prot = vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED); + *ptep = pte_mkyoung(pte_mkdirty(pfn_pte(pfn, prot))); /* Invalidate this entry in the TLB, guest kernel ASID only */ kvm_mips_host_tlb_inv(vcpu, badvaddr, false, true); -- cgit v1.2.3-70-g09d2 From ed2adb74217a4054a92e0a0746e31ec6f5e466c8 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 13 Nov 2020 12:09:51 +0100 Subject: MIPS: mm: shorten lines by using macro Introduce helper macro to make lines shorter. Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/cache.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 3e81ba000096..f66a8bfc030e 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -155,26 +155,28 @@ void __update_cache(unsigned long address, pte_t pte) unsigned long _page_cachable_default; EXPORT_SYMBOL(_page_cachable_default); +#define PM(p) __pgprot(_page_cachable_default | (p)) + static inline void setup_protection_map(void) { if (cpu_has_rixi) { - protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - - protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); - protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); - protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); + protection_map[0] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[1] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[2] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[3] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[4] = PM(_PAGE_PRESENT); + protection_map[5] = PM(_PAGE_PRESENT); + protection_map[6] = PM(_PAGE_PRESENT); + protection_map[7] = PM(_PAGE_PRESENT); + + protection_map[8] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[9] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[10] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); + protection_map[11] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); + protection_map[12] = PM(_PAGE_PRESENT); + protection_map[13] = PM(_PAGE_PRESENT); + protection_map[14] = PM(_PAGE_PRESENT | _PAGE_WRITE); + protection_map[15] = PM(_PAGE_PRESENT | _PAGE_WRITE); } else { protection_map[0] = PAGE_NONE; @@ -196,6 +198,8 @@ static inline void setup_protection_map(void) } } +#undef PM + void cpu_cache_init(void) { if (cpu_has_3k_cache) { -- cgit v1.2.3-70-g09d2 From 0df162e1377a585ced8adb932f7d6e4164e91ccf Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 13 Nov 2020 12:09:52 +0100 Subject: MIPS: mm: Clean up setup of protection map Protection map difference between RIXI and non RIXI cpus is _PAGE_NO_EXEC and _PAGE_NO_READ usage. Both already take care of cpu_has_rixi while setting up the page bits. So we just need one setup of protection map and can drop the now unused (and broken for RIXI) PAGE_* defines. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pgtable.h | 8 ------ arch/mips/mm/cache.c | 55 ++++++++++++++--------------------------- 2 files changed, 18 insertions(+), 45 deletions(-) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index e5ef0fdd4838..158ba3aa3bf1 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -25,14 +25,6 @@ struct mm_struct; struct vm_area_struct; -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \ - _page_cachable_default) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ - _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \ - _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | \ - _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) #define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index f66a8bfc030e..36bcf4e955e8 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -159,43 +159,24 @@ EXPORT_SYMBOL(_page_cachable_default); static inline void setup_protection_map(void) { - if (cpu_has_rixi) { - protection_map[0] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[1] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[2] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[3] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[4] = PM(_PAGE_PRESENT); - protection_map[5] = PM(_PAGE_PRESENT); - protection_map[6] = PM(_PAGE_PRESENT); - protection_map[7] = PM(_PAGE_PRESENT); - - protection_map[8] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[9] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[10] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[11] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); - protection_map[12] = PM(_PAGE_PRESENT); - protection_map[13] = PM(_PAGE_PRESENT); - protection_map[14] = PM(_PAGE_PRESENT | _PAGE_WRITE); - protection_map[15] = PM(_PAGE_PRESENT | _PAGE_WRITE); - - } else { - protection_map[0] = PAGE_NONE; - protection_map[1] = PAGE_READONLY; - protection_map[2] = PAGE_COPY; - protection_map[3] = PAGE_COPY; - protection_map[4] = PAGE_READONLY; - protection_map[5] = PAGE_READONLY; - protection_map[6] = PAGE_COPY; - protection_map[7] = PAGE_COPY; - protection_map[8] = PAGE_NONE; - protection_map[9] = PAGE_READONLY; - protection_map[10] = PAGE_SHARED; - protection_map[11] = PAGE_SHARED; - protection_map[12] = PAGE_READONLY; - protection_map[13] = PAGE_READONLY; - protection_map[14] = PAGE_SHARED; - protection_map[15] = PAGE_SHARED; - } + protection_map[0] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[1] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[2] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[3] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[4] = PM(_PAGE_PRESENT); + protection_map[5] = PM(_PAGE_PRESENT); + protection_map[6] = PM(_PAGE_PRESENT); + protection_map[7] = PM(_PAGE_PRESENT); + + protection_map[8] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[9] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[10] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | + _PAGE_NO_READ); + protection_map[11] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); + protection_map[12] = PM(_PAGE_PRESENT); + protection_map[13] = PM(_PAGE_PRESENT); + protection_map[14] = PM(_PAGE_PRESENT | _PAGE_WRITE); + protection_map[15] = PM(_PAGE_PRESENT | _PAGE_WRITE); } #undef PM -- cgit v1.2.3-70-g09d2 From 6ce91ba8589ab08143939f9d6a58993e36773e75 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 19 Nov 2020 15:53:00 +0800 Subject: MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init() Since commit 02cf2119684e ("Cleanup the mess in cpu_cache_init."), cpu_has_6k_cache and cpu_has_8k_cache have no user, r6k_cache_init() and r8k_cache_init() are not defined for over 15 years, just remove them. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cpu-features.h | 2 -- arch/mips/mm/cache.c | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f2e216eef7da..336e02b3b3ce 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -115,8 +115,6 @@ #ifndef cpu_has_3k_cache #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) #endif -#define cpu_has_6k_cache 0 -#define cpu_has_8k_cache 0 #ifndef cpu_has_4k_cache #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) #endif diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 36bcf4e955e8..23b16bfd97b2 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -188,21 +188,11 @@ void cpu_cache_init(void) r3k_cache_init(); } - if (cpu_has_6k_cache) { - extern void __weak r6k_cache_init(void); - - r6k_cache_init(); - } if (cpu_has_4k_cache) { extern void __weak r4k_cache_init(void); r4k_cache_init(); } - if (cpu_has_8k_cache) { - extern void __weak r8k_cache_init(void); - - r8k_cache_init(); - } if (cpu_has_tx39_cache) { extern void __weak tx39_cache_init(void); -- cgit v1.2.3-70-g09d2 From 91c7a7e0656de077911332f2acdb60f6fd4a134f Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 19 Nov 2020 15:53:01 +0800 Subject: MIPS: Loongson64: Fix wrong scache size when execute lscpu As the user manual and code comment said, Loongson-3 has 4-scache banks, while Loongson-2K has only 2 banks, so we should multiply the number of scache banks, this multiply operation should be done by c->scache.sets instead of scache_size, otherwise we will get the wrong scache size when execute lscpu. For example, the scache size should be 8192K instead of 2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related info in the following boot message: [loongson@linux ~]$ dmesg | grep "Unified secondary cache" [ 0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes. [ 4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes. E.g. without this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 2048K 2048K 2048K 2048K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 2048K With this patch: [loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size 8192K 8192K 8192K 8192K [loongson@linux ~]$ lscpu | grep "L2 cache" L2 cache: 8192K Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-r4k.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 9cede7ce37e6..99521764c75b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1623,15 +1623,13 @@ static void __init loongson3_sc_init(void) c->scache.sets = 64 << ((config2 >> 8) & 15); c->scache.ways = 1 + (config2 & 15); - scache_size = c->scache.sets * - c->scache.ways * - c->scache.linesz; - /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) - scache_size *= 2; + c->scache.sets *= 2; else - scache_size *= 4; + c->scache.sets *= 4; + + scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; c->scache.waybit = 0; c->scache.waysize = scache_size / c->scache.ways; -- cgit v1.2.3-70-g09d2 From 74a2810b7c1fcd60c87a8c47f95660628e00e97c Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Wed, 25 Nov 2020 18:07:18 +0800 Subject: MIPS: KASLR: Correct valid bits in apply_r_mips_26_rel() Apply_r_mips_26_rel() relocates instructions like j, jal and etc. These instructions consist of 6bits function field and 26bits address field. The value of target_addr as follows, ================================================================= | high 4bits | low 28bits | ================================================================= |the high 4bits of this PC | the low 26bits of instructions << 2| ================================================================= Thus, loc_orig and log_new both need high 4bits rather than high 6bits. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/relocate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 3d80a51256de..8561c7ac94dc 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -95,7 +95,7 @@ static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset) /* Original target address */ target_addr <<= 2; - target_addr += (unsigned long)loc_orig & ~0x03ffffff; + target_addr += (unsigned long)loc_orig & 0xf0000000; /* Get the new target address */ target_addr += offset; @@ -105,7 +105,7 @@ static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset) return -ENOEXEC; } - target_addr -= (unsigned long)loc_new & ~0x03ffffff; + target_addr -= (unsigned long)loc_new & 0xf0000000; target_addr >>= 2; *loc_new = (*loc_new & ~0x03ffffff) | (target_addr & 0x03ffffff); -- cgit v1.2.3-70-g09d2 From a307a4ce9ecd2e23c71318201330d9d648b3f818 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Wed, 25 Nov 2020 18:07:46 +0800 Subject: MIPS: Loongson64: Add KASLR support Provide a weak plat_get_fdt() in relocate.c in case some platform enable USE_OF while plat_get_fdt() is useless. 1MB RELOCATION_TABLE_SIZE is small for Loongson64 because too many instructions should be relocated. 2MB is enough in present. Add KASLR support for Loongson64. KASLR(kernel address space layout randomization) To enable KASLR on Loongson64: First, make loongson3_defconfig. Then, enable CONFIG_RELOCATABLE and CONFIG_RANDOMIZE_BASE. Finally, compile the kernel. To test KASLR on Loongson64: Start machine with KASLR kernel. The first time: # cat /proc/iomem 00200000-0effffff : System RAM 02f30000-03895e9f : Kernel code 03895ea0-03bc7fff : Kernel data 03e30000-04f43f7f : Kernel bss The second time: # cat /proc/iomem 00200000-0effffff : System RAM 022f0000-02c55e9f : Kernel code 02c55ea0-02f87fff : Kernel data 031f0000-04303f7f : Kernel bss We see that code, data and bss sections become randomize. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 5 ++++- arch/mips/kernel/relocate.c | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0f638bfaf63a..44a47adb1275 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -488,6 +488,7 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_RELOCATABLE select ZONE_DMA32 select NUMA select SMP @@ -2778,7 +2779,8 @@ config RELOCATABLE depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \ CPU_MIPS32_R5 || CPU_MIPS64_R5 || \ CPU_MIPS32_R6 || CPU_MIPS64_R6 || \ - CPU_P5600 || CAVIUM_OCTEON_SOC + CPU_P5600 || CAVIUM_OCTEON_SOC || \ + CPU_LOONGSON64 help This builds a kernel image that retains relocation information so it can be loaded someplace besides the default 1MB. @@ -2789,6 +2791,7 @@ config RELOCATION_TABLE_SIZE hex "Relocation table size" depends on RELOCATABLE range 0x0 0x01000000 + default "0x00200000" if CPU_LOONGSON64 default "0x00100000" help A table of relocation data will be appended to the kernel binary diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 8561c7ac94dc..57bdd2761c78 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -294,6 +294,13 @@ static inline int __init relocation_addr_valid(void *loc_new) return 1; } +#if defined(CONFIG_USE_OF) +void __weak *plat_get_fdt(void) +{ + return NULL; +} +#endif + void *__init relocate_kernel(void) { void *loc_new; -- cgit v1.2.3-70-g09d2 From f0e82242b16826077a2775eacfe201d803bb7a22 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Fri, 20 Nov 2020 15:48:47 +0800 Subject: mips: cdmm: fix use-after-free in mips_cdmm_bus_discover kfree(dev) has been called inside put_device so anther kfree would cause a use-after-free bug/ Fixes: 8286ae03308c ("MIPS: Add CDMM bus support") Reported-by: Hulk Robot Signed-off-by: Qinglang Miao Acked-by: Serge Semin Signed-off-by: Thomas Bogendoerfer --- drivers/bus/mips_cdmm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c index 9f7ed1fcd428..626dedd110cb 100644 --- a/drivers/bus/mips_cdmm.c +++ b/drivers/bus/mips_cdmm.c @@ -559,10 +559,8 @@ static void mips_cdmm_bus_discover(struct mips_cdmm_bus *bus) dev_set_name(&dev->dev, "cdmm%u-%u", cpu, id); ++id; ret = device_register(&dev->dev); - if (ret) { + if (ret) put_device(&dev->dev); - kfree(dev); - } } } -- cgit v1.2.3-70-g09d2 From cbab54d9c2b2a73abe541790df28add14b2385bd Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Wed, 25 Nov 2020 18:11:30 +0800 Subject: MIPS: No need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable() After commit 9cce844abf07 ("MIPS: CPU#0 is not hotpluggable"), c->hotpluggable is 0 for CPU 0 and it will not generate a control file in sysfs for this CPU: [root@linux loongson]# cat /sys/devices/system/cpu/cpu0/online cat: /sys/devices/system/cpu/cpu0/online: No such file or directory [root@linux loongson]# echo 0 > /sys/devices/system/cpu/cpu0/online bash: /sys/devices/system/cpu/cpu0/online: Permission denied So no need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable(), just remove them. Signed-off-by: Tiezhu Yang Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/smp.c | 3 --- arch/mips/kernel/smp-bmips.c | 3 --- arch/mips/loongson64/smp.c | 3 --- 3 files changed, 9 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 076db9a06b5e..66ce5527da54 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -290,9 +290,6 @@ static int octeon_cpu_disable(void) { unsigned int cpu = smp_processor_id(); - if (cpu == 0) - return -EBUSY; - if (!octeon_bootloader_entry_addr) return -ENOTSUPP; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 1dbfb5aadffd..359b176b665f 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -362,9 +362,6 @@ static int bmips_cpu_disable(void) { unsigned int cpu = smp_processor_id(); - if (cpu == 0) - return -EBUSY; - pr_info("SMP: CPU%d is offline\n", cpu); set_cpu_online(cpu, false); diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index aa0cd723e61d..b8c1fc3158fd 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -544,9 +544,6 @@ static int loongson3_cpu_disable(void) unsigned long flags; unsigned int cpu = smp_processor_id(); - if (cpu == 0) - return -EBUSY; - set_cpu_online(cpu, false); calculate_cpu_foreign_map(); local_irq_save(flags); -- cgit v1.2.3-70-g09d2 From 915d8aac69d32bf4272a015bf7bf3516deeaad5e Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 27 Nov 2020 10:53:32 +0100 Subject: MIPS: mm: Remove unused is_aligned_hugepage_range Function is_aligned_hugepage_range is no longer needed. Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/hugetlbpage.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c index 77ffece9c270..b9f76f433617 100644 --- a/arch/mips/mm/hugetlbpage.c +++ b/arch/mips/mm/hugetlbpage.c @@ -58,18 +58,6 @@ pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr, return (pte_t *) pmd; } -/* - * This function checks for proper alignment of input addr and len parameters. - */ -int is_aligned_hugepage_range(unsigned long addr, unsigned long len) -{ - if (len & ~HPAGE_MASK) - return -EINVAL; - if (addr & ~HPAGE_MASK) - return -EINVAL; - return 0; -} - int pmd_huge(pmd_t pmd) { return (pmd_val(pmd) & _PAGE_HUGE) != 0; -- cgit v1.2.3-70-g09d2 From 1dac4585f585d3aa1a5af4821128ea2642700e48 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Wed, 25 Nov 2020 18:11:02 +0800 Subject: MIPS: Loongson64: Fix up reserving kernel memory range Reserve memory from &_text to &_end. Otherwise if kernel address was modified, the memory range of start_pfn to kernel_start_pfn would be reserved. Then we could not use this range. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/numa.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index 509b360e4d28..c6f0c48384f8 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -151,6 +151,9 @@ static void __init node_mem_init(unsigned int node) NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn; if (node == 0) { + /* kernel start address */ + unsigned long kernel_start_pfn = PFN_DOWN(__pa_symbol(&_text)); + /* kernel end address */ unsigned long kernel_end_pfn = PFN_UP(__pa_symbol(&_end)); @@ -158,8 +161,8 @@ static void __init node_mem_init(unsigned int node) max_low_pfn = end_pfn; /* Reserve the kernel text/data/bss */ - memblock_reserve(start_pfn << PAGE_SHIFT, - ((kernel_end_pfn - start_pfn) << PAGE_SHIFT)); + memblock_reserve(kernel_start_pfn << PAGE_SHIFT, + ((kernel_end_pfn - kernel_start_pfn) << PAGE_SHIFT)); /* Reserve 0xfe000000~0xffffffff for RS780E integrated GPU */ if (node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT)) -- cgit v1.2.3-70-g09d2 From 79109a515ac3f1009632f4a4c81597e9438a2d65 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:20 +0000 Subject: MIPS: configs: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from all MIPS configurations. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Cc: Sam Ravnborg Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/gcw0_defconfig | 1 - arch/mips/configs/gpr_defconfig | 1 - arch/mips/configs/lemote2f_defconfig | 1 - arch/mips/configs/loongson3_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/rs90_defconfig | 1 - 6 files changed, 6 deletions(-) diff --git a/arch/mips/configs/gcw0_defconfig b/arch/mips/configs/gcw0_defconfig index 7e28a4fe9d84..460683b52285 100644 --- a/arch/mips/configs/gcw0_defconfig +++ b/arch/mips/configs/gcw0_defconfig @@ -73,7 +73,6 @@ CONFIG_DRM_PANEL_NOVATEK_NT39016=y CONFIG_DRM_INGENIC=y CONFIG_DRM_ETNAVIV=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 9085f4d6c698..87e20f3391ed 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -251,7 +251,6 @@ CONFIG_SSB_DRIVER_PCICORE=y # CONFIG_VGA_ARB is not set # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_USB_HID=m CONFIG_USB_HIDDEV=y diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig index 3a9a453b1264..688c91918db2 100644 --- a/arch/mips/configs/lemote2f_defconfig +++ b/arch/mips/configs/lemote2f_defconfig @@ -145,7 +145,6 @@ CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 38a817ead8e7..9c5fadef38cb 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -286,7 +286,6 @@ CONFIG_DRM_VIRTIO_GPU=y CONFIG_FB_RADEON=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=m -CONFIG_BACKLIGHT_GENERIC=m # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 914af125a7fa..0ef2373404e5 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -450,7 +450,6 @@ CONFIG_WDT_MTX1=y # CONFIG_VGA_ARB is not set # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_SOUND=m CONFIG_SND=m diff --git a/arch/mips/configs/rs90_defconfig b/arch/mips/configs/rs90_defconfig index dfbb9fed9a42..4f540bb94628 100644 --- a/arch/mips/configs/rs90_defconfig +++ b/arch/mips/configs/rs90_defconfig @@ -97,7 +97,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=300 CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_INGENIC=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y -- cgit v1.2.3-70-g09d2 From 8b3165e54566e8bb8f4b7d4e5f12ced78ce462bb Mon Sep 17 00:00:00 2001 From: Xingxing Su Date: Thu, 3 Dec 2020 15:22:51 +0800 Subject: MIPS: Enable GCOV Enable gcov profiling of the entire kernel on mips. Required changes include disabling profiling for: * arch/kernel/boot/compressed: not linked to main kernel. Lightly tested on Loongson 3A3000 an 3A4000, seems to work as expected. without "GCOV_PROFILE := n" in compressed Makefile, build errors as follows: ... ld: arch/mips/boot/compressed/string.o:(.data+0x88): undefined reference to `__gcov_merge_add' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_I_00100_0_memcpy': string.c:(.text.startup+0x4): undefined reference to `__gcov_init' ld: arch/mips/boot/compressed/string.o: in function `_GLOBAL__sub_D_00100_1_memcpy': string.c:(.text.exit+0x0): undefined reference to `__gcov_exit' ... Signed-off-by: Youling Tang Signed-off-by: Xingxing Su Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + arch/mips/boot/compressed/Makefile | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 44a47adb1275..b99498958b5c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -9,6 +9,7 @@ config MIPS select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI) select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL + select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_SUPPORTS_UPROBES select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF if 64BIT diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index 4c3bc7e3d56d..47cd9dc7454a 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -36,6 +36,7 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ # Prevents link failures: __sanitizer_cov_trace_pc() is not linked in. KCOV_INSTRUMENT := n +GCOV_PROFILE := n # decompressor objects (linked with vmlinuz) vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o -- cgit v1.2.3-70-g09d2 From d121f125af22a16f0f679293756d28a9691fa46d Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Thu, 3 Dec 2020 13:36:48 +0100 Subject: MIPS: Don't round up kernel sections size for memblock_add() Linux doesn't own the memory immediately after the kernel image. On Octeon bootloader places a shared structure right close after the kernel _end, refer to "struct cvmx_bootinfo *octeon_bootinfo" in cavium-octeon/setup.c. If check_kernel_sections_mem() rounds the PFNs up, first memblock_alloc() inside early_init_dt_alloc_memory_arch() <= device_tree_init() returns memory block overlapping with the above octeon_bootinfo structure, which is being overwritten afterwards. Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map") Signed-off-by: Alexander Sverdlin Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index ca579deef939..9d11f68a9e8b 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -498,8 +498,8 @@ static void __init request_crashkernel(struct resource *res) static void __init check_kernel_sections_mem(void) { - phys_addr_t start = PFN_PHYS(PFN_DOWN(__pa_symbol(&_text))); - phys_addr_t size = PFN_PHYS(PFN_UP(__pa_symbol(&_end))) - start; + phys_addr_t start = __pa_symbol(&_text); + phys_addr_t size = __pa_symbol(&_end) - start; if (!memblock_is_region_memory(start, size)) { pr_info("Kernel sections are not in the memory maps\n"); -- cgit v1.2.3-70-g09d2 From ca13300a88a37a90160d352cede05776ea723919 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Thu, 3 Dec 2020 13:36:49 +0100 Subject: MIPS: OCTEON: Don't add kernel sections into memblock allocator Because check_kernel_sections_mem() does exactly this for all platforms. Signed-off-by: Alexander Sverdlin Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/setup.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 561389d3fadb..982826ba0ef7 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -973,8 +973,6 @@ void __init plat_mem_setup(void) uint64_t crashk_end; #ifndef CONFIG_CRASH_DUMP int64_t memory; - uint64_t kernel_start; - uint64_t kernel_size; #endif total = 0; @@ -1078,13 +1076,6 @@ void __init plat_mem_setup(void) } } cvmx_bootmem_unlock(); - /* Add the memory region for the kernel. */ - kernel_start = (unsigned long) _text; - kernel_size = _end - _text; - - /* Adjust for physical offset. */ - kernel_start &= ~0xffffffff80000000ULL; - memblock_add(kernel_start, kernel_size); #endif /* CONFIG_CRASH_DUMP */ #ifdef CONFIG_CAVIUM_RESERVE32 -- cgit v1.2.3-70-g09d2 From d8d3276bfc49e114103c54d5f93268c70dcf3600 Mon Sep 17 00:00:00 2001 From: Wei Li Date: Thu, 3 Dec 2020 14:54:43 +0800 Subject: MIPS: SMP-CPS: Add support for irq migration when CPU offline Currently we won't migrate irqs when offline CPUs, which has been implemented on most architectures. That will lead to some devices work incorrectly if the bound cores are offline. While that can be easily supported by enabling GENERIC_IRQ_MIGRATION. But i don't pretty known the reason it was not supported on all MIPS platforms. This patch add the support for irq migration on MIPS CPS platform, and it's tested on the interAptiv processor. Signed-off-by: Wei Li Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + arch/mips/kernel/smp-cps.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b99498958b5c..b49a390df1cb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2488,6 +2488,7 @@ config MIPS_CPS select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6 select SYS_SUPPORTS_SMP select WEAK_ORDERING + select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU help Select this if you wish to run an SMP kernel across multiple cores within a MIPS Coherent Processing System. When this option is diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dbb3f1fc71ab..8b027c72b8ef 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -461,6 +462,7 @@ static int cps_cpu_disable(void) smp_mb__after_atomic(); set_cpu_online(cpu, false); calculate_cpu_foreign_map(); + irq_migrate_all_off_this_cpu(); return 0; } -- cgit v1.2.3-70-g09d2 From 4f1682b8a97dc24e57e8bcb62b23c216d8425266 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 3 Dec 2020 11:19:03 +0800 Subject: MIPS: Move memblock_dump_all() to the end of setup_arch() In order to get more memblock configuration with memblock=debug in the boot cmdline, move memblock_dump_all() to the end of setup_arch(), this can help us to get dmi_setup() and resource_init() memblock info, at least for now. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 9d11f68a9e8b..7e1f8e277437 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -688,8 +688,6 @@ static void __init arch_mem_init(char **cmdline_p) fdt_init_reserved_mem(); - memblock_dump_all(); - early_memtest(PFN_PHYS(ARCH_PFN_OFFSET), PFN_PHYS(max_low_pfn)); } @@ -787,6 +785,8 @@ void __init setup_arch(char **cmdline_p) cpu_cache_init(); paging_init(); + + memblock_dump_all(); } unsigned long kernelsp[NR_CPUS]; -- cgit v1.2.3-70-g09d2 From c0aac3a51cb6364bed367ee3e1a96ed414f386b4 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Fri, 4 Dec 2020 09:11:46 +0800 Subject: MIPS: KASLR: Avoid endless loop in sync_icache if synci_step is zero Most platforms do not need to do synci instruction operations when synci_step is 0. But for example, the synci implementation on Loongson64 platform has some changes. On the one hand, it ensures that the memory access instructions have been completed. On the other hand, it guarantees that all prefetch instructions need to be fetched again. And its address information is useless. Thus, only one synci operation is required when synci_step is 0 on Loongson64 platform. I guess that some other platforms have similar implementations on synci, so add judgment conditions in `while` to ensure that at least all platforms perform synci operations once. For those platforms that do not need synci, they just do one more operation similar to nop. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/relocate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 57bdd2761c78..47aeb3350a76 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -64,7 +64,7 @@ static void __init sync_icache(void *kbase, unsigned long kernel_length) : "r" (kbase)); kbase += step; - } while (kbase < kend); + } while (step && kbase < kend); /* Completion barrier */ __sync(); -- cgit v1.2.3-70-g09d2 From 991838f90e9315468cd1d1daed29d27faae77a9b Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Sat, 28 Nov 2020 22:53:53 +0100 Subject: MIPS: DTS: img: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. Signed-off-by: Alexander Dahl Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/img/pistachio_marduk.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/img/pistachio_marduk.dts b/arch/mips/boot/dts/img/pistachio_marduk.dts index bf69da96dc8b..a8708783f04b 100644 --- a/arch/mips/boot/dts/img/pistachio_marduk.dts +++ b/arch/mips/boot/dts/img/pistachio_marduk.dts @@ -46,9 +46,10 @@ regulator-max-microvolt = <1800000>; }; - leds { + led-controller { compatible = "pwm-leds"; - heartbeat { + + led-1 { label = "marduk:red:heartbeat"; pwms = <&pwm 3 300000>; max-brightness = <255>; -- cgit v1.2.3-70-g09d2 From 5b058973d3205578aa6c9a71392e072a11ca44ef Mon Sep 17 00:00:00 2001 From: Anders Roxell Date: Fri, 11 Dec 2020 11:24:37 +0100 Subject: mips: lib: uncached: fix non-standard usage of variable 'sp' When building mips tinyconfig with clang the following warning show up: arch/mips/lib/uncached.c:45:6: warning: variable 'sp' is uninitialized when used here [-Wuninitialized] if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) ^~ arch/mips/lib/uncached.c:40:18: note: initialize the variable 'sp' to silence this warning register long sp __asm__("$sp"); ^ = 0 1 warning generated. Rework to make an explicit inline move, instead of the non-standard use of specifying registers for local variables. This is what's written from the gcc-10 manual [1] about specifying registers for local variables: "6.47.5.2 Specifying Registers for Local Variables ................................................. [...] "The only supported use for this feature is to specify registers for input and output operands when calling Extended 'asm' (*note Extended Asm::). [...]". [1] https://docs.w3cub.com/gcc~10/local-register-variables Signed-off-by: Anders Roxell Reported-by: Nathan Chancellor Reported-by: Naresh Kamboju Reviewed-by: Nick Desaulniers Signed-off-by: Thomas Bogendoerfer --- arch/mips/lib/uncached.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c index 09d5deea747f..f80a67c092b6 100644 --- a/arch/mips/lib/uncached.c +++ b/arch/mips/lib/uncached.c @@ -37,10 +37,12 @@ */ unsigned long run_uncached(void *func) { - register long sp __asm__("$sp"); register long ret __asm__("$2"); long lfunc = (long)func, ufunc; long usp; + long sp; + + __asm__("move %0, $sp" : "=r" (sp)); if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) usp = CKSEG1ADDR(sp); -- cgit v1.2.3-70-g09d2 From a8c0f1c634507a36ef87a23cfd93720f6142ad9a Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Mon, 7 Dec 2020 20:21:42 +0800 Subject: MIPS: Select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL to enable sysfs memblock debug In the current code, CONFIG_ARCH_KEEP_MEMBLOCK is not set for MIPS arch, memblock_discard() will discard memory and reserved arrays if they were allocated, select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL to give a chance to track "memory" and "reserved" memblocks after early boot, with this patch, we can see the following two sysfs interfaces under DEBUG_FS. /sys/kernel/debug/memblock/memory /sys/kernel/debug/memblock/reserved Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b49a390df1cb..85c7b0637734 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -10,6 +10,7 @@ config MIPS select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_GCOV_PROFILE_ALL + select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL select ARCH_SUPPORTS_UPROBES select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF if 64BIT -- cgit v1.2.3-70-g09d2 From 41bb1a9b85dd613787a54414a1ae7d4181b9de5d Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 27 Nov 2020 10:16:03 +0100 Subject: MIPS: mm: Add back define for PAGE_SHARED There are still some drivers using PAGE_SHARED constant so put it back. Reported-by: kernel test robot Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pgtable.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 158ba3aa3bf1..4f9c37616d42 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -25,6 +25,8 @@ struct mm_struct; struct vm_area_struct; +#define PAGE_SHARED vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED) + #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) #define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ -- cgit v1.2.3-70-g09d2 From 99fbc70f8547c0782dcde25679c647a11393b801 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Fri, 27 Nov 2020 12:13:55 +0100 Subject: MIPS: Octeon: irq: Alloc desc before configuring IRQ Allocate the IRQ descriptors where necessary before configuring them via irq_set_chip_and_handler(). Fixes the following soft lockup: watchdog: BUG: soft lockup - CPU#5 stuck for 22s! [modprobe:72] Modules linked in: irq event stamp: 33288 hardirqs last enabled at (33287): [] restore_partial+0x74/0x150 hardirqs last disabled at (33288): [] handle_int+0x128/0x178 softirqs last enabled at (33284): [] __do_softirq+0x5c4/0x6d0 softirqs last disabled at (33279): [] irq_exit+0xe8/0xf0 CPU: 5 PID: 72 Comm: modprobe Not tainted 4.19.80-... #1 $ 0 : 0000000000000000 0000000000000001 0000000000000003 8000000002bdc640 $ 4 : 0000000000000000 0000000000000000 0000000000000000 0000000000000000 $ 8 : 0000000000000001 0000000000000001 0000000000000000 ffffffff803076cc $12 : 0000000000000000 0000000000000000 ffffffff817f0000 0000000008000000 $16 : ffffffff80a96d10 ffffffff80a90000 8000000002c41780 8000000002c41788 $20 : 0000000000000001 ffffffff8013b248 800000008ef28080 ffffffff80bb8700 $24 : 0000000003bf0000 ffffffff802d0610 $28 : 800000008ef20000 800000008ef23bd0 0000000000000006 ffffffff8020d6f8 Hi : 0000000000000160 Lo : 0000000000000014 epc : ffffffff8020d72c smp_call_function_many+0x2f4/0x370 ra : ffffffff8020d6f8 smp_call_function_many+0x2c0/0x370 Status: 10008ce3 KX SX UX KERNEL EXL IE Cause : 40808000 (ExcCode 00) PrId : 000d900a (Cavium Octeon II) CPU: 5 PID: 72 Comm: modprobe Not tainted 4.19.80-... #1 Stack : ffffffff80ab0000 00000051801c0da0 0000000010000ce0 5e70a8a65518aeac 5e70a8a65518aeac 0000000000000000 800000008e0cfb48 ffffffff81820000 800000008e0cfad4 00000000f0ce6f64 0000000000000001 0000000000000000 ffffffff801ccfb8 0000000000000000 0000000000000000 ffffffff817f0000 800000008531d840 ffffffff80a90000 fffe000000000000 0000000000000000 ffffffff80b20000 ffffffffffffffff ffffffff80bb3980 ffffffff80bb3980 ffffffff80a90000 00000000fffffffe ffffffff8057a760 0000000000000028 ffffffff80c50028 800000008ef20000 800000008e0cfb40 ffffffff80b20000 ffffffff80835d6c 0000000000000000 800000008e0cfc78 5e70a8a65518aeac ffffffff80a9dbf7 ffffffff80835c2c ffffffff801357a4 ffffffff809bdd50 ... Call Trace: [] show_stack+0x9c/0x130 [] dump_stack+0xdc/0x140 [] watchdog_timer_fn+0x3e8/0x478 [] __hrtimer_run_queues+0x18c/0x6d8 [] hrtimer_interrupt+0x104/0x2e8 [] c0_compare_interrupt+0x60/0x90 [] __handle_irq_event_percpu+0xb4/0x4a0 [] handle_irq_event_percpu+0x34/0x90 [] handle_percpu_irq+0x9c/0xe0 [] generic_handle_irq+0x34/0x50 [] do_IRQ+0x18/0x28 [] plat_irq_dispatch+0x90/0x128 [] handle_int+0x16c/0x178 [] smp_call_function_many+0x2f4/0x370 [] smp_call_function+0x40/0xa0 [] flush_tlb_mm+0x44/0x140 [] tlb_flush_mmu+0x38/0x90 [] arch_tlb_finish_mmu+0x4c/0x88 [] tlb_finish_mmu+0x24/0x50 [] exit_mmap+0x11c/0x1b8 [] mmput+0x84/0x138 [] do_exit+0x314/0xc88 [] do_group_exit+0x48/0xb0 [] __wake_up_parent+0x0/0x18 Signed-off-by: Alexander Sverdlin Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-irq.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 6501a842c41a..bd47e15d02c7 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -1505,10 +1505,20 @@ static int __init octeon_irq_init_ciu( goto err; } + r = irq_alloc_desc_at(OCTEON_IRQ_MBOX0, -1); + if (r < 0) { + pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_MBOX0"); + goto err; + } r = octeon_irq_set_ciu_mapping( OCTEON_IRQ_MBOX0, 0, 32, 0, chip_mbox, handle_percpu_irq); if (r) goto err; + r = irq_alloc_desc_at(OCTEON_IRQ_MBOX1, -1); + if (r < 0) { + pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_MBOX1"); + goto err; + } r = octeon_irq_set_ciu_mapping( OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq); if (r) @@ -1546,6 +1556,11 @@ static int __init octeon_irq_init_ciu( if (r) goto err; + r = irq_alloc_descs(OCTEON_IRQ_WDOG0, OCTEON_IRQ_WDOG0, 16, -1); + if (r < 0) { + pr_err("Failed to allocate desc for %s\n", "OCTEON_IRQ_WDOGx"); + goto err; + } /* CIU_1 */ for (i = 0; i < 16; i++) { r = octeon_irq_set_ciu_mapping( -- cgit v1.2.3-70-g09d2 From 47683459ba8f032fec81399dde1b346a1d2a4ff6 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sat, 5 Dec 2020 16:55:07 +0800 Subject: MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org Use @kernel.org address as the main communications end point. Update the corresponding M-entries and .mailmap (for git shortlog translation). Signed-off-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- .mailmap | 2 ++ MAINTAINERS | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index 1e14566a3d56..e6ea21990a67 100644 --- a/.mailmap +++ b/.mailmap @@ -119,6 +119,8 @@ Henk Vergonet Henrik Kretzschmar Henrik Rydberg Herbert Xu +Huacai Chen +Huacai Chen Jacob Shin Jaegeuk Kim Jaegeuk Kim diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..88319de9c0b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9640,7 +9640,7 @@ F: arch/arm64/kvm/ F: include/kvm/arm_* KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips) -M: Huacai Chen +M: Huacai Chen M: Aleksandar Markovic L: linux-mips@vger.kernel.org L: kvm@vger.kernel.org @@ -11728,7 +11728,7 @@ F: drivers/*/*/*loongson2* F: drivers/*/*loongson2* MIPS/LOONGSON64 ARCHITECTURE -M: Huacai Chen +M: Huacai Chen M: Jiaxun Yang L: linux-mips@vger.kernel.org S: Maintained -- cgit v1.2.3-70-g09d2 From e22a26421fce36802785d742acaa4b2f4c37b995 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 16:44:13 +0100 Subject: MAINTAINERS: Remove JZ4780 DMA driver entry The entry for MIPS Ingenic JZ4780 DMA driver is not up to date anymore. Zubair Lutfullah Kakakhel's email bounces and no maintenance is provided. Suggested-by: Paul Cercueil Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thomas Bogendoerfer --- MAINTAINERS | 5 ----- 1 file changed, 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 88319de9c0b0..f463320197b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8673,11 +8673,6 @@ F: include/uapi/rdma/ F: samples/bpf/ibumad_kern.c F: samples/bpf/ibumad_user.c -INGENIC JZ4780 DMA Driver -M: Zubair Lutfullah Kakakhel -S: Maintained -F: drivers/dma/dma-jz4780.c - INGENIC JZ4780 NAND DRIVER M: Harvey Hunt L: linux-mtd@lists.infradead.org -- cgit v1.2.3-70-g09d2 From 3bd5a2350262f1d316c9ff7b86a97335da5f2118 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 16:44:14 +0100 Subject: MAINTAINERS: Add linux-mips mailing list to JZ47xx entries The entries for JZ47xx SoCs and its drivers lacked MIPS mailing list. Only MTD NAND driver pointed linux-mtd. Add linux-mips so the relevant patches will get attention of MIPS developers. Signed-off-by: Krzysztof Kozlowski Acked-by: Paul Cercueil Signed-off-by: Thomas Bogendoerfer --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f463320197b1..c70c72ef7c66 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8676,11 +8676,13 @@ F: samples/bpf/ibumad_user.c INGENIC JZ4780 NAND DRIVER M: Harvey Hunt L: linux-mtd@lists.infradead.org +L: linux-mips@vger.kernel.org S: Maintained F: drivers/mtd/nand/raw/ingenic/ INGENIC JZ47xx SoCs M: Paul Cercueil +L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ingenic/ F: arch/mips/generic/board-ingenic.c -- cgit v1.2.3-70-g09d2 From ad4fddef5f2345aa9214e979febe2f47639c10d9 Mon Sep 17 00:00:00 2001 From: Anders Roxell Date: Fri, 27 Nov 2020 09:39:43 +0100 Subject: mips: fix Section mismatch in reference When building mips tinyconfig with clang the following error show up: WARNING: modpost: vmlinux.o(.text+0x1940c): Section mismatch in reference from the function r4k_cache_init() to the function .init.text:loongson3_sc_init() The function r4k_cache_init() references the function __init loongson3_sc_init(). This is often because r4k_cache_init lacks a __init annotation or the annotation of loongson3_sc_init is wrong. Remove marked __init from function loongson3_sc_init(), mips_sc_probe_cm3(), and mips_sc_probe(). Signed-off-by: Anders Roxell Reviewed-by: Nick Desaulniers Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-r4k.c | 2 +- arch/mips/mm/sc-mips.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 99521764c75b..4f976d687ab0 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1609,7 +1609,7 @@ static void __init loongson2_sc_init(void) c->options |= MIPS_CPU_INCLUSIVE_CACHES; } -static void __init loongson3_sc_init(void) +static void loongson3_sc_init(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config2, lsize; diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index dd0a5becaabd..06ec304ad4d1 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -146,7 +146,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) return 1; } -static int __init mips_sc_probe_cm3(void) +static int mips_sc_probe_cm3(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned long cfg = read_gcr_l2_config(); @@ -180,7 +180,7 @@ static int __init mips_sc_probe_cm3(void) return 0; } -static inline int __init mips_sc_probe(void) +static inline int mips_sc_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config1, config2; -- cgit v1.2.3-70-g09d2