From b67ab6fb63bbbe6d2c0edebd28c27ea425c8b55b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 13 Mar 2023 21:40:26 +0900 Subject: dt-bindings: iommu: renesas, ipmmu-vmsa: Update for R-Car Gen4 Since R-Car Gen4 does not have the main IPMMU IMSSTR register, update the bindings to drop the interrupt bit number from the renesas,ipmmu-main property. Signed-off-by: Yoshihiro Shimoda [geert: Re-add removed items level, add minItems/maxItems constraints] Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230313124026.954514-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Joerg Roedel --- .../bindings/iommu/renesas,ipmmu-vmsa.yaml | 32 ++++++++++++++++------ 1 file changed, 24 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml index 72308a4c14e7..be90f68c11d1 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml @@ -74,16 +74,16 @@ properties: renesas,ipmmu-main: $ref: /schemas/types.yaml#/definitions/phandle-array items: - - items: + - minItems: 1 + items: - description: phandle to main IPMMU - - description: the interrupt bit number associated with the particular - cache IPMMU device. The interrupt bit number needs to match the main - IPMMU IMSSTR register. Only used by cache IPMMU instances. + - description: + The interrupt bit number associated with the particular cache + IPMMU device. If present, the interrupt bit number needs to match + the main IPMMU IMSSTR register. Only used by cache IPMMU + instances. description: - Reference to the main IPMMU phandle plus 1 cell. The cell is - the interrupt bit number associated with the particular cache IPMMU - device. The interrupt bit number needs to match the main IPMMU IMSSTR - register. Only used by cache IPMMU instances. + Reference to the main IPMMU. required: - compatible @@ -109,6 +109,22 @@ allOf: required: - power-domains + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen4-ipmmu-vmsa + then: + properties: + renesas,ipmmu-main: + items: + - maxItems: 1 + else: + properties: + renesas,ipmmu-main: + items: + - minItems: 2 + examples: - | #include -- cgit v1.3.1 From 7f061c19f6521ef2b3e6f784ae344ebb562a5343 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 10:13:58 +0100 Subject: dt-bindings: arm-smmu: Add compatible for SM8550 SoC Add the SoC specific compatible for SM8550 implementing arm,mmu-500. Signed-off-by: Abel Vesa Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230207-topic-sm8550-upstream-smmu-bindings-v3-1-cb15a7123cfe@linaro.org Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe18..ea81e9b1860c 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -53,6 +53,7 @@ properties: - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 - const: qcom,smmu-500 - const: arm,mmu-500 @@ -389,6 +390,7 @@ allOf: - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 then: properties: clock-names: false -- cgit v1.3.1 From 5c3686616b1840b3143b227eb58fb1c1621d204e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 17:44:16 +0100 Subject: dt-bindings: arm-smmu: Use qcom,smmu compatible for MMU500 adreno SMMUs qcom,smmu-500 was introduced to prevent people from adding new compatibles for what seems to roughly be the same hardware. Use it for qcom,adreno-smmu-compatible targets as well. While at it, fix the "arm,smmu-500" -> "arm,mmu-500" typo in the comment. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230313-topic-gpu_smmu_bindings-v3-1-66ab655fbfd5@linaro.org Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ea81e9b1860c..b3a8f5864648 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -76,9 +76,19 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - const: arm,mmu-500 - - - description: Qcom Adreno GPUs implementing "arm,smmu-500" + - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" + items: + - enum: + - qcom,sc7280-smmu-500 + - qcom,sm8150-smmu-500 + - qcom,sm8250-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) + deprecated: true items: + # Do not add additional SoC to this list. Instead use previous list. - enum: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 -- cgit v1.3.1 From 16d1646871fbe800c9751f0816a970f9126a6586 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 17:44:17 +0100 Subject: dt-bindings: arm-smmu: Add SM8350 Adreno SMMU Document the Adreno SMMU present on SM8350. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230313-topic-gpu_smmu_bindings-v3-2-66ab655fbfd5@linaro.org Signed-off-by: Will Deacon --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index b3a8f5864648..f45e4296a5ea 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -82,6 +82,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 + - qcom,sm8350-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 -- cgit v1.3.1 From 3ad6585509dc8157e598dbd06b71efed2e45fee8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:52:08 +0100 Subject: dt-bindings: arm-smmu: Document SM61[12]5 GPU SMMU Both of these SoCs have a Qualcomm MMU500 implementation of SMMU in front of their GPUs that expect 3 clocks. Both of them also have an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500 from the "no clocks" list (intentionally 'breaking' the schema checks of APPS SMMU, as now it *can* accept clocks - with the current structure of this file it would have taken a wastefully-long time to sort this out properly..) and add necessary yaml to describe the clocks required by the GPU SMMUs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230315-topic-kamorta_adrsmmu-v1-1-d1c0dea90bd9@linaro.org Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index f45e4296a5ea..ba677d401e24 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -80,6 +80,8 @@ properties: items: - enum: - qcom,sc7280-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 @@ -376,6 +378,30 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + items: + - enum: + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + clock-names: + items: + - const: mem + - const: hlos + - const: iface + + clocks: + items: + - description: GPU memory bus clock + - description: Voter clock required for HLOS SMMU access + - description: Interface clock required for register access + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -395,8 +421,6 @@ allOf: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - - qcom,sm6115-smmu-500 - - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 -- cgit v1.3.1 From e494245c756e270e3450983b654c38e6f8aa0b18 Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Tue, 11 Apr 2023 17:31:31 +0800 Subject: dt-bindings: media: mediatek,vcodec: Remove dma-ranges property After commit f1ad5338a4d5 ("of: Fix "dma-ranges" handling for bus controllers"), the dma-ranges of the leaf node doesn't work. Remove it for vcodec here. For mediatek,vcodec-decoder.yaml and mediatek,vcodec-encoder.yaml, this property is in the leaf node, it is invalid as the above comment. Currently there is only mt8195 VENC node has this property in upstream. Indeed, VENC is affected, but it is not a fatal issue. Originally it expects its iova range locate at 4GB-8GB. However after that commit, its expectation doesn't come true, it will fall back to 0-4GB iova and also could work well. Cc: Tiffany Lin Cc: Andrew-CT Chen Cc: Yunfei Dong Cc: Mauro Carvalho Chehab Cc: Matthias Brugger Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Acked-by: Hans Verkuil Link: https://lore.kernel.org/r/20230411093144.2690-2-yong.wu@mediatek.com Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml | 5 ----- Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 5 ----- 2 files changed, 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml index aa55ca65d6ed..fad59b486d5d 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -56,11 +56,6 @@ properties: List of the hardware port in respective IOMMU block for current Socs. Refer to bindings/iommu/mediatek,iommu.yaml. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - mediatek,vpu: $ref: /schemas/types.yaml#/definitions/phandle description: diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index 0f2ea8d9a10c..a2051b31fa29 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -49,11 +49,6 @@ properties: List of the hardware port in respective IOMMU block for current Socs. Refer to bindings/iommu/mediatek,iommu.yaml. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - mediatek,vpu: $ref: /schemas/types.yaml#/definitions/phandle description: -- cgit v1.3.1 From 559549b1f250a1b5bec3c6c3a9354deead371bde Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Tue, 11 Apr 2023 17:31:32 +0800 Subject: dt-bindings: media: mediatek,jpeg: Remove dma-ranges property After commit f1ad5338a4d5 ("of: Fix "dma-ranges" handling for bus controllers"), the dma-ranges of the leaf node doesn't work. Remove it for jpeg here. Currently there is only mt8195 jpeg node has this property in upstream, and it already uses parent-child node, this property did work. But instead, MediaTek iommu will control the masters' iova ranges by the master's larb/port id internally, then this property is unnecessary. Cc: Mauro Carvalho Chehab Cc: Matthias Brugger Cc: Bin Liu Cc: kyrie wu Cc: Xia Jiang Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Reviewed-by: Hans Verkuil Link: https://lore.kernel.org/r/20230411093144.2690-3-yong.wu@mediatek.com Signed-off-by: Joerg Roedel --- .../devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml | 7 ------- .../devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml | 7 ------- Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml | 5 ----- 3 files changed, 19 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml index 71595c013dbb..e5448c60e3eb 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml @@ -26,11 +26,6 @@ properties: Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. Ports are according to the HW. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - "#address-cells": const: 2 @@ -89,7 +84,6 @@ required: - compatible - power-domains - iommus - - dma-ranges - ranges additionalProperties: false @@ -115,7 +109,6 @@ examples: <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>, <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; - dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml index 95990539f7c0..596186497b68 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -26,11 +26,6 @@ properties: Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. Ports are according to the HW. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - "#address-cells": const: 2 @@ -89,7 +84,6 @@ required: - compatible - power-domains - iommus - - dma-ranges - ranges additionalProperties: false @@ -113,7 +107,6 @@ examples: <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; - dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml index c8412e8ab353..37800e1908cc 100644 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml @@ -44,11 +44,6 @@ properties: Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. Ports are according to the HW. - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - required: - compatible - reg -- cgit v1.3.1