From 6bac1ffa9ca4f26907921c52ee56c049cec1df1b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 11 Sep 2024 17:09:06 +0200 Subject: dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema Convert the Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller to dt-schema. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240911-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson8-clkc-v1-1-e0b8623c090d@linaro.org Signed-off-by: Jerome Brunet --- .../bindings/clock/amlogic,meson8-clkc.yaml | 45 +++++++++++++++++++ .../bindings/clock/amlogic,meson8b-clkc.txt | 51 ---------------------- 2 files changed, 45 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml delete mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml new file mode 100644 index 000000000000..ab73d4654171 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller + +maintainers: + - Neil Armstrong + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson8-clkc + - amlogic,meson8b-clkc + - items: + - const: amlogic,meson8m2-clkc + - const: amlogic,meson8-clkc + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + items: + - const: xtal + - const: ddr_pll + - const: clk_32k + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#reset-cells' + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt deleted file mode 100644 index cc51e4746b3b..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit - -The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and -supplies clock to various controllers within the SoC. - -Required Properties: - -- compatible: must be one of: - - "amlogic,meson8-clkc" for Meson8 (S802) SoCs - - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs - - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs -- #clock-cells: should be 1. -- #reset-cells: should be 1. -- clocks: list of clock phandles, one for each entry in clock-names -- clock-names: should contain the following: - * "xtal": the 24MHz system oscillator - * "ddr_pll": the DDR PLL clock - * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) - -Parent node should have the following properties : -- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" -- reg: base address and size of the HHI system control register space. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be -used in device tree sources. - -Similarly a preprocessor macro for each reset line is defined in -dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the -device tree sources). - - -Example: Clock controller node: - - clkc: clock-controller { - compatible = "amlogic,meson8b-clkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - }; -- cgit v1.3.1 From 61b17d072d811df5733a1570889b8c6fa6834bf8 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 18 Aug 2024 23:43:39 +0300 Subject: dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings Add new entry to the SM8450 dt-bindings and add SM8475-specific clocks to SM8450 GCC header file. Signed-off-by: Danila Tikhonov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 4 +++- include/dt-bindings/clock/qcom,gcc-sm8450.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml index d848361beeb3..77273aee5d52 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: - const: qcom,gcc-sm8450 + enum: + - qcom,gcc-sm8450 + - qcom,sm8475-gcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h index 9679410843a0..7320e63c3a2f 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8450.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -194,6 +194,9 @@ #define GCC_VIDEO_AXI0_CLK 182 #define GCC_VIDEO_AXI1_CLK 183 #define GCC_VIDEO_XO_CLK 184 +/* Additional SM8475-specific clocks */ +#define SM8475_GCC_GPLL2 185 +#define SM8475_GCC_GPLL3 186 /* GCC resets */ #define GCC_CAMERA_BCR 0 -- cgit v1.3.1 From d4fdee9f6d6a0c524adb329d9a971a198bdfb367 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 18 Aug 2024 23:43:41 +0300 Subject: dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240818204348.197788-4-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml index 4794c53793a8..e9123bbfd491 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - qcom,sm8450-dispcc + - qcom,sm8475-dispcc clocks: minItems: 3 -- cgit v1.3.1 From 4816898460144b651d79c2e3e1c7a3c1f0507a62 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 18 Aug 2024 23:43:43 +0300 Subject: dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240818204348.197788-6-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 2d2c59aa8c6b..b9d29e4f65de 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -26,6 +26,7 @@ properties: enum: - qcom,sm4450-gpucc - qcom,sm8450-gpucc + - qcom,sm8475-gpucc - qcom,sm8550-gpucc - qcom,sm8650-gpucc - qcom,x1e80100-gpucc -- cgit v1.3.1 From 29be508d1d7ffb241c39b8b7471253d81fb18a6a Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 18 Aug 2024 23:43:45 +0300 Subject: dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240818204348.197788-8-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 9829ba28fe0e..62714fa54db8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - qcom,sm8450-videocc + - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc -- cgit v1.3.1 From f63115162502c4de4e225d653e9d3b68bfebfa9d Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 18 Aug 2024 23:43:47 +0300 Subject: dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20240818204348.197788-10-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 26afbbe65511..0766f66c7dc4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -26,6 +26,7 @@ properties: enum: - qcom,sc8280xp-camcc - qcom,sm8450-camcc + - qcom,sm8475-camcc - qcom,sm8550-camcc - qcom,sm8650-camcc - qcom,x1e80100-camcc -- cgit v1.3.1 From 5011cc7ad9aeea98029385f8a0e81a0ebfc45bed Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 30 Sep 2024 23:49:59 +0200 Subject: dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML Convert RK3328 clock controller bindings to DT schema Changes against original bindings: - Add clocks and clock-names as the device has at least one input clock. Signed-off-by: Johan Jonker Reviewed-by: Krzysztof Kozlowski [add Krzysztof's review from v1, shorten commit description] Link: https://lore.kernel.org/r/20240930215001.1999212-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../bindings/clock/rockchip,rk3328-cru.txt | 58 ----------------- .../bindings/clock/rockchip,rk3328-cru.yaml | 74 ++++++++++++++++++++++ 2 files changed, 74 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt deleted file mode 100644 index 904ae682ea90..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3328 Clock and Reset Unit - -The RK3328 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3328-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "clkin_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - - "hdmi_phy" - output clock of the hdmi phy pll - optional - -Example: Clock controller node: - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff120000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff120000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml new file mode 100644 index 000000000000..f079c7a2559b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3328 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3328 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "clkin_i2s" - external I2S clock - optional, + - "gmac_clkin" - external GMAC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + - "hdmi_phy" - output clock of the hdmi phy pll - optional + +properties: + compatible: + enum: + - rockchip,rk3328-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru"; + reg = <0xff440000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; -- cgit v1.3.1 From 698a3e3c5ee6b2f91f3813a36a3b2f9ac0ec981b Mon Sep 17 00:00:00 2001 From: Harry Austen Date: Fri, 13 Sep 2024 19:11:37 +0000 Subject: dt-bindings: clock: xilinx: describe whether dynamic reconfig is enabled Xilinx clocking wizard IP core's dynamic reconfiguration support is optionally enabled at build time. Add a devicetree boolean property to describe whether the hardware supports this feature or not. Since dynamic reconfiguration support was previously assumed enabled, introduce a property to indicate the inverse, in order to maintain devicetree backwards compatibility. Hence, this new xlnx,static-config property should be specified when dynamic reconfiguration support is disabled in the IP core configuration. Signed-off-by: Harry Austen Link: https://lore.kernel.org/r/20240913191037.2690-6-hpausten@protonmail.com Acked-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index 9d5324dc1027..b44a76a958f4 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -39,6 +39,11 @@ properties: - const: clk_in1 - const: s_axi_aclk + xlnx,static-config: + $ref: /schemas/types.yaml#/definitions/flag + description: + Indicate whether the core has been configured without support for dynamic + runtime reconfguration of the clocking primitive MMCM/PLL. xlnx,speed-grade: $ref: /schemas/types.yaml#/definitions/uint32 @@ -70,6 +75,7 @@ examples: compatible = "xlnx,clocking-wizard"; reg = <0xb0000000 0x10000>; #clock-cells = <1>; + xlnx,static-config; xlnx,speed-grade = <1>; xlnx,nr-outputs = <6>; clock-names = "clk_in1", "s_axi_aclk"; -- cgit v1.3.1 From 40d8566e9aa9628f71211d4b0b9ff8294496eb13 Mon Sep 17 00:00:00 2001 From: Daniel Machon Date: Mon, 16 Sep 2024 11:49:19 +0200 Subject: dt-bindings: clock: add support for lan969x Lan969x is going to reuse the existing lan966x clock driver - document that by adding compatible strings for the different SKU's that we support. Signed-off-by: Daniel Machon Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-1-0e150336074d@microchip.com Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/clock/microchip,lan966x-gck.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml index df2bec188706..16106e8b637f 100644 --- a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml @@ -16,7 +16,18 @@ description: | properties: compatible: - const: microchip,lan966x-gck + oneOf: + - enum: + - microchip,lan966x-gck + - microchip,lan9691-gck + - items: + - enum: + - microchip,lan9698-gck + - microchip,lan9696-gck + - microchip,lan9694-gck + - microchip,lan9693-gck + - microchip,lan9692-gck + - const: microchip,lan9691-gck reg: minItems: 1 -- cgit v1.3.1 From a4a7cbe36623ffaabbae413c0eacf40d033db71f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 6 Sep 2024 10:25:07 +0200 Subject: dt-bindings: clocks: add binding for gated-fixed-clocks In contrast to fixed clocks that are described as ungateable, boards sometimes use additional oscillators for things like PCIe reference clocks, that need actual supplies to get enabled and enable-gpios to be toggled for them to work. This adds a binding for such oscillators that are not configurable themself, but need to handle supplies for them to work. In schematics they often can be seen as ---------------- Enable - | 100MHz,3.3V, | - VDD | 3225 | GND - | | - OUT ---------------- or similar. The enable pin might be separate but can also just be tied to the vdd supply, hence it is optional in the binding. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring (Arm) Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240906082511.2963890-2-heiko@sntech.de Signed-off-by: Stephen Boyd --- .../bindings/clock/gated-fixed-clock.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml b/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml new file mode 100644 index 000000000000..d3e0faf3c64d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gated Fixed clock + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: gated-fixed-clock + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-output-names: + maxItems: 1 + + enable-gpios: + description: + Contains a single GPIO specifier for the GPIO that enables and disables + the oscillator. + maxItems: 1 + + vdd-supply: + description: handle of the regulator that provides the supply voltage + +required: + - compatible + - "#clock-cells" + - clock-frequency + - vdd-supply + +additionalProperties: false + +examples: + - | + clock-1000000000 { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + vdd-supply = <®_vdd>; + }; +... -- cgit v1.3.1 From 6e7c710f0b9a5e89237d98bec3eea89d51bbf834 Mon Sep 17 00:00:00 2001 From: Théo Lebrun Date: Mon, 7 Oct 2024 15:49:16 +0200 Subject: Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Switch from one sub-node per functionality in the system-controller to a single node representing the entire OLB instance. This is the recommended approach for controllers handling many different functionalities; it is a single controller and should be represented by a single devicetree node. The clock bindings is removed and all properties will be described by: soc/mobileye/mobileye,eyeq5-olb.yaml Reviewed-by: Rob Herring (Arm) Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20241007-mbly-clk-v5-1-e9d8994269cb@bootlin.com Signed-off-by: Stephen Boyd --- .../bindings/clock/mobileye,eyeq5-clk.yaml | 51 ---------------------- 1 file changed, 51 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml deleted file mode 100644 index 2d4f2cde1e58..000000000000 --- a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml +++ /dev/null @@ -1,51 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mobileye EyeQ5 clock controller - -description: - The EyeQ5 clock controller handles 10 read-only PLLs derived from the main - crystal clock. It also exposes one divider clock, a child of one of the PLLs. - Its registers live in a shared region called OLB. - -maintainers: - - Grégory Clement - - Théo Lebrun - - Vladimir Kondratiev - -properties: - compatible: - const: mobileye,eyeq5-clk - - reg: - maxItems: 2 - - reg-names: - items: - - const: plls - - const: ospi - - "#clock-cells": - const: 1 - - clocks: - maxItems: 1 - description: - Input parent clock to all PLLs. Expected to be the main crystal. - - clock-names: - items: - - const: ref - -required: - - compatible - - reg - - reg-names - - "#clock-cells" - - clocks - - clock-names - -additionalProperties: false -- cgit v1.3.1 From ea1cca026842bc83af92785e61a4433bcc71ea70 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 17 Oct 2024 10:17:05 +0300 Subject: dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana Reviewed-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd --- .../bindings/clock/mediatek,apmixedsys.yaml | 4 +- .../bindings/clock/mediatek,infracfg.yaml | 8 ++- .../bindings/clock/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,topckgen.yaml | 4 +- MAINTAINERS | 12 ++++ .../dt-bindings/clock/mediatek,mt6735-apmixedsys.h | 16 +++++ .../dt-bindings/clock/mediatek,mt6735-infracfg.h | 25 +++++++ .../dt-bindings/clock/mediatek,mt6735-pericfg.h | 37 ++++++++++ .../dt-bindings/clock/mediatek,mt6735-topckgen.h | 79 ++++++++++++++++++++++ .../dt-bindings/reset/mediatek,mt6735-infracfg.h | 27 ++++++++ .../dt-bindings/reset/mediatek,mt6735-pericfg.h | 31 +++++++++ 11 files changed, 239 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index db5f48e4dd15..591a9e862c7d 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in . + The clock values can be found in + and . properties: compatible: @@ -34,6 +35,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixed - mediatek,mt6795-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml index 252c46d316ee..d1d30700d9b0 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: description: The Mediatek infracfg controller provides various clocks and reset outputs - to the system. The clock values can be found in , - and reset values in and - . + to the system. The clock values can be found in + and , and reset values in + , and + . properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6795-infracfg - mediatek,mt6779-infracfg_ao diff --git a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml index 2f06baecfd23..b98cf45efe2f 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt6795-pericfg - mediatek,mt7622-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index bdf3b55bd56f..c080fb0a1618 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in . + The clock values can be found in and + . properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt6795-topckgen diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f..c5fdf3cccc9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14528,6 +14528,18 @@ S: Maintained F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml F: drivers/mmc/host/mtk-sd.c +MEDIATEK MT6735 CLOCK & RESET DRIVERS +M: Yassine Oudjana +L: linux-clk@vger.kernel.org +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h +F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h + MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau M: Lorenzo Bianconi diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h new file mode 100644 index 000000000000..b4705204409c --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H +#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MMPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_VENCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_APLL1 7 +#define CLK_APMIXED_APLL2 8 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..d8dd51e15637 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H +#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H + +#define CLK_INFRA_DBG 0 +#define CLK_INFRA_GCE 1 +#define CLK_INFRA_TRBG 2 +#define CLK_INFRA_CPUM 3 +#define CLK_INFRA_DEVAPC 4 +#define CLK_INFRA_AUDIO 5 +#define CLK_INFRA_GCPU 6 +#define CLK_INFRA_L2C_SRAM 7 +#define CLK_INFRA_M4U 8 +#define CLK_INFRA_CLDMA 9 +#define CLK_INFRA_CONNMCU_BUS 10 +#define CLK_INFRA_KP 11 +#define CLK_INFRA_APXGPT 12 +#define CLK_INFRA_SEJ 13 +#define CLK_INFRA_CCIF0_AP 14 +#define CLK_INFRA_CCIF1_AP 15 +#define CLK_INFRA_PMIC_SPI 16 +#define CLK_INFRA_PMIC_WRAP 17 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..16bc21bbd95b --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H +#define _DT_BINDINGS_CLK_MT6735_PERICFG_H + +#define CLK_PERI_DISP_PWM 0 +#define CLK_PERI_THERM 1 +#define CLK_PERI_PWM1 2 +#define CLK_PERI_PWM2 3 +#define CLK_PERI_PWM3 4 +#define CLK_PERI_PWM4 5 +#define CLK_PERI_PWM5 6 +#define CLK_PERI_PWM6 7 +#define CLK_PERI_PWM7 8 +#define CLK_PERI_PWM 9 +#define CLK_PERI_USB0 10 +#define CLK_PERI_IRDA 11 +#define CLK_PERI_APDMA 12 +#define CLK_PERI_MSDC30_0 13 +#define CLK_PERI_MSDC30_1 14 +#define CLK_PERI_MSDC30_2 15 +#define CLK_PERI_MSDC30_3 16 +#define CLK_PERI_UART0 17 +#define CLK_PERI_UART1 18 +#define CLK_PERI_UART2 19 +#define CLK_PERI_UART3 20 +#define CLK_PERI_UART4 21 +#define CLK_PERI_BTIF 22 +#define CLK_PERI_I2C0 23 +#define CLK_PERI_I2C1 24 +#define CLK_PERI_I2C2 25 +#define CLK_PERI_I2C3 26 +#define CLK_PERI_AUXADC 27 +#define CLK_PERI_SPI0 28 +#define CLK_PERI_IRTX 29 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h new file mode 100644 index 000000000000..d4b1e113cc0a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H +#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H + +#define CLK_TOP_AD_SYS_26M_CK 0 +#define CLK_TOP_CLKPH_MCK_O 1 +#define CLK_TOP_DMPLL 2 +#define CLK_TOP_DPI_CK 3 +#define CLK_TOP_WHPLL_AUDIO_CK 4 + +#define CLK_TOP_SYSPLL_D2 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL_D5 7 +#define CLK_TOP_SYSPLL1_D2 8 +#define CLK_TOP_SYSPLL1_D4 9 +#define CLK_TOP_SYSPLL1_D8 10 +#define CLK_TOP_SYSPLL1_D16 11 +#define CLK_TOP_SYSPLL2_D2 12 +#define CLK_TOP_SYSPLL2_D4 13 +#define CLK_TOP_SYSPLL3_D2 14 +#define CLK_TOP_SYSPLL3_D4 15 +#define CLK_TOP_SYSPLL4_D2 16 +#define CLK_TOP_SYSPLL4_D4 17 +#define CLK_TOP_UNIVPLL_D2 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL_D5 20 +#define CLK_TOP_UNIVPLL_D26 21 +#define CLK_TOP_UNIVPLL1_D2 22 +#define CLK_TOP_UNIVPLL1_D4 23 +#define CLK_TOP_UNIVPLL1_D8 24 +#define CLK_TOP_UNIVPLL2_D2 25 +#define CLK_TOP_UNIVPLL2_D4 26 +#define CLK_TOP_UNIVPLL2_D8 27 +#define CLK_TOP_UNIVPLL3_D2 28 +#define CLK_TOP_UNIVPLL3_D4 29 +#define CLK_TOP_MSDCPLL_D2 30 +#define CLK_TOP_MSDCPLL_D4 31 +#define CLK_TOP_MSDCPLL_D8 32 +#define CLK_TOP_MSDCPLL_D16 33 +#define CLK_TOP_VENCPLL_D3 34 +#define CLK_TOP_TVDPLL_D2 35 +#define CLK_TOP_TVDPLL_D4 36 +#define CLK_TOP_DMPLL_D2 37 +#define CLK_TOP_DMPLL_D4 38 +#define CLK_TOP_DMPLL_D8 39 +#define CLK_TOP_AD_SYS_26M_D2 40 + +#define CLK_TOP_AXI_SEL 41 +#define CLK_TOP_MEM_SEL 42 +#define CLK_TOP_DDRPHY_SEL 43 +#define CLK_TOP_MM_SEL 44 +#define CLK_TOP_PWM_SEL 45 +#define CLK_TOP_VDEC_SEL 46 +#define CLK_TOP_MFG_SEL 47 +#define CLK_TOP_CAMTG_SEL 48 +#define CLK_TOP_UART_SEL 49 +#define CLK_TOP_SPI_SEL 50 +#define CLK_TOP_USB20_SEL 51 +#define CLK_TOP_MSDC50_0_SEL 52 +#define CLK_TOP_MSDC30_0_SEL 53 +#define CLK_TOP_MSDC30_1_SEL 54 +#define CLK_TOP_MSDC30_2_SEL 55 +#define CLK_TOP_MSDC30_3_SEL 56 +#define CLK_TOP_AUDIO_SEL 57 +#define CLK_TOP_AUDINTBUS_SEL 58 +#define CLK_TOP_PMICSPI_SEL 59 +#define CLK_TOP_SCP_SEL 60 +#define CLK_TOP_ATB_SEL 61 +#define CLK_TOP_DPI0_SEL 62 +#define CLK_TOP_SCAM_SEL 63 +#define CLK_TOP_MFG13M_SEL 64 +#define CLK_TOP_AUD1_SEL 65 +#define CLK_TOP_AUD2_SEL 66 +#define CLK_TOP_IRDA_SEL 67 +#define CLK_TOP_IRTX_SEL 68 +#define CLK_TOP_DISPPWM_SEL 69 + +#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..9df969090377 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H +#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H + +#define MT6735_INFRA_RST0_EMI_REG 0 +#define MT6735_INFRA_RST0_DRAMC0_AO 1 +#define MT6735_INFRA_RST0_AP_CIRQ_EINT 2 +#define MT6735_INFRA_RST0_APXGPT 3 +#define MT6735_INFRA_RST0_SCPSYS 4 +#define MT6735_INFRA_RST0_KP 5 +#define MT6735_INFRA_RST0_PMIC_WRAP 6 +#define MT6735_INFRA_RST0_CLDMA_AO_TOP 7 +#define MT6735_INFRA_RST0_USBSIF_TOP 8 +#define MT6735_INFRA_RST0_EMI 9 +#define MT6735_INFRA_RST0_CCIF 10 +#define MT6735_INFRA_RST0_DRAMC0 11 +#define MT6735_INFRA_RST0_EMI_AO_REG 12 +#define MT6735_INFRA_RST0_CCIF_AO 13 +#define MT6735_INFRA_RST0_TRNG 14 +#define MT6735_INFRA_RST0_SYS_CIRQ 15 +#define MT6735_INFRA_RST0_GCE 16 +#define MT6735_INFRA_RST0_M4U 17 +#define MT6735_INFRA_RST0_CCIF1 18 +#define MT6735_INFRA_RST0_CLDMA_TOP_PD 19 + +#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..a62bb192835a --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H +#define _DT_BINDINGS_RESET_MT6735_PERICFG_H + +#define MT6735_PERI_RST0_UART0 0 +#define MT6735_PERI_RST0_UART1 1 +#define MT6735_PERI_RST0_UART2 2 +#define MT6735_PERI_RST0_UART3 3 +#define MT6735_PERI_RST0_UART4 4 +#define MT6735_PERI_RST0_BTIF 5 +#define MT6735_PERI_RST0_DISP_PWM_PERI 6 +#define MT6735_PERI_RST0_PWM 7 +#define MT6735_PERI_RST0_AUXADC 8 +#define MT6735_PERI_RST0_DMA 9 +#define MT6735_PERI_RST0_IRDA 10 +#define MT6735_PERI_RST0_IRTX 11 +#define MT6735_PERI_RST0_THERM 12 +#define MT6735_PERI_RST0_MSDC2 13 +#define MT6735_PERI_RST0_MSDC3 14 +#define MT6735_PERI_RST0_MSDC0 15 +#define MT6735_PERI_RST0_MSDC1 16 +#define MT6735_PERI_RST0_I2C0 17 +#define MT6735_PERI_RST0_I2C1 18 +#define MT6735_PERI_RST0_I2C2 19 +#define MT6735_PERI_RST0_I2C3 20 +#define MT6735_PERI_RST0_USB 21 + +#define MT6735_PERI_RST1_SPI0 22 + +#endif -- cgit v1.3.1 From d62f45b5e95fa9e557af071915a3fbfa0d766c8f Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Thu, 12 Sep 2024 22:10:36 +0300 Subject: dt-bindings: reset: npcm: add clock properties This commit adds a 25MHz reference clock and clock-cell properties to the NPCM reset document. The addition is necessitated by the integration of the NPCM8xx clock auxiliary bus device into the NPCM reset driver. The inclusion of the NPCM8xx clock properties in the reset document is crucial as the reset block also serves as a clock provider for the NPCM8xx clock. This enhancement is intended to facilitate the use of the NPCM8xx clock driver. Signed-off-by: Tomer Maimon Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240912191038.981105-2-tmaimon77@gmail.com Signed-off-by: Stephen Boyd --- .../bindings/reset/nuvoton,npcm750-reset.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml index d82e65e37cc0..72523f1bbc18 100644 --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm750-reset.yaml @@ -21,6 +21,13 @@ properties: '#reset-cells': const: 2 + '#clock-cells': + const: 1 + + clocks: + items: + - description: specify external 25MHz reference clock. + nuvoton,sysgcr: $ref: /schemas/types.yaml#/definitions/phandle description: a phandle to access GCR registers. @@ -39,6 +46,17 @@ required: - '#reset-cells' - nuvoton,sysgcr +if: + properties: + compatible: + contains: + enum: + - nuvoton,npcm845-reset +then: + required: + - '#clock-cells' + - clocks + additionalProperties: false examples: -- cgit v1.3.1 From beec58479cfb33c090572e0237ce9d670a7ce410 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 18 Oct 2024 10:53:46 +0200 Subject: dt-bindings: clock: ti: Convert interface.txt to json-schema Convert the OMAP interface clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. Signed-off-by: Andreas Kemnade Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241018085347.95071-2-andreas@kemnade.info Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ti/interface.txt | 55 ----------------- .../bindings/clock/ti/ti,interface-clock.yaml | 71 ++++++++++++++++++++++ 2 files changed, 71 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt create mode 100644 Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt deleted file mode 100644 index 85fb1f2d2d28..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ /dev/null @@ -1,55 +0,0 @@ -Binding for Texas Instruments interface clock. - -This binding uses the common clock binding[1]. This clock is -quite much similar to the basic gate-clock [2], however, -it supports a number of additional features, including -companion clock finding (match corresponding functional gate -clock) and hardware autoidle enable / disable. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml - -Required properties: -- compatible : shall be one of: - "ti,omap3-interface-clock" - basic OMAP3 interface clock - "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware - capability for waiting clock to be ready - "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW - handling - "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling - "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling - "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling - "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW - handling -- #clock-cells : from common clock binding; shall be set to 0 -- clocks : link to phandle of parent clock -- reg : base address for the control register - -Optional properties: -- clock-output-names : from common clock binding. -- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) - -Examples: - aes1_ick: aes1_ick@48004a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x48004a14 0x4>; - ti,bit-shift = <3>; - }; - - cam_ick: cam_ick@48004f10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x48004f10 0x4>; - ti,bit-shift = <0>; - }; - - ssi_ick_3430es2: ssi_ick_3430es2@48004a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x48004a10 0x4>; - ti,bit-shift = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml new file mode 100644 index 000000000000..1eaf95d88e0b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,interface-clock.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interface clock. + +maintainers: + - Tero Kristo + +description: | + This clock is quite much similar to the basic gate-clock[1], however, + it supports a number of additional features, including + companion clock finding (match corresponding functional gate + clock) and hardware autoidle enable / disable. + + [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml + +properties: + compatible: + enum: + - ti,omap3-interface-clock # basic OMAP3 interface clock + - ti,omap3-no-wait-interface-clock # interface clock which has no hardware + # capability for waiting clock to be ready + - ti,omap3-hsotgusb-interface-clock # interface clock with USB specific HW handling + - ti,omap3-dss-interface-clock # interface clock with DSS specific HW handling + - ti,omap3-ssi-interface-clock # interface clock with SSI specific HW handling + - ti,am35xx-interface-clock # interface clock with AM35xx specific HW handling + - ti,omap2430-interface-clock # interface clock with OMAP2430 specific HW handling + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,bit-shift: + description: + bit shift for the bit enabling/disabling the clock + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 31 + +required: + - compatible + - clocks + - '#clock-cells' + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + aes1_ick: clock-controller@3 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <3>; + }; + }; -- cgit v1.3.1 From 0fcd58492f066ad0b0d2a82ce0e3466dd3d1f981 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 18 Oct 2024 10:53:47 +0200 Subject: dt-bindings: clock: ti: Convert divider.txt to json-schema Convert the OMAP divider clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. Signed-off-by: Andreas Kemnade Link: https://lore.kernel.org/r/20241018085347.95071-3-andreas@kemnade.info Reviewed-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ti/composite.txt | 2 +- .../devicetree/bindings/clock/ti/divider.txt | 115 ------------ .../bindings/clock/ti/ti,divider-clock.yaml | 193 +++++++++++++++++++++ 3 files changed, 194 insertions(+), 116 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt create mode 100644 Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index 6f7e1331b546..b02f22490dcb 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -17,7 +17,7 @@ merged to this clock. The component clocks shall be of one of the [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/clock/ti/mux.txt -[3] Documentation/devicetree/bindings/clock/ti/divider.txt +[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml [4] Documentation/devicetree/bindings/clock/ti/gate.txt Required properties: diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt deleted file mode 100644 index 4d7c76f0b356..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/divider.txt +++ /dev/null @@ -1,115 +0,0 @@ -Binding for TI divider clock - -This binding uses the common clock binding[1]. It assumes a -register-mapped adjustable clock rate divider that does not gate and has -only one input clock or parent. By default the value programmed into -the register is one less than the actual divisor value. E.g: - -register value actual divisor value -0 1 -1 2 -2 3 - -This assumption may be modified by the following optional properties: - -ti,index-starts-at-one - valid divisor values start at 1, not the default -of 0. E.g: -register value actual divisor value -1 1 -2 2 -3 3 - -ti,index-power-of-two - valid divisor values are powers of two. E.g: -register value actual divisor value -0 1 -1 2 -2 4 - -Additionally an array of valid dividers may be supplied like so: - - ti,dividers = <4>, <8>, <0>, <16>; - -Which will map the resulting values to a divisor table by their index: -register value actual divisor value -0 4 -1 8 -2 -3 16 - -Any zero value in this array means the corresponding bit-value is invalid -and must not be used. - -The binding must also provide the register to control the divider and -unless the divider array is provided, min and max dividers. Optionally -the number of bits to shift that mask, if necessary. If the shift value -is missing it is the same as supplying a zero shift. - -This binding can also optionally provide support to the hardware autoidle -feature, see [2]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt - -Required properties: -- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link to phandle of parent clock -- reg : offset for register controlling adjustable divider - -Optional properties: -- clock-output-names : from common clock binding. -- ti,dividers : array of integers defining divisors -- ti,bit-shift : number of bits to shift the divider value, defaults to 0 -- ti,min-div : min divisor for dividing the input clock rate, only - needed if the first divisor is offset from the default value (1) -- ti,max-div : max divisor for dividing the input clock rate, only needed - if ti,dividers is not defined. -- ti,index-starts-at-one : valid divisor programming starts at 1, not zero, - only valid if ti,dividers is not defined. -- ti,index-power-of-two : valid divisor programming must be a power of two, - only valid if ti,dividers is not defined. -- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock, - see [2] -- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, - see [2] -- ti,set-rate-parent : clk_set_rate is propagated to parent -- ti,latch-bit : latch the divider value to HW, only needed if the register - access requires this. As an example dra76x DPLL_GMAC H14 divider implements - such behavior. - -Examples: -dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_usb_ck>; - ti,max-div = <127>; - reg = <0x190>; - ti,index-starts-at-one; -}; - -aess_fclk: aess_fclk@4a004528 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&abe_clk>; - ti,bit-shift = <24>; - reg = <0x528>; - ti,max-div = <2>; -}; - -dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - reg = <0x0134>; - ti,index-starts-at-one; -}; - -ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml new file mode 100644 index 000000000000..3fbe236eb565 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments divider clock + +maintainers: + - Tero Kristo + +description: | + This clock It assumes a register-mapped adjustable clock rate divider + that does not gate and has only one input clock or parent. By default the + value programmed into the register is one less than the actual divisor value. + E.g: + + register value actual divisor value + 0 1 + 1 2 + 2 3 + + This assumption may be modified by the following optional properties: + + ti,index-starts-at-one - valid divisor values start at 1, not the default + of 0. E.g: + register value actual divisor value + 1 1 + 2 2 + 3 3 + + ti,index-power-of-two - valid divisor values are powers of two. E.g: + register value actual divisor value + 0 1 + 1 2 + 2 4 + + Additionally an array of valid dividers may be supplied like so: + + ti,dividers = <4>, <8>, <0>, <16>; + + Which will map the resulting values to a divisor table by their index: + register value actual divisor value + 0 4 + 1 8 + 2 + 3 16 + + Any zero value in this array means the corresponding bit-value is invalid + and must not be used. + + The binding must also provide the register to control the divider and + unless the divider array is provided, min and max dividers. Optionally + the number of bits to shift that mask, if necessary. If the shift value + is missing it is the same as supplying a zero shift. + + This binding can also optionally provide support to the hardware autoidle + feature, see [1]. + + [1] Documentation/devicetree/bindings/clock/ti/autoidle.txt + +properties: + compatible: + enum: + - ti,divider-clock + - ti,composite-divider-clock + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,dividers: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + array of integers defining divisors + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + number of bits to shift the divider value + maximum: 31 + default: 0 + + ti,min-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + min divisor for dividing the input clock rate, only + needed if the first divisor is offset from the default value (1) + minimum: 1 + default: 1 + + + ti,max-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max divisor for dividing the input clock rate, only needed + if ti,dividers is not defined. + + ti,index-starts-at-one: + type: boolean + description: + valid divisor programming starts at 1, not zero, + only valid if ti,dividers is not defined + + ti,index-power-of-two: + type: boolean + description: + valid divisor programming must be a power of two, + only valid if ti,dividers is not defined. + + ti,autoidle-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + bit shift of the autoidle enable bit for the clock, + see [1]. + maximum: 31 + default: 0 + + ti,invert-autoidle-bit: + type: boolean + description: + autoidle is enabled by setting the bit to 0, + see [1] + + ti,set-rate-parent: + type: boolean + description: + clk_set_rate is propagated to parent | + + ti,latch-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + latch the divider value to HW, only needed if the register + compatible access requires this. As an example dra76x DPLL_GMAC + H14 divider implements such behavior. + +dependentSchemas: + ti,dividers: + properties: + ti,min-div: false + ti,max-div: false + ti,index-power-of-two: false + ti,index-starts-at-one: false + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + reg = <0x190>; + ti,index-starts-at-one; + }; + + clock-controller@528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + reg = <0x528>; + ti,max-div = <2>; + }; + + clock-controller@a40 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + }; -- cgit v1.3.1 From 731237359d83bfb4f27eea5b7a8935af5c72a5ac Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 15 Oct 2024 15:34:03 +0800 Subject: dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL Sort compatible entries by alphabetical order. Then, add compatible string "nxp,imx95-hsio-blk-ctl" for i.MX95. Signed-off-by: Richard Zhu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1728977644-8207-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml index 5dc360b2ea4b..d0291bfff23a 100644 --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml @@ -13,9 +13,10 @@ properties: compatible: items: - enum: - - nxp,imx95-lvds-csr - - nxp,imx95-display-csr - nxp,imx95-camera-csr + - nxp,imx95-display-csr + - nxp,imx95-hsio-blk-ctl + - nxp,imx95-lvds-csr - nxp,imx95-netcmix-blk-ctrl - nxp,imx95-vpu-csr - const: syscon -- cgit v1.3.1 From f029d870096fcd8565a2ee8c2d0078b9aaec4fdb Mon Sep 17 00:00:00 2001 From: Pengfei Li Date: Wed, 23 Oct 2024 11:46:49 -0700 Subject: dt-bindings: clock: Add i.MX91 clock support i.MX91 has similar Clock Control Module(CCM) design as i.MX93, only add few new clock compared to i.MX93. Add a new compatible string and some new clocks for i.MX91. Signed-off-by: Pengfei Li Reviewed-by: Frank Li Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241023184651.381265-4-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/clock/imx93-clock.yaml | 1 + include/dt-bindings/clock/imx93-clock.h | 5 +++++ 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx93-clock.yaml b/Documentation/devicetree/bindings/clock/imx93-clock.yaml index ccb53c6b96c1..98c0800732ef 100644 --- a/Documentation/devicetree/bindings/clock/imx93-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx93-clock.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx91-ccm - fsl,imx93-ccm reg: diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index a1d0b326bb6b..6c685067288b 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -204,5 +204,10 @@ #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 #define IMX93_CLK_PDM_IPG 201 +#define IMX91_CLK_ENET1_QOS_TSN 202 +#define IMX91_CLK_ENET_TIMER 203 +#define IMX91_CLK_ENET2_REGULAR 204 +#define IMX91_CLK_ENET2_REGULAR_GATE 205 +#define IMX91_CLK_ENET1_QOS_TSN_GATE 206 #endif -- cgit v1.3.1 From 133e4a44f1a09c7e76c5dbecb4c7667980c3e53d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Oct 2024 03:24:40 +0200 Subject: dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible Document compatible for RPMh clock controller on SAR2130P platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-1-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index ca857942ed6c..a561a306b947 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,qdu1000-rpmh-clk - qcom,sa8775p-rpmh-clk + - qcom,sar2130p-rpmh-clk - qcom,sc7180-rpmh-clk - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk -- cgit v1.3.1 From 3ee315537e941fb92cff31b259641d19e798b4e6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Oct 2024 03:24:41 +0200 Subject: dt-bindings: clock: qcom: document SAR2130P Global Clock Controller Add bindings for the Global Clock Controller (GCC) present on the Qualcomm SAR2130P platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-2-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sar2130p-gcc.yaml | 65 ++++++++ include/dt-bindings/clock/qcom,sar2130p-gcc.h | 185 +++++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sar2130p-gcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml new file mode 100644 index 000000000000..9a430bbd872a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on sar2130p + +maintainers: + - Dmitry Baryshkov + +description: | + Qualcomm global clock control module provides the clocks, resets and + power domains on sar2130p. + + See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h + +properties: + compatible: + const: qcom,sar2130p-gcc + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: PCIe 0 pipe clock + - description: PCIe 1 pipe clock + - description: Primary USB3 PHY wrapper pipe clock + + protected-clocks: + maxItems: 240 + + power-domains: + maxItems: 1 + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + gcc: clock-controller@100000 { + compatible = "qcom,sar2130p-gcc"; + reg = <0x100000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&usb_0_ssphy>; + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sar2130p-gcc.h b/include/dt-bindings/clock/qcom,sar2130p-gcc.h new file mode 100644 index 000000000000..69d2dd2538a6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sar2130p-gcc.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL9 3 +#define GCC_GPLL9_OUT_EVEN 4 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 5 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_CAMERA_AHB_CLK 8 +#define GCC_CAMERA_HF_AXI_CLK 9 +#define GCC_CAMERA_SF_AXI_CLK 10 +#define GCC_CAMERA_XO_CLK 11 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 12 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 13 +#define GCC_DDRSS_GPU_AXI_CLK 14 +#define GCC_DDRSS_PCIE_SF_CLK 15 +#define GCC_DISP_AHB_CLK 16 +#define GCC_DISP_HF_AXI_CLK 17 +#define GCC_GP1_CLK 18 +#define GCC_GP1_CLK_SRC 19 +#define GCC_GP2_CLK 20 +#define GCC_GP2_CLK_SRC 21 +#define GCC_GP3_CLK 22 +#define GCC_GP3_CLK_SRC 23 +#define GCC_GPU_CFG_AHB_CLK 24 +#define GCC_GPU_GPLL0_CLK_SRC 25 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 26 +#define GCC_GPU_MEMNOC_GFX_CLK 27 +#define GCC_GPU_SNOC_DVM_GFX_CLK 28 +#define GCC_IRIS_SS_HF_AXI1_CLK 29 +#define GCC_IRIS_SS_SPD_AXI1_CLK 30 +#define GCC_PCIE_0_AUX_CLK 31 +#define GCC_PCIE_0_AUX_CLK_SRC 32 +#define GCC_PCIE_0_CFG_AHB_CLK 33 +#define GCC_PCIE_0_MSTR_AXI_CLK 34 +#define GCC_PCIE_0_PHY_RCHNG_CLK 35 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 36 +#define GCC_PCIE_0_PIPE_CLK 37 +#define GCC_PCIE_0_PIPE_CLK_SRC 38 +#define GCC_PCIE_0_SLV_AXI_CLK 39 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 40 +#define GCC_PCIE_1_AUX_CLK 41 +#define GCC_PCIE_1_AUX_CLK_SRC 42 +#define GCC_PCIE_1_CFG_AHB_CLK 43 +#define GCC_PCIE_1_MSTR_AXI_CLK 44 +#define GCC_PCIE_1_PHY_RCHNG_CLK 45 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 46 +#define GCC_PCIE_1_PIPE_CLK 47 +#define GCC_PCIE_1_PIPE_CLK_SRC 48 +#define GCC_PCIE_1_SLV_AXI_CLK 49 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 50 +#define GCC_PDM2_CLK 51 +#define GCC_PDM2_CLK_SRC 52 +#define GCC_PDM_AHB_CLK 53 +#define GCC_PDM_XO4_CLK 54 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 55 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 56 +#define GCC_QMIP_GPU_AHB_CLK 57 +#define GCC_QMIP_PCIE_AHB_CLK 58 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 59 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 60 +#define GCC_QMIP_VIDEO_LSR_AHB_CLK 61 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 62 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 63 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 64 +#define GCC_QUPV3_WRAP0_CORE_CLK 65 +#define GCC_QUPV3_WRAP0_S0_CLK 66 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S1_CLK 68 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S2_CLK 70 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S3_CLK 72 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S4_CLK 74 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S5_CLK 76 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 78 +#define GCC_QUPV3_WRAP1_CORE_CLK 79 +#define GCC_QUPV3_WRAP1_S0_CLK 80 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S1_CLK 82 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S2_CLK 84 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S3_CLK 86 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S4_CLK 88 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S5_CLK 90 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 91 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95 +#define GCC_SDCC1_AHB_CLK 96 +#define GCC_SDCC1_APPS_CLK 97 +#define GCC_SDCC1_APPS_CLK_SRC 98 +#define GCC_SDCC1_ICE_CORE_CLK 99 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 100 +#define GCC_USB30_PRIM_MASTER_CLK 101 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 102 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 103 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 104 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 105 +#define GCC_USB30_PRIM_SLEEP_CLK 106 +#define GCC_USB3_PRIM_PHY_AUX_CLK 107 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 108 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 109 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 110 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 111 +#define GCC_VIDEO_AHB_CLK 112 +#define GCC_VIDEO_AXI0_CLK 113 +#define GCC_VIDEO_AXI1_CLK 114 +#define GCC_VIDEO_XO_CLK 115 +#define GCC_GPLL4 116 +#define GCC_GPLL5 117 +#define GCC_GPLL7 118 +#define GCC_DDRSS_SPAD_CLK 119 +#define GCC_DDRSS_SPAD_CLK_SRC 120 +#define GCC_VIDEO_AXI0_SREG 121 +#define GCC_VIDEO_AXI1_SREG 122 +#define GCC_IRIS_SS_HF_AXI1_SREG 123 +#define GCC_IRIS_SS_SPD_AXI1_SREG 124 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PDM_BCR 16 +#define GCC_QUPV3_WRAPPER_0_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUSB2PHY_PRIM_BCR 19 +#define GCC_QUSB2PHY_SEC_BCR 20 +#define GCC_SDCC1_BCR 21 +#define GCC_USB30_PRIM_BCR 22 +#define GCC_USB3_DP_PHY_PRIM_BCR 23 +#define GCC_USB3_DP_PHY_SEC_BCR 24 +#define GCC_USB3_PHY_PRIM_BCR 25 +#define GCC_USB3_PHY_SEC_BCR 26 +#define GCC_USB3PHY_PHY_PRIM_BCR 27 +#define GCC_USB3PHY_PHY_SEC_BCR 28 +#define GCC_VIDEO_AXI0_CLK_ARES 29 +#define GCC_VIDEO_AXI1_CLK_ARES 30 +#define GCC_VIDEO_BCR 31 +#define GCC_IRIS_SS_HF_AXI_CLK_ARES 32 +#define GCC_IRIS_SS_SPD_AXI_CLK_ARES 33 +#define GCC_DDRSS_SPAD_CLK_ARES 34 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_0_PHY_GDSC 1 +#define PCIE_1_GDSC 2 +#define PCIE_1_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB3_PHY_GDSC 5 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC 6 +#define HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC 7 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9 + +#endif -- cgit v1.3.1 From 528e7bb0cabad075ba6e6c84ba30301718cc75e3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Oct 2024 03:24:42 +0200 Subject: dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible Document compatible for the TCSR Clock Controller on SAR2130P platform. It is mostly compatible with the SM8550, except that it doesn't provide UFS clocks. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-3-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 48fdd562d743..3b546deb514a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -21,6 +21,7 @@ properties: compatible: items: - enum: + - qcom,sar2130p-tcsr - qcom,sm8550-tcsr - qcom,sm8650-tcsr - qcom,x1e80100-tcsr -- cgit v1.3.1 From adac76e7edb1ebdfdb4be179900e1d129912d847 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Oct 2024 03:24:43 +0200 Subject: dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible Document compatible for the Display Clock Controller on SAR2130P platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-4-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index c17035a180db..c57d55a9293c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -22,6 +22,7 @@ description: | properties: compatible: enum: + - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc - qcom,x1e80100-dispcc -- cgit v1.3.1 From 111481020aa599764790c807312465a4c94f4b5c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 27 Oct 2024 03:24:44 +0200 Subject: dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 ++ include/dt-bindings/clock/qcom,sar2130p-gpucc.h | 33 ++++++++++++++++++++++ include/dt-bindings/reset/qcom,sar2130p-gpucc.h | 14 +++++++++ 3 files changed, 49 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,sar2130p-gpucc.h create mode 100644 include/dt-bindings/reset/qcom,sar2130p-gpucc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index 2d2c59aa8c6b..ea71ed73a92f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -14,6 +14,7 @@ description: | domains on Qualcomm SoCs. See also:: + include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -24,6 +25,7 @@ description: | properties: compatible: enum: + - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc - qcom,sm8550-gpucc diff --git a/include/dt-bindings/clock/qcom,sar2130p-gpucc.h b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h new file mode 100644 index 000000000000..a2204369110a --- /dev/null +++ b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_FF_CLK_SRC 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GMU_CLK 8 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9 +#define GPU_CC_HUB_AON_CLK 10 +#define GPU_CC_HUB_CLK_SRC 11 +#define GPU_CC_HUB_CX_INT_CLK 12 +#define GPU_CC_MEMNOC_GFX_CLK 13 +#define GPU_CC_PLL0 14 +#define GPU_CC_PLL1 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h new file mode 100644 index 000000000000..99ba5f092e2a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H + +#define GPUCC_GPU_CC_GX_BCR 0 +#define GPUCC_GPU_CC_ACD_BCR 1 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 2 + +#endif -- cgit v1.3.1 From 03e525c66de2535dc1afd26be004621c7c5a253e Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Mon, 28 Oct 2024 11:35:02 +0530 Subject: dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding Add binding for the Qualcomm IPQ5424 Global Clock Controller Signed-off-by: Sricharan Ramabadhran Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241028060506.246606-3-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq5332-gcc.yaml | 41 ++- include/dt-bindings/clock/qcom,ipq5424-gcc.h | 156 +++++++++++ include/dt-bindings/reset/qcom,ipq5424-gcc.h | 310 +++++++++++++++++++++ 3 files changed, 500 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,ipq5424-gcc.h create mode 100644 include/dt-bindings/reset/qcom,ipq5424-gcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 9193de681de2..1230183fc0a9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -4,31 +4,35 @@ $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on IPQ5332 +title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424 maintainers: - Bjorn Andersson description: | Qualcomm global clock control module provides the clocks, resets and power - domains on IPQ5332. + domains on IPQ5332 and IPQ5424. - See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h - -allOf: - - $ref: qcom,gcc.yaml# + See also: + include/dt-bindings/clock/qcom,gcc-ipq5332.h + include/dt-bindings/clock/qcom,gcc-ipq5424.h properties: compatible: - const: qcom,ipq5332-gcc + enum: + - qcom,ipq5332-gcc + - qcom,ipq5424-gcc clocks: + minItems: 5 items: - description: Board XO clock source - description: Sleep clock source - description: PCIE 2lane PHY pipe clock source - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - description: USB PCIE wrapper pipe clock source + - description: PCIE 2-lane PHY2 pipe clock source + - description: PCIE 2-lane PHY3 pipe clock source '#power-domain-cells': false '#interconnect-cells': @@ -38,6 +42,29 @@ required: - compatible - clocks +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,ipq5332-gcc + then: + properties: + clocks: + maxItems: 5 + + - if: + properties: + compatible: + contains: + const: qcom,ipq5424-gcc + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + unevaluatedProperties: false examples: diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h new file mode 100644 index 000000000000..755ce7a71c7c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H + +#define GPLL0 0 +#define GPLL4 1 +#define GPLL2 2 +#define GPLL2_OUT_MAIN 3 +#define GCC_SLEEP_CLK_SRC 4 +#define GCC_APSS_DBG_CLK 5 +#define GCC_USB0_EUD_AT_CLK 6 +#define GCC_PCIE0_AXI_M_CLK_SRC 7 +#define GCC_PCIE0_AXI_M_CLK 8 +#define GCC_PCIE1_AXI_M_CLK_SRC 9 +#define GCC_PCIE1_AXI_M_CLK 10 +#define GCC_PCIE2_AXI_M_CLK_SRC 11 +#define GCC_PCIE2_AXI_M_CLK 12 +#define GCC_PCIE3_AXI_M_CLK_SRC 13 +#define GCC_PCIE3_AXI_M_CLK 14 +#define GCC_PCIE0_AXI_S_CLK_SRC 15 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 16 +#define GCC_PCIE0_AXI_S_CLK 17 +#define GCC_PCIE1_AXI_S_CLK_SRC 18 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 19 +#define GCC_PCIE1_AXI_S_CLK 20 +#define GCC_PCIE2_AXI_S_CLK_SRC 21 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 22 +#define GCC_PCIE2_AXI_S_CLK 23 +#define GCC_PCIE3_AXI_S_CLK_SRC 24 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 25 +#define GCC_PCIE3_AXI_S_CLK 26 +#define GCC_PCIE0_PIPE_CLK_SRC 27 +#define GCC_PCIE0_PIPE_CLK 28 +#define GCC_PCIE1_PIPE_CLK_SRC 29 +#define GCC_PCIE1_PIPE_CLK 30 +#define GCC_PCIE2_PIPE_CLK_SRC 31 +#define GCC_PCIE2_PIPE_CLK 32 +#define GCC_PCIE3_PIPE_CLK_SRC 33 +#define GCC_PCIE3_PIPE_CLK 34 +#define GCC_PCIE_AUX_CLK_SRC 35 +#define GCC_PCIE0_AUX_CLK 36 +#define GCC_PCIE1_AUX_CLK 37 +#define GCC_PCIE2_AUX_CLK 38 +#define GCC_PCIE3_AUX_CLK 39 +#define GCC_PCIE0_AHB_CLK 40 +#define GCC_PCIE1_AHB_CLK 41 +#define GCC_PCIE2_AHB_CLK 42 +#define GCC_PCIE3_AHB_CLK 43 +#define GCC_USB0_AUX_CLK_SRC 44 +#define GCC_USB0_AUX_CLK 45 +#define GCC_USB0_MASTER_CLK 46 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 47 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 48 +#define GCC_USB0_MOCK_UTMI_CLK 49 +#define GCC_USB0_PIPE_CLK_SRC 50 +#define GCC_USB0_PIPE_CLK 51 +#define GCC_USB0_PHY_CFG_AHB_CLK 52 +#define GCC_USB0_SLEEP_CLK 53 +#define GCC_SDCC1_APPS_CLK_SRC 54 +#define GCC_SDCC1_APPS_CLK 55 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 56 +#define GCC_SDCC1_ICE_CORE_CLK 57 +#define GCC_SDCC1_AHB_CLK 58 +#define GCC_PCNOC_BFDCD_CLK_SRC 59 +#define GCC_NSSCFG_CLK 60 +#define GCC_NSSNOC_NSSCC_CLK 61 +#define GCC_NSSCC_CLK 62 +#define GCC_NSSNOC_PCNOC_1_CLK 63 +#define GCC_QPIC_AHB_CLK 64 +#define GCC_QPIC_CLK 65 +#define GCC_MDIO_AHB_CLK 66 +#define GCC_PRNG_AHB_CLK 67 +#define GCC_UNIPHY0_AHB_CLK 68 +#define GCC_UNIPHY1_AHB_CLK 69 +#define GCC_UNIPHY2_AHB_CLK 70 +#define GCC_CMN_12GPLL_AHB_CLK 71 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 72 +#define GCC_NSSNOC_SNOC_CLK 73 +#define GCC_NSSNOC_SNOC_1_CLK 74 +#define GCC_WCSS_AHB_CLK_SRC 75 +#define GCC_QDSS_AT_CLK_SRC 76 +#define GCC_NSSNOC_ATB_CLK 77 +#define GCC_QDSS_AT_CLK 78 +#define GCC_QDSS_TSCTR_CLK_SRC 79 +#define GCC_NSS_TS_CLK 80 +#define GCC_QPIC_IO_MACRO_CLK_SRC 81 +#define GCC_QPIC_IO_MACRO_CLK 82 +#define GCC_LPASS_AXIM_CLK_SRC 83 +#define GCC_LPASS_CORE_AXIM_CLK 84 +#define GCC_LPASS_SWAY_CLK_SRC 85 +#define GCC_LPASS_SWAY_CLK 86 +#define GCC_CNOC_LPASS_CFG_CLK 87 +#define GCC_SNOC_LPASS_CLK 88 +#define GCC_ADSS_PWM_CLK_SRC 89 +#define GCC_ADSS_PWM_CLK 90 +#define GCC_XO_CLK_SRC 91 +#define GCC_NSSNOC_XO_DCD_CLK 92 +#define GCC_NSSNOC_QOSGEN_REF_CLK 93 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 94 +#define GCC_UNIPHY0_SYS_CLK 95 +#define GCC_UNIPHY1_SYS_CLK 96 +#define GCC_UNIPHY2_SYS_CLK 97 +#define GCC_CMN_12GPLL_SYS_CLK 98 +#define GCC_UNIPHY_SYS_CLK_SRC 99 +#define GCC_NSS_TS_CLK_SRC 100 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 101 +#define GCC_ANOC_PCIE1_1LANE_M_CLK 102 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 103 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 104 +#define GCC_CNOC_PCIE0_1LANE_S_CLK 105 +#define GCC_CNOC_PCIE1_1LANE_S_CLK 106 +#define GCC_CNOC_PCIE2_2LANE_S_CLK 107 +#define GCC_CNOC_PCIE3_2LANE_S_CLK 108 +#define GCC_CNOC_USB_CLK 109 +#define GCC_CNOC_WCSS_AHB_CLK 110 +#define GCC_QUPV3_AHB_MST_CLK 111 +#define GCC_QUPV3_AHB_SLV_CLK 112 +#define GCC_QUPV3_I2C0_CLK 113 +#define GCC_QUPV3_I2C1_CLK 114 +#define GCC_QUPV3_SPI0_CLK 115 +#define GCC_QUPV3_SPI1_CLK 116 +#define GCC_QUPV3_UART0_CLK 117 +#define GCC_QUPV3_UART1_CLK 118 +#define GCC_QPIC_CLK_SRC 119 +#define GCC_QUPV3_I2C0_CLK_SRC 120 +#define GCC_QUPV3_I2C1_CLK_SRC 121 +#define GCC_QUPV3_I2C0_DIV_CLK_SRC 122 +#define GCC_QUPV3_I2C1_DIV_CLK_SRC 123 +#define GCC_QUPV3_SPI0_CLK_SRC 124 +#define GCC_QUPV3_SPI1_CLK_SRC 125 +#define GCC_QUPV3_UART0_CLK_SRC 126 +#define GCC_QUPV3_UART1_CLK_SRC 127 +#define GCC_USB1_MASTER_CLK 128 +#define GCC_USB1_MOCK_UTMI_CLK_SRC 129 +#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 130 +#define GCC_USB1_MOCK_UTMI_CLK 131 +#define GCC_USB1_SLEEP_CLK 132 +#define GCC_USB1_PHY_CFG_AHB_CLK 133 +#define GCC_USB0_MASTER_CLK_SRC 134 +#define GCC_QDSS_DAP_CLK 135 +#define GCC_PCIE0_RCHNG_CLK_SRC 136 +#define GCC_PCIE0_RCHNG_CLK 137 +#define GCC_PCIE1_RCHNG_CLK_SRC 138 +#define GCC_PCIE1_RCHNG_CLK 139 +#define GCC_PCIE2_RCHNG_CLK_SRC 140 +#define GCC_PCIE2_RCHNG_CLK 141 +#define GCC_PCIE3_RCHNG_CLK_SRC 142 +#define GCC_PCIE3_RCHNG_CLK 143 +#define GCC_IM_SLEEP_CLK 144 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq5424-gcc.h b/include/dt-bindings/reset/qcom,ipq5424-gcc.h new file mode 100644 index 000000000000..16a72771c79a --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5424-gcc.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H + +#define GCC_QUPV3_BCR 0 +#define GCC_QUPV3_I2C0_BCR 1 +#define GCC_QUPV3_UART0_BCR 2 +#define GCC_QUPV3_I2C1_BCR 3 +#define GCC_QUPV3_UART1_BCR 4 +#define GCC_QUPV3_SPI0_BCR 5 +#define GCC_QUPV3_SPI1_BCR 6 +#define GCC_IMEM_BCR 7 +#define GCC_TME_BCR 8 +#define GCC_DDRSS_BCR 9 +#define GCC_PRNG_BCR 10 +#define GCC_BOOT_ROM_BCR 11 +#define GCC_NSS_BCR 12 +#define GCC_MDIO_BCR 13 +#define GCC_UNIPHY0_BCR 14 +#define GCC_UNIPHY1_BCR 15 +#define GCC_UNIPHY2_BCR 16 +#define GCC_WCSS_BCR 17 +#define GCC_SEC_CTRL_BCR 19 +#define GCC_TME_SEC_BUS_BCR 20 +#define GCC_ADSS_BCR 21 +#define GCC_LPASS_BCR 22 +#define GCC_PCIE0_BCR 23 +#define GCC_PCIE0_LINK_DOWN_BCR 24 +#define GCC_PCIE0PHY_PHY_BCR 25 +#define GCC_PCIE0_PHY_BCR 26 +#define GCC_PCIE1_BCR 27 +#define GCC_PCIE1_LINK_DOWN_BCR 28 +#define GCC_PCIE1PHY_PHY_BCR 29 +#define GCC_PCIE1_PHY_BCR 30 +#define GCC_PCIE2_BCR 31 +#define GCC_PCIE2_LINK_DOWN_BCR 32 +#define GCC_PCIE2PHY_PHY_BCR 33 +#define GCC_PCIE2_PHY_BCR 34 +#define GCC_PCIE3_BCR 35 +#define GCC_PCIE3_LINK_DOWN_BCR 36 +#define GCC_PCIE3PHY_PHY_BCR 37 +#define GCC_PCIE3_PHY_BCR 38 +#define GCC_USB_BCR 39 +#define GCC_QUSB2_0_PHY_BCR 40 +#define GCC_USB0_PHY_BCR 41 +#define GCC_USB3PHY_0_PHY_BCR 42 +#define GCC_QDSS_BCR 43 +#define GCC_SNOC_BCR 44 +#define GCC_ANOC_BCR 45 +#define GCC_PCNOC_BCR 46 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 47 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 49 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 50 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 51 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 52 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 53 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 54 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 55 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 56 +#define GCC_QPIC_BCR 57 +#define GCC_SDCC_BCR 58 +#define GCC_DCC_BCR 59 +#define GCC_SPDM_BCR 60 +#define GCC_MPM_BCR 61 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 62 +#define GCC_RBCPR_BCR 63 +#define GCC_CMN_BLK_BCR 64 +#define GCC_TCSR_BCR 65 +#define GCC_TLMM_BCR 66 +#define GCC_QUPV3_AHB_MST_ARES 67 +#define GCC_QUPV3_CORE_ARES 68 +#define GCC_QUPV3_2X_CORE_ARES 69 +#define GCC_QUPV3_SLEEP_ARES 70 +#define GCC_QUPV3_AHB_SLV_ARES 71 +#define GCC_QUPV3_I2C0_ARES 72 +#define GCC_QUPV3_UART0_ARES 73 +#define GCC_QUPV3_I2C1_ARES 74 +#define GCC_QUPV3_UART1_ARES 75 +#define GCC_QUPV3_SPI0_ARES 76 +#define GCC_QUPV3_SPI1_ARES 77 +#define GCC_DEBUG_ARES 78 +#define GCC_GP1_ARES 79 +#define GCC_GP2_ARES 80 +#define GCC_GP3_ARES 81 +#define GCC_IMEM_AXI_ARES 82 +#define GCC_IMEM_CFG_AHB_ARES 83 +#define GCC_TME_ARES 84 +#define GCC_TME_TS_ARES 85 +#define GCC_TME_SLOW_ARES 86 +#define GCC_TME_RTC_TOGGLE_ARES 87 +#define GCC_TIC_ARES 88 +#define GCC_PRNG_AHB_ARES 89 +#define GCC_BOOT_ROM_AHB_ARES 90 +#define GCC_NSSNOC_ATB_ARES 91 +#define GCC_NSS_TS_ARES 92 +#define GCC_NSSNOC_QOSGEN_REF_ARES 93 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 94 +#define GCC_NSSNOC_MEMNOC_ARES 95 +#define GCC_NSSNOC_SNOC_ARES 96 +#define GCC_NSSCFG_ARES 97 +#define GCC_NSSNOC_NSSCC_ARES 98 +#define GCC_NSSCC_ARES 99 +#define GCC_MDIO_AHB_ARES 100 +#define GCC_UNIPHY0_SYS_ARES 101 +#define GCC_UNIPHY0_AHB_ARES 102 +#define GCC_UNIPHY1_SYS_ARES 103 +#define GCC_UNIPHY1_AHB_ARES 104 +#define GCC_UNIPHY2_SYS_ARES 105 +#define GCC_UNIPHY2_AHB_ARES 106 +#define GCC_NSSNOC_XO_DCD_ARES 107 +#define GCC_NSSNOC_SNOC_1_ARES 108 +#define GCC_NSSNOC_PCNOC_1_ARES 109 +#define GCC_NSSNOC_MEMNOC_1_ARES 110 +#define GCC_DDRSS_ATB_ARES 111 +#define GCC_DDRSS_AHB_ARES 112 +#define GCC_GEMNOC_AHB_ARES 113 +#define GCC_GEMNOC_Q6_AXI_ARES 114 +#define GCC_GEMNOC_NSSNOC_ARES 115 +#define GCC_GEMNOC_SNOC_ARES 116 +#define GCC_GEMNOC_APSS_ARES 117 +#define GCC_GEMNOC_QOSGEN_EXTREF_ARES 118 +#define GCC_GEMNOC_TS_ARES 119 +#define GCC_DDRSS_SMS_SLOW_ARES 120 +#define GCC_GEMNOC_CNOC_ARES 121 +#define GCC_GEMNOC_XO_DBG_ARES 122 +#define GCC_GEMNOC_ANOC_ARES 123 +#define GCC_DDRSS_LLCC_ATB_ARES 124 +#define GCC_LLCC_TPDM_CFG_ARES 125 +#define GCC_TME_BUS_ARES 126 +#define GCC_SEC_CTRL_ACC_ARES 127 +#define GCC_SEC_CTRL_ARES 128 +#define GCC_SEC_CTRL_SENSE_ARES 129 +#define GCC_SEC_CTRL_AHB_ARES 130 +#define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES 131 +#define GCC_ADSS_PWM_ARES 132 +#define GCC_TME_ATB_ARES 133 +#define GCC_TME_DBGAPB_ARES 134 +#define GCC_TME_DEBUG_ARES 135 +#define GCC_TME_AT_ARES 136 +#define GCC_TME_APB_ARES 137 +#define GCC_TME_DMI_DBG_HS_ARES 138 +#define GCC_APSS_AHB_ARES 139 +#define GCC_APSS_AXI_ARES 140 +#define GCC_CPUSS_TRIG_ARES 141 +#define GCC_APSS_DBG_ARES 142 +#define GCC_APSS_TS_ARES 143 +#define GCC_APSS_ATB_ARES 144 +#define GCC_Q6_AXIM_ARES 145 +#define GCC_Q6_AXIS_ARES 146 +#define GCC_Q6_AHB_ARES 147 +#define GCC_Q6_AHB_S_ARES 148 +#define GCC_Q6SS_ATBM_ARES 149 +#define GCC_Q6_TSCTR_1TO2_ARES 150 +#define GCC_Q6SS_PCLKDBG_ARES 151 +#define GCC_Q6SS_TRIG_ARES 152 +#define GCC_Q6SS_BOOT_CBCR_ARES 153 +#define GCC_WCSS_DBG_IFC_APB_ARES 154 +#define GCC_WCSS_DBG_IFC_ATB_ARES 155 +#define GCC_WCSS_DBG_IFC_NTS_ARES 156 +#define GCC_WCSS_DBG_IFC_DAPBUS_ARES 157 +#define GCC_WCSS_DBG_IFC_APB_BDG_ARES 158 +#define GCC_WCSS_DBG_IFC_NTS_BDG_ARES 159 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES 160 +#define GCC_WCSS_ECAHB_ARES 161 +#define GCC_WCSS_ACMT_ARES 162 +#define GCC_WCSS_AHB_S_ARES 163 +#define GCC_WCSS_AXI_M_ARES 164 +#define GCC_PCNOC_WAPSS_ARES 165 +#define GCC_SNOC_WAPSS_ARES 166 +#define GCC_LPASS_SWAY_ARES 167 +#define GCC_LPASS_CORE_AXIM_ARES 168 +#define GCC_PCIE0_AHB_ARES 169 +#define GCC_PCIE0_AXI_M_ARES 170 +#define GCC_PCIE0_AXI_S_ARES 171 +#define GCC_PCIE0_AXI_S_BRIDGE_ARES 172 +#define GCC_PCIE0_PIPE_ARES 173 +#define GCC_PCIE0_AUX_ARES 174 +#define GCC_PCIE1_AHB_ARES 175 +#define GCC_PCIE1_AXI_M_ARES 176 +#define GCC_PCIE1_AXI_S_ARES 177 +#define GCC_PCIE1_AXI_S_BRIDGE_ARES 178 +#define GCC_PCIE1_PIPE_ARES 179 +#define GCC_PCIE1_AUX_ARES 180 +#define GCC_PCIE2_AHB_ARES 181 +#define GCC_PCIE2_AXI_M_ARES 182 +#define GCC_PCIE2_AXI_S_ARES 183 +#define GCC_PCIE2_AXI_S_BRIDGE_ARES 184 +#define GCC_PCIE2_PIPE_ARES 185 +#define GCC_PCIE2_AUX_ARES 186 +#define GCC_PCIE3_AHB_ARES 187 +#define GCC_PCIE3_AXI_M_ARES 188 +#define GCC_PCIE3_AXI_S_ARES 189 +#define GCC_PCIE3_AXI_S_BRIDGE_ARES 190 +#define GCC_PCIE3_PIPE_ARES 191 +#define GCC_PCIE3_AUX_ARES 192 +#define GCC_USB0_MASTER_ARES 193 +#define GCC_USB0_AUX_ARES 194 +#define GCC_USB0_MOCK_UTMI_ARES 195 +#define GCC_USB0_PIPE_ARES 196 +#define GCC_USB0_SLEEP_ARES 197 +#define GCC_USB0_PHY_CFG_AHB_ARES 198 +#define GCC_QDSS_AT_ARES 199 +#define GCC_QDSS_STM_ARES 200 +#define GCC_QDSS_TRACECLKIN_ARES 201 +#define GCC_QDSS_TSCTR_DIV2_ARES 202 +#define GCC_QDSS_TSCTR_DIV3_ARES 203 +#define GCC_QDSS_TSCTR_DIV4_ARES 204 +#define GCC_QDSS_TSCTR_DIV8_ARES 205 +#define GCC_QDSS_TSCTR_DIV16_ARES 206 +#define GCC_QDSS_DAP_ARES 207 +#define GCC_QDSS_APB2JTAG_ARES 208 +#define GCC_QDSS_ETR_USB_ARES 209 +#define GCC_QDSS_DAP_AHB_ARES 210 +#define GCC_QDSS_CFG_AHB_ARES 211 +#define GCC_QDSS_EUD_AT_ARES 212 +#define GCC_QDSS_TS_ARES 213 +#define GCC_QDSS_USB_ARES 214 +#define GCC_SYS_NOC_AXI_ARES 215 +#define GCC_SNOC_QOSGEN_EXTREF_ARES 216 +#define GCC_CNOC_LPASS_CFG_ARES 217 +#define GCC_SYS_NOC_AT_ARES 218 +#define GCC_SNOC_PCNOC_AHB_ARES 219 +#define GCC_SNOC_TME_ARES 220 +#define GCC_SNOC_XO_DCD_ARES 221 +#define GCC_SNOC_TS_ARES 222 +#define GCC_ANOC0_AXI_ARES 223 +#define GCC_ANOC_PCIE0_1LANE_M_ARES 224 +#define GCC_ANOC_PCIE2_2LANE_M_ARES 225 +#define GCC_ANOC_PCIE1_1LANE_M_ARES 226 +#define GCC_ANOC_PCIE3_2LANE_M_ARES 227 +#define GCC_ANOC_PCNOC_AHB_ARES 228 +#define GCC_ANOC_QOSGEN_EXTREF_ARES 229 +#define GCC_ANOC_XO_DCD_ARES 230 +#define GCC_SNOC_XO_DBG_ARES 231 +#define GCC_AGGRNOC_ATB_ARES 232 +#define GCC_AGGRNOC_TS_ARES 233 +#define GCC_USB0_EUD_AT_ARES 234 +#define GCC_PCNOC_TIC_ARES 235 +#define GCC_PCNOC_AHB_ARES 236 +#define GCC_PCNOC_XO_DBG_ARES 237 +#define GCC_SNOC_LPASS_ARES 238 +#define GCC_PCNOC_AT_ARES 239 +#define GCC_PCNOC_XO_DCD_ARES 240 +#define GCC_PCNOC_TS_ARES 241 +#define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES 242 +#define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES 243 +#define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES 244 +#define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES 245 +#define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES 246 +#define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES 247 +#define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES 248 +#define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES 249 +#define GCC_Q6_AXIM_RESET 250 +#define GCC_Q6_AXIS_RESET 251 +#define GCC_Q6_AHB_S_RESET 252 +#define GCC_Q6_AHB_RESET 253 +#define GCC_Q6SS_DBG_RESET 254 +#define GCC_WCSS_ECAHB_RESET 255 +#define GCC_WCSS_DBG_BDG_RESET 256 +#define GCC_WCSS_DBG_RESET 257 +#define GCC_WCSS_AXI_M_RESET 258 +#define GCC_WCSS_AHB_S_RESET 259 +#define GCC_WCSS_ACMT_RESET 260 +#define GCC_WCSSAON_RESET 261 +#define GCC_PCIE0_PIPE_RESET 262 +#define GCC_PCIE0_CORE_STICKY_RESET 263 +#define GCC_PCIE0_AXI_S_STICKY_RESET 264 +#define GCC_PCIE0_AXI_S_RESET 265 +#define GCC_PCIE0_AXI_M_STICKY_RESET 266 +#define GCC_PCIE0_AXI_M_RESET 267 +#define GCC_PCIE0_AUX_RESET 268 +#define GCC_PCIE0_AHB_RESET 269 +#define GCC_PCIE1_PIPE_RESET 270 +#define GCC_PCIE1_CORE_STICKY_RESET 271 +#define GCC_PCIE1_AXI_S_STICKY_RESET 272 +#define GCC_PCIE1_AXI_S_RESET 273 +#define GCC_PCIE1_AXI_M_STICKY_RESET 274 +#define GCC_PCIE1_AXI_M_RESET 275 +#define GCC_PCIE1_AUX_RESET 276 +#define GCC_PCIE1_AHB_RESET 277 +#define GCC_PCIE2_PIPE_RESET 278 +#define GCC_PCIE2_CORE_STICKY_RESET 279 +#define GCC_PCIE2_AXI_S_STICKY_RESET 280 +#define GCC_PCIE2_AXI_S_RESET 281 +#define GCC_PCIE2_AXI_M_STICKY_RESET 282 +#define GCC_PCIE2_AXI_M_RESET 283 +#define GCC_PCIE2_AUX_RESET 284 +#define GCC_PCIE2_AHB_RESET 285 +#define GCC_PCIE3_PIPE_RESET 286 +#define GCC_PCIE3_CORE_STICKY_RESET 287 +#define GCC_PCIE3_AXI_S_STICKY_RESET 288 +#define GCC_PCIE3_AXI_S_RESET 289 +#define GCC_PCIE3_AXI_M_STICKY_RESET 290 +#define GCC_PCIE3_AXI_M_RESET 291 +#define GCC_PCIE3_AUX_RESET 292 +#define GCC_PCIE3_AHB_RESET 293 +#define GCC_NSS_PARTIAL_RESET 294 +#define GCC_UNIPHY0_XPCS_ARES 295 +#define GCC_UNIPHY1_XPCS_ARES 296 +#define GCC_UNIPHY2_XPCS_ARES 297 +#define GCC_USB1_BCR 298 +#define GCC_QUSB2_1_PHY_BCR 299 + +#endif -- cgit v1.3.1 From 43b53bca61b032270395152ba93d6e9ead47f0de Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 22 Aug 2024 16:57:18 +0530 Subject: dt-bindings: clock: qcom: Add GCC clocks for QCS8300 Add support for qcom global clock controller bindings for QCS8300 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,qcs8300-gcc.yaml | 66 ++++++ include/dt-bindings/clock/qcom,qcs8300-gcc.h | 234 +++++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,qcs8300-gcc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml new file mode 100644 index 000000000000..081bc452081f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300 + +maintainers: + - Taniya Das + - Imran Shaik + +description: | + Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and + power domains on QCS8300 + + See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h + +properties: + compatible: + const: qcom,qcs8300-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: PCIE Phy Auxiliary clock source + - description: First EMAC controller reference clock + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,qcs8300-gcc"; + reg = <0x00100000 0xc7018>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&pcie_phy_aux_clk>, + <&rxc0_ref_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,qcs8300-gcc.h b/include/dt-bindings/clock/qcom,qcs8300-gcc.h new file mode 100644 index 000000000000..a0083b1d2126 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-gcc.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS8300_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QCS8300_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL4 3 +#define GCC_GPLL7 4 +#define GCC_GPLL9 5 +#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 8 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 9 +#define GCC_AHB2PHY0_CLK 10 +#define GCC_AHB2PHY2_CLK 11 +#define GCC_AHB2PHY3_CLK 12 +#define GCC_BOOT_ROM_AHB_CLK 13 +#define GCC_CAMERA_AHB_CLK 14 +#define GCC_CAMERA_HF_AXI_CLK 15 +#define GCC_CAMERA_SF_AXI_CLK 16 +#define GCC_CAMERA_THROTTLE_XO_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 19 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 +#define GCC_DDRSS_GPU_AXI_CLK 21 +#define GCC_DISP_AHB_CLK 22 +#define GCC_DISP_HF_AXI_CLK 23 +#define GCC_DISP_XO_CLK 24 +#define GCC_EDP_REF_CLKREF_EN 25 +#define GCC_EMAC0_AXI_CLK 26 +#define GCC_EMAC0_PHY_AUX_CLK 27 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 28 +#define GCC_EMAC0_PTP_CLK 29 +#define GCC_EMAC0_PTP_CLK_SRC 30 +#define GCC_EMAC0_RGMII_CLK 31 +#define GCC_EMAC0_RGMII_CLK_SRC 32 +#define GCC_EMAC0_SLV_AHB_CLK 33 +#define GCC_GP1_CLK 34 +#define GCC_GP1_CLK_SRC 35 +#define GCC_GP2_CLK 36 +#define GCC_GP2_CLK_SRC 37 +#define GCC_GP3_CLK 38 +#define GCC_GP3_CLK_SRC 39 +#define GCC_GP4_CLK 40 +#define GCC_GP4_CLK_SRC 41 +#define GCC_GP5_CLK 42 +#define GCC_GP5_CLK_SRC 43 +#define GCC_GPU_CFG_AHB_CLK 44 +#define GCC_GPU_GPLL0_CLK_SRC 45 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 46 +#define GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK 47 +#define GCC_GPU_MEMNOC_GFX_CLK 48 +#define GCC_GPU_SNOC_DVM_GFX_CLK 49 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 50 +#define GCC_GPU_TCU_THROTTLE_CLK 51 +#define GCC_PCIE_0_AUX_CLK 52 +#define GCC_PCIE_0_AUX_CLK_SRC 53 +#define GCC_PCIE_0_CFG_AHB_CLK 54 +#define GCC_PCIE_0_MSTR_AXI_CLK 55 +#define GCC_PCIE_0_PHY_AUX_CLK 56 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 57 +#define GCC_PCIE_0_PHY_RCHNG_CLK 58 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 59 +#define GCC_PCIE_0_PIPE_CLK 60 +#define GCC_PCIE_0_PIPE_CLK_SRC 61 +#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 62 +#define GCC_PCIE_0_PIPEDIV2_CLK 63 +#define GCC_PCIE_0_SLV_AXI_CLK 64 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 65 +#define GCC_PCIE_1_AUX_CLK 66 +#define GCC_PCIE_1_AUX_CLK_SRC 67 +#define GCC_PCIE_1_CFG_AHB_CLK 68 +#define GCC_PCIE_1_MSTR_AXI_CLK 69 +#define GCC_PCIE_1_PHY_AUX_CLK 70 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 71 +#define GCC_PCIE_1_PHY_RCHNG_CLK 72 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 73 +#define GCC_PCIE_1_PIPE_CLK 74 +#define GCC_PCIE_1_PIPE_CLK_SRC 75 +#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 76 +#define GCC_PCIE_1_PIPEDIV2_CLK 77 +#define GCC_PCIE_1_SLV_AXI_CLK 78 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 79 +#define GCC_PCIE_CLKREF_EN 80 +#define GCC_PCIE_THROTTLE_CFG_CLK 81 +#define GCC_PDM2_CLK 82 +#define GCC_PDM2_CLK_SRC 83 +#define GCC_PDM_AHB_CLK 84 +#define GCC_PDM_XO4_CLK 85 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 86 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 87 +#define GCC_QMIP_DISP_AHB_CLK 88 +#define GCC_QMIP_DISP_ROT_AHB_CLK 89 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 90 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 91 +#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 92 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 93 +#define GCC_QUPV3_WRAP0_CORE_CLK 94 +#define GCC_QUPV3_WRAP0_S0_CLK 95 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 96 +#define GCC_QUPV3_WRAP0_S1_CLK 97 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 98 +#define GCC_QUPV3_WRAP0_S2_CLK 99 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 100 +#define GCC_QUPV3_WRAP0_S3_CLK 101 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 102 +#define GCC_QUPV3_WRAP0_S4_CLK 103 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 104 +#define GCC_QUPV3_WRAP0_S5_CLK 105 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S6_CLK 107 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S7_CLK 109 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 110 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 111 +#define GCC_QUPV3_WRAP1_CORE_CLK 112 +#define GCC_QUPV3_WRAP1_S0_CLK 113 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 114 +#define GCC_QUPV3_WRAP1_S1_CLK 115 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 116 +#define GCC_QUPV3_WRAP1_S2_CLK 117 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 118 +#define GCC_QUPV3_WRAP1_S3_CLK 119 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 120 +#define GCC_QUPV3_WRAP1_S4_CLK 121 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 122 +#define GCC_QUPV3_WRAP1_S5_CLK 123 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 124 +#define GCC_QUPV3_WRAP1_S6_CLK 125 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 126 +#define GCC_QUPV3_WRAP1_S7_CLK 127 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 128 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 129 +#define GCC_QUPV3_WRAP3_CORE_CLK 130 +#define GCC_QUPV3_WRAP3_QSPI_CLK 131 +#define GCC_QUPV3_WRAP3_S0_CLK 132 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 133 +#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 134 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 135 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 136 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 137 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 138 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 139 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 140 +#define GCC_SDCC1_AHB_CLK 141 +#define GCC_SDCC1_APPS_CLK 142 +#define GCC_SDCC1_APPS_CLK_SRC 143 +#define GCC_SDCC1_ICE_CORE_CLK 144 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 145 +#define GCC_SGMI_CLKREF_EN 146 +#define GCC_UFS_PHY_AHB_CLK 147 +#define GCC_UFS_PHY_AXI_CLK 148 +#define GCC_UFS_PHY_AXI_CLK_SRC 149 +#define GCC_UFS_PHY_ICE_CORE_CLK 150 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 151 +#define GCC_UFS_PHY_PHY_AUX_CLK 152 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 153 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 154 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 155 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 156 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 157 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 158 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 159 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 160 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 161 +#define GCC_USB20_MASTER_CLK 162 +#define GCC_USB20_MASTER_CLK_SRC 163 +#define GCC_USB20_MOCK_UTMI_CLK 164 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 165 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 166 +#define GCC_USB20_SLEEP_CLK 167 +#define GCC_USB30_PRIM_MASTER_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 169 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172 +#define GCC_USB30_PRIM_SLEEP_CLK 173 +#define GCC_USB3_PRIM_PHY_AUX_CLK 174 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 177 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 178 +#define GCC_USB_CLKREF_EN 179 +#define GCC_VIDEO_AHB_CLK 180 +#define GCC_VIDEO_AXI0_CLK 181 +#define GCC_VIDEO_AXI1_CLK 182 +#define GCC_VIDEO_XO_CLK 183 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_PCIE_0_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_UFS_PHY_GDSC 3 +#define GCC_USB20_PRIM_GDSC 4 +#define GCC_USB30_PRIM_GDSC 5 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_PCIE_0_BCR 1 +#define GCC_PCIE_0_LINK_DOWN_BCR 2 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_0_PHY_BCR 4 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_1_BCR 6 +#define GCC_PCIE_1_LINK_DOWN_BCR 7 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_PHY_BCR 9 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10 +#define GCC_SDCC1_BCR 11 +#define GCC_UFS_PHY_BCR 12 +#define GCC_USB20_PRIM_BCR 13 +#define GCC_USB2_PHY_PRIM_BCR 14 +#define GCC_USB2_PHY_SEC_BCR 15 +#define GCC_USB30_PRIM_BCR 16 +#define GCC_USB3_DP_PHY_PRIM_BCR 17 +#define GCC_USB3_PHY_PRIM_BCR 18 +#define GCC_USB3_PHY_TERT_BCR 19 +#define GCC_USB3_UNIPHY_MP0_BCR 20 +#define GCC_USB3_UNIPHY_MP1_BCR 21 +#define GCC_USB3PHY_PHY_PRIM_BCR 22 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 23 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 24 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 +#define GCC_VIDEO_BCR 26 +#define GCC_VIDEO_AXI0_CLK_ARES 27 +#define GCC_VIDEO_AXI1_CLK_ARES 28 + +#endif -- cgit v1.3.1 From 5fbe6f51ca987dfbeab3d06144afc2d2cd835c66 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 12 Nov 2024 17:26:18 +0100 Subject: dt-bindings: clock: ti: Convert mux.txt to json-schema Convert the OMAP mux clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. Choose GPL-only license because original binding was also GPL. Signed-off-by: Andreas Kemnade Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20241112162618.400194-1-andreas@kemnade.info Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ti/composite.txt | 2 +- Documentation/devicetree/bindings/clock/ti/mux.txt | 78 ------------- .../devicetree/bindings/clock/ti/ti,mux-clock.yaml | 125 +++++++++++++++++++++ 3 files changed, 126 insertions(+), 79 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt create mode 100644 Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt index b02f22490dcb..238e6f7d74f8 100644 --- a/Documentation/devicetree/bindings/clock/ti/composite.txt +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -16,7 +16,7 @@ merged to this clock. The component clocks shall be of one of the "ti,*composite*-clock" types. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/mux.txt +[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml [3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml [4] Documentation/devicetree/bindings/clock/ti/gate.txt diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt deleted file mode 100644 index cd56d3c1c09f..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ /dev/null @@ -1,78 +0,0 @@ -Binding for TI mux clock. - -This binding uses the common clock binding[1]. It assumes a -register-mapped multiplexer with multiple input clock signals or -parents, one of which can be selected as output. This clock does not -gate or adjust the parent rate via a divider or multiplier. - -By default the "clocks" property lists the parents in the same order -as they are programmed into the register. E.g: - - clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; - -results in programming the register as follows: - -register value selected parent clock -0 foo_clock -1 bar_clock -2 baz_clock - -Some clock controller IPs do not allow a value of zero to be programmed -into the register, instead indexing begins at 1. The optional property -"index-starts-at-one" modified the scheme as follows: - -register value selected clock parent -1 foo_clock -2 bar_clock -3 baz_clock - -The binding must provide the register to control the mux. Optionally -the number of bits to shift the control field in the register can be -supplied. If the shift value is missing it is the same as supplying -a zero shift. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks -- reg : register offset for register controlling adjustable mux - -Optional properties: -- clock-output-names : from common clock binding. -- ti,bit-shift : number of bits to shift the bit-mask, defaults to - 0 if not present -- ti,index-starts-at-one : valid input select programming starts at 1, not - zero -- ti,set-rate-parent : clk_set_rate is propagated to parent clock, - not supported by the composite-mux-clock subtype -- ti,latch-bit : latch the mux value to HW, only needed if the register - access requires this. As an example, dra7x DPLL_GMAC H14 muxing - implements such behavior. - -Examples: - -sys_clkin_ck: sys_clkin_ck@4a306110 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; - reg = <0x0110>; - ti,index-starts-at-one; -}; - -abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&sys_32k_ck>; - ti,bit-shift = <24>; - reg = <0x0108>; -}; - -mcbsp5_mux_fck: mcbsp5_mux_fck { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; - reg = <0x02d8>; -}; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml new file mode 100644 index 000000000000..485b6aae85d4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments mux clock + +maintainers: + - Tero Kristo + +description: | + This clock assumes a register-mapped multiplexer with multiple inpt clock + signals or parents, one of which can be selected as output. This clock does + not gate or adjust the parent rate via a divider or multiplier. + + By default the "clocks" property lists the parents in the same order + as they are programmed into the register. E.g: + + clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; + + Results in programming the register as follows: + + register value selected parent clock + 0 foo_clock + 1 bar_clock + 2 baz_clock + + Some clock controller IPs do not allow a value of zero to be programmed + into the register, instead indexing begins at 1. The optional property + "index-starts-at-one" modified the scheme as follows: + + register value selected clock parent + 1 foo_clock + 2 bar_clock + 3 baz_clock + + The binding must provide the register to control the mux. Optionally + the number of bits to shift the control field in the register can be + supplied. If the shift value is missing it is the same as supplying + a zero shift. + +properties: + compatible: + enum: + - ti,mux-clock + - ti,composite-mux-clock + + "#clock-cells": + const: 0 + + clocks: true + + clock-output-names: + maxItems: 1 + + reg: + maxItems: 1 + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of bits to shift the bit-mask + maximum: 31 + default: 0 + + ti,index-starts-at-one: + type: boolean + description: + Valid input select programming starts at 1, not zero + + ti,set-rate-parent: + type: boolean + description: + clk_set_rate is propagated to parent clock, + not supported by the composite-mux-clock subtype. + + ti,latch-bit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Latch the mux value to HW, only needed if the register + access requires this. As an example, dra7x DPLL_GMAC H14 muxing + implements such behavior. + maximum: 31 + +if: + properties: + compatible: + contains: + const: ti,composite-mux-clock +then: + properties: + ti,set-rate-parent: false + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock-controller@110 { + compatible = "ti,mux-clock"; + reg = <0x0110>; + #clock-cells = <0>; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>; + ti,index-starts-at-one; + ti,set-rate-parent; + }; + + clock-controller@120 { + compatible = "ti,composite-mux-clock"; + reg = <0x0120>; + #clock-cells = <0>; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + }; -- cgit v1.3.1 From 0c193c2424daebffdfc64e5c0a5544b02867702e Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Thu, 14 Nov 2024 09:26:00 +0200 Subject: dt-bindings: clock: actions,owl-cmu: convert to YAML Convert the Actions Semi Owl CMU bindings to DT schema. Changes during conversion: - Since all Actions Semi Owl SoCs utilize the internal low frequency oscillator as a parent for some clocks, require it. Signed-off-by: Ivaylo Ivanov Reviewed-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20241114072601.265011-1-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/actions,owl-cmu.txt | 52 ------------------- .../devicetree/bindings/clock/actions,owl-cmu.yaml | 60 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 61 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/actions,owl-cmu.txt create mode 100644 Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt b/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt deleted file mode 100644 index d19885b7c73f..000000000000 --- a/Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Actions Semi Owl Clock Management Unit (CMU) - -The Actions Semi Owl Clock Management Unit generates and supplies clock -to various controllers within the SoC. The clock binding described here is -applicable to S900, S700 and S500 SoC's. - -Required Properties: - -- compatible: should be one of the following, - "actions,s900-cmu" - "actions,s700-cmu" - "actions,s500-cmu" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: Reference to the parent clocks ("hosc", "losc") -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier, and client nodes can use this identifier -to specify the clock which they consume. - -All available clocks are defined as preprocessor macros in corresponding -dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or -actions,s500-cmu.h header and can be used in device tree sources. - -External clocks: - -The hosc clock used as input for the plls is generated outside the SoC. It is -expected that it is defined using standard clock bindings as "hosc". - -Actions Semi S900 CMU also requires one more clock: - - "losc" - internal low frequency oscillator - -Example: Clock Management Unit node: - - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; - reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes clock generated by the clock -management unit: - - uart: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - interrupts = ; - clocks = <&cmu CLK_UART5>; - }; diff --git a/Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml b/Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml new file mode 100644 index 000000000000..28396441bc98 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi Owl Clock Management Unit (CMU) + +maintainers: + - Manivannan Sadhasivam + +description: | + The Actions Semi Owl Clock Management Unit generates and supplies clock + to various controllers within the SoC. + + See also: + include/dt-bindings/clock/actions,s500-cmu.h + include/dt-bindings/clock/actions,s700-cmu.h + include/dt-bindings/clock/actions,s900-cmu.h + +properties: + compatible: + enum: + - actions,s500-cmu + - actions,s700-cmu + - actions,s900-cmu + + reg: + maxItems: 1 + + clocks: + items: + - description: Host oscillator source + - description: Internal low frequency oscillator source + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@e0160000 { + compatible = "actions,s900-cmu"; + reg = <0xe0160000 0x1000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f..0e2489f8a758 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1996,7 +1996,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-actions@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/actions.yaml -F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt +F: Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml F: Documentation/devicetree/bindings/dma/owl-dma.yaml F: Documentation/devicetree/bindings/i2c/i2c-owl.yaml F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml -- cgit v1.3.1 From a7479860bb4099a8eef64999e843c085838248e4 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Wed, 6 Nov 2024 11:14:30 +0000 Subject: dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Add device tree bindings for syscon clock and reset controllers (IMGSYS, MFGCFG, VDECSYS and VENCSYS). Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/mediatek,syscon.yaml | 4 ++++ MAINTAINERS | 6 ++++++ include/dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ include/dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ include/dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ include/dt-bindings/reset/mediatek,mt6735-vdecsys.h | 9 +++++++++ 8 files changed, 71 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index 10483e26878f..a86a64893c67 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -28,6 +28,10 @@ properties: - mediatek,mt2712-mfgcfg - mediatek,mt2712-vdecsys - mediatek,mt2712-vencsys + - mediatek,mt6735-imgsys + - mediatek,mt6735-mfgcfg + - mediatek,mt6735-vdecsys + - mediatek,mt6735-vencsys - mediatek,mt6765-camsys - mediatek,mt6765-imgsys - mediatek,mt6765-mipi0a diff --git a/MAINTAINERS b/MAINTAINERS index 1c6063dc46ae..c6d4f0c48cda 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14538,11 +14538,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h new file mode 100644 index 000000000000..f250c26c5eb4 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H + +#define CLK_IMG_SMI_LARB2 0 +#define CLK_IMG_CAM_SMI 1 +#define CLK_IMG_CAM_CAM 2 +#define CLK_IMG_SEN_TG 3 +#define CLK_IMG_SEN_CAM 4 +#define CLK_IMG_CAM_SV 5 +#define CLK_IMG_SUFOD 6 +#define CLK_IMG_FD 7 + +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h new file mode 100644 index 000000000000..d2d99a48348a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H + +#define CLK_MFG_BG3D 0 + +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h new file mode 100644 index 000000000000..f94cec10c89f --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H + +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h new file mode 100644 index 000000000000..e5a9cb4f269f --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H + +#define CLK_VENC_SMI_LARB3 0 +#define CLK_VENC_VENC 1 +#define CLK_VENC_JPGENC 2 +#define CLK_VENC_JPGDEC 3 + +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h new file mode 100644 index 000000000000..c489242b226e --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H + +#define MT6735_MFG_RST0_AXI 0 +#define MT6735_MFG_RST0_G3D 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h new file mode 100644 index 000000000000..b6ae5d249192 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H + +#define MT6735_VDEC_RST0_VDEC 0 +#define MT6735_VDEC_RST1_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ -- cgit v1.3.1 From 0f7c637d1103d79829dec198e5f1b678c1feb5f2 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Tue, 12 Nov 2024 01:08:48 +0100 Subject: dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC. clk-en7523 driver for EN7581 SoC is mapping all the scu memory region while it is configuring the chip-scu one via a syscon. Update the reg mapping definition for this device. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-1-8ada5e394ae4@kernel.org Reviewed-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- .../bindings/clock/airoha,en7523-scu.yaml | 23 ++++++++-------------- 1 file changed, 8 insertions(+), 15 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 84353fd09428..fe2c5c1baf43 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -34,8 +34,10 @@ properties: - airoha,en7581-scu reg: - minItems: 2 - maxItems: 4 + items: + - description: scu base address + - description: misc scu base address + minItems: 1 "#clock-cells": description: @@ -60,9 +62,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address + minItems: 2 '#reset-cells': false @@ -73,11 +73,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address - - description: reset base address - - description: pb scu base address + maxItems: 1 additionalProperties: false @@ -96,12 +92,9 @@ examples: #address-cells = <2>; #size-cells = <2>; - scuclk: clock-controller@1fa20000 { + scuclk: clock-controller@1fb00000 { compatible = "airoha,en7581-scu"; - reg = <0x0 0x1fa20000 0x0 0x400>, - <0x0 0x1fb00000 0x0 0x90>, - <0x0 0x1fb00830 0x0 0x8>, - <0x0 0x1fbe3400 0x0 0xfc>; + reg = <0x0 0x1fb00000 0x0 0x970>; #clock-cells = <1>; #reset-cells = <1>; }; -- cgit v1.3.1 From f03b086624aa7cfbc6f3bf4ac728639602b4c478 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Mon, 4 Nov 2024 17:37:06 +0100 Subject: dt-bindings: clock: Add Marvell PXA1908 clock bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanović Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-4-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..fb15b0d0cd4c --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif -- cgit v1.3.1 From 47f3f5a82a31527e027929c5cec3dd1ef5ef30f5 Mon Sep 17 00:00:00 2001 From: Nuno Sa Date: Tue, 29 Oct 2024 14:59:41 +0100 Subject: dt-bindings: clock: axi-clkgen: include AXI clk In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one and add clock-names to differentiate between parent clocks and the bus clock. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-1-bc5e0733ad76@analog.com Reviewed-by: Conor Dooley Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml index 5e942bccf277..2b2041818a0a 100644 --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -26,9 +26,21 @@ properties: description: Specifies the reference clock(s) from which the output frequency is derived. This must either reference one clock if only the first clock - input is connected or two if both clock inputs are connected. - minItems: 1 - maxItems: 2 + input is connected or two if both clock inputs are connected. The last + clock is the AXI bus clock that needs to be enabled so we can access the + core registers. + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: clkin1 + - const: s_axi_aclk + - items: + - const: clkin1 + - const: clkin2 + - const: s_axi_aclk '#clock-cells': const: 0 @@ -40,6 +52,7 @@ required: - compatible - reg - clocks + - clock-names - '#clock-cells' additionalProperties: false @@ -50,5 +63,6 @@ examples: compatible = "adi,axi-clkgen-2.00.a"; #clock-cells = <0>; reg = <0xff000000 0x1000>; - clocks = <&osc 1>; + clocks = <&osc 1>, <&clkc 15>; + clock-names = "clkin1", "s_axi_aclk"; }; -- cgit v1.3.1 From a370b2d22dc0a68631fadca5080cd78fa99e4284 Mon Sep 17 00:00:00 2001 From: Théo Lebrun Date: Wed, 6 Nov 2024 17:03:52 +0100 Subject: dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some compatibles expose a single clock. For those, we used to let them using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>). Switch away from that: enforce a cell for all compatibles. This is more straight forward, and avoids devicetree changes whenever a compatible goes from exposing a single clock to multiple ones. Also, dt-bindings get simpler. *This is an ABI break*. Change it while EyeQ5 platform support is at its infancy, without any user. More clocks might hide in each OLB as some registers are still unknown. Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring (Arm) Signed-off-by: Stephen Boyd --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 24 +--------------------- 1 file changed, 1 insertion(+), 23 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml index f7e606d45ebc..6d11472ba5a7 100644 --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -41,9 +41,7 @@ properties: enum: [ 1, 2 ] '#clock-cells': - description: - Cell is clock index. Optional if compatible has a single clock. - enum: [ 0, 1 ] + const: 1 clocks: maxItems: 1 @@ -312,26 +310,6 @@ allOf: properties: '#reset-cells': false - # Compatibles exposing a single clock. - - if: - properties: - compatible: - contains: - enum: - - mobileye,eyeq6h-central-olb - - mobileye,eyeq6h-east-olb - - mobileye,eyeq6h-west-olb - - mobileye,eyeq6h-ddr0-olb - - mobileye,eyeq6h-ddr1-olb - then: - properties: - '#clock-cells': - const: 0 - else: - properties: - '#clock-cells': - const: 1 - # Only EyeQ5 has pinctrl in OLB. - if: not: -- cgit v1.3.1