From 1d77040bde2d21dc7db575d4b43c1da24c94cca1 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 25 Oct 2016 20:36:56 +0800 Subject: PCI: layerscape: Add LS1046a support Add support for the LS1046a PCIe controller. This device has a different LUT_DBG offset, so add "lut_dbg" to ls_pcie_drvdata to describe this difference. [bhelgaas: changelog, remove now-unused PCIE_LUT_DBG] Signed-off-by: Mingkai Hu Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 41e9f55a1467..ee1c72d5162e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -15,6 +15,7 @@ Required properties: - compatible: should contain the platform identifier such as: "fsl,ls1021a-pcie", "snps,dw-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls1046a-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- cgit v1.2.3-70-g09d2 From 2fa39159b6a9931d6fd82ecbe65357e0ad77e1a4 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 14 Nov 2016 15:20:57 -0600 Subject: Documentation/devicetree: Add PCIe max-link-speed property Some of the host drivers have the requirement of knowing whether the EP would never train at some link speed at all. For instance, on some boards, the link won't train at 5 GT/s but the host driver still sacrifice some cycles to wait for the result of training at 5 GT/s as the host could actually support 5 GT/s. So we could parse this new property and make the host drivers be aware of these cases. Signed-off-by: Shawn Lin Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 08dcfad09f8d..50f9e2ca5b13 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -18,3 +18,9 @@ driver implementation may support the following properties: host bridges in the system, otherwise potentially conflicting domain numbers may be assigned to root buses behind different host bridges. The domain number for each host bridge in the system must be unique. +- max-link-speed: + If present this property specifies PCI gen for link capability. Host + drivers could add this as a strategy to avoid unnecessary operation for + unsupported link speed, for instance, trying to do training for + unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' + for gen2, and '1' for gen1. Any other values are invalid. -- cgit v1.2.3-70-g09d2 From f29224ae95c9805256ca99d425a29fe7eb7f1395 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 31 Oct 2016 17:38:34 -0700 Subject: PCI: iproc: Add PAXCv2 related binding Add new compatible string "brcm,iproc-pcie-paxc-v2" to the iProc PCIe device tree binding document. "brcm,iproc-pcie-paxc-v2" is for the second generation of the Broadcom iProc PCIe PAXC host controller. Update the binding document with more detailed description of each compatible string and compatible SoCs. Add description of optional property "msi-map", for use with MSI controllers with sideband data. Signed-off-by: Ray Jui Signed-off-by: Bjorn Helgaas Reviewed-by: Scott Branden --- .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 31 ++++++++++++++++------ 1 file changed, 23 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index 01b88f4e0d5b..071bbc24ad20 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -1,10 +1,15 @@ * Broadcom iProc PCIe controller with the platform bus interface Required properties: -- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc" - for PAXC. PAXB-based root complex is used for external endpoint devices. - PAXC-based root complex is connected to emulated endpoint devices - internal to the ASIC +- compatible: + "brcm,iproc-pcie" for the first generation of PAXB based controller, +used in SoCs including NSP, Cygnus, NS2, and Pegasus + "brcm,iproc-pcie-paxc" for the first generation of PAXC based +controller, used in NS2 + "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based +controller, used in Stingray + PAXB-based root complex is used for external endpoint devices. PAXC-based +root complex is connected to emulated endpoint devices internal to the ASIC - reg: base address and length of the PCIe controller I/O register space - #interrupt-cells: set to <1> - interrupt-map-mask and interrupt-map, standard PCI properties to define the @@ -19,6 +24,7 @@ Required properties: Optional properties: - phys: phandle of the PCIe PHY device - phy-names: must be "pcie-phy" +- dma-coherent: present if DMA operations are coherent - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done by the ASIC after power on reset. In this case, SW needs to configure it @@ -41,10 +47,19 @@ For older platforms without MSI integrated in the GIC, iProc PCIe core provides an event queue based MSI support. The iProc MSI uses host memories to store MSI posted writes in the event queues -- msi-parent: Link to the device node of the MSI controller. On newer iProc -platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc -platforms without MSI support in its interrupt controller, one may use the -event queue based MSI support integrated within the iProc PCIe core. +On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used + +- msi-map: Maps a Requester ID to an MSI controller and associated MSI +sideband data + +- msi-parent: Link to the device node of the MSI controller, used when no MSI +sideband data is passed between the iProc PCIe controller and the MSI +controller + +Refer to the following binding documents for more detailed description on +the use of 'msi-map' and 'msi-parent': + Documentation/devicetree/bindings/pci/pci-msi.txt + Documentation/devicetree/bindings/interrupt-controller/msi.txt When the iProc event queue based MSI is used, one needs to define the following properties in the MSI device node: -- cgit v1.2.3-70-g09d2 From 8bfdccdb4bcc9fabc968846296206c85f65e91ce Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 31 Oct 2016 17:38:36 -0700 Subject: PCI: iproc: Remove redundant outbound properties Remove the following outbound related device tree properties: brcm,pcie-ob-window-size brcm,pcie-ob-oarr-size The above two properties are a bit duplicated in functions. In addition, the next generation iProc PCIe controller has outbound mapping window that supports more than just two sizes, which cannot be properly supported by these properties. [bhelgaas: changelog] Signed-off-by: Ray Jui Signed-off-by: Bjorn Helgaas Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 7 ------- 1 file changed, 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index 071bbc24ad20..f827b8d394e2 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -35,11 +35,6 @@ effective: Required: - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal address used by the iProc PCIe core (not the PCIe address) -- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB) - -Optional: -- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to -increase the outbound window size MSI support (optional): @@ -95,9 +90,7 @@ Example: phy-names = "pcie-phy"; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x00000000>; - brcm,pcie-ob-window-size = <256>; msi-parent = <&msi0>; -- cgit v1.2.3-70-g09d2 From 3589c66cca7f0fd76861b40e7ca7d01c82bfe9c3 Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 31 Oct 2016 17:38:38 -0700 Subject: PCI: iproc: Add optional dma-ranges Add description for optional device tree property 'dma-ranges' for inbound mapping. Signed-off-by: Oza Oza Signed-off-by: Ray Jui Signed-off-by: Bjorn Helgaas Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index f827b8d394e2..5dbfb82ef88c 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -25,6 +25,9 @@ Optional properties: - phys: phandle of the PCIe PHY device - phy-names: must be "pcie-phy" - dma-coherent: present if DMA operations are coherent +- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done + by the ASIC after power on reset. In this case, SW is required to configure +the mapping, based on inbound memory regions specified by this property. - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done by the ASIC after power on reset. In this case, SW needs to configure it -- cgit v1.2.3-70-g09d2 From 702ed3be1b1bf4dea05954168321741c0910c645 Mon Sep 17 00:00:00 2001 From: Emil Velikov Date: Mon, 21 Nov 2016 16:24:49 -0600 Subject: PCI: Create revision file in sysfs Currently the revision isn't available via sysfs/libudev thus if one wants to know the value one needs to read through the config file, which can be quite time-consuming because it wakes/powers up the device. There are at least two userspace components which could make use the new file: libpciaccess and libdrm. The former wakes up _every_ PCI device, which can be observed via glxinfo when using Mesa 10.0+ drivers. The latter, in association with Mesa 13.0, can lead to 2-3 second delays while starting firefox, thunderbird or chromium. Link: https://bugs.freedesktop.org/show_bug.cgi?id=98502 Tested-by: Mauro Santos Signed-off-by: Emil Velikov Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Reviewed-by: Daniel Vetter --- Documentation/ABI/testing/sysfs-bus-pci | 7 +++++++ Documentation/filesystems/sysfs-pci.txt | 2 ++ drivers/pci/pci-sysfs.c | 2 ++ 3 files changed, 11 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index b3bc50f650ee..5a1732b78707 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -294,3 +294,10 @@ Description: a firmware bug to the system vendor. Writing to this file taints the kernel with TAINT_FIRMWARE_WORKAROUND, which reduces the supportability of your system. + +What: /sys/bus/pci/devices/.../revision +Date: November 2016 +Contact: Emil Velikov +Description: + This file contains the revision field of the the PCI device. + The value comes from device config space. The file is read only. diff --git a/Documentation/filesystems/sysfs-pci.txt b/Documentation/filesystems/sysfs-pci.txt index 74eaac26f8b8..6ea1ceda6f52 100644 --- a/Documentation/filesystems/sysfs-pci.txt +++ b/Documentation/filesystems/sysfs-pci.txt @@ -17,6 +17,7 @@ that support it. For example, a given bus might look like this: | |-- resource0 | |-- resource1 | |-- resource2 + | |-- revision | |-- rom | |-- subsystem_device | |-- subsystem_vendor @@ -41,6 +42,7 @@ files, each with their own function. resource PCI resource host addresses (ascii, ro) resource0..N PCI resource N, if present (binary, mmap, rw[1]) resource0_wc..N_wc PCI WC map resource N, if prefetchable (binary, mmap) + revision PCI revision (ascii, ro) rom PCI ROM resource, if present (binary, ro) subsystem_device PCI subsystem device (ascii, ro) subsystem_vendor PCI subsystem vendor (ascii, ro) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index bcd10c795284..066628776e1b 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -50,6 +50,7 @@ pci_config_attr(vendor, "0x%04x\n"); pci_config_attr(device, "0x%04x\n"); pci_config_attr(subsystem_vendor, "0x%04x\n"); pci_config_attr(subsystem_device, "0x%04x\n"); +pci_config_attr(revision, "0x%02x\n"); pci_config_attr(class, "0x%06x\n"); pci_config_attr(irq, "%u\n"); @@ -568,6 +569,7 @@ static struct attribute *pci_dev_attrs[] = { &dev_attr_device.attr, &dev_attr_subsystem_vendor.attr, &dev_attr_subsystem_device.attr, + &dev_attr_revision.attr, &dev_attr_class.attr, &dev_attr_irq.attr, &dev_attr_local_cpus.attr, -- cgit v1.2.3-70-g09d2 From f7acf811a0869a847107ee95d62a4c41359e7bbe Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Mon, 31 Oct 2016 17:38:40 -0700 Subject: PCI: iproc: Add PAXBv2 binding info Add new compatible string 'brcm,iproc-pcie-paxb-v2', for the next generation of the iProc PAXB PCIe host controller. Signed-off-by: Oza Oza Signed-off-by: Ray Jui Signed-off-by: Bjorn Helgaas Reviewed-by: Scott Branden --- Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt index 5dbfb82ef88c..b8e48b4762b2 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt @@ -4,6 +4,8 @@ Required properties: - compatible: "brcm,iproc-pcie" for the first generation of PAXB based controller, used in SoCs including NSP, Cygnus, NS2, and Pegasus + "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based +controllers, used in Stingray "brcm,iproc-pcie-paxc" for the first generation of PAXC based controller, used in NS2 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based -- cgit v1.2.3-70-g09d2 From d0491fc39bdd45575cd0094af18703d38665a309 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 22 Nov 2016 10:43:29 +0000 Subject: PCI: qcom: Add support for MSM8996 PCIe controller Add support for the MSM8996/APQ8096 PCIe controller. MSM8996 supports Gen 1/2, one lane, 3 PCIe root complexes with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Add a post_init callback to qcom_pcie_ops, as the PCIe pipe clocks are only setup after the phy is powered on. It also adds an ltssm_enable callback as it is very much different from other supported SoCs in the driver. Signed-off-by: Srinivas Kandagatla Signed-off-by: Bjorn Helgaas Acked-by: Stanimir Varbanov --- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- drivers/pci/host/pcie-qcom.c | 177 ++++++++++++++++++++- 2 files changed, 185 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 4059a6f89bc1..e15f9b19901f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -7,6 +7,7 @@ - "qcom,pcie-ipq8064" for ipq8064 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 + - "qcom,pcie-msm8996" for msm8996 or apq8096 - reg: Usage: required @@ -92,6 +93,17 @@ - "aux" Auxiliary (AUX) clock - "bus_master" Master AXI clock - "bus_slave" Slave AXI clock + +- clock-names: + Usage: required for msm8996/apq8096 + Value type: + Definition: Should contain the following entries + - "pipe" Pipe Clock driving internal logic + - "aux" Auxiliary (AUX) clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - resets: Usage: required Value type: @@ -115,7 +127,7 @@ - "core" Core reset - power-domains: - Usage: required for apq8084 + Usage: required for apq8084 and msm8996/apq8096 Value type: Definition: A phandle and power domain specifier pair to the power domain which is responsible for collapsing diff --git a/drivers/pci/host/pcie-qcom.c b/drivers/pci/host/pcie-qcom.c index ef0a84c7a588..8b02db2da6cc 100644 --- a/drivers/pci/host/pcie-qcom.c +++ b/drivers/pci/host/pcie-qcom.c @@ -36,11 +36,17 @@ #include "pcie-designware.h" +#define PCIE20_PARF_SYS_CTRL 0x00 #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C #define PCIE20_PARF_DBI_BASE_ADDR 0x168 -#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c +#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C +#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 +#define PCIE20_PARF_LTSSM 0x1B0 +#define PCIE20_PARF_SID_OFFSET 0x234 +#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -72,9 +78,18 @@ struct qcom_pcie_resources_v1 { struct regulator *vdda; }; +struct qcom_pcie_resources_v2 { + struct clk *aux_clk; + struct clk *master_clk; + struct clk *slave_clk; + struct clk *cfg_clk; + struct clk *pipe_clk; +}; + union qcom_pcie_resources { struct qcom_pcie_resources_v0 v0; struct qcom_pcie_resources_v1 v1; + struct qcom_pcie_resources_v2 v2; }; struct qcom_pcie; @@ -82,7 +97,9 @@ struct qcom_pcie; struct qcom_pcie_ops { int (*get_resources)(struct qcom_pcie *pcie); int (*init)(struct qcom_pcie *pcie); + int (*post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); + void (*ltssm_enable)(struct qcom_pcie *pcie); }; struct qcom_pcie { @@ -116,17 +133,35 @@ static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg) return dw_handle_msi_irq(pp); } -static int qcom_pcie_establish_link(struct qcom_pcie *pcie) +static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie) { u32 val; - if (dw_pcie_link_up(&pcie->pp)) - return 0; - /* enable link training */ val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE; writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); +} + +static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie) +{ + u32 val; + + /* enable link training */ + val = readl(pcie->parf + PCIE20_PARF_LTSSM); + val |= BIT(8); + writel(val, pcie->parf + PCIE20_PARF_LTSSM); +} + +static int qcom_pcie_establish_link(struct qcom_pcie *pcie) +{ + + if (dw_pcie_link_up(&pcie->pp)) + return 0; + + /* Enable Link Training state machine */ + if (pcie->ops->ltssm_enable) + pcie->ops->ltssm_enable(pcie); return dw_pcie_wait_for_link(&pcie->pp); } @@ -421,6 +456,113 @@ err_res: return ret; } +static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_v2 *res = &pcie->res.v2; + struct device *dev = pcie->pp.dev; + + res->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->cfg_clk = devm_clk_get(dev, "cfg"); + if (IS_ERR(res->cfg_clk)) + return PTR_ERR(res->cfg_clk); + + res->master_clk = devm_clk_get(dev, "bus_master"); + if (IS_ERR(res->master_clk)) + return PTR_ERR(res->master_clk); + + res->slave_clk = devm_clk_get(dev, "bus_slave"); + if (IS_ERR(res->slave_clk)) + return PTR_ERR(res->slave_clk); + + res->pipe_clk = devm_clk_get(dev, "pipe"); + if (IS_ERR(res->pipe_clk)) + return PTR_ERR(res->pipe_clk); + + return 0; +} + +static int qcom_pcie_init_v2(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_v2 *res = &pcie->res.v2; + struct device *dev = pcie->pp.dev; + u32 val; + int ret; + + ret = clk_prepare_enable(res->aux_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable aux clock\n"); + return ret; + } + + ret = clk_prepare_enable(res->cfg_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable cfg clock\n"); + goto err_cfg_clk; + } + + ret = clk_prepare_enable(res->master_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable master clock\n"); + goto err_master_clk; + } + + ret = clk_prepare_enable(res->slave_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable slave clock\n"); + goto err_slave_clk; + } + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* change DBI base address */ + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val &= ~BIT(29); + writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + + val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val |= BIT(4); + writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val |= BIT(31); + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + + return 0; + +err_slave_clk: + clk_disable_unprepare(res->master_clk); +err_master_clk: + clk_disable_unprepare(res->cfg_clk); +err_cfg_clk: + clk_disable_unprepare(res->aux_clk); + + return ret; +} + +static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_v2 *res = &pcie->res.v2; + struct device *dev = pcie->pp.dev; + int ret; + + ret = clk_prepare_enable(res->pipe_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable pipe clock\n"); + return ret; + } + + return 0; +} + static int qcom_pcie_link_up(struct pcie_port *pp) { struct qcom_pcie *pcie = to_qcom_pcie(pp); @@ -429,6 +571,17 @@ static int qcom_pcie_link_up(struct pcie_port *pp) return !!(val & PCI_EXP_LNKSTA_DLLLA); } +static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_v2 *res = &pcie->res.v2; + + clk_disable_unprepare(res->pipe_clk); + clk_disable_unprepare(res->slave_clk); + clk_disable_unprepare(res->master_clk); + clk_disable_unprepare(res->cfg_clk); + clk_disable_unprepare(res->aux_clk); +} + static void qcom_pcie_host_init(struct pcie_port *pp) { struct qcom_pcie *pcie = to_qcom_pcie(pp); @@ -444,6 +597,9 @@ static void qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err_deinit; + if (pcie->ops->post_init) + pcie->ops->post_init(pcie); + dw_pcie_setup_rc(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) @@ -487,12 +643,22 @@ static const struct qcom_pcie_ops ops_v0 = { .get_resources = qcom_pcie_get_resources_v0, .init = qcom_pcie_init_v0, .deinit = qcom_pcie_deinit_v0, + .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable, }; static const struct qcom_pcie_ops ops_v1 = { .get_resources = qcom_pcie_get_resources_v1, .init = qcom_pcie_init_v1, .deinit = qcom_pcie_deinit_v1, + .ltssm_enable = qcom_pcie_v0_v1_ltssm_enable, +}; + +static const struct qcom_pcie_ops ops_v2 = { + .get_resources = qcom_pcie_get_resources_v2, + .init = qcom_pcie_init_v2, + .post_init = qcom_pcie_post_init_v2, + .deinit = qcom_pcie_deinit_v2, + .ltssm_enable = qcom_pcie_v2_ltssm_enable, }; static int qcom_pcie_probe(struct platform_device *pdev) @@ -572,6 +738,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 }, { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 }, + { .compatible = "qcom,pcie-msm8996", .data = &ops_v2 }, { } }; -- cgit v1.2.3-70-g09d2 From 528925c4394f69744b88fc6506640fa8b6e6b56b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Nov 2016 11:57:13 +0100 Subject: dt-bindings: pci: tegra: Add Tegra210 support Add support for the PCI host controller found on Tegra210 SoCs. It is very similar to the variant found on Tegra124, with a couple of small differences regarding the power supplies. Signed-off-by: Thierry Reding Signed-off-by: Bjorn Helgaas --- .../bindings/pci/nvidia,tegra20-pcie.txt | 110 +++++++++++++++++++++ 1 file changed, 110 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index b8cc395fffea..982a74ea6df9 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -110,6 +110,20 @@ Power supplies for Tegra124: - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must supply 1.05 V. +Power supplies for Tegra210: +- Required: + - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must + supply 1.05 V. + - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output + clocks. Must supply 1.8 V. + - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. + - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). + Must supply 3.3 V. + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must + supply 1.8 V. + Root ports are defined as subnodes of the PCIe controller node. Required properties: @@ -436,3 +450,99 @@ Board DTS: status = "okay"; }; }; + +Tegra210: +--------- + +SoC DTSI: + + pcie-controller@01003000 { + compatible = "nvidia,tegra210-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA210_CLK_PCIE>, + <&tegra_car TEGRA210_CLK_AFI>, + <&tegra_car TEGRA210_CLK_PLL_E>, + <&tegra_car TEGRA210_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + +Board DTS: + + pcie-controller@01003000 { + status = "okay"; + + avdd-pll-uerefe-supply = <&avdd_1v05_pll>; + hvddio-pex-supply = <&vdd_1v8>; + dvddio-pex-supply = <&vdd_pex_1v05>; + dvdd-pex-pll-supply = <&vdd_pex_1v05>; + hvdd-pex-pll-e-supply = <&vdd_1v8>; + vddio-pex-ctl-supply = <&vdd_1v8>; + + pci@1,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; + status = "okay"; + }; + + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; + phy-names = "pcie-0"; + status = "okay"; + }; + }; -- cgit v1.2.3-70-g09d2 From 49da21108f773b50b01b9fd0b6ca97b91b6ff216 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 6 Dec 2016 16:51:31 +0100 Subject: PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar Add fallback compatibility string for the R-Car Gen 3 family. This is in keeping with the both the existing fallback compatibility string for the R-Car Gen 2 family and the fallback scheme being adopted wherever appropriate for drivers for Renesas SoCs. Signed-off-by: Simon Horman Signed-off-by: Bjorn Helgaas --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 + drivers/pci/host/pcie-rcar.c | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 6cf99690eef9..eee518db90b9 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -7,6 +7,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c index 85971bc276c6..aca85be101f8 100644 --- a/drivers/pci/host/pcie-rcar.c +++ b/drivers/pci/host/pcie-rcar.c @@ -1078,6 +1078,7 @@ static const struct of_device_id rcar_pcie_of_match[] = { { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 }, { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init }, + { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init }, {}, }; -- cgit v1.2.3-70-g09d2