From 5a5d6753035451027a6ae92f478eb0b07f801348 Mon Sep 17 00:00:00 2001 From: Varshini Rajendran Date: Tue, 3 Sep 2024 12:12:40 +0530 Subject: dt-bindings: interrupt-controller: Add support for sam9x7 aic Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. New compatible is introduced to capture the differences like the number of interrupts supported in the integration of the IP to that of the previous designs. Signed-off-by: Varshini Rajendran Signed-off-by: Thomas Gleixner Acked-by: Rob Herring (Arm) Acked-by: Dharma Balasubiramani Link: https://lore.kernel.org/all/20240903064240.49415-1-varshini.rajendran@microchip.com --- Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml index d4658fe3867c..d671ed884c9e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -23,6 +23,7 @@ properties: - atmel,sama5d3-aic - atmel,sama5d4-aic - microchip,sam9x60-aic + - microchip,sam9x7-aic reg: maxItems: 1 -- cgit v1.3.1 From 3d5fb05e829682fd7d0d08cfcf6415aa50d4cb22 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 10 Oct 2024 00:08:15 +0100 Subject: dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. Also add macros for the NMI and IRQ0-15 interrupts which map the SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be used in the first cell of the interrupt specifiers. For the second cell of the interrupt specifier, since NMI, IRQn and TINTn support different types of interrupts between themselves, add helper macros to make it easier for the user to work out what's available. Signed-off-by: Fabrizio Castro Signed-off-by: Thomas Gleixner Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/all/20241009230817.798582-2-fabrizio.castro.jz@renesas.com --- .../interrupt-controller/renesas,rzv2h-icu.yaml | 278 +++++++++++++++++++++ 1 file changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml new file mode 100644 index 000000000000..d7ef4f1323a7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -0,0 +1,278 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Interrupt Control Unit + +maintainers: + - Fabrizio Castro + - Geert Uytterhoeven + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: + The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, and + TINT), error interrupts, DMAC requests, GPT interrupts, and internal + interrupts. + +properties: + compatible: + const: renesas,r9a09g057-icu # RZ/V2H(P) + + '#interrupt-cells': + description: The first cell is the SPI number of the NMI or the + PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to + specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + minItems: 58 + items: + - description: NMI interrupt + - description: PORT_IRQ0 interrupt + - description: PORT_IRQ1 interrupt + - description: PORT_IRQ2 interrupt + - description: PORT_IRQ3 interrupt + - description: PORT_IRQ4 interrupt + - description: PORT_IRQ5 interrupt + - description: PORT_IRQ6 interrupt + - description: PORT_IRQ7 interrupt + - description: PORT_IRQ8 interrupt + - description: PORT_IRQ9 interrupt + - description: PORT_IRQ10 interrupt + - description: PORT_IRQ11 interrupt + - description: PORT_IRQ12 interrupt + - description: PORT_IRQ13 interrupt + - description: PORT_IRQ14 interrupt + - description: PORT_IRQ15 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Software interrupt, INTA55_0 + - description: Software interrupt, INTA55_1 + - description: Software interrupt, INTA55_2 + - description: Software interrupt, INTA55_3 + - description: Error interrupt to CA55 + - description: GTCCRA compare match/input capture (U0) + - description: GTCCRB compare match/input capture (U0) + - description: GTCCRA compare match/input capture (U1) + - description: GTCCRB compare match/input capture (U1) + + interrupt-names: + minItems: 58 + items: + - const: nmi + - const: port_irq0 + - const: port_irq1 + - const: port_irq2 + - const: port_irq3 + - const: port_irq4 + - const: port_irq5 + - const: port_irq6 + - const: port_irq7 + - const: port_irq8 + - const: port_irq9 + - const: port_irq10 + - const: port_irq11 + - const: port_irq12 + - const: port_irq13 + - const: port_irq14 + - const: port_irq15 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: int-ca55-0 + - const: int-ca55-1 + - const: int-ca55-2 + - const: int-ca55-3 + - const: icu-error-ca55 + - const: gpt-u0-gtciada + - const: gpt-u0-gtciadb + - const: gpt-u1-gtciada + - const: gpt-u1-gtciadb + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g057-icu"; + reg = <0x10400000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; -- cgit v1.3.1 From 37a99ff53d1d913ec5b435cbe977a811b7b37995 Mon Sep 17 00:00:00 2001 From: Kevin Chen Date: Wed, 16 Oct 2024 10:24:09 +0800 Subject: dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC The ASPEED AST27XX interrupt controller(INTC) contains second level and third level interrupt controller. INTC0: The second level INTC, which used to assert GIC if interrupt in INTC1 asserted. INTC1_x: The third level INTC, which used to assert INTC0 if interrupt in modules of INTC asserted. The relationship is like the following: +-----+ +-------+ +---------+---module0 | GIC |---| INTC0 |--+--| INTC1_0 |---module1 | | | | | | |---... +-----+ +-------+ | +---------+---module31 | | +---------+---module0 +---| INTC1_1 |---module1 | | |---... | +---------+---module31 ... | +---------+---module0 +---| INTC1_5 |---module1 | |---... +---------+---module31 Signed-off-by: Kevin Chen Signed-off-by: Thomas Gleixner Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/all/20241016022410.1154574-2-kevin_chen@aspeedtech.com --- .../interrupt-controller/aspeed,ast2700-intc.yaml | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml new file mode 100644 index 000000000000..55636d06a674 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed AST2700 Interrupt Controller + +description: + This interrupt controller hardware is second level interrupt controller that + is hooked to a parent interrupt controller. It's useful to combine multiple + interrupt sources into 1 interrupt to parent interrupt controller. + +maintainers: + - Kevin Chen + +properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + interrupts: + maxItems: 6 + description: | + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable and raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +-------+ +---------+---module0 + | GIC |---| INTC0 |--+--| INTC1_0 |---module2 + | | | | | | |---... + +-----+ +-------+ | +---------+---module31 + | + | +---------+---module0 + +---| INTC1_1 |---module2 + | | |---... + | +---------+---module31 + ... + | +---------+---module0 + +---| INTC1_5 |---module2 + | |---... + +---------+---module31 + + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + interrupt-controller@12101b00 { + compatible = "aspeed,ast2700-intc-ic"; + reg = <0 0x12101b00 0 0x10>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = , + , + , + , + , + ; + }; + }; -- cgit v1.3.1 From 2631c2b8e5c3406af62b60413ea04e155be9ebcc Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 31 Oct 2024 14:08:57 +0800 Subject: dt-bindings: interrupt-controller: Add T-HEAD C900 ACLINT SSWI device Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured T-HEAD ACLINT device. This ACLINT device contains a SSWI device to support fast S-mode IPI. Add necessary compatible string for the T-HEAD ACLINT SSWI device. Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Reviewed-by: Conor Dooley Link: https://lore.kernel.org/all/20241031060859.722258-2-inochiama@gmail.com Link: https://www.xrvm.com/product/xuantie/C920 --- .../thead,c900-aclint-sswi.yaml | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml new file mode 100644 index 000000000000..8d330906bbbd --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +description: + The SSWI device is a part of the THEAD ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a THEAD + platform. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. + +properties: + compatible: + items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; + reg = <0x94000000 0x00004000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + }; +... -- cgit v1.3.1