From ab2866f12ca18747413ba41409231d44e0c6149b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Aug 2022 11:24:47 +0200 Subject: arm64: dts: renesas: r8a779g0: Fix HSCIF0 interrupt number The interrupt number for the HSCIF0 serial port, which serves as the serial console on the White Hawk board, is incorrect, causing userspace to hang immediately as soon as it tries to print something. Kernel output is unaffected, as it is printed using polling. Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/751dcef40d4534e856ed49b1d5b3a3e8d365ec42.1661419377.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 7cbb0de060dd..1c15726cff8b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -85,7 +85,7 @@ "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 96>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, <&scif_clk>; -- cgit v1.2.3-70-g09d2 From a43306faeea860a6e36b1f0e23881ab4bb75943e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:48 +0200 Subject: arm64: dts: renesas: r8a779g0: Add RWDT node Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Thanh Quan. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/187904c279be6654ea3deb11b7250b64dd18c3b5.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 1c15726cff8b..63319fee25d9 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -59,6 +59,17 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779g0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779g0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit v1.2.3-70-g09d2 From 495e36c3a3134b0f3b89f64cd90d3ed722ac0586 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:49 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Enable watchdog timer Enable the watchdog timer on the White Hawk CPU board. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/77a0e29d965032115de1f07ceecb2d5d07db74eb.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index ea4ae4b893ab..9d20d3e10edc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -43,3 +43,8 @@ &scif_clk { clock-frequency = <24000000>; }; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 4cebce2577239fc02fd396327b01db97b2f6e257 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:50 +0200 Subject: arm64: dts: renesas: r8a779g0: Add pinctrl device node Add a device node for the Pin Function Controller on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ecddcadd2fad46b1cf4c9be3ec750f360b9730e4.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 63319fee25d9..71fce6c03af0 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -70,6 +70,15 @@ status = "disabled"; }; + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779g0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, + <0 0xe6068000 0 0x16c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779g0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit v1.2.3-70-g09d2 From 7a8d590de81328537dc43ceebe4ad29cde3dc08b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:51 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Add serial port pin control Complete the description of the serial console and the external serial clock by adding pin control. Based on larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/74c862ef6e46b4af398d9b371ff38fae17b3db05.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 9d20d3e10edc..ba8cc162076c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -40,6 +40,21 @@ status = "okay"; }; +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + hscif0_pins: hscif0 { + groups = "hscif0_data"; + function = "hscif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + &scif_clk { clock-frequency = <24000000>; }; -- cgit v1.2.3-70-g09d2 From ff77ba0514855c106f8683b56a9a79b7464509c3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:52 +0200 Subject: arm64: dts: renesas: r8a779g0: Add I2C nodes Add device nodes for the I2C Bus Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/272fd18fed2d7addfbdb7945ae2134988a7c3a7e.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 84 +++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 71fce6c03af0..475b428ea734 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -100,6 +100,90 @@ #power-domain-cells = <1>; }; + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779g0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779g0", "renesas,rcar-gen4-hscif", -- cgit v1.2.3-70-g09d2 From 77643815b019d3e78b2ca028d701f95df58e7cf3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:53 +0200 Subject: arm64: dts: renesas: white-hawk: Add I2C0 and EEPROMs Enable the I2C0 bus on the White Hawk CPU board, and describe the I2C EEPROMs present on the White Hawk CPU and BreakOut boards. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/d01cada6f2d3e44dd6cb26cfa8e4ce6382f1fbff.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 9 +++++++++ 2 files changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index ba8cc162076c..27daba944a33 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -40,6 +40,21 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -49,6 +64,11 @@ function = "hscif0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index bc0ac109b17c..afa807e4f704 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -20,3 +20,12 @@ stdout-path = "serial0:921600n8"; }; }; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; -- cgit v1.2.3-70-g09d2 From 78c84f468084e844e03ffb13da09ce7decd1659c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:54 +0200 Subject: arm64: dts: renesas: white-hawk: Add CSI/DSI sub-board Add a DTS file for the R-Car V4H White Hawk CSI/DSI sub-board (RTP8A779G0ASKB0SC0SA000), and include it from the main r8a779g0-white-hawk.dts. For now its contents are limited to the Board ID EEPROM. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/265f7782743c539c57906e8207785f8b0d80d5d0.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 1 + 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi new file mode 100644 index 000000000000..ae7522b60e5d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board + * + * Copyright (C) 2022 Glider bv + */ + +&i2c0 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "csi-dsi-sub-board-id"; + reg = <0x52>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index afa807e4f704..07b0675ef6b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" +#include "r8a779g0-white-hawk-csi-dsi.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; -- cgit v1.2.3-70-g09d2 From 9c1277a25fe538595ddc27d214f2cd64c306fdf5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:55 +0200 Subject: arm64: dts: renesas: white-hawk: Add Ethernet sub-board Add a DTS file for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) sub-board (RTP8A779G0ASKB0SE0SA000), and include it from the main r8a779g0-white-hawk.dts. For now its contents are limited to the Board ID EEPROM. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/991600919513dd05a9a7d9c170c6924baf14d1a2.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 1 + 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi new file mode 100644 index 000000000000..4f411f95c674 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) + * sub-board + * + * Copyright (C) 2022 Glider bv + */ + +&i2c0 { + eeprom@53 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board-id"; + reg = <0x53>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index 07b0675ef6b8..e8be90903081 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" #include "r8a779g0-white-hawk-csi-dsi.dtsi" +#include "r8a779g0-white-hawk-ethernet.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; -- cgit v1.2.3-70-g09d2 From 120c7a58388f499b4d165c002fd645fbf501735c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:56 +0200 Subject: arm64: dts: renesas: r8a779g0: Add GPIO nodes Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/81176a5e12a5828cdcdd4b107d0b2e5970232c31.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 135 ++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 475b428ea734..e5f3973b71f7 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -79,6 +79,141 @@ <0 0xe6068000 0 0x16c>; }; + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 29>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6058180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 20>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6058980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 30>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 128 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6060980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 160 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@e6061180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 192 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@e6061980 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6061980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 224 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@e6068180 { + compatible = "renesas,gpio-r8a779g0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6068180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 256 14>; + interrupt-controller; + #interrupt-cells = <2>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779g0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit v1.2.3-70-g09d2 From 60dc0e87fb450da93bce6324e31f5326b04d4185 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:57 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Add GP LEDs Describe the three General Purpose LEDs on the White Hawk CPU board, so they can be used as indicator LEDs. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/007acd941ef925057f1f9b925ed4e339dbd29a74.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 27daba944a33..684c250d3c73 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -7,10 +7,38 @@ #include "r8a779g0.dtsi" +#include +#include + / { model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led-3 { + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ -- cgit v1.2.3-70-g09d2 From 6672f84001dc7c79253e0de891a2bd72e1ae1acc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:58 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Add push switches Describe the three Push Switches on the White Hawk CPU board, so they can be used for user input. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e18d0d5087a514db611295f5d1e13c950cf7dae7.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 684c250d3c73..f2ad18912f83 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -8,12 +8,44 @@ #include "r8a779g0.dtsi" #include +#include #include / { model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW47"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW48"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW49"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; @@ -97,6 +129,11 @@ function = "i2c0"; }; + keys_pins: keys { + pins = "GP_5_0", "GP_5_1", "GP_5_2"; + bias-pull-up; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; -- cgit v1.2.3-70-g09d2 From 848c82db56923a8b0b0218da55e3478df4908186 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:59 +0200 Subject: arm64: dts: renesas: r8a779g0: Add RAVB nodes Add device nodes for the Renesas Ethernet AVB (EtherAVB-IF) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/980e7a62d8dc3a1e2387a2d93a6296625b105506.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 141 ++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index e5f3973b71f7..d70f0600ae5a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -334,6 +334,147 @@ status = "disabled"; }; + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 211>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6810000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 212>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779g0", + "renesas,etheravb-rcar-gen4"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15", "ch16", "ch17", + "ch18", "ch19", "ch20", "ch21", + "ch22", "ch23", "ch24"; + clocks = <&cpg CPG_MOD 213>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- cgit v1.2.3-70-g09d2 From 7bb9e424357b707ff5a58c99ae10f37a3cf5dbbd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:54:00 +0200 Subject: arm64: dts: renesas: white-hawk: Move aliases and chosen The serial console port on White Hawk is located on the CPU board. Hence move the aliases and chosen nodes containing serial console configuration from the main White Hawk DTS file to the DTS file that describes the CPU board. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b03b74f4b5ee3c3e828e753beb334ec43162c132.1662715538.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index f2ad18912f83..e382b2d5c8d4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -15,6 +15,14 @@ model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + aliases { + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index e8be90903081..04a2b6b83e74 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -13,14 +13,6 @@ / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - aliases { - serial0 = &hscif0; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; }; &i2c0 { -- cgit v1.2.3-70-g09d2 From 96f7071d2b757b58e67592ea8d81f226b085feed Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:54:01 +0200 Subject: arm64: dts: renesas: white-hawk-cpu: Add Ethernet support Describe the wiring of the first Ethernet AVB instance to the Micrel KSZ9031RNXVB PHY. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/50a31bc8267ab4c90bff27ef3aca1169f8ebc7ae.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index e382b2d5c8d4..77f0130a2f85 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -16,6 +16,7 @@ compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; aliases { + ethernet0 = &avb0; serial0 = &hscif0; }; @@ -96,6 +97,24 @@ }; }; +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -127,6 +146,24 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; hscif0_pins: hscif0 { groups = "hscif0_data"; function = "hscif0"; -- cgit v1.2.3-70-g09d2 From 5c2b5a284960e2c90325131627413c67423f41ad Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 14 Sep 2022 17:01:29 +0200 Subject: arm64: dts: renesas: spider: Move aliases and chosen The serial console and serial debug ports on Spider are located on the CPU board. Hence move the aliases and chosen nodes containing serial port configuration from the main Spider DTS file to the DTS file that describes the CPU board. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/c03500bb10eae10caeb3f4f97bc979eeee6cce75.1663167551.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 9 --------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 4a876d47f59b..d4e087d1159c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -11,6 +11,15 @@ model = "Renesas Spider CPU board"; compatible = "renesas,spider-cpu", "renesas,r8a779f0"; + aliases { + serial0 = &scif3; + serial1 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 7a7c8ffba711..7aac3f4d319c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -12,15 +12,6 @@ / { model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; compatible = "renesas,spider-breakout", "renesas,spider-cpu", "renesas,r8a779f0"; - - aliases { - serial0 = &scif3; - serial1 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; &i2c4 { -- cgit v1.2.3-70-g09d2 From 567934a8c3cc8a53bb1ebbbc28ffcedf88f0a864 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 13 Sep 2022 02:06:55 +0000 Subject: arm64: dts: renesas: spider-cpu: Add missing bootargs This patch adds missing bootargs for R-Car S4 Spider board. One note is that current Spider board doesn't have Ethernet support yet, but this patch adds standard settings for it, too. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87leqo58ox.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index d4e087d1159c..a45df1041705 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -17,6 +17,7 @@ }; chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:115200n8"; }; -- cgit v1.2.3-70-g09d2 From f4b7dffdc8bdaed2546491c50db6f98286f32738 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 13 Sep 2022 02:07:13 +0000 Subject: arm64: dts: renesas: white-hawk-cpu: Add missing bootargs This patch adds missing bootargs for R-Car V4H White Hawk board. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87k06858oe.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 77f0130a2f85..895f0bd9f754 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -21,6 +21,7 @@ }; chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:921600n8"; }; -- cgit v1.2.3-70-g09d2 From 167720e4bcc83bfc72c717abdfd5d5cd4dc80b61 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 14 Sep 2022 16:15:14 +0200 Subject: arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - CMT, - SDHI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f14fde21270bf8269a61a75fc6e50af2765f2a42.1663164707.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 8539013f5870..ed9400f903c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -247,7 +247,7 @@ cmt0: timer@e60f0000 { compatible = "renesas,r8a779a0-cmt0", - "renesas,rcar-gen3-cmt0"; + "renesas,rcar-gen4-cmt0"; reg = <0 0xe60f0000 0 0x1004>; interrupts = , ; @@ -260,7 +260,7 @@ cmt1: timer@e6130000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = , , @@ -279,7 +279,7 @@ cmt2: timer@e6140000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6140000 0 0x1004>; interrupts = , , @@ -298,7 +298,7 @@ cmt3: timer@e6148000 { compatible = "renesas,r8a779a0-cmt1", - "renesas,rcar-gen3-cmt1"; + "renesas,rcar-gen4-cmt1"; reg = <0 0xe6148000 0 0x1004>; interrupts = , , @@ -2065,7 +2065,7 @@ mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779a0", - "renesas,rcar-gen3-sdhi"; + "renesas,rcar-gen4-sdhi"; reg = <0 0xee140000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779A0_CLK_SD0H>; -- cgit v1.2.3-70-g09d2 From 1ca318459c026eaaf7984edcf6e79eaf0aaea185 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 14 Sep 2022 14:42:11 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc-som: Drop enabling wdt2 WDT CH2 is specifically to check the operation of Cortex-M33 CPU so don't enable WDT2 by default. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220914134211.199631-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index cf3b3d118ef1..2a0feb53f0dc 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -263,8 +263,3 @@ status = "okay"; timeout-sec = <60>; }; - -&wdt2 { - status = "okay"; - timeout-sec = <60>; -}; -- cgit v1.2.3-70-g09d2 From 53072ba67e534ddd208697d3465004738f1d4d61 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 15 Sep 2022 17:52:55 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS Move including the rzg2ul-smarc-som.dtsi from the carrier board rzg2ul-smarc.dtsi to the actual RZ/G2UL SMARC EVK board dts r9a07g043u11-smarc.dts. Also move the SW_SW0_DEV_SEL and SW_ET0_EN_N macros to board dts as they are used by SoM and carrier board DTS/I. This is in preparation of re-using the SoM and carrier board DTSIs for RZ/Five SMARC EVK. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220915165256.352843-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 12 ++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 11 ----------- 2 files changed, 12 insertions(+), 11 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 121e55282d18..059885a01ede 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -6,7 +6,19 @@ */ /dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + #include "r9a07g043.dtsi" +#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f9835c12023e..2a1331ed1a5c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,17 +5,6 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ -/* - * DIP-Switch SW1 setting - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) - * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) - * Please change below macros according to SW1 setting - */ -#define SW_SW0_DEV_SEL 1 -#define SW_ET0_EN_N 1 - -#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -- cgit v1.2.3-70-g09d2 From 4ebf297b93403897668ee003427a9b780023c298 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 16 Sep 2022 11:02:51 +0100 Subject: arm64: dts: renesas: Adjust whitespace around '{' Drop extra space around the '{' sign. No functional changes (same DTB). Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ff6aab388eb7..689aa4ba416b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -619,7 +619,7 @@ interrupts = ; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 35e7255471b8..2283d4fb8736 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -778,7 +778,7 @@ interrupts = ; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g044", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index d27b6c388580..358d4c34465f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -784,7 +784,7 @@ interrupts = ; }; - sdhi0: mmc@11c00000 { + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g054", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; -- cgit v1.2.3-70-g09d2