From 3a361eabbff081dbd63ac5159d1fe85ca3c4a56e Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Sat, 7 Mar 2020 09:47:23 -0800 Subject: ARM: dts: keystone-k2g: Add DSS node Add DT node for DSS. K2G has DSS version 6. Keystone family DSS are somewhat different compered to the old OMAP family DSSes and the binding looks different too. Signed-off-by: Jyri Sarha Signed-off-by: Tomi Valkeinen Signed-off-by: Jyri Sarha Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 1c833105d6c5..08ba31780baa 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -324,6 +324,28 @@ clock-names = "gpio"; }; + dss: dss@02540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = ; + + power-domains = <&k2g_pds 0x2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + max-memory-bandwidth = <230000000>; + }; + edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02700000 0x8000>; -- cgit v1.2.3-70-g09d2 From 7856488bd83b0182548a84d05c07326321ae6138 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Sat, 7 Mar 2020 09:47:24 -0800 Subject: ARM: dts: keystone-k2g-evm: add HDMI video support Add DT nodes for HDMI video support for K2G EVM. The HDMI uses SiI9022 DPI as HDMI encoder. The DSS DPI is connected to SiI9022 HDMI encoder's video input and encoder's output goes to HDMI connector. Signed-off-by: Jyri Sarha Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 101 +++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index b7f10bf94576..db640bab8c1d 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -45,6 +45,19 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &k2g_pinctrl { @@ -89,6 +102,13 @@ >; }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + ecap0_pins: ecap0_pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ @@ -160,6 +180,40 @@ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; + + vout_pins: pinmux_vout_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ + K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ + K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ + K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ + K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ + K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ + K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ + K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ + K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ + K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ + K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ + K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ + K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ + K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ + K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ + K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ + K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ + K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ + K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ + K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ + K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ + K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ + K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ + K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ + K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ + >; + }; }; &uart0 { @@ -357,3 +411,50 @@ pinctrl-0 = <&emac_pins>; status = "okay"; }; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&vout_pins>; + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 155c58f225281a7e4bb675370252477f2f9b9a30 Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Fri, 6 Mar 2020 18:44:12 +0100 Subject: ARM: dts: bcm2711: Update expgpio's GPIO labels The 6th line of the GPIO expander is used to power the board's SD card. Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20200306174413.20634-11-nsaenzjulienne@suse.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index e738de379b8d..685667de30c0 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -66,7 +66,7 @@ "GLOBAL_RESET", "VDD_SD_IO_SEL", "CAM_GPIO", - "", + "SD_PWR_ON", ""; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 8f7a54a74d72c8e5b4023b2ee035508237ee853d Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Fri, 6 Mar 2020 18:44:13 +0100 Subject: ARM: dts: bcm2711: Add vmmc regulator in emmc2 The SD card power can be controlled trough a pin routed into the board's external GPIO expander. Turn that into a regulator and provide it to emmc2. Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20200306174413.20634-12-nsaenzjulienne@suse.de --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 685667de30c0..dd94e92aa7c4 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -53,6 +53,16 @@ 3300000 0x0>; status = "okay"; }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; }; &firmware { @@ -171,6 +181,7 @@ /* EMMC2 is used to drive the SD card */ &emmc2 { vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; broken-cd; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 3ac395a5b3f3b678663fbb58381fdae2b1b57588 Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Tue, 3 Mar 2020 18:32:16 +0100 Subject: ARM: dts: bcm283x: Use firmware PM driver for V3D The register based driver turned out to be unstable, specially on RPi3a+ but not limited to it. While a fix is being worked on, we roll back to using firmware based scheme. Fixes: e1dc2b2e1bef ("ARM: bcm283x: Switch V3D over to using the PM driver instead of firmware") Signed-off-by: Nicolas Saenz Julienne Tested-by: Stefan Wahren Link: https://lore.kernel.org/r/20200303173217.3987-1-nsaenzjulienne@suse.de --- arch/arm/boot/dts/bcm2835-common.dtsi | 1 - arch/arm/boot/dts/bcm2835-rpi-common.dtsi | 12 ++++++++++++ arch/arm/boot/dts/bcm2835.dtsi | 1 + arch/arm/boot/dts/bcm2836.dtsi | 1 + arch/arm/boot/dts/bcm2837.dtsi | 1 + 5 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm2835-rpi-common.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi index 2b1d9d4c0cde..4119271c979d 100644 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-common.dtsi @@ -130,7 +130,6 @@ compatible = "brcm,bcm2835-v3d"; reg = <0x7ec00000 0x1000>; interrupts = <1 10>; - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; }; vc4: gpu { diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi new file mode 100644 index 000000000000..8a55b6cded59 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's + * firmware interface. + */ + +#include + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 53bf4579cc22..0549686134ea 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 82d6c4662ae4..b390006aef79 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2836"; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 9e95fee78e19..0199ec98cd61 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -1,5 +1,6 @@ #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2837"; -- cgit v1.2.3-70-g09d2 From f06f924a65fb3991614fb23a783d4fef9c8d14ea Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Thu, 26 Mar 2020 14:44:57 +0100 Subject: ARM: bcm2835_defconfig: Enable fixed-regulator This regulator is now used to control the SD card's power supply on the Raspberry Pi 4. Suggested-by: Stefan Wahren Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20200326134458.13992-1-nsaenzjulienne@suse.de --- arch/arm/configs/bcm2835_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 38437541ea76..0d5aa4a24c20 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -103,6 +103,7 @@ CONFIG_WATCHDOG=y CONFIG_BCM2835_WDT=y CONFIG_MFD_SYSCON=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y -- cgit v1.2.3-70-g09d2 From 86aeee4d0a4cc5f7a28fe209444887b93a9a47ca Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Thu, 5 Oct 2017 03:59:15 +0200 Subject: ARM: Prepare Realtek RTD1195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce ARCH_REALTEK Kconfig option also for 32-bit Arm. Override the text offset to cope with boot ROM occupying first 0xa800 bytes and further reservations up to 0xf4000 (compare Device Tree). Add a custom machine_desc to enforce memory carveout for I/O registers. Signed-off-by: Andreas Färber --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 3 +++ arch/arm/mach-realtek/Kconfig | 11 +++++++++++ arch/arm/mach-realtek/Makefile | 2 ++ arch/arm/mach-realtek/rtd1195.c | 40 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 59 insertions(+) create mode 100644 arch/arm/mach-realtek/Kconfig create mode 100644 arch/arm/mach-realtek/Makefile create mode 100644 arch/arm/mach-realtek/rtd1195.c (limited to 'arch/arm') diff --git a/MAINTAINERS b/MAINTAINERS index e64e5db31497..3ec2757c78fb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2270,6 +2270,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/realtek.yaml +F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ ARM/RENESAS ARM64 ARCHITECTURE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 66a04f6f4775..cbd6629e7d75 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -698,6 +698,8 @@ source "arch/arm/mach-qcom/Kconfig" source "arch/arm/mach-rda/Kconfig" +source "arch/arm/mach-realtek/Kconfig" + source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 7d5cd0f85461..0fb6de83dd50 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -148,6 +148,8 @@ head-y := arch/arm/kernel/head$(MMUEXT).o textofs-y := 0x00008000 # We don't want the htc bootloader to corrupt kernel during resume textofs-$(CONFIG_PM_H1940) := 0x00108000 +# RTD1195 has Boot ROM at start of address space +textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory ifeq ($(CONFIG_ARCH_SA1100),y) textofs-$(CONFIG_SA1111) := 0x00208000 @@ -208,6 +210,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom machine-$(CONFIG_ARCH_RDA) += rda +machine-$(CONFIG_ARCH_REALTEK) += realtek machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc diff --git a/arch/arm/mach-realtek/Kconfig b/arch/arm/mach-realtek/Kconfig new file mode 100644 index 000000000000..19fdcf093fd1 --- /dev/null +++ b/arch/arm/mach-realtek/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +menuconfig ARCH_REALTEK + bool "Realtek SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select GENERIC_IRQ_CHIP + select RESET_CONTROLLER + help + This enables support for the Realtek RTD1195 SoC family. diff --git a/arch/arm/mach-realtek/Makefile b/arch/arm/mach-realtek/Makefile new file mode 100644 index 000000000000..5382d5bbdd3c --- /dev/null +++ b/arch/arm/mach-realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y += rtd1195.o diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c new file mode 100644 index 000000000000..0381a4447384 --- /dev/null +++ b/arch/arm/mach-realtek/rtd1195.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek RTD1195 + * + * Copyright (c) 2017-2019 Andreas Färber + */ + +#include +#include + +static void __init rtd1195_memblock_remove(phys_addr_t base, phys_addr_t size) +{ + int ret; + + ret = memblock_remove(base, size); + if (ret) + pr_err("Failed to remove memblock %pa (%d)\n", &base, ret); +} + +static void __init rtd1195_reserve(void) +{ + /* Exclude boot ROM from RAM */ + rtd1195_memblock_remove(0x00000000, 0x0000a800); + + /* Exclude peripheral register spaces from RAM */ + rtd1195_memblock_remove(0x18000000, 0x00070000); + rtd1195_memblock_remove(0x18100000, 0x01000000); +} + +static const char *const rtd1195_dt_compat[] __initconst = { + "realtek,rtd1195", + NULL +}; + +DT_MACHINE_START(rtd1195, "Realtek RTD1195") + .dt_compat = rtd1195_dt_compat, + .reserve = rtd1195_reserve, + .l2c_aux_val = 0x0, + .l2c_aux_mask = ~0x0, +MACHINE_END -- cgit v1.2.3-70-g09d2 From 517a77d07c3940074e4d926c8824e74e27881bdc Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Thu, 5 Oct 2017 05:52:52 +0200 Subject: ARM: dts: Prepare Realtek RTD1195 and MeLE X1000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Realtek RTD1195 SoC and MeLE X1000 TV box. Reuse the existing RTD1295 watchdog compatible for now. Reviewed-by: Rob Herring [AF: Fixed r-bus size, fixed GIC, updated memreserve & memory] Signed-off-by: Andreas Färber --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/rtd1195-mele-x1000.dts | 32 ++++++++ arch/arm/boot/dts/rtd1195.dtsi | 130 +++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/rtd1195-mele-x1000.dts create mode 100644 arch/arm/boot/dts/rtd1195.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..d874019c1ff7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -896,6 +896,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \ dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb +dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-mele-x1000.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts new file mode 100644 index 000000000000..e2050cb64474 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195-mele-x1000.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "mele,x1000", "realtek,rtd1195"; + model = "MeLE X1000"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x18000000>, /* up to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi new file mode 100644 index 000000000000..c5713a5ef472 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/memreserve/ 0x00000000 0x0000a800; /* boot code */ +/memreserve/ 0x0000a800 0x000f5800; +/memreserve/ 0x17fff000 0x00001000; + +#include + +/ { + compatible = "realtek,rtd1195"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1000000000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@b000 { + reg = <0x0000b000 0x1000>; + }; + + audio@1b00000 { + reg = <0x01b00000 0x400000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x01ffe000 0x4000>; + }; + + secure@10000000 { + reg = <0x10000000 0x100000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <27000000>; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x18000000 0x18000000 0x00070000>, + <0x18100000 0x18100000 0x01000000>, + <0x80000000 0x80000000 0x80000000>; + + wdt: watchdog@18007680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x18007680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@18007800 { + compatible = "snps,dw-apb-uart"; + reg = <0x18007800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@1801b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1801b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From af19d9b8844f5e4573e59a42914af83200bf86a4 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sat, 23 Nov 2019 18:49:16 +0100 Subject: ARM: dts: rtd1195: Exclude boot ROM from memory ranges MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Carve out 0xa800 for the boot ROM from the /memory@0 node, updating it to /memory@a800, and add it to /soc ranges. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195-mele-x1000.dts | 4 ++-- arch/arm/boot/dts/rtd1195.dtsi | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts index e2050cb64474..c7951b9a2c97 100644 --- a/arch/arm/boot/dts/rtd1195-mele-x1000.dts +++ b/arch/arm/boot/dts/rtd1195-mele-x1000.dts @@ -19,9 +19,9 @@ stdout-path = "serial0:115200n8"; }; - memory@0 { + memory@a800 { device_type = "memory"; - reg = <0x00000000 0x18000000>, /* up to r-bus */ + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ <0x18070000 0x00090000>, /* r-bus to NOR flash */ <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ }; diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index c5713a5ef472..0d7c2be750f6 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -88,7 +88,8 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x18000000 0x18000000 0x00070000>, + ranges = <0x00000000 0x00000000 0x0000a800>, + <0x18000000 0x18000000 0x00070000>, <0x18100000 0x18100000 0x01000000>, <0x80000000 0x80000000 0x80000000>; -- cgit v1.2.3-70-g09d2 From ede8b703750c8cd5bd50feb18a9f300697d3b196 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Fri, 8 Nov 2019 19:22:23 +0100 Subject: ARM: dts: rtd1195: Introduce r-bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Model Realtek's register bus in DT. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------ 1 file changed, 30 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index 0d7c2be750f6..a8f7b9caacba 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -93,28 +93,36 @@ <0x18100000 0x18100000 0x01000000>, <0x80000000 0x80000000 0x80000000>; - wdt: watchdog@18007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x18007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@18007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x18007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; - }; - - uart1: serial@1801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; + rbus: bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x70000>; + + wdt: watchdog@7680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x7680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; }; gic: interrupt-controller@ff011000 { -- cgit v1.2.3-70-g09d2 From 824c46117ae00590ff7f3bccea31eb97b50f8fb9 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sun, 17 Nov 2019 23:28:26 +0100 Subject: ARM: dts: rtd1195: Add Realtek Horseradish EVB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a Device Tree for Realtek's RTD1195 EVB "Horseradish". Signed-off-by: Andreas Färber --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rtd1195-horseradish.dts | 32 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/boot/dts/rtd1195-horseradish.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d874019c1ff7..bf7d016c9d2d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -897,6 +897,7 @@ dtb-$(CONFIG_ARCH_RDA) += \ rda8810pl-orangepi-2g-iot.dtb \ rda8810pl-orangepi-i96.dtb dtb-$(CONFIG_ARCH_REALTEK) += \ + rtd1195-horseradish.dtb \ rtd1195-mele-x1000.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/rtd1195-horseradish.dts new file mode 100644 index 000000000000..9d06d3d34c74 --- /dev/null +++ b/arch/arm/boot/dts/rtd1195-horseradish.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "realtek,horseradish", "realtek,rtd1195"; + model = "Realtek Horseradish EVB"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From c5021279aa71f188780741afb9b50206918d7df9 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 26 Nov 2019 06:43:44 +0100 Subject: ARM: dts: rtd1195: Introduce iso and misc syscon MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group watchdog and UART0 into an Isolation syscon mfd node. Group UART1 into a Miscellaneous syscon mfd node. Cc: James Tai Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 58 +++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index a8f7b9caacba..a74f530dc439 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -100,28 +100,22 @@ #size-cells = <1>; ranges = <0x0 0x18000000 0x70000>; - wdt: watchdog@7680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x7680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@7800 { - compatible = "snps,dw-apb-uart"; - reg = <0x7800 0x400>; - reg-shift = <2>; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; }; - uart1: serial@1b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x1b200 0x100>; - reg-shift = <2>; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; reg-io-width = <4>; - clock-frequency = <27000000>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; }; }; @@ -137,3 +131,31 @@ }; }; }; + +&iso { + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; -- cgit v1.2.3-70-g09d2 From aff13f7cc8697ca95ca111845e07be5245659726 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Sat, 23 Nov 2019 23:14:05 +0100 Subject: ARM: dts: rtd1195: Add CRT syscon node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prepare a CRT syscon mfd node. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index a74f530dc439..ac37366ff7c4 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -100,6 +100,15 @@ #size-cells = <1>; ranges = <0x0 0x18000000 0x70000>; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + iso: syscon@7000 { compatible = "syscon", "simple-mfd"; reg = <0x7000 0x1000>; -- cgit v1.2.3-70-g09d2 From 6f7f0d95380fa36b1102f3f8b8dc4e0f9a9af51f Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 21 Oct 2019 04:30:14 +0200 Subject: ARM: dts: rtd1195: Add reset nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add reset controller nodes for Realtek RTD1195 SoC. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index ac37366ff7c4..886845e52205 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -141,7 +141,33 @@ }; }; +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; +}; + &iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + wdt: watchdog@680 { compatible = "realtek,rtd1295-watchdog"; reg = <0x680 0x100>; -- cgit v1.2.3-70-g09d2 From a4516dc56ea88331ccb9672193c8dac81f47b061 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Wed, 23 Oct 2019 11:21:45 +0200 Subject: ARM: dts: rtd1195: Add UART resets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Associate the UART nodes with the corresponding reset controller bits. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index 886845e52205..09acb99083c1 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -8,6 +8,7 @@ /memreserve/ 0x17fff000 0x00001000; #include +#include / { compatible = "realtek,rtd1195"; @@ -179,6 +180,7 @@ reg = <0x800 0x400>; reg-shift = <2>; reg-io-width = <4>; + resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; clock-frequency = <27000000>; status = "disabled"; }; @@ -190,6 +192,7 @@ reg = <0x200 0x100>; reg-shift = <2>; reg-io-width = <4>; + resets = <&reset2 RTD1195_RSTN_UR1>; clock-frequency = <27000000>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From fcf8628246522b8bc23f5669016d25402091593c Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 25 Nov 2019 07:37:36 +0100 Subject: ARM: dts: rtd1195: Add SB2 and SCPU Wrapper syscon nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add syscon mfd nodes for SB2 and SCPU Wrapper to RTD1195 DT. Acked-by: James Tai Signed-off-by: Andreas Färber --- arch/arm/boot/dts/rtd1195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index 09acb99083c1..21897210d9d0 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -119,6 +119,15 @@ ranges = <0x0 0x7000 0x1000>; }; + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + misc: syscon@1b000 { compatible = "syscon", "simple-mfd"; reg = <0x1b000 0x1000>; @@ -127,6 +136,15 @@ #size-cells = <1>; ranges = <0x0 0x1b000 0x1000>; }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; }; gic: interrupt-controller@ff011000 { -- cgit v1.2.3-70-g09d2 From 37aed36cfec3b35469be3dc5fb52c8a459414cff Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 12 Feb 2020 11:08:27 +0100 Subject: ARM: rockchip: Replace by The Rockchip platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include instead of . Signed-off-by: Geert Uytterhoeven Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200212100830.446-5-geert+renesas@glider.be Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index f9797a2b5d0d..beea4564eed4 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -9,9 +9,9 @@ #include #include #include +#include #include #include -#include #include #include #include -- cgit v1.2.3-70-g09d2 From 0b973c65d2f2da049252bc8370e4cf037b99c7e9 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 23 Jan 2020 00:48:07 +0000 Subject: ARM: rockchip: fix spelling mistake "to" -> "too" There is a spelling mistake in a pr_err message. Fix it. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20200123004807.2833556-1-colin.king@canonical.com Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 649e0a54784c..d60856898d97 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -180,7 +180,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) rsize = resource_size(&res); if (rsize < trampoline_sz) { - pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", + pr_err("%s: reserved block with size 0x%x is too small for trampoline size 0x%x\n", __func__, rsize, trampoline_sz); return -EINVAL; } -- cgit v1.2.3-70-g09d2 From f8beebe019467c690f02ce75bb48fb5afa7b2730 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 09:35:24 +0100 Subject: ARM: exynos_defconfig: Enable serial bus and BCM HCIUART drivers Enable serial bus and BCM HCIUART Bluetooth drivers available on the Exynos3250-based Rinato board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 3c3a00fc71f6..1ea2f87533ef 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -69,6 +69,7 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m @@ -133,6 +134,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SAMSUNG=y CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y CONFIG_TCG_TPM=y CONFIG_TCG_TIS_I2C_INFINEON=y -- cgit v1.2.3-70-g09d2 From 8620cc2f99b734bfc7988b62f3d3c8c6fca04598 Mon Sep 17 00:00:00 2001 From: Stenkin Evgeniy Date: Thu, 19 Mar 2020 18:34:11 +0100 Subject: ARM: dts: exynos: Add devicetree file for the Galaxy S2 Add devicetree file for the Exynos4210 based Galaxy S2 (GT-I9100 version). Signed-off-by: Stenkin Evgeniy Signed-off-by: Paul Cercueil Reviewed-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos4210-i9100.dts | 768 +++++++++++++++++++++++++++++++++ 2 files changed, 769 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4210-i9100.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..20c49f84188d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_EXYNOS3) += \ exynos3250-monk.dtb \ exynos3250-rinato.dtb dtb-$(CONFIG_ARCH_EXYNOS4) += \ + exynos4210-i9100.dtb \ exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts new file mode 100644 index 000000000000..a4147113f0c4 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Stenkin Evgeniy + * Copyright (c) 2020 Paul Cercueil + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include + +/ { + model = "Samsung Galaxy S2 (GT-I9100)"; + compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-down { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + vol-up { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + ok { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "ok"; + debounce-interval = <10>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + + i2c_max17042_fuel: i2c-gpio { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpy4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpy4 1 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <5>; + + battery@36 { + compatible = "maxim,max17042"; + + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&max17042_fuel_irq>; + pinctrl-names = "default"; + + reg = <0x36>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + }; + }; + + spi-lcd { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + num-chipselects = <1>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + + spi-max-frequency = <1200000>; + + vdd3-supply = <&vmipi_reg>; + vci-supply = <&vcclcd_reg>; + + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + power-on-delay = <10>; + reset-delay = <10>; + + panel-width-mm = <90>; + panel-height-mm = <154>; + + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; + }; + }; +}; + +&camera { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; + +&ehci { + status = "okay"; + + phys = <&exynos_usbphy 1>; + phy-names = "host"; +}; + +&exynos_usbphy { + status = "okay"; + + vbus-supply = <&safe1_sreg>; +}; + +&fimc_0 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + samsung,invert-vden; + samsung,invert-vclk; + + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + + port@3 { + reg = <3>; + + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + status = "okay"; + + mali-supply = <&vg3d_breg>; + regulator-microvolt-offset = <50000>; + regulator-microsecs-delay = <50>; +}; + +&hsotg { + status = "okay"; + + dr_mode = "otg"; + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; +}; + +&i2c_3 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + + mxt224-touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c_5 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; + pinctrl-names = "default"; + + regulators { + vadc_reg: LDO1 { + regulator-name = "VADC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + }; + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vhsic_reg: LDO5 { + regulator-name = "VHSIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vtouch_reg: LDO11 { + regulator-name = "TOUCH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmotor_reg: LDO14 { + regulator-name = "VCC_2.8V_MOTOR"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vled_reg: LDO15 { + regulator-name = "LED_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtf_reg: LDO17 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtouchled_reg: LDO18 { + regulator-name = "TOUCH_LED_3.3V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vg3d_breg: BUCK3 { + regulator-name = "G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + regulator-always-on; + }; + + chargercv_reg: CHARGER_CV { + regulator-name = "CHARGER_CV"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <4100000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_7 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + + ak8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-states { + gpa0-0 { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-1 { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-2 { + samsung,pins = "gpa0-2"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-3 { + samsung,pins = "gpa0-3"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + }; +}; + +&pinctrl_1 { + mhl_int: mhl-int { + samsung,pins = "gpf3-5"; + samsung,pin-pud = ; + }; + + i2c_mhl_bus: i2c-mhl-bus { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb_sel: usb-sel { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_en: bt-en { + samsung,pins = "gpl0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_res: bt-res { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + otg_gp: otg-gp { + samsung,pins = "gpx3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + mag_mhl_gpio: mag-mhl-gpio { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max8997_irq: max8997-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + max17042_fuel_irq: max17042-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-pud = ; + }; + + tsp224_irq: tsp224-irq { + samsung,pins = "gpx0-4"; + samsung,pin-pud = ; + }; +}; + +&sdhci_0 { + status = "okay"; + + bus-width = <8>; + non-removable; + vmmc-supply = <&vemmc_reg>; + + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; + pinctrl-names = "default"; +}; + +&sdhci_2 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vtf_reg>; + + pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; + pinctrl-names = "default"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&vtf_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + + shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From b6353c31ab641d99a7879d9fae557c8793bd2243 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 09:35:23 +0100 Subject: ARM: dts: exynos: Enable Bluetooth support for Rinato board Add a node for the BCM43342A Bluetooth chip on the serial bus #0 on the Exynos3250-based Rinato board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-rinato.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 86c26a4edfd7..03f214089fd4 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -629,6 +629,15 @@ assigned-clocks = <&cmu CLK_SCLK_UART0>; assigned-clock-rates = <100000000>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; }; &serial_1 { -- cgit v1.2.3-70-g09d2 From a19f6efc01df901c16a57455485613236eaad55e Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 10:46:24 +0100 Subject: ARM: dts: exynos: Enable WLAN support for the Trats board Add a node for BCM4330/3 SDIO chip on SDHCI bus #3 and the required MMC power sequence node for the Exynos4210-based Trats board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-trats.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 7c39dd1c4d3a..df901f113df5 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -121,6 +121,11 @@ }; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -471,6 +476,30 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&tflash_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 8807d356bfea92b0a8f04ce421800ed83400cd22 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 15:20:37 +0100 Subject: ARM: dts: exynos: Fix GPIO polarity for thr GalaxyS3 CM36651 sensor's bus GPIO lines for the CM36651 sensor I2C bus use the normal not the inverted polarity. This bug has been there since adding the CM36651 sensor by commit 85cb4e0bd229 ("ARM: dts: add cm36651 light/proximity sensor node for exynos4412-trats2"), but went unnoticed because the "i2c-gpio" driver ignored the GPIO polarity specified in the device-tree. The recent conversion of "i2c-gpio" driver to the new, descriptor based GPIO API, automatically made it the DT-specified polarity aware, what broke the CM36651 sensor operation. Fixes: 85cb4e0bd229 ("ARM: dts: add cm36651 light/proximity sensor node for exynos4412-trats2") CC: stable@vger.kernel.org # 4.16+ Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 44f97546dd0a..f910aa924bfb 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -68,7 +68,7 @@ i2c_cm36651: i2c-gpio-2 { compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; + gpios = <&gpf0 0 GPIO_ACTIVE_HIGH>, <&gpf0 1 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-70-g09d2 From 8df80c1801c99e2a000c20ee2ab1a94ddd326720 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 15:39:09 +0100 Subject: ARM: dts: exynos: Convert to new i2c-gpio bindings The updated "i2c-gpio" driver bindings require to define the SDA and SCL GPIO lines in the separate properties and mark both as GPIO_OPEN_DRAIN. Covert all Exynos dts files to follow this style. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-monk.dts | 3 ++- arch/arm/boot/dts/exynos3250-rinato.dts | 3 ++- arch/arm/boot/dts/exynos4210-i9100.dts | 4 ++-- arch/arm/boot/dts/exynos4210-universal_c210.dts | 3 ++- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 6 ++++-- arch/arm/boot/dts/exynos4412-midas.dtsi | 9 ++++++--- arch/arm/boot/dts/exynos5250-arndale.dts | 5 ++--- 7 files changed, 20 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 248bd372fe70..ca29d7ed8216 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -57,7 +57,8 @@ i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 03f214089fd4..5f44ea0df74e 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -52,7 +52,8 @@ i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index a4147113f0c4..6d0c04d77a39 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -128,8 +128,8 @@ #address-cells = <1>; #size-cells = <0>; - sda-gpios = <&gpy4 0 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpy4 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <5>; battery@36 { diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9dda6bdb9253..f030217494d6 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -164,7 +164,8 @@ hdmi_ddc: i2c-ddc { compatible = "i2c-gpio"; - gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index f910aa924bfb..53b3ca3effab 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -53,7 +53,8 @@ i2c_ak8975: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -68,7 +69,8 @@ i2c_cm36651: i2c-gpio-2 { compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_HIGH>, <&gpf0 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 3023bc3b68ce..72c9bbb08f27 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -140,7 +140,8 @@ i2c_max77693: i2c-gpio-1 { compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -188,7 +189,8 @@ i2c_max77693_fuel: i2c-gpio-3 { compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -228,7 +230,8 @@ i2c-mhl { compatible = "i2c-gpio"; - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6904091d4837..e9f2b9a15e12 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -641,9 +641,8 @@ pinctrl-0 = <&i2c2_gpio_bus>; status = "okay"; compatible = "i2c-gpio"; - gpios = <&gpa0 6 0 /* sda */ - &gpa0 7 0 /* scl */ - >; + sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-70-g09d2 From 5453c5c9c5afadd6c2d0f6f0c6b168202b0310c1 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 15:44:55 +0100 Subject: ARM: dts: exynos: Correct regulator names Both CPU-freq and dev-freq drivers support proper regulator lookup from device-tree, so the early introduced hacks for registering main ARM VDD regulator under 'vdd_arm' name are no longer needed. Similar for devfreq. Fix this by removing the obsolete comments and changing the regulator names to the one, which match the schematics and style for the given board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-origen.dts | 7 +------ arch/arm/boot/dts/exynos4210-trats.dts | 7 +------ arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- arch/arm/boot/dts/exynos4412-midas.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-origen.dts | 14 +++++++------- arch/arm/boot/dts/exynos5250-arndale.dts | 8 ++++---- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 2 +- 8 files changed, 23 insertions(+), 33 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 0d1e1a9c2f6e..890525b10d22 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -251,12 +251,7 @@ }; buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM_1.2V"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index df901f113df5..c15c6d7cd352 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -408,12 +408,7 @@ }; varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index f030217494d6..dd24e64632eb 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -318,7 +318,7 @@ max8952,sync-freq = <0>; max8952,ramp-speed = <0>; - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <770000>; regulator-max-microvolt = <1400000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 72c9bbb08f27..2c8111c6b065 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -823,7 +823,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -834,7 +834,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -845,7 +845,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; @@ -856,7 +856,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-boot-on; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 73d6a71da88d..a5c1ce1e396c 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -430,7 +430,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -438,7 +438,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -446,7 +446,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1050000>; regulator-always-on; @@ -454,7 +454,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-microvolt-offset = <50000>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index ecd14b283a6b..dc865be40751 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -363,7 +363,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -372,7 +372,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -381,7 +381,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -390,7 +390,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -399,7 +399,7 @@ }; buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; + regulator-name = "VDD_M12"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -408,7 +408,7 @@ }; buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; + regulator-name = "VDD12_5M"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -417,7 +417,7 @@ }; buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; + regulator-name = "VDDF28_EMMC"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <3000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index e9f2b9a15e12..c4cc7611898c 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -454,7 +454,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -463,7 +463,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1300000>; regulator-always-on; @@ -472,7 +472,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -481,7 +481,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1300000>; regulator-always-on; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index e9a09dd0a49b..dd7f8385d81e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -673,7 +673,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "PVDD_ARM_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1500000>; regulator-always-on; -- cgit v1.2.3-70-g09d2 From ad0e74f0d67009c9db4a1e31ffba7badd06d805f Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 16:08:06 +0100 Subject: ARM: dts: exynos: Correct the MAX8997 interrupts on the Trats board Remove the 'interrupts' and 'interrupts-parent' properties, which have been superseded by the interrupts-extended property. While touching this, fix the interrupts flags to correctly describe the hardware. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-trats.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index c15c6d7cd352..3d791db6095c 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -285,11 +285,10 @@ max8997_pmic@66 { compatible = "maxim,max8997-pmic"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; + interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; max8997,pmic-buck1-uses-gpio-dvs; max8997,pmic-buck2-uses-gpio-dvs; -- cgit v1.2.3-70-g09d2 From d22928095975acd4ac6c9fd5df768ffde82ebfdf Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 16:09:46 +0100 Subject: ARM: dts: exynos: Remove useless address/size cells for mshc_0 on Rinato mshc_0 node doesn't have any children, so there is no need for address and size-cells properties. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-rinato.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 5f44ea0df74e..1b48151a84cf 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -606,8 +606,6 @@ }; &mshc_0 { - #address-cells = <1>; - #size-cells = <0>; broken-cd; non-removable; cap-mmc-highspeed; -- cgit v1.2.3-70-g09d2 From 95384e977c426e73971e7393c393ccce66c084ec Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 27 Mar 2020 13:53:17 +0100 Subject: ARM: dts: exynos: Enable WLAN support for the Rinato board Add a node for BCM43342A SDIO chip on MSHC bus #1 and the required MMC power sequence node for the Exynos3250-based Rinato board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-rinato.dts | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 1b48151a84cf..aba8350cfdaf 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -50,6 +50,11 @@ }; }; + wlan_pwrseq: mshc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + }; + i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -624,6 +629,35 @@ status = "okay"; }; +&mshc_1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac"; + reg = <1>; + + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { assigned-clocks = <&cmu CLK_SCLK_UART0>; assigned-clock-rates = <100000000>; -- cgit v1.2.3-70-g09d2 From f1b0ffaa686f21e8538bb38f0e147ee2ce80e67f Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 27 Mar 2020 14:00:05 +0100 Subject: ARM: dts: exynos: Enable WLAN support for the UniversalC210 board Add a node for BCM4330/2 SDIO chip on SDHCI bus #3 and the required MMC power sequence node for the Exynos4210-based UniversalC210 board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index dd24e64632eb..02fde1a75ebd 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -50,6 +50,11 @@ enable-active-high; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -564,6 +569,29 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&ldo5_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; /delete-property/dmas; -- cgit v1.2.3-70-g09d2 From a8360727870bce0b4adb6f08a94bb6bc4cdf6c39 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 26 Mar 2020 10:46:26 +0100 Subject: ARM: exynos_defconfig: Compile MAC80211/CFG80211 as modules MAC80211/CFG80211 framework requires loading regulatory.db from /lib/firmware directory, so it makes very little sense to have it built-in. Change it to be built as modules to let it properly load the needed firmware/db files. As a side effect of this change, the size of the compressed modules on SquashFS increased significantly from 27MiB to 38MiB, so increase the size of BLK_DEV_RAM to allow the modules to fit into it. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 1ea2f87533ef..1bbbc677f0e3 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -79,8 +79,8 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m -CONFIG_CFG80211=y -CONFIG_MAC80211=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m CONFIG_MAC80211_LEDS=y CONFIG_NFC=y CONFIG_NFC_DIGITAL=m @@ -95,7 +95,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=32768 +CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y -- cgit v1.2.3-70-g09d2 From 778627c78f01c6a05abb1211f3e3d763c236506c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 26 Mar 2020 22:10:14 +0100 Subject: ARM: s3c64xx: convert to use i2c_new_client_device() Move away from the deprecated API and remove printing a stale 'ret' value. Signed-off-by: Wolfram Sang Acked-by: Charles Keepax Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c64xx/mach-crag6410-module.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index 937d0a83f8fd..34f1baa10c54 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c @@ -405,10 +405,9 @@ static int wlf_gf_module_probe(struct i2c_client *i2c, gf_mods[i].name, rev + 1); for (j = 0; j < gf_mods[i].num_i2c_devs; j++) { - if (!i2c_new_device(i2c->adapter, - &(gf_mods[i].i2c_devs[j]))) - dev_err(&i2c->dev, - "Failed to register dev: %d\n", ret); + if (IS_ERR(i2c_new_client_device(i2c->adapter, + &(gf_mods[i].i2c_devs[j])))) + dev_err(&i2c->dev, "Failed to register\n"); } spi_register_board_info(gf_mods[i].spi_devs, -- cgit v1.2.3-70-g09d2 From 7ed609b0020fd1db5acde66248f5623328834b72 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 10 Jan 2020 23:27:44 +0100 Subject: ARM: dts: at91: sama5d3: switch to new clock bindings Switch sama5d3 boards to the new PMC clock bindings. This prevents the wb50n to use the out of spec rate for USART1. Link: https://lore.kernel.org/r/20200110222744.1261464-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-dvk_su60_somc.dtsi | 2 +- arch/arm/boot/dts/at91-wb50n.dtsi | 4 - arch/arm/boot/dts/sama5d3.dtsi | 424 +++--------------------------- arch/arm/boot/dts/sama5d3_can.dtsi | 20 +- arch/arm/boot/dts/sama5d3_emac.dtsi | 8 +- arch/arm/boot/dts/sama5d3_gmac.dtsi | 11 +- arch/arm/boot/dts/sama5d3_lcd.dtsi | 19 +- arch/arm/boot/dts/sama5d3_mci2.dtsi | 11 +- arch/arm/boot/dts/sama5d3_tcb1.dtsi | 12 +- arch/arm/boot/dts/sama5d3_uart.dtsi | 20 +- arch/arm/boot/dts/sama5d3xmb.dtsi | 6 +- arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 6 +- 12 files changed, 56 insertions(+), 487 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi index 21876da7c442..c1c8650dafce 100644 --- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi +++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi @@ -62,7 +62,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck2>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; clock-names = "mclk"; }; }; diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi index 4ed8500a5cb8..1487b893cfa7 100644 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -46,10 +46,6 @@ atmel,osc-bypass; }; -&usart1_clk { - atmel,clk-output-range = <0 132000000>; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index f11b018e9173..f3ce561b46ab 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -108,7 +108,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "mci_clk"; }; @@ -123,7 +123,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "spi_clk"; status = "disabled"; }; @@ -137,7 +137,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "pclk"; status = "disabled"; }; @@ -148,7 +148,7 @@ #size-cells = <0>; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -166,7 +166,7 @@ scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -184,7 +184,7 @@ scl-gpios = <&pioC 27 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -197,7 +197,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "usart"; status = "disabled"; }; @@ -211,7 +211,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "usart"; status = "disabled"; }; @@ -222,7 +222,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -232,7 +232,7 @@ reg = <0xf002c000 0x300>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; status = "disabled"; }; @@ -242,7 +242,7 @@ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; clock-names = "isi_clk"; status = "disabled"; port { @@ -267,7 +267,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "mci_clk"; }; @@ -282,7 +282,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "spi_clk"; status = "disabled"; }; @@ -296,7 +296,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "pclk"; status = "disabled"; }; @@ -323,7 +323,7 @@ &pinctrl_adc0_ad10 &pinctrl_adc0_ad11 >; - clocks = <&adc_clk>, + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xfff>; @@ -370,7 +370,7 @@ scl-gpios = <&pioA 19 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; status = "disabled"; }; @@ -383,7 +383,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "usart"; status = "disabled"; }; @@ -397,7 +397,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "usart"; status = "disabled"; }; @@ -408,7 +408,7 @@ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; dma-names = "tx"; - clocks = <&sha_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "sha_clk"; }; @@ -419,7 +419,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; dma-names = "tx", "rx"; - clocks = <&aes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; clock-names = "aes_clk"; }; @@ -430,7 +430,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; dma-names = "tx", "rx"; - clocks = <&tdes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; clock-names = "tdes_clk"; }; @@ -438,14 +438,14 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xf8040000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; }; hsmc: hsmc@ffffc000 { compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; reg = <0xffffc000 0x1000>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -462,7 +462,7 @@ reg = <0xffffe600 0x200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; clock-names = "dma_clk"; }; @@ -471,14 +471,14 @@ reg = <0xffffe800 0x200>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; clock-names = "dma_clk"; }; ramc0: ramc@ffffea00 { compatible = "atmel,sama5d3-ddramc"; reg = <0xffffea00 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; clock-names = "ddrck", "mpddr"; }; @@ -491,7 +491,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; clock-names = "usart"; status = "disabled"; }; @@ -967,7 +967,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; pioB: gpio@fffff400 { @@ -978,7 +978,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; }; pioC: gpio@fffff600 { @@ -989,7 +989,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; }; pioD: gpio@fffff800 { @@ -1000,7 +1000,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; }; pioE: gpio@fffffa00 { @@ -1011,7 +1011,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; }; }; @@ -1019,353 +1019,9 @@ compatible = "atmel,sama5d3-pmc", "syscon"; reg = <0xfffffc00 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <8000000 50000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <2>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <6>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <7>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <8>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <9>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <10>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <12>; - atmel,clk-output-range = <0 83000000>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <13>; - atmel,clk-output-range = <0 83000000>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <14>; - atmel,clk-output-range = <0 83000000>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <15>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <18>; - #clock-cells = <0>; - atmel,clk-output-range = <0 41500000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 41500000>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 41500000>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <22>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 166000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 166000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 166000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <28>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <29>; - atmel,clk-output-range = <0 83000000>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <30>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <31>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <32>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <33>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <37>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <39>; - atmel,clk-output-range = <0 83000000>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <42>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <43>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <44>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <45>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <48>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <49>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; reset_controller: rstc@fffffe00 { @@ -1384,7 +1040,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; watchdog: watchdog@fffffe40 { @@ -1426,7 +1082,7 @@ reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -1540,7 +1196,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1549,7 +1205,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1565,7 +1221,7 @@ 0x1 0x0 0x40000000 0x10000000 0x2 0x0 0x50000000 0x10000000 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 2470dd3fff25..9ac29bf3f933 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -31,29 +31,13 @@ }; - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "can_clk"; status = "disabled"; }; @@ -64,7 +48,7 @@ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "can_clk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 9aef414bcd2e..45226108850d 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -31,12 +31,6 @@ }; pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <35>; - }; - }; }; macb1: ethernet@f802c000 { @@ -45,7 +39,7 @@ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 3667765a138b..884df7a54dbb 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -63,22 +63,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <34>; - }; - }; - }; - macb0: ethernet@f0028000 { compatible = "atmel,sama5d3-gem"; reg = <0xf0028000 0x100>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 2cf046cd4e99..308d2fc276d6 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -16,7 +16,7 @@ compatible = "atmel,sama5d3-hlcdc"; reg = <0xf0030000 0x2000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -192,23 +192,6 @@ }; }; }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <36>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 3c83c1c36ac8..7141ee97ec3e 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -30,15 +30,6 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - mci2_clk: mci2_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; @@ -47,7 +38,7 @@ dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&mci2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "mci_clk"; status = "disabled"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 215802b8db30..2b18c5c2cc03 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -17,23 +17,13 @@ ahb { apb { - pmc: pmc@fffffc00 { - periphck { - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 166000000>; - }; - }; - }; - tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index cb62adbd28ed..a3eaba995cf4 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -36,29 +36,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <17>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -69,7 +53,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "usart"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 35031bbc7e70..a499de8a7a64 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -46,7 +46,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -60,9 +60,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi index 8a6916a69da4..fa9e5e2a745d 100644 --- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi @@ -45,7 +45,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -59,9 +59,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { -- cgit v1.2.3-70-g09d2 From 82a5df83e444d4a8aef01c1ba81c38f5bb66b06a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 16 Jan 2020 18:35:10 +0100 Subject: ARM: dts: at91: at91sam9n12: switch to new clock bindings Switch at91sam9n12 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200116173510.427403-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9n12.dtsi | 324 ++++-------------------------------- arch/arm/boot/dts/at91sam9n12ek.dts | 2 +- 2 files changed, 29 insertions(+), 297 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index ea675174432e..a994d076dc7e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -104,7 +104,7 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -116,278 +116,10 @@ pmc: pmc@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 555000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <30000000 100000000 0>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9n12-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <29>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; }; rstc@fffffe00 { @@ -400,7 +132,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; shdwc@fffffe10 { @@ -439,7 +171,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -452,7 +184,7 @@ #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -462,7 +194,7 @@ #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -470,7 +202,7 @@ compatible = "atmel,at91sam9n12-hlcdc"; reg = <0xf8038000 0x2000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk", "sys_clk", "slow_clk"; status = "disabled"; @@ -499,7 +231,7 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "dma_clk"; }; @@ -817,7 +549,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -828,7 +560,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioC: gpio@fffff800 { @@ -839,7 +571,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioD: gpio@fffffa00 { @@ -850,7 +582,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; }; @@ -860,7 +592,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -874,7 +606,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "pclk"; status = "disabled"; }; @@ -885,7 +617,7 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "usart"; status = "disabled"; }; @@ -896,7 +628,7 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +639,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -918,7 +650,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -934,7 +666,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; status = "disabled"; }; @@ -949,7 +681,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; status = "disabled"; }; @@ -964,7 +696,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -980,7 +712,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1009,7 +741,7 @@ reg = <0xf8034000 0x300>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -1017,7 +749,7 @@ compatible = "atmel,at91sam9260-udc"; reg = <0xf803c000 0x4000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -1027,7 +759,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1045,7 +777,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index d36e162a8817..870b83ff6b97 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -59,7 +59,7 @@ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; -- cgit v1.2.3-70-g09d2 From 15090390cac613ab2d0db416e3e5f1699bf21547 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 17 Jan 2020 22:06:19 +0100 Subject: ARM: dts: at91: at91sam9g45: switch to new clock bindings Switch at91sam9g45 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200117210619.17768-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9g45.dtsi | 338 ++++----------------------------- arch/arm/boot/dts/at91sam9m10g45ek.dts | 4 +- 2 files changed, 40 insertions(+), 302 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index fd179097a4bf..3034c23e697d 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -103,14 +103,14 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe400 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; ramc1: ramc@ffffe600 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe600 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -128,271 +128,9 @@ compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioDE_clk: pioDE_clk { - #clock-cells = <0>; - reg = <5>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <24>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <25>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <26>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <27>; - }; - - aestdessha_clk: aestdessha_clk { - #clock-cells = <0>; - reg = <28>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <29>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; rstc@fffffd00 { @@ -405,7 +143,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; @@ -421,7 +159,7 @@ #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -431,7 +169,7 @@ #size-cells = <0>; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -440,7 +178,7 @@ reg = <0xffffec00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "dma_clk"; }; @@ -883,7 +621,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff400 { @@ -894,7 +632,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff600 { @@ -905,7 +643,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffff800 { @@ -916,7 +654,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; pioE: gpio@fffffa00 { @@ -927,7 +665,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -937,7 +675,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -950,7 +688,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -963,7 +701,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -976,7 +714,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -989,7 +727,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "usart"; status = "disabled"; }; @@ -1000,7 +738,7 @@ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -1009,7 +747,7 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xfffcc000 0x100>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; i2c0: i2c@fff84000 { @@ -1020,7 +758,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; status = "disabled"; }; @@ -1032,7 +770,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; status = "disabled"; }; @@ -1042,7 +780,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -1053,7 +791,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "pclk"; status = "disabled"; }; @@ -1064,7 +802,7 @@ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ac97_clk"; status = "disabled"; }; @@ -1075,7 +813,7 @@ compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; @@ -1111,7 +849,7 @@ compatible = "atmel,at91sam9g45-isi"; reg = <0xfffb4000 0x4000>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "isi_clk"; status = "disabled"; port { @@ -1125,7 +863,7 @@ reg = <0xfffb8000 0x300>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -1138,7 +876,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1152,7 +890,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1176,7 +914,7 @@ interrupts = <14 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1189,7 +927,7 @@ interrupts = <15 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1201,7 +939,7 @@ reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -1294,7 +1032,7 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "lcdc_clk"; status = "disabled"; }; @@ -1303,7 +1041,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1312,7 +1050,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1330,7 +1068,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 84bed6f55fcd..a3a5c82d9f29 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -72,9 +72,9 @@ pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { -- cgit v1.2.3-70-g09d2 From 0e0e528d8260f10d32d6bc58fc987d553f3148a2 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 24 Mar 2020 13:41:54 +0100 Subject: ARM: dts: at91: rm9200: switch to new clock bindings Switch at91rm9200 boards to the new PMC clock bindings. Link: https://lore.kernel.org/r/20200324124154.368335-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91rm9200.dtsi | 296 +++----------------------------------- 1 file changed, 23 insertions(+), 273 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 44385718d9d4..a5040f5ea641 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -101,259 +101,9 @@ compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 80000000>; - atmel,clk-divisors = <1 2 3 4>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 0 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - udpck: udpck { - #clock-cells = <0>; - reg = <2>; - clocks = <&usb>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <4>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - reg = <12>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <20>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <21>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <22>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <23>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; st: timer@fffffd00 { @@ -383,7 +133,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -395,7 +145,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -405,7 +155,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -415,7 +165,7 @@ compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -429,7 +179,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "pclk"; status = "disabled"; }; @@ -440,7 +190,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "pclk"; status = "disabled"; }; @@ -451,7 +201,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -463,7 +213,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ether_clk"; status = "disabled"; }; @@ -803,7 +553,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -814,7 +564,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -825,7 +575,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffffa00 { @@ -836,7 +586,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -846,7 +596,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -859,7 +609,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -872,7 +622,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -885,7 +635,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -898,7 +648,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +657,7 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -920,7 +670,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -947,7 +697,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From a1af7f36c70369b971ee1cf679dd68368dad23f0 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 2 Apr 2020 00:15:00 +0200 Subject: ARM: dts: at91: sama5d2_ptc_ek: fix sdmmc0 node description Remove non-removable and mmc-ddr-1_8v properties from the sdmmc0 node which come probably from an unchecked copy/paste. Signed-off-by: Ludovic Desroches Fixes:42ed535595ec "ARM: dts: at91: introduce the sama5d2 ptc ek board" Cc: stable@vger.kernel.org # 4.19 and later Link: https://lore.kernel.org/r/20200401221504.41196-1-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 1c24ac8019ba..772809c54c1f 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -125,8 +125,6 @@ bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From baa998aecb75c04d62be0a4ab6b724af6d73a0f9 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 2 Apr 2020 00:19:47 +0200 Subject: ARM: dts: at91: sama5d2_ptc_ek: fix vbus pin The gpio property for the vbus pin doesn't match the pinctrl and is not correct. Signed-off-by: Ludovic Desroches Fixes: 42ed535595ec "ARM: dts: at91: introduce the sama5d2 ptc ek board" Cc: stable@vger.kernel.org # 4.19 and later Link: https://lore.kernel.org/r/20200401221947.41502-1-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 772809c54c1f..b803fa1f2039 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -40,7 +40,7 @@ ahb { usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; -- cgit v1.2.3-70-g09d2 From d08f4a5ac9fe2121b4d809d8529b5d4927971061 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 2 Apr 2020 00:15:02 +0200 Subject: ARM: dts: at91: sama5d2_ptc_ek: add PB_USER as wakeup source Add the push button PB_USER as wakeup source Signed-off-by: Ludovic Desroches Link: https://lore.kernel.org/r/20200401221504.41196-3-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index b803fa1f2039..32435ce1dab2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -412,6 +412,7 @@ label = "PB_USER"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; -- cgit v1.2.3-70-g09d2 From d0815bc1b4559eddd671a3c51ba77fcd04c0fea4 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 2 Apr 2020 00:15:03 +0200 Subject: ARM: dts: at91: sama5d27_som1_ek: enable i2c0 Enable i2c0 controller. Signed-off-by: Ludovic Desroches Link: https://lore.kernel.org/r/20200401221504.41196-4-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index b0853bf7901c..1a26e1a12931 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -115,6 +115,13 @@ status = "okay"; }; + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + }; + pwm0: pwm@f802c000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; @@ -281,6 +288,12 @@ bias-disable; }; + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + pinctrl_i2c1_default: i2c1_default { pinmux = , ; -- cgit v1.2.3-70-g09d2 From 32542faf867f78e13cfec4178311795305c8c177 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 2 Apr 2020 00:15:04 +0200 Subject: ARM: dts: at91: sama5d27_som1_ek: add an alias for i2c0 Add aliases for i2c devices to not rely on probe order for i2c device numbering. Signed-off-by: Ludovic Desroches Link: https://lore.kernel.org/r/20200401221504.41196-5-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 1a26e1a12931..535627c6045b 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -20,6 +20,7 @@ serial0 = &uart1; /* DBGU */ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ + i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; }; -- cgit v1.2.3-70-g09d2 From c378150337efa7a4b03394b0229a9110bda8403c Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 3 Apr 2020 06:12:24 +0000 Subject: ARM: dts: at91: sam9x60ek: Use quad mode in the spi-nor flash Both the QSPI controller and the sst26vf064b flash support quad mode, enable it. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200403061222.1277147-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sam9x60ek.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index b484745bf2d4..8c3f621efc4b 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -579,6 +579,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; at91bootstrap@0 { -- cgit v1.2.3-70-g09d2 From 471f0532ea37160aa2751cd241478ceb738f1923 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 3 Apr 2020 06:12:25 +0000 Subject: ARM: dts: at91: sama5d27_som1: Add SPI NOR flash mapping Add SoM1 flash mapping, identical with the other SPI NOR flash mappings found on the other at91 boards. Signed-off-by: Claudiu Beznea Tested-by: Tudor Ambarus Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200403061222.1277147-2-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 6281590150c8..919000f467e6 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -34,12 +34,44 @@ pinctrl-0 = <&pinctrl_qspi1_default>; flash@0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; }; }; -- cgit v1.2.3-70-g09d2 From 0fd3a8f58f78b498784b72c1971c225c4e69ddac Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 3 Apr 2020 06:12:26 +0000 Subject: ARM: dts: at91: sam9x60ek: Add sdmmc1 node sdmmc1 is not populated by default on sam9x60ek, but there are cases where it is populated with wilc3000. Add the node, but keep it disabled. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200403061222.1277147-4-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sam9x60ek.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 8c3f621efc4b..a5f5718c711a 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -542,6 +542,18 @@ }; }; + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + gpio_keys { pinctrl_key_gpio_default: pinctrl_key_gpio { atmel,pins = ; @@ -568,6 +580,15 @@ disable-wp; }; +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + no-1-8-v; + non-removable; + status = "disabled"; /* Conflict with flx4. */ +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; -- cgit v1.2.3-70-g09d2 From 51cca920ce84356d53068ac83a53ba8c45879a0e Mon Sep 17 00:00:00 2001 From: Cyrille Pitchen Date: Fri, 3 Apr 2020 06:12:26 +0000 Subject: ARM: dts: at91: sama5d2_xplained: Add QSPI0 + SPI NOR memory nodes This patch enables the QSPI0 controller, configures its pin muxing and declares a jedec,spi-nor memory. sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash memory which advertises a maximum frequency of 80MHz for Quad IO Fast Read. Set the spi-max-frequency to 80MHz knowing that actually the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz. Signed-off-by: Cyrille Pitchen Tested-by: Tudor Ambarus Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200403061222.1277147-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 68 +++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 055ee53e4773..e0c6cff1a312 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -72,6 +72,58 @@ }; apb { + qspi0: spi@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + status = "disabled"; /* conflict with sdmmc1 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; + + misc@00800000 { + label = "misc"; + reg = <0x00800000 0x00000000>; + }; + }; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; @@ -535,6 +587,22 @@ bias-disable; }; + pinctrl_qspi0_default: qspi0_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = , -- cgit v1.2.3-70-g09d2 From 2fdc4e1c8cb1b291b920f514afad8d7ce286851d Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 3 Apr 2020 06:12:27 +0000 Subject: ARM: dts: at91: at91-sama5d27_som1: Enable eeprom device There is an EEPROM on at91-sama5d27_som1 connected to i2c0. i2c0 node has to be moved from at91-sama5d27_som1_ek to at91-sama5d27_som1. Enable the i2c EEPROM found on at91-sama5d27_som1. Add an alias for the i2c node. Signed-off-by: Ludovic Desroches Tested-by: Tudor Ambarus Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200403061222.1277147-5-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 22 ++++++++++++++++++++++ arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 14 -------------- 2 files changed, 22 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 919000f467e6..b1f994c0ae79 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -13,6 +13,10 @@ model = "Atmel SAMA5D27 SoM1"; compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -89,7 +93,25 @@ }; }; + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + + at24@50 { + compatible = "24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; pinctrl_qspi1_default: qspi1_default { sck_cs { diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 535627c6045b..b0853bf7901c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -20,7 +20,6 @@ serial0 = &uart1; /* DBGU */ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ - i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; }; @@ -116,13 +115,6 @@ status = "okay"; }; - i2c0: i2c@f8028000 { - dmas = <0>, <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_default>; - status = "okay"; - }; - pwm0: pwm@f802c000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; @@ -289,12 +281,6 @@ bias-disable; }; - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - pinctrl_i2c1_default: i2c1_default { pinmux = , ; -- cgit v1.2.3-70-g09d2 From 8d77c0296150f96036e647fd27ed3a8ad0f7cf1b Mon Sep 17 00:00:00 2001 From: Razvan Stefanescu Date: Wed, 25 Mar 2020 12:22:22 +0200 Subject: ARM: configs: at91: sama5: enable SAMA5D2_PIOBU Driver is enabled as a module. Signed-off-by: Razvan Stefanescu Link: https://lore.kernel.org/r/20200325102223.24827-1-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index bab7861443dc..258a18e659a5 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -128,6 +128,7 @@ CONFIG_SPI=y CONFIG_SPI_ATMEL=y CONFIG_SPI_GPIO=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_SAMA5D2_PIOBU=m CONFIG_POWER_SUPPLY=y CONFIG_BATTERY_ACT8945A=y CONFIG_POWER_RESET=y -- cgit v1.2.3-70-g09d2 From 6a2ab88ca789804cad89d558625147edd26a1d37 Mon Sep 17 00:00:00 2001 From: Razvan Stefanescu Date: Wed, 25 Mar 2020 12:22:23 +0200 Subject: ARM: configs: at91: sama5: enable MCP16502 regulator Driver is built as a module. Signed-off-by: Razvan Stefanescu Link: https://lore.kernel.org/r/20200325102223.24827-2-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 258a18e659a5..8e1f78c19920 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -143,6 +143,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ACT8865=y CONFIG_REGULATOR_ACT8945A=y +CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_PWM=m CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y -- cgit v1.2.3-70-g09d2 From 68a95ef72cefeeabbc68d36f191f49743a3d9c08 Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Fri, 10 Apr 2020 19:43:20 +0300 Subject: ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP This is the addition of the new SAMA5D2 Industrial Connectivity Platform(ICP). Signed-off-by: Cristian Birsan Link: https://lore.kernel.org/r/20200410164320.7658-3-cristian.birsan@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-sama5d2_icp.dts | 797 +++++++++++++++++++++++++++++++++ 2 files changed, 798 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d2_icp.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..e5072d417e2c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -55,6 +55,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-nattis-2-natte-2.dtb \ at91-sama5d27_som1_ek.dtb \ at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ at91-sama5d3_xplained.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts new file mode 100644 index 000000000000..cc9fa700eafb --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Radu Pirea & Razvan Stefanescu, + * Codrin Ciubotariu , + * Cristian Birsan + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include + +/ { + model = "Microchip SAMA5D2-ICP"; + compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ + serial1 = &uart1; /* mikro BUS 3 */ + serial3 = &uart3; /* mikro BUS 2 */ + serial5 = &uart5; /* flx2 */ + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + status = "okay"; + + sw4 { + label = "USER_PB1"; + gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* conflict with pwm0 */ + + red { + label = "red"; + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "blue"; + gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_io_reg>; + vref-supply = <&vdd_io_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&flx0 { /* mikrobus2 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "spi_clk"; + cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; + atmel,fifo-size = <16>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + switch0: ksz8563@0 { + compatible = "microchip,ksz8563"; + reg = <0>; + phy-mode = "mii"; + reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; + + spi-max-frequency = <500000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&macb0>; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; + + uart5: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "usart"; + pinctrl-0 = <&pinctrl_flx2_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; /* Conflict w/ qspi1. */ + }; +}; + +&flx3 { /* mikrobus1 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + atmel,fifo-size = <16>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <0>, <0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + atmel,fifo-size = <16>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; + + regulators { + vdd_io_reg: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; + }; +}; + +&i2c0 { /* mikrobus i2c */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus_i2c>; + status = "okay"; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&pioA { + pinctrl_adc_default: adc_default { + pinmux = , + , + ; + bias-disable; + }; + + /* + * The ADTRG pin can work on any edge type. + * In here it's being pulled up, so need to + * connect it to ground to get an edge e.g. + * Trigger can be configured on falling, rise + * or any edge, and the pull-up can be changed + * to pull-down or left floating according to + * needs. + */ + pinctrl_adtrg_default: adtrg_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_qspi1_default: qspi1_default { + pinmux = , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_mikrobus_i2c: mikrobus_i2c { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus1_an: mikrobus1_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_rst: mikrobus1_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm: mikrobus1_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_int: mikrobus1_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus2_an: mikrobus2_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_rst: mikrobus2_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi: mikrobus2_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_ksz_spi_cs: ksz_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_int: mikrobus2_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus3_an: mikrobus3_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_rst: mikrobus3_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi: mikrobus3_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus3_pwm: mikrobus3_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_int: mikrobus3_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_uart: mikrobus3_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_flx2_default: flx2_default { + pinmux = , + , + , + ; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds, HSIC */ +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "qspi: at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "qspi: bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "qspi: bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "qspi: bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "qspi: device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "qspi: kernel"; + reg = <0x00200000 0x00600000>; + }; + }; +}; + +&sdmmc0 { + no-1-8-v; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&shutdown_controller { + atmel,shdwc-debouncer = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; +}; + +&spi0 { /* mikrobus3 spi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 5b167212d673f4fcf02ff4d8266d76daf0d5e061 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 30 Mar 2020 04:22:22 +0200 Subject: ARM: dts: imx6q-dhcom: Add DH 560-200 display unit support Add DT bits to support the DH 560-200 display unit, which can be plugged into the side of the PDK2 board. The display unit contains a display, EDT ETM0700G0EDH6 and an EDT FT5x06 touchscreen controller. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP Linux Team Cc: Shawn Guo To: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 115 ++++++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index bb74fc62d913..a2dd7e549568 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -22,6 +22,53 @@ clock-frequency = <24000000>; }; + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + ddc-i2c-bus = <&i2c2>; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx-sgtl5000"; @@ -65,6 +112,15 @@ VDDA-supply = <®_3p3v>; VDDIO-supply = <&sw2_reg>; }; + + touchscreen@38 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; }; &iomuxc { @@ -77,9 +133,7 @@ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 @@ -132,6 +186,52 @@ >; }; + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_touchscreen: touchscreen-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 + >; + }; + pinctrl_pcie: pcie-grp { fsl,pins = < MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 @@ -139,6 +239,10 @@ }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -146,6 +250,13 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; + status = "okay"; +}; + &ssi1 { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From ff5b89c2858f28006f9f9c0a88c55a679488192c Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Sun, 8 Mar 2020 14:34:37 +0800 Subject: arm: dts: mt7623: add phy-mode property for gmac2 Add phy-mode property required by phylink on gmac2 Fixes: b8fc9f30821e ("net: ethernet: mediatek: Add basic PHYLINK support") Signed-off-by: Sean Wang Link: https://lore.kernel.org/r/70e3eff31ecd500ed4862d9de28325a4dbd15105.1583648927.git.sean.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index b7606130ade9..0447748f9fa0 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -138,6 +138,7 @@ mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + phy-mode = "rgmii"; phy-handle = <&phy5>; }; -- cgit v1.2.3-70-g09d2 From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Thu, 19 Mar 2020 23:44:24 +0100 Subject: ARM: dts: qcom: add scm definition to ipq806x Add missing scm definition for ipq806x soc Signed-off-by: Ansuel Smith Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 4021f661cd11..b912da9a3ff3 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -93,6 +93,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-70-g09d2 From 8acc36189dcaf4487d8c6ba7445948f39b1d248a Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Fri, 3 Apr 2020 13:40:40 +0200 Subject: ARM: dts: qcom: ipq4019: fix high resolution timer Cherry-picked from CAF QSDK repo. Original commit message: The kernel is failing in switching the timer for high resolution mode and clock source operates in 10ms resolution. The always-on property needs to be given for timer device tree node to make clock source working in 1ns resolution. Signed-off-by: Abhishek Sahu Signed-off-by: Pavel Kubelun Signed-off-by: Christian Lamparter Tested-by: Robert Marko Cc: Luka Perkov Link: https://lore.kernel.org/r/20200403114040.349787-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bfa9ce4c6e69..c6956015dedc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -166,6 +166,7 @@ <1 4 0xf08>, <1 1 0xf08>; clock-frequency = <48000000>; + always-on; }; soc { -- cgit v1.2.3-70-g09d2 From 5d2408c6cd594fa29c3989db65629827475d948c Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Thu, 2 Apr 2020 09:34:21 +0000 Subject: ARM: configs: sunxi: Add sun8i analog codec On my orange pi PC, I got lot of "sun4i-codec 1c22c00.codec: Failed to register our card". This was due to a missing component: the sun8i analog codec. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 61b8be19e527..b105ce7120cc 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -107,6 +107,7 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN8I_CODEC_ANALOG=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y -- cgit v1.2.3-70-g09d2 From 4a0cc312443d1de8d2c8839bedf67065012f722e Mon Sep 17 00:00:00 2001 From: Stefan Mavrodiev Date: Sat, 21 Mar 2020 09:57:56 +0200 Subject: ARM: dts: sun7i: Add A20-OLinuXino-LIME-eMMC There is new version of A20-OLinuXino-LIME with eMMC storage. The card routing is the same as in A20-OLinuXino-LIME2-eMMC, so this is basically copy/paste. Signed-off-by: Stefan Mavrodiev Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..3823090d07e7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1110,6 +1110,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-olimex-som204-evb.dtb \ sun7i-a20-olimex-som204-evb-emmc.dtb \ sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime-emmc.dtb \ sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-lime2-emmc.dtb \ sun7i-a20-olinuxino-micro.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts new file mode 100644 index 000000000000..033cab3443f8 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +#include "sun7i-a20-olinuxino-lime.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME-eMMC"; + compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; -- cgit v1.2.3-70-g09d2 From c21c2c86f6067d4d7c2bf5eab4940dd0c18dbecf Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Sat, 28 Mar 2020 17:16:32 +0800 Subject: ARM: dts: sun8i-h3: add opp table for mali gpu OPP table value is get from orangepi lichee linux-3.4 kernel driver. Signed-off-by: Qiang Yu Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index e83aa6866e7e..4e89701df91f 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -112,6 +112,26 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -205,9 +225,7 @@ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; + operating-points-v2 = <&gpu_opp_table>; }; ths: thermal-sensor@1c25000 { -- cgit v1.2.3-70-g09d2 From 9a0e4df7f9bebb07cc0a1737d6f63f9dcbac3cbc Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 22 Feb 2020 22:08:50 -0600 Subject: ARM: dts: sunxi: a83t: Add msgbox node The A83T SoC contains a message box that can be used to send messages and interrupts back and forth between the ARM application CPUs and the ARISC coprocessor. Add a device tree node for it. Tested-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 655404d6d3a3..c010b27fdb6a 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -610,6 +610,16 @@ clock-names = "bus", "mod"; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-a83t-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a83t-musb", "allwinner,sun8i-a33-musb"; -- cgit v1.2.3-70-g09d2 From 667aeaef74513173efc1755935cc8d225d30b50a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 22 Feb 2020 22:08:51 -0600 Subject: ARM: dts: sunxi: h3/h5: Add msgbox node The H3 and H5 SoCs contain a message box that can be used to send messages and interrupts back and forth between the ARM application CPUs and the ARISC coprocessor. Add a device tree node for it. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 01a5df9aa71b..22d533d18992 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -239,6 +239,16 @@ }; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-h3-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; -- cgit v1.2.3-70-g09d2 From 34b6826df7462c541752cf8b1de2691b26d78ae0 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Sat, 11 Apr 2020 19:48:43 +0200 Subject: ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWR-LED on the bananapi m2 zero board is on when gpio PL10 is low. This has been verified on a board and in the schematics [1]. [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#Documents Fixes: 8b8061fcbfae ("ARM: dts: sun8i: h2+: add support for Banana Pi M2 Zero board") Signed-off-by: Vincent Stehlé Cc: Icenowy Zheng Cc: Maxime Ripard Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d277d043031b..4c6704e4c57e 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -31,7 +31,7 @@ pwr_led { label = "bananapi-m2-zero:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ default-state = "on"; }; }; -- cgit v1.2.3-70-g09d2 From 911d1ef131945f57b7c229331da18c8fc9727efd Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 19 Dec 2019 21:20:52 +0100 Subject: ARM: defconfig: u8500: Enable new drivers for samsung-golden The new device tree for samsung-golden depends on some additional drivers that are not selected in the u8500 defconfig yet: - Bluetooth: hci_bcm - WiFi: brcmfmac - Touchscreen: atmel_mxt_ts - Vibrator: gpio-vibra - Sensors: inv_mpu6050 (IMU) Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20191219202052.19039-10-stephan@gerhold.net Signed-off-by: Linus Walleij --- arch/arm/configs/u8500_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 4dd5c92fe3b7..0fd2726cf1c1 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -32,6 +32,9 @@ CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NETFILTER=y CONFIG_PHONET=y +CONFIG_BT=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y CONFIG_CFG80211=y CONFIG_CFG80211_DEBUGFS=y CONFIG_MAC80211=y @@ -44,6 +47,7 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_NETDEVICES=y CONFIG_SMSC911X=y CONFIG_SMSC_PHY=y +CONFIG_BRCMFMAC=m CONFIG_CW1200=y CONFIG_CW1200_WLAN_SDIO=y CONFIG_INPUT_EVDEV=y @@ -54,9 +58,11 @@ CONFIG_KEYBOARD_STMPE=y CONFIG_KEYBOARD_TC3589X=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_BU21013=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AB8500_PONKEY=y +CONFIG_INPUT_GPIO_VIBRA=y CONFIG_RMI4_CORE=y CONFIG_RMI4_I2C=y CONFIG_RMI4_F11=y @@ -64,7 +70,9 @@ CONFIG_RMI4_F11=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y +CONFIG_I2C_MUX=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y @@ -115,6 +123,7 @@ CONFIG_IIO=y CONFIG_IIO_SW_TRIGGER=y CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_GYRO_3AXIS=y +CONFIG_INV_MPU6050_I2C=y CONFIG_BH1780=y CONFIG_AK8974=y CONFIG_IIO_ST_MAGN_3AXIS=y -- cgit v1.2.3-70-g09d2 From 2ae6193a1b95a128d040f0181d592bbf2705407b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 5 Apr 2020 19:32:51 +0200 Subject: ARM: dts: ux500: samsung-golden: Add proximity sensor samsung-golden has the same sharp,gp2ap002s00f proximity sensor that is also used in samsung-skomer. A driver was added for it in commit 97d642e23037 ("iio: light: Add a driver for Sharp GP2AP002x00F"). Now that it was merged we can add an entry for it in the device tree for samsung-golden. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200405173252.67614-1-stephan@gerhold.net Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 313f0ab16866..0e9e33f4ca3c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -146,6 +146,32 @@ pinctrl-1 = <&u2rxtx_c_1_sleep>; }; + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + reg = <0x44>; + + /* GPIO146 (PS_INT) */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&proximity_default>; + + sharp,proximity-far-hysteresis = <0x40>; + sharp,proximity-close-hysteresis = <0x0f>; + }; + }; + i2c@80128000 { status = "okay"; @@ -375,6 +401,15 @@ }; }; + proximity { + proximity_default: proximity_default { + golden_cfg1 { + pins = "GPIO146_D13"; /* PS_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + imu { imu_default: imu_default { golden_cfg1 { -- cgit v1.2.3-70-g09d2 From e1e2662036c01acc1418942d8febe0e726624669 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 13 Apr 2020 14:09:25 +0000 Subject: ARM: dts: at91: sama5d27_wlsom1: Add alias for i2c0 wlsom1 has an ATECC608A-TNGTLS Secure Element connected on the i2c0 bus. Add alias for the i2c device to not rely on probe order for the i2c device numbering. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200413140922.154886-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index db3e2239eee8..bea3d60b9722 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -17,6 +17,10 @@ model = "Microchip SAMA5D27 WLSOM1"; compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; -- cgit v1.2.3-70-g09d2 From f2e3d666a448e239420d6517f29eb3ab06a4740d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 12 Mar 2020 17:50:12 +0800 Subject: ARM: dts: imx7: Correct CPU supply name i.MX7 uses cpufreq-dt driver which requires the CPU supply name to be either "cpu0-supply" or "cpu-supply", correct it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-tqma7.dtsi | 2 +- arch/arm/boot/dts/imx7d-zii-rmu2.dts | 2 +- arch/arm/boot/dts/imx7d-zii-rpu2.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 9aaed85138cb..8773344b54aa 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -16,7 +16,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &i2c1 { diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index 2b8d6cc45a53..e5e20b07f184 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -33,7 +33,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &ecspi1 { diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index 39812c92bf0d..cbf0dbb4c198 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -182,7 +182,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &clks { -- cgit v1.2.3-70-g09d2 From 2d7401f8632fabea6b55a6c693caaa7436f14187 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 12 Mar 2020 17:50:13 +0800 Subject: ARM: dts: imx7d: Add cpu1 supply Each cpu-core is supposed to list its supply separately, add supply for cpu1. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 4 ++++ arch/arm/boot/dts/imx7d-colibri.dtsi | 4 ++++ arch/arm/boot/dts/imx7d-nitrogen7.dts | 4 ++++ arch/arm/boot/dts/imx7d-sdb.dts | 4 ++++ arch/arm/boot/dts/imx7d-tqma7.dtsi | 4 ++++ 5 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 89267cd59037..713483c39c9d 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -37,6 +37,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index c59d72e50920..219a0404a058 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -13,6 +13,10 @@ }; }; +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + &gpmi { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 6b4acea1ef79..e0751e6ba3c0 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -121,6 +121,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 869efbc4af42..17cca8a9f77b 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -162,6 +162,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi index 8ad3048dac0d..598aed1ffd99 100644 --- a/arch/arm/boot/dts/imx7d-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi @@ -9,3 +9,7 @@ #include "imx7d.dtsi" #include "imx7-tqma7.dtsi" + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; -- cgit v1.2.3-70-g09d2 From e7e5af7df1f518610aca8fa29a2eb711eb2ed5b2 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 16 Mar 2020 16:33:45 +0200 Subject: ARM: dts: colibri: introduce device trees with UHS-I support 1. Introduce dtsi with overlay configuration for enabling UHS-I for Colibri iMX6S/DL V1.1x re-design. 2. Introduce new dts for the Colibri iMX6S/DL V1.1x on Colibri Evaluation Carrier Board V3.x. However, disable 1.8V for the Colibri Evaluation Board since this carrier board has 3.3V pull-ups on. 3. Provide proper configuration for VGEN3, which allows that rail to be automatically switched to 1.8 volts for proper UHS-I operation mode. Signed-off-by: Igor Opaniuk Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts | 31 ++++++++++++++++ arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi | 44 +++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-colibri.dtsi | 11 +++++- 4 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts create mode 100644 arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..eccdf796276c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -412,6 +412,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-v1_1-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts new file mode 100644 index 000000000000..223275f028f1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1_1-uhs.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", + "toradex,colibri_imx6dl-v1_1", + "toradex,colibri_imx6dl-eval-v3", + "toradex,colibri_imx6dl", + "fsl,imx6dl"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; + /* + * Please make sure your carrier board does not pull-up any of + * the MMC/SD signals to 3.3 volt before attempting to activate + * UHS-I support. + * To let signaling voltage be changed to 1.8V, please + * delete no-1-8-v property (example below): + * /delete-property/no-1-8-v; + */ +}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi new file mode 100644 index 000000000000..7672fbfc29be --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&iomuxc { + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; + wakeup-source; + keep-power-in-suspend; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 6e3c6b4925a7..240b86d2eb71 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -193,7 +193,16 @@ regulator-always-on; }; - /* vgen3: unused */ + /* + * +V3.3_1.8_SD1 coming off VGEN3 and supplying + * the i.MX 6 NVCC_SD1. + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; -- cgit v1.2.3-70-g09d2 From df823a8208c434eee6e4e9aa016c956d0968e2e2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 15 Apr 2020 12:12:29 +0200 Subject: media: cec: rename CEC platform drivers config options Most CEC platform drivers are using VIDEO_*_CEC pattern, some with an _HDMI extension too. Well, they're not related to V4L2 support, and we don't really need those big config names. So drop VIDEO_* from them, remove _HDMI (if present) and move CEC to the start. This way, all platform driver options are now CEC_. Acked-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- arch/arm/configs/exynos_defconfig | 2 +- arch/arm/configs/multi_v7_defconfig | 2 +- drivers/media/cec/platform/Kconfig | 22 +++++++++++----------- drivers/media/cec/platform/Makefile | 16 ++++++++-------- drivers/media/cec/platform/cros-ec/Makefile | 2 +- drivers/media/cec/platform/meson/Makefile | 4 ++-- drivers/media/cec/platform/s5p/Makefile | 2 +- drivers/media/cec/platform/seco/Makefile | 2 +- drivers/media/cec/platform/seco/seco-cec.c | 2 +- drivers/media/cec/platform/sti/Makefile | 2 +- drivers/media/cec/platform/stm32/Makefile | 2 +- drivers/media/cec/platform/tegra/Makefile | 2 +- 12 files changed, 30 insertions(+), 30 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 3c3a00fc71f6..2c779ac13270 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -207,7 +207,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVID=m CONFIG_CEC_PLATFORM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_CEC=m +CONFIG_CEC_SAMSUNG_S5P=m # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_S5K6A3=m CONFIG_VIDEO_S5C73M3=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f8e45351c3f9..9c86b1ab2f1d 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -638,7 +638,7 @@ CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVID=m CONFIG_CEC_PLATFORM_DRIVERS=y -CONFIG_VIDEO_SAMSUNG_S5P_CEC=m +CONFIG_CEC_SAMSUNG_S5P=m CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ML86V7667=m CONFIG_IMX_IPUV3_CORE=m diff --git a/drivers/media/cec/platform/Kconfig b/drivers/media/cec/platform/Kconfig index 6a8bb8b68344..2c4dd7401dd8 100644 --- a/drivers/media/cec/platform/Kconfig +++ b/drivers/media/cec/platform/Kconfig @@ -2,7 +2,7 @@ # # Platform drivers -config VIDEO_CROS_EC_CEC +config CEC_CROS_EC tristate "ChromeOS EC CEC driver" depends on CROS_EC select CEC_CORE @@ -14,7 +14,7 @@ config VIDEO_CROS_EC_CEC The CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_MESON_AO_CEC +config CEC_MESON_AO tristate "Amlogic Meson AO CEC driver" depends on ARCH_MESON || COMPILE_TEST select CEC_CORE @@ -24,7 +24,7 @@ config VIDEO_MESON_AO_CEC generic CEC framework interface. CEC bus is present in the HDMI connector and enables communication -config VIDEO_MESON_G12A_AO_CEC +config CEC_MESON_G12A_AO tristate "Amlogic Meson G12A AO CEC driver" depends on ARCH_MESON || COMPILE_TEST depends on COMMON_CLK && OF @@ -52,7 +52,7 @@ config CEC_GPIO The CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_SAMSUNG_S5P_CEC +config CEC_SAMSUNG_S5P tristate "Samsung S5P CEC driver" depends on ARCH_EXYNOS || COMPILE_TEST select CEC_CORE @@ -63,7 +63,7 @@ config VIDEO_SAMSUNG_S5P_CEC CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_STI_HDMI_CEC +config CEC_STI tristate "STMicroelectronics STiH4xx HDMI CEC driver" depends on ARCH_STI || COMPILE_TEST select CEC_CORE @@ -74,7 +74,7 @@ config VIDEO_STI_HDMI_CEC CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_STM32_HDMI_CEC +config CEC_STM32 tristate "STMicroelectronics STM32 HDMI CEC driver" depends on ARCH_STM32 || COMPILE_TEST select REGMAP @@ -86,7 +86,7 @@ config VIDEO_STM32_HDMI_CEC CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_TEGRA_HDMI_CEC +config CEC_TEGRA tristate "Tegra HDMI CEC driver" depends on ARCH_TEGRA || COMPILE_TEST select CEC_CORE @@ -97,7 +97,7 @@ config VIDEO_TEGRA_HDMI_CEC The CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_SECO_CEC +config CEC_SECO tristate "SECO Boards HDMI CEC driver" depends on (X86 || IA64) || COMPILE_TEST select PCI @@ -110,10 +110,10 @@ config VIDEO_SECO_CEC CEC bus is present in the HDMI connector and enables communication between compatible devices. -config VIDEO_SECO_RC +config CEC_SECO_RC bool "SECO Boards IR RC5 support" - depends on VIDEO_SECO_CEC - depends on RC_CORE=y || RC_CORE = VIDEO_SECO_CEC + depends on CEC_SECO + depends on RC_CORE=y || RC_CORE = CEC_SECO help If you say yes here you will get support for the SECO Boards Consumer-IR in seco-cec driver. diff --git a/drivers/media/cec/platform/Makefile b/drivers/media/cec/platform/Makefile index e5fb5d383e5c..3a947159b25a 100644 --- a/drivers/media/cec/platform/Makefile +++ b/drivers/media/cec/platform/Makefile @@ -3,12 +3,12 @@ # Makefile for the CEC platform device drivers. # -obj-$(CONFIG_CEC_GPIO) += cec-gpio/ - -obj-$(CONFIG_VIDEO_CROS_EC_CEC) += cros-ec/ -obj-$(CONFIG_VIDEO_MESON_AO_CEC) += meson/ -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_CEC) += s5p/ -obj-$(CONFIG_VIDEO_SECO_CEC) += seco/ -obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += sti/ -obj-$(CONFIG_VIDEO_TEGRA_HDMI_CEC) += tegra/ +# Please keep it in alphabetic order +obj-$(CONFIG_CEC_CROS_EC) += cros-ec/ +obj-$(CONFIG_CEC_GPIO) += cec-gpio/ +obj-$(CONFIG_CEC_MESON_AO) += meson/ +obj-$(CONFIG_CEC_SAMSUNG_S5P) += s5p/ +obj-$(CONFIG_CEC_SECO) += seco/ +obj-$(CONFIG_CEC_STI) += sti/ +obj-$(CONFIG_CEC_TEGRA) += tegra/ diff --git a/drivers/media/cec/platform/cros-ec/Makefile b/drivers/media/cec/platform/cros-ec/Makefile index 2615cdc6e227..d7e3511078ef 100644 --- a/drivers/media/cec/platform/cros-ec/Makefile +++ b/drivers/media/cec/platform/cros-ec/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_CROS_EC_CEC) += cros-ec-cec.o +obj-$(CONFIG_CEC_CROS_EC) += cros-ec-cec.o diff --git a/drivers/media/cec/platform/meson/Makefile b/drivers/media/cec/platform/meson/Makefile index 6bf728addbf8..34fc5d444d0e 100644 --- a/drivers/media/cec/platform/meson/Makefile +++ b/drivers/media/cec/platform/meson/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_MESON_AO_CEC) += ao-cec.o -obj-$(CONFIG_VIDEO_MESON_G12A_AO_CEC) += ao-cec-g12a.o +obj-$(CONFIG_CEC_MESON_AO) += ao-cec.o +obj-$(CONFIG_CEC_MESON_G12A_AO) += ao-cec-g12a.o diff --git a/drivers/media/cec/platform/s5p/Makefile b/drivers/media/cec/platform/s5p/Makefile index bd0103b91bee..92bf7b8557c5 100644 --- a/drivers/media/cec/platform/s5p/Makefile +++ b/drivers/media/cec/platform/s5p/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_SAMSUNG_S5P_CEC) += s5p-cec.o +obj-$(CONFIG_CEC_SAMSUNG_S5P) += s5p-cec.o s5p-cec-y += s5p_cec.o exynos_hdmi_cecctrl.o diff --git a/drivers/media/cec/platform/seco/Makefile b/drivers/media/cec/platform/seco/Makefile index 79fde6947ff2..aa1ca8ccdb8b 100644 --- a/drivers/media/cec/platform/seco/Makefile +++ b/drivers/media/cec/platform/seco/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_SECO_CEC) += seco-cec.o +obj-$(CONFIG_CEC_SECO) += seco-cec.o diff --git a/drivers/media/cec/platform/seco/seco-cec.c b/drivers/media/cec/platform/seco/seco-cec.c index 2ff62a488b27..075dd79beb6f 100644 --- a/drivers/media/cec/platform/seco/seco-cec.c +++ b/drivers/media/cec/platform/seco/seco-cec.c @@ -343,7 +343,7 @@ static const struct cec_adap_ops secocec_cec_adap_ops = { .adap_transmit = secocec_adap_transmit, }; -#ifdef CONFIG_VIDEO_SECO_RC +#ifdef CONFIG_CEC_SECO_RC static int secocec_ir_probe(void *priv) { struct secocec_data *cec = priv; diff --git a/drivers/media/cec/platform/sti/Makefile b/drivers/media/cec/platform/sti/Makefile index d0c6b4ae94d6..26ec5ba1c633 100644 --- a/drivers/media/cec/platform/sti/Makefile +++ b/drivers/media/cec/platform/sti/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += stih-cec.o +obj-$(CONFIG_CEC_STI) += stih-cec.o diff --git a/drivers/media/cec/platform/stm32/Makefile b/drivers/media/cec/platform/stm32/Makefile index 5c89dbce0f67..b7597a00befa 100644 --- a/drivers/media/cec/platform/stm32/Makefile +++ b/drivers/media/cec/platform/stm32/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_STM32_HDMI_CEC) += stm32-cec.o +obj-$(CONFIG_CEC_STM32) += stm32-cec.o diff --git a/drivers/media/cec/platform/tegra/Makefile b/drivers/media/cec/platform/tegra/Makefile index 97e57c7493c0..275d1c019d49 100644 --- a/drivers/media/cec/platform/tegra/Makefile +++ b/drivers/media/cec/platform/tegra/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_VIDEO_TEGRA_HDMI_CEC) += tegra_cec.o +obj-$(CONFIG_CEC_TEGRA) += tegra_cec.o -- cgit v1.2.3-70-g09d2 From 5429ef62bcf360aae06740cbe065be01e5cfb6fc Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 22 Jan 2020 19:38:21 +0000 Subject: compiler/gcc: Raise minimum GCC version for kernel builds to 4.8 It is very rare to see versions of GCC prior to 4.8 being used to build the mainline kernel. These old compilers are also know to have codegen issues which can lead to silent miscompilation: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 Raise the minimum GCC version for kernel build to 4.8 and remove some tautological Kconfig dependencies as a consequence. Cc: Masahiro Yamada Acked-by: Arnd Bergmann Reviewed-by: Nick Desaulniers Signed-off-by: Will Deacon --- Documentation/process/changes.rst | 2 +- arch/arm/crypto/Kconfig | 12 ++++++------ crypto/Kconfig | 1 - include/linux/compiler-gcc.h | 5 ++--- init/Kconfig | 1 - scripts/gcc-plugins/Kconfig | 2 +- 6 files changed, 10 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index 91c5ff8e161e..5cfb54c2aaa6 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -29,7 +29,7 @@ you probably needn't concern yourself with pcmciautils. ====================== =============== ======================================== Program Minimal version Command to check the version ====================== =============== ======================================== -GNU C 4.6 gcc --version +GNU C 4.8 gcc --version GNU make 3.81 make --version binutils 2.23 ld -v flex 2.5.35 flex --version diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig index 2674de6ada1f..c9bf2df85cb9 100644 --- a/arch/arm/crypto/Kconfig +++ b/arch/arm/crypto/Kconfig @@ -30,7 +30,7 @@ config CRYPTO_SHA1_ARM_NEON config CRYPTO_SHA1_ARM_CE tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON select CRYPTO_SHA1_ARM select CRYPTO_HASH help @@ -39,7 +39,7 @@ config CRYPTO_SHA1_ARM_CE config CRYPTO_SHA2_ARM_CE tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON select CRYPTO_SHA256_ARM select CRYPTO_HASH help @@ -96,7 +96,7 @@ config CRYPTO_AES_ARM_BS config CRYPTO_AES_ARM_CE tristate "Accelerated AES using ARMv8 Crypto Extensions" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON select CRYPTO_SKCIPHER select CRYPTO_LIB_AES select CRYPTO_SIMD @@ -106,7 +106,7 @@ config CRYPTO_AES_ARM_CE config CRYPTO_GHASH_ARM_CE tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON select CRYPTO_HASH select CRYPTO_CRYPTD select CRYPTO_GF128MUL @@ -118,13 +118,13 @@ config CRYPTO_GHASH_ARM_CE config CRYPTO_CRCT10DIF_ARM_CE tristate "CRCT10DIF digest algorithm using PMULL instructions" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON depends on CRC_T10DIF select CRYPTO_HASH config CRYPTO_CRC32_ARM_CE tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions" - depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + depends on KERNEL_MODE_NEON depends on CRC32 select CRYPTO_HASH diff --git a/crypto/Kconfig b/crypto/Kconfig index c24a47406f8f..34a8c5bfd062 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -316,7 +316,6 @@ config CRYPTO_AEGIS128 config CRYPTO_AEGIS128_SIMD bool "Support SIMD acceleration for AEGIS-128" depends on CRYPTO_AEGIS128 && ((ARM || ARM64) && KERNEL_MODE_NEON) - depends on !ARM || CC_IS_CLANG || GCC_VERSION >= 40800 default y config CRYPTO_AEGIS128_AESNI_SSE2 diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index d7ee4c6bad48..e2f725273261 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -10,7 +10,8 @@ + __GNUC_MINOR__ * 100 \ + __GNUC_PATCHLEVEL__) -#if GCC_VERSION < 40600 +/* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 */ +#if GCC_VERSION < 40800 # error Sorry, your compiler is too old - please upgrade it. #endif @@ -126,9 +127,7 @@ #if defined(CONFIG_ARCH_USE_BUILTIN_BSWAP) && !defined(__CHECKER__) #define __HAVE_BUILTIN_BSWAP32__ #define __HAVE_BUILTIN_BSWAP64__ -#if GCC_VERSION >= 40800 #define __HAVE_BUILTIN_BSWAP16__ -#endif #endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP && !__CHECKER__ */ #if GCC_VERSION >= 70000 diff --git a/init/Kconfig b/init/Kconfig index 9e22ee8fbd75..035d38a4f9ad 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -1285,7 +1285,6 @@ config LD_DEAD_CODE_DATA_ELIMINATION bool "Dead code and data elimination (EXPERIMENTAL)" depends on HAVE_LD_DEAD_CODE_DATA_ELIMINATION depends on EXPERT - depends on !(FUNCTION_TRACER && CC_IS_GCC && GCC_VERSION < 40800) depends on $(cc-option,-ffunction-sections -fdata-sections) depends on $(ld-option,--gc-sections) help diff --git a/scripts/gcc-plugins/Kconfig b/scripts/gcc-plugins/Kconfig index 013ba3a57669..ce0b99fb5847 100644 --- a/scripts/gcc-plugins/Kconfig +++ b/scripts/gcc-plugins/Kconfig @@ -8,7 +8,7 @@ config HAVE_GCC_PLUGINS menuconfig GCC_PLUGINS bool "GCC plugins" depends on HAVE_GCC_PLUGINS - depends on CC_IS_GCC && GCC_VERSION >= 40800 + depends on CC_IS_GCC depends on $(success,$(srctree)/scripts/gcc-plugin.sh $(CC)) default y help -- cgit v1.2.3-70-g09d2 From ba637aa019e038a518236bb56afcdb86ebfd269c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Jan 2020 11:37:13 +0100 Subject: ARM: integrator: Drop unneeded select of SPARSE_IRQ Support for ARM Ltd. Integrator systems depends on ARCH_MULTIPLATFORM. As the latter selects SPARSE_IRQ, there is no need for ARCH_INTEGRATOR to select SPARSE_IRQ. Signed-off-by: Geert Uytterhoeven Cc: Linus Walleij Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 982eabc36163..fbc35e9db46d 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -12,7 +12,6 @@ menuconfig ARCH_INTEGRATOR select POWER_RESET_VERSATILE select POWER_SUPPLY select SOC_INTEGRATOR_CM - select SPARSE_IRQ select VERSATILE_FPGA_IRQ help Support for ARM's Integrator platform. -- cgit v1.2.3-70-g09d2 From 65fd41e6fa2ee0905b06379d1ef1ff52b3f27156 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 21 Jan 2020 11:37:20 +0100 Subject: ARM: realview: Drop unneeded select of multi-platform features Support for ARM Ltd. RealView systems depends on ARCH_MULTIPLATFORM, which selects USE_OF. Support for ARMv6 and ARMv7 variants depends on ARCH_MULTI_V6 or ARCH_MULTI_V7, which both select ARCH_MULTI_V6_V7 and thus MIGHT_HAVE_CACHE_L2X0. Support for ARMv7 variants depends on ARCH_MULTI_V7, which selects HAVE_SMP. Hence there is no need for the affected RealView-specific symbols to select any of them. Signed-off-by: Geert Uytterhoeven Cc: Linus Walleij Signed-off-by: Linus Walleij --- arch/arm/mach-realview/Kconfig | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 44ebbf9ec673..0f139a20e113 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -21,7 +21,6 @@ menuconfig ARCH_REALVIEW select POWER_RESET_VERSATILE select POWER_SUPPLY select SOC_REALVIEW - select USE_OF help This enables support for ARM Ltd RealView boards. @@ -56,8 +55,6 @@ config REALVIEW_EB_ARM1176 config REALVIEW_EB_A9MP bool "Support Multicore Cortex-A9 Tile" depends on MACH_REALVIEW_EB && ARCH_MULTI_V7 - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 help Enable support for the Cortex-A9MPCore tile fitted to the Realview(R) Emulation Baseboard platform. @@ -66,7 +63,6 @@ config REALVIEW_EB_ARM11MP bool "Support ARM11MPCore Tile" depends on MACH_REALVIEW_EB && ARCH_MULTI_V6 select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 help Enable support for the ARM11MPCore tile fitted to the Realview(R) Emulation Baseboard platform. @@ -75,7 +71,6 @@ config MACH_REALVIEW_PB11MP bool "Support RealView(R) Platform Baseboard for ARM11MPCore" depends on ARCH_MULTI_V6 select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 help Include support for the ARM(R) RealView(R) Platform Baseboard for the ARM11MPCore. This platform has an on-board ARM11MPCore and has @@ -87,7 +82,6 @@ config MACH_REALVIEW_PB1176 depends on ARCH_MULTI_V6 select CPU_V6 select HAVE_TCM - select MIGHT_HAVE_CACHE_L2X0 help Include support for the ARM(R) RealView(R) Platform Baseboard for ARM1176JZF-S. @@ -103,8 +97,6 @@ config MACH_REALVIEW_PBA8 config MACH_REALVIEW_PBX bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9" depends on ARCH_MULTI_V7 - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 select ZONE_DMA help Include support for the ARM(R) RealView(R) Platform Baseboard -- cgit v1.2.3-70-g09d2 From db1e113578193c9f8d308cf1edfc1cb050984268 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Apr 2020 16:19:52 -0600 Subject: ARM: versatile: Remove dead sched_clock code Now that there's a DT based sched_clock driver in drivers/clocksource/timer-versatile.c and all the Arm reference platforms are DT only, the non-DT versatile sched_clock code can be removed. Cc: Linus Walleij Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20200409221952.31287-1-robh@kernel.org Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 1 - arch/arm/mach-realview/Kconfig | 1 - arch/arm/plat-versatile/Kconfig | 7 ------ arch/arm/plat-versatile/Makefile | 1 - arch/arm/plat-versatile/include/plat/sched_clock.h | 7 ------ arch/arm/plat-versatile/sched-clock.c | 28 ---------------------- 6 files changed, 45 deletions(-) delete mode 100644 arch/arm/plat-versatile/Kconfig delete mode 100644 arch/arm/plat-versatile/include/plat/sched_clock.h delete mode 100644 arch/arm/plat-versatile/sched-clock.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 66a04f6f4775..4595e5cd6602 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -735,7 +735,6 @@ source "arch/arm/mach-ux500/Kconfig" source "arch/arm/mach-versatile/Kconfig" source "arch/arm/mach-vexpress/Kconfig" -source "arch/arm/plat-versatile/Kconfig" source "arch/arm/mach-vt8500/Kconfig" diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 0f139a20e113..0bed0d3ab364 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -16,7 +16,6 @@ menuconfig ARCH_REALVIEW select MACH_REALVIEW_EB if ARCH_MULTI_V5 select MFD_SYSCON select PLAT_VERSATILE - select PLAT_VERSATILE_SCHED_CLOCK select POWER_RESET select POWER_RESET_VERSATILE select POWER_SUPPLY diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig deleted file mode 100644 index 748238f9f10e..000000000000 --- a/arch/arm/plat-versatile/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -if PLAT_VERSATILE - -config PLAT_VERSATILE_SCHED_CLOCK - bool - -endif diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index e856f0a4ac6e..5de44a57c4de 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/plat-versatile/include/plat/sched_clock.h b/arch/arm/plat-versatile/include/plat/sched_clock.h deleted file mode 100644 index 83fdaef23c2e..000000000000 --- a/arch/arm/plat-versatile/include/plat/sched_clock.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef ARM_PLAT_SCHED_CLOCK_H -#define ARM_PLAT_SCHED_CLOCK_H - -void versatile_sched_clock_init(void __iomem *, unsigned long); - -#endif diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c deleted file mode 100644 index ecb7913d2f53..000000000000 --- a/arch/arm/plat-versatile/sched-clock.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * linux/arch/arm/plat-versatile/sched-clock.c - * - * Copyright (C) 1999 - 2003 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - */ -#include -#include -#include - -#include - -static void __iomem *ctr; - -static u64 notrace versatile_read_sched_clock(void) -{ - if (ctr) - return readl(ctr); - - return 0; -} - -void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) -{ - ctr = reg; - sched_clock_register(versatile_read_sched_clock, 32, rate); -} -- cgit v1.2.3-70-g09d2 From ce7107697986edff2bd7e8d0c0990d3109b5a009 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Apr 2020 16:20:14 -0600 Subject: ARM: versatile: Drop mapping IB2 module registers As of commit 153969fd952d ("ARM: versatile: Drop CLCD platform data"), the IB2 module is not accessed in the platform code, so let's remove mapping it. Cc: Linus Walleij Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20200409222014.31828-1-robh@kernel.org Signed-off-by: Linus Walleij --- arch/arm/mach-versatile/versatile_dt.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c index c00ea4f77af6..02ba68abe533 100644 --- a/arch/arm/mach-versatile/versatile_dt.c +++ b/arch/arm/mach-versatile/versatile_dt.c @@ -39,8 +39,6 @@ #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ -#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ -#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000) /* * System controller bit assignment @@ -54,7 +52,6 @@ #define VERSATILE_TIMER4_EnSel 21 static void __iomem *versatile_sys_base; -static void __iomem *versatile_ib2_ctrl; unsigned int mmc_status(struct device *dev) { @@ -169,8 +166,6 @@ static void __init versatile_dt_init(void) versatile_sys_base = of_iomap(np, 0); WARN_ON(!versatile_sys_base); - versatile_ib2_ctrl = ioremap(VERSATILE_IB2_CTL_BASE, SZ_4K); - versatile_dt_pci_init(); of_platform_default_populate(NULL, versatile_auxdata_lookup, NULL); -- cgit v1.2.3-70-g09d2 From 7860c8738a164035a24fa471a27d25214e1211b0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Jan 2020 17:08:55 -0600 Subject: ARM: tegra: Kill off "simple-panel" compatibles "simple-panel" is a Linux driver and has never been an accepted upstream compatible string, so remove it. Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 3 +-- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 +- arch/arm/boot/dts/tegra20-harmony.dts | 2 +- arch/arm/boot/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 2 +- arch/arm/boot/dts/tegra20-seaboard.dts | 2 +- arch/arm/boot/dts/tegra20-ventana.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 2 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 2 +- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- 13 files changed, 13 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index d3e032e7d21a..08be733ee2cd 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -46,8 +46,7 @@ avdd-dsi-csi-supply = <&avdd_1v2_reg>; panel@0 { - compatible = "panasonic,vvx10f004b00", - "simple-panel"; + compatible = "panasonic,vvx10f004b00"; reg = <0>; power-supply = <&avdd_lcd_reg>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 8c2ee6e7d6f1..73361dbe2e43 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ }; panel: panel { - compatible = "lg,lp129qe", "simple-panel"; + compatible = "lg,lp129qe"; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index 3c0f2681fcde..37ad508b61d9 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -223,7 +223,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index d8004d68efa0..af4740847769 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -205,7 +205,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 1d96d92b72a7..02cd67ea2503 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -665,7 +665,7 @@ }; panel: panel { - compatible = "auo,b101aw03", "simple-panel"; + compatible = "auo,b101aw03"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index cda5448c2ace..c73510cd501c 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -57,7 +57,7 @@ }; panel: panel { - compatible = "innolux,n156bge-l21", "simple-panel"; + compatible = "innolux,n156bge-l21"; power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index be0ab9b84b9a..cce3a3fb82ed 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -604,7 +604,7 @@ }; panel: panel { - compatible = "samsung,ltn101nt05", "simple-panel"; + compatible = "samsung,ltn101nt05"; ddc-i2c-bus = <&lvds_ddc>; power-supply = <&vdd_pnl_reg>; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f91441683aad..376ecb6435f4 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -826,7 +826,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index f44551e2d9d0..022649119821 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -611,7 +611,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 749fc6d1ff70..b39c26806bf2 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -195,7 +195,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index 0be50e881684..e29dca92ba0a 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -196,7 +196,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 4b4f49a49394..5ee5d141bd81 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -432,7 +432,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wb01", "simple-panel"; + compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; power-supply = <&vdd_pnl1_reg>; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 5965150ecdd2..8e106e784dce 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -159,7 +159,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; -- cgit v1.2.3-70-g09d2 From 248a8ffd2c9de33b67bb0469fab7867f960c7169 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sun, 22 Mar 2020 17:16:31 +0100 Subject: dts: arm: stih418: Fix complain about IRQ_TYPE_NONE usage Since commit 83a86fbb5b56 ("irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE") kernel is complaining about the IRQ_TYPE_NONE usage which shouldn't be used. Use IRQ_TYPE_LEVEL_HIGH instead. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih418.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 83411322bd92..a05e2278b448 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -50,7 +50,7 @@ ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; - interrupts = ; + interrupts = ; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; @@ -62,7 +62,7 @@ ehci0: usb@9a03e00 { compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; @@ -76,7 +76,7 @@ ohci1: usb@9a83c00 { compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; - interrupts = ; + interrupts = ; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; @@ -88,7 +88,7 @@ ehci1: usb@9a83e00 { compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; -- cgit v1.2.3-70-g09d2 From 7f21a85085b7211ec1d1583d10912ad272ab76bc Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sun, 22 Mar 2020 17:16:16 +0100 Subject: dts: arm: stih407-family: remove duplicated rng nodes the 2 rng nodes are duplicated within the stih407-family.dtsi Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih407-family.dtsi | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 7c36c37260a4..23a1746f3baa 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -767,20 +767,6 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; -- cgit v1.2.3-70-g09d2 From 5e4096ef03dcabd39e1d98856cd92f7359bc13e0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 15 Apr 2020 18:50:55 +0200 Subject: ARM/fbdev: sa11x0: Switch to use GPIO descriptors This converts the SA11x0 frame buffer driver to use GPIO descriptors. Get the GPIO optional and register a look-up table specifically for the Shannon machine. Signed-off-by: Linus Walleij Cc: Russell King Signed-off-by: Bartlomiej Zolnierkiewicz Link: https://patchwork.freedesktop.org/patch/msgid/20200415165055.193113-1-linus.walleij@linaro.org --- arch/arm/mach-sa1100/shannon.c | 9 +++++++++ drivers/video/fbdev/sa1100fb.c | 20 +++++++++----------- drivers/video/fbdev/sa1100fb.h | 3 +++ 3 files changed, 21 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c index 5bc82e2671c6..351f891b4842 100644 --- a/arch/arm/mach-sa1100/shannon.c +++ b/arch/arm/mach-sa1100/shannon.c @@ -104,6 +104,14 @@ static struct fixed_voltage_config shannon_cf_vcc_pdata __initdata = { .enabled_at_boot = 1, }; +static struct gpiod_lookup_table shannon_display_gpio_table = { + .dev_id = "sa11x0-fb", + .table = { + GPIO_LOOKUP("gpio", 22, "shannon-lcden", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static void __init shannon_init(void) { sa11x0_register_fixed_regulator(0, &shannon_cf_vcc_pdata, @@ -113,6 +121,7 @@ static void __init shannon_init(void) sa11x0_register_pcmcia(0, &shannon_pcmcia0_gpio_table); sa11x0_register_pcmcia(1, &shannon_pcmcia1_gpio_table); sa11x0_ppc_configure_mcp(); + gpiod_add_lookup_table(&shannon_display_gpio_table); sa11x0_register_lcd(&shannon_lcd_info); sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); sa11x0_register_mcp(&shannon_mcp_data); diff --git a/drivers/video/fbdev/sa1100fb.c b/drivers/video/fbdev/sa1100fb.c index 2d285cc384cf..3e6e13f7a831 100644 --- a/drivers/video/fbdev/sa1100fb.c +++ b/drivers/video/fbdev/sa1100fb.c @@ -173,7 +173,7 @@ #include #include #include -#include +#include #include #include #include @@ -799,8 +799,8 @@ static void sa1100fb_enable_controller(struct sa1100fb_info *fbi) writel_relaxed(fbi->dbar2, fbi->base + DBAR2); writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0); - if (machine_is_shannon()) - gpio_set_value(SHANNON_GPIO_DISP_EN, 1); + if (fbi->shannon_lcden) + gpiod_set_value(fbi->shannon_lcden, 1); dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1)); dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2)); @@ -817,8 +817,8 @@ static void sa1100fb_disable_controller(struct sa1100fb_info *fbi) dev_dbg(fbi->dev, "Disabling LCD controller\n"); - if (machine_is_shannon()) - gpio_set_value(SHANNON_GPIO_DISP_EN, 0); + if (fbi->shannon_lcden) + gpiod_set_value(fbi->shannon_lcden, 0); set_current_state(TASK_UNINTERRUPTIBLE); add_wait_queue(&fbi->ctrlr_wait, &wait); @@ -1173,12 +1173,10 @@ static int sa1100fb_probe(struct platform_device *pdev) return ret; } - if (machine_is_shannon()) { - ret = devm_gpio_request_one(&pdev->dev, SHANNON_GPIO_DISP_EN, - GPIOF_OUT_INIT_LOW, "display enable"); - if (ret) - return ret; - } + fbi->shannon_lcden = gpiod_get_optional(&pdev->dev, "shannon-lcden", + GPIOD_OUT_LOW); + if (IS_ERR(fbi->shannon_lcden)) + return PTR_ERR(fbi->shannon_lcden); /* Initialize video memory */ ret = sa1100fb_map_video_memory(fbi); diff --git a/drivers/video/fbdev/sa1100fb.h b/drivers/video/fbdev/sa1100fb.h index d0aa33b0b88a..b4363444fa5d 100644 --- a/drivers/video/fbdev/sa1100fb.h +++ b/drivers/video/fbdev/sa1100fb.h @@ -10,6 +10,8 @@ * for more details. */ +struct gpio_desc; + #define LCCR0 0x0000 /* LCD Control Reg. 0 */ #define LCSR 0x0004 /* LCD Status Reg. */ #define DBAR1 0x0010 /* LCD DMA Base Address Reg. channel 1 */ @@ -33,6 +35,7 @@ struct sa1100fb_info { struct device *dev; const struct sa1100fb_rgb *rgb[NR_RGB]; void __iomem *base; + struct gpio_desc *shannon_lcden; /* * These are the addresses we mapped -- cgit v1.2.3-70-g09d2 From 4c427ab28fd1cd988fce9517527476cfebd27485 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 15 Apr 2020 14:49:23 +0200 Subject: ARM: shmobile: defconfig: Refresh for v5.7-rc1 Update the defconfig for Renesas ARM boards: - Enable CONFIG_DRM_DISPLAY_CONNECTOR (for HDMI, VGA, and composite display connectors on various R-Car H1, Gen2, and RZ/G1 boards, since commit 0c275c30176b2e78 ("drm/bridge: Add bridge driver for display connectors")). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200415124923.2510-1-geert+renesas@glider.be --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 838307a9bb92..ef3b9d0d6e50 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -125,6 +125,7 @@ CONFIG_VIDEO_ML86V7667=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_SII902X=y CONFIG_DRM_SIMPLE_BRIDGE=y -- cgit v1.2.3-70-g09d2 From d92798d5759d7894921b320de64b9e83dfb3000c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 16 Mar 2020 11:25:39 +0100 Subject: ARM: dts: r8a7791: Add TPU device node Enable support for the 4 PWM channels provided by the 16-bit Timer Pulse Unit on R-Car M2-W, by adding a device node describing the TPU. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200316102540.28887-2-geert+renesas@glider.be --- arch/arm/boot/dts/r8a7791.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6e5bd86731cd..ba006daf5eee 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -291,6 +291,17 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7791", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7791-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit v1.2.3-70-g09d2 From 124eb5dc4ca5f4beeef1c0f29f3a053a0d0f5e46 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 16 Mar 2020 11:25:40 +0100 Subject: ARM: dts: r8a7791: Add PWM device nodes Enable support for the 7 PWM channels provided by PWM Timers on R-Car M2-W, by adding device nodes describing the PWM Timers. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200316102540.28887-3-geert+renesas@glider.be --- arch/arm/boot/dts/r8a7791.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index ba006daf5eee..b2d329a5d8d5 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1078,6 +1078,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; -- cgit v1.2.3-70-g09d2 From 546283d580c7564f895a47910dbe59c53a091d35 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Thu, 19 Mar 2020 11:23:31 +0100 Subject: ARM: dts: stm32: fix a typo for DAC io-channel-cells on stm32f429 Fix a typo on STM32F429 DAC, e.g. s/channels/channel Fixes: 25329b23fae9 ("ARM: dts: stm32: Add DAC support on stm32f429") Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index d7770699feb5..393f43c85a3c 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -414,14 +414,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From a7c0bbc3fd612531714bd6aae33bbdedb215a9f5 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Thu, 19 Mar 2020 11:26:11 +0100 Subject: ARM: dts: stm32: fix a typo for DAC io-channel-cells on stm32h743 Fix a typo on STM32H743 DAC, e.g. s/channels/channel Fixes: 1536dec45e77 ("ARM: dts: stm32: Add DAC support on stm32h743") Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 05eb02e6d083..9b7fc68380e9 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -180,14 +180,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From 4bbb76eedde97a84b54e89527993bb1d9493e1c7 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Thu, 19 Mar 2020 11:30:26 +0100 Subject: ARM: dts: stm32: fix a typo for DAC io-channel-cells on stm32mp15 Fix a typo on STM32MP15 DAC, e.g. s/channels/channel Fixes: da6cddc7e8a4 ("ARM: dts: stm32: Add DAC support to stm32mp157c") Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3ea05ba48215..5260818543e5 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -550,14 +550,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From 88fcb8a340e5221fdb0317a26f16d1df1776f0a9 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:05 +0100 Subject: ARM: dts: stm32: enable stm32mp157's &gpu by default In the original stm32mp157c.dtsi, the GPU was disabled as some SoC variants lacked a GPU. We now have separate a dtsi for each SoC variant and variants without a GPU lack the node altogether. As we need no board support for using the GPU, enable it by default and while at it remove the now redundant status = "okay" in existing board device trees. Suggested-by: Lucas Stach Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157.dtsi | 1 - arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi | 4 ---- arch/arm/boot/dts/stm32mp157c-ed1.dts | 1 - arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 1 - 4 files changed, 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 3f0a4a91cce6..5e733cd16ff9 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -15,7 +15,6 @@ clocks = <&rcc GPU>, <&rcc GPU_K>; clock-names = "bus" ,"core"; resets = <&rcc GPU_R>; - status = "disabled"; }; dsi: dsi@5a000000 { diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi index f81dc3134135..f97e0d2ecf17 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi @@ -97,10 +97,6 @@ status = "okay"; }; -&gpu { - status = "okay"; -}; - &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 9d2592db630c..e9aad3e101ac 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -126,7 +126,6 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c4 { diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index d946e0a02f5c..558a91a6962b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -137,7 +137,6 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c1 { -- cgit v1.2.3-70-g09d2 From 9c32f980d999b4f441044f94005b3e649d036694 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:06 +0100 Subject: ARM: dts: stm32: preset stm32mp15x video #address- and #size-cells The cell count for address and size is defined by the binding and not something a board would change. Avoid each board adding this boilerplate by having the cell size specification in the SoC DTSI. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 +++++ arch/arm/boot/dts/stm32mp157.dtsi | 7 +++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 5260818543e5..d70fc774e0a4 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1423,6 +1423,11 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; iwdg2: watchdog@5a002000 { diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi index 5e733cd16ff9..54e73ccea446 100644 --- a/arch/arm/boot/dts/stm32mp157.dtsi +++ b/arch/arm/boot/dts/stm32mp157.dtsi @@ -24,7 +24,14 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; -- cgit v1.2.3-70-g09d2 From 276bd3f003b18f4bff3b5db68bd3a746653cb8f8 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:07 +0100 Subject: ARM: dts: stm32: remove now redundant STM32MP15x video cell sizes With the cell sizes specified in the SoC DTSIs in a previous commit, individual boards no longer need to specify them, thus drop them. No functional change. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 8 -------- arch/arm/boot/dts/stm32mp157c-ev1.dts | 8 -------- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 3 --- 3 files changed, 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 7985b80967ca..9a8a26710ac1 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -27,15 +27,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -83,9 +78,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 8a4c7ff31a92..26db0fe93a98 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -98,15 +98,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; phy-dsi-supply = <®18>; status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -240,9 +235,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_in>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 558a91a6962b..f964e2ae7d60 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -394,9 +394,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&sii9022_in>; -- cgit v1.2.3-70-g09d2 From 6ddf19e09fb29d1661ca4f0a5eaff7141879c7fe Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:08 +0100 Subject: ARM: dts: stm32: use uniform label names for sleep pinctrl phandles Some labels follow the *_sleep_pins_* naming scheme, but some also use *_pins_sleep_*. Because most labels use the former and for uniformity with variants like sdmmc1_b4_pins_a and sdmmc1_dir_pins_a, adopt the *_sleep_pins_* scheme throughout. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 28 ++++++++++++++-------------- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 2 +- arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 4 ++-- arch/arm/boot/dts/stm32mp157c-ed1.dts | 2 +- arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 +++--- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 12 ++++++------ 6 files changed, 27 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 73c07f0dfad2..1971a9603ba6 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -37,7 +37,7 @@ }; }; - cec_pins_sleep_a: cec-sleep-0 { + cec_sleep_pins_a: cec-sleep-0 { pins { pinmux = ; /* HDMI_CEC */ }; @@ -52,7 +52,7 @@ }; }; - cec_pins_sleep_b: cec-sleep-1 { + cec_sleep_pins_b: cec-sleep-1 { pins { pinmux = ; /* HDMI_CEC */ }; @@ -142,7 +142,7 @@ }; }; - ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ , /* ETH_RGMII_GTX_CLK */ @@ -182,7 +182,7 @@ }; }; - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ , /* ETH1_RMII_TXD1 */ @@ -250,7 +250,7 @@ }; }; - i2c1_pins_sleep_a: i2c1-1 { + i2c1_sleep_pins_a: i2c1-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -267,7 +267,7 @@ }; }; - i2c1_pins_sleep_b: i2c1-3 { + i2c1_sleep_pins_b: i2c1-3 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -284,7 +284,7 @@ }; }; - i2c2_pins_sleep_a: i2c2-1 { + i2c2_sleep_pins_a: i2c2-1 { pins { pinmux = , /* I2C2_SCL */ ; /* I2C2_SDA */ @@ -300,7 +300,7 @@ }; }; - i2c2_pins_sleep_b1: i2c2-3 { + i2c2_sleep_pins_b1: i2c2-3 { pins { pinmux = ; /* I2C2_SDA */ }; @@ -316,7 +316,7 @@ }; }; - i2c5_pins_sleep_a: i2c5-1 { + i2c5_sleep_pins_a: i2c5-1 { pins { pinmux = , /* I2C5_SCL */ ; /* I2C5_SDA */ @@ -335,7 +335,7 @@ }; }; - i2s2_pins_sleep_a: i2s2-1 { + i2s2_sleep_pins_a: i2s2-1 { pins { pinmux = , /* I2S2_SDO */ , /* I2S2_WS */ @@ -379,7 +379,7 @@ }; }; - ltdc_pins_sleep_a: ltdc-a-1 { + ltdc_sleep_pins_a: ltdc-a-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -448,7 +448,7 @@ }; }; - ltdc_pins_sleep_b: ltdc-b-1 { + ltdc_sleep_pins_b: ltdc-b-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -1145,7 +1145,7 @@ }; }; - i2c2_pins_sleep_b2: i2c2-1 { + i2c2_sleep_pins_b2: i2c2-1 { pins { pinmux = ; /* I2C2_SCL */ }; @@ -1161,7 +1161,7 @@ }; }; - i2c4_pins_sleep_a: i2c4-1 { + i2c4_sleep_pins_a: i2c4-1 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 425175f7d83c..aba38950f2e9 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -82,7 +82,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index af99e132e1b1..06ea8c1a7c56 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -77,7 +77,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; @@ -147,7 +147,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_pins_sleep_b>; + pinctrl-1 = <<dc_sleep_pins_b>; status = "okay"; port { diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index e9aad3e101ac..0aaae0df5b07 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -131,7 +131,7 @@ &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 26db0fe93a98..b19056557ef0 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -136,7 +136,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -171,7 +171,7 @@ &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_pins_sleep_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -225,7 +225,7 @@ &i2c5 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_pins_sleep_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index f964e2ae7d60..fcf50131e5fe 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -112,14 +112,14 @@ &cec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_pins_sleep_b>; + pinctrl-1 = <&cec_sleep_pins_b>; status = "okay"; }; ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -142,7 +142,7 @@ &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_pins_sleep_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; i2c-scl-rising-time-ns = <100>; i2c-scl-falling-time-ns = <7>; status = "okay"; @@ -217,7 +217,7 @@ &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; @@ -366,7 +366,7 @@ clock-names = "pclk", "i2sclk", "x8k", "x11k"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_pins_sleep_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; status = "okay"; i2s2_port: port { @@ -390,7 +390,7 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_pins_sleep_a>; + pinctrl-1 = <<dc_sleep_pins_a>; status = "okay"; port { -- cgit v1.2.3-70-g09d2 From c19e7f74966a868f5a2fd3a446ade159c79a3694 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:09 +0100 Subject: ARM: dts: stm32: use uniform node names for sleep pinctrl groups While all sleep pinctrl group labels now follow a fixed naming scheme, node _names_ for these groups don't: - Some use ${dev}-[0-9], where the suffix is the normal group suffix + 1 - Some use ${dev}-sleep-[0-9], where suffix is the normal group suffix - The <dc node uses ${dev}-[a-z]-[0-9], where the letter matches the phandle and the number suffix is the normal group's suffix + 1 For uniformity, standardize on using ${dev}-[0-9]+ for all normal pinctrl groups and ${dev}-sleep-[0-9]+ for all sleep pinctrl groups. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 50 ++++++++++++++++---------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 1971a9603ba6..377a8b2b3a3a 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -6,7 +6,7 @@ #include &pinctrl { - adc1_in6_pins_a: adc1-in6 { + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = ; }; @@ -58,13 +58,13 @@ }; }; - dac_ch1_pins_a: dac-ch1 { + dac_ch1_pins_a: dac-ch1-0 { pins { pinmux = ; }; }; - dac_ch2_pins_a: dac-ch2 { + dac_ch2_pins_a: dac-ch2-0 { pins { pinmux = ; }; @@ -250,14 +250,14 @@ }; }; - i2c1_sleep_pins_a: i2c1-1 { + i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ }; }; - i2c1_pins_b: i2c1-2 { + i2c1_pins_b: i2c1-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -267,7 +267,7 @@ }; }; - i2c1_sleep_pins_b: i2c1-3 { + i2c1_sleep_pins_b: i2c1-sleep-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -284,14 +284,14 @@ }; }; - i2c2_sleep_pins_a: i2c2-1 { + i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = , /* I2C2_SCL */ ; /* I2C2_SDA */ }; }; - i2c2_pins_b1: i2c2-2 { + i2c2_pins_b1: i2c2-1 { pins { pinmux = ; /* I2C2_SDA */ bias-disable; @@ -300,7 +300,7 @@ }; }; - i2c2_sleep_pins_b1: i2c2-3 { + i2c2_sleep_pins_b1: i2c2-sleep-1 { pins { pinmux = ; /* I2C2_SDA */ }; @@ -316,7 +316,7 @@ }; }; - i2c5_sleep_pins_a: i2c5-1 { + i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = , /* I2C5_SCL */ ; /* I2C5_SDA */ @@ -335,7 +335,7 @@ }; }; - i2s2_sleep_pins_a: i2s2-1 { + i2s2_sleep_pins_a: i2s2-sleep-0 { pins { pinmux = , /* I2S2_SDO */ , /* I2S2_WS */ @@ -343,7 +343,7 @@ }; }; - ltdc_pins_a: ltdc-a-0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -379,7 +379,7 @@ }; }; - ltdc_sleep_pins_a: ltdc-a-1 { + ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -412,7 +412,7 @@ }; }; - ltdc_pins_b: ltdc-b-0 { + ltdc_pins_b: ltdc-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -448,7 +448,7 @@ }; }; - ltdc_sleep_pins_b: ltdc-b-1 { + ltdc_sleep_pins_b: ltdc-sleep-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -710,7 +710,7 @@ }; }; - sai2a_sleep_pins_a: sai2a-1 { + sai2a_sleep_pins_a: sai2a-sleep-0 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ @@ -720,7 +720,7 @@ }; - sai2a_pins_b: sai2a-2 { + sai2a_pins_b: sai2a-1 { pins1 { pinmux = , /* SAI2_SD_A */ , /* SAI2_FS_A */ @@ -731,7 +731,7 @@ }; }; - sai2a_sleep_pins_b: sai2a-sleep-3 { + sai2a_sleep_pins_b: sai2a-sleep-1 { pins { pinmux = , /* SAI2_SD_A */ , /* SAI2_FS_A */ @@ -754,7 +754,7 @@ }; }; - sai2b_sleep_pins_a: sai2b-1 { + sai2b_sleep_pins_a: sai2b-sleep-0 { pins { pinmux = , /* SAI2_SD_B */ , /* SAI2_SCK_B */ @@ -763,14 +763,14 @@ }; }; - sai2b_pins_b: sai2b-2 { + sai2b_pins_b: sai2b-1 { pins { pinmux = ; /* SAI2_SD_B */ bias-disable; }; }; - sai2b_sleep_pins_b: sai2b-3 { + sai2b_sleep_pins_b: sai2b-sleep-1 { pins { pinmux = ; /* SAI2_SD_B */ }; @@ -785,7 +785,7 @@ }; }; - sai4a_sleep_pins_a: sai4a-1 { + sai4a_sleep_pins_a: sai4a-sleep-0 { pins { pinmux = ; /* SAI4_SD_A */ }; @@ -1048,7 +1048,7 @@ }; }; - spdifrx_sleep_pins_a: spdifrx-1 { + spdifrx_sleep_pins_a: spdifrx-sleep-0 { pins { pinmux = ; /* SPDIF_IN1 */ }; @@ -1145,7 +1145,7 @@ }; }; - i2c2_sleep_pins_b2: i2c2-1 { + i2c2_sleep_pins_b2: i2c2-sleep-0 { pins { pinmux = ; /* I2C2_SCL */ }; @@ -1161,7 +1161,7 @@ }; }; - i2c4_sleep_pins_a: i2c4-1 { + i2c4_sleep_pins_a: i2c4-sleep-0 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ -- cgit v1.2.3-70-g09d2 From 666b5ca85cd34f219a1b237a64d09e778980e231 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Thu, 26 Mar 2020 23:02:11 +0100 Subject: ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board The Linux Automation MC-1 is a SBC built around the Octavo Systems OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and a PMIC. The board has eMMC and a SD slot for storage and GbE for both connectivity and power. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 185 ++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 252 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 230 +++++++++++++++++++++++++++ 4 files changed, 669 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-osd32.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..f43467b02bcd 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1033,7 +1033,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ - stm32mp157c-ev1.dtb + stm32mp157c-ev1.dtb \ + stm32mp157c-lxa-mc1.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 377a8b2b3a3a..eb85ad19c926 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -162,6 +162,57 @@ }; }; + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ @@ -324,6 +375,23 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + i2s2_pins_a: i2s2-0 { pins { pinmux = , /* I2S2_SDO */ @@ -481,6 +549,68 @@ }; }; + ltdc_pins_c: ltdc-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_c: ltdc-sleep-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + , /* LTDC_HSYNC */ + ; /* LTDC_CLK */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -550,6 +680,21 @@ }; }; + pwm3_pins_b: pwm3-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_b: pwm3-sleep-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + pwm4_pins_a: pwm4-0 { pins { pinmux = , /* TIM4_CH3 */ @@ -597,6 +742,25 @@ }; }; + pwm5_pins_b: pwm5-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_b: pwm5-sleep-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH4 */ @@ -987,6 +1151,27 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts new file mode 100644 index 000000000000..5700e6b700d3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include + +/ { + model = "Linux Automation MC-1 board"; + compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ + }; + + chosen { + stdout-path = &uart4; + }; + + led-act { + compatible = "gpio-leds"; + + led-green { + label = "mc1:green:act"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-rgb { + compatible = "pwm-leds"; + + led-red { + label = "mc1:red:rgb"; + pwms = <&leds_pwm 1 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-green { + label = "mc1:green:rgb"; + pwms = <&leds_pwm 2 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-blue { + label = "mc1:blue:rgb"; + pwms = <&leds_pwm 3 1000000 0>; + max-brightness = <255>; + active-low; + }; + }; + + panel: panel { + compatible = "edt,etm0700g0edh6", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + port { + panel_input: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + + reg_3v3: regulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + /* supplied by either debug board or PoE */ + reg_5v2: regulator_5v2 { + compatible = "regulator-fixed"; + regulator-name = "5V2"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + rxc-skew-ps = <1860>; + txc-skew-ps = <1860>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", + "HWID4", "HWID5"; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + interrupt-parent = <&gpiod>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ + vcc-supply = <®_3v3>; + reg = <0x38>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_c>; + pinctrl-1 = <<dc_sleep_pins_c>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; +}; + +&pmic { + regulators { + buck4-supply = <®_5v2>; /* VIN */ + ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ + ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ + boost-supply = <®_5v2>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to + * work, thus enable internal pull-ups. + */ + pins1 { + /delete-property/ bias-disable; + bias-pull-up; + }; + pins2 { + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers3 { + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm3_pins_b>; + pinctrl-1 = <&pwm3_sleep_pins_b>; + status = "okay"; + }; +}; + +&timers5 { + status = "okay"; + + leds_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_b>; + pinctrl-1 = <&pwm5_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi new file mode 100644 index 000000000000..713485a95795 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +#include "stm32mp15-pinctrl.dtsi" + +#include + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + reg_sip_eeprom: regulator_eeprom { + compatible = "regulator-fixed"; + regulator-name = "sip_eeprom"; + regulator-always-on; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + }; + + pmic_watchdog: watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + sip_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + vcc-supply = <®_sip_eeprom>; + reg = <0x50>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From a49e244797f92bc32286cdbb7ab6621bca1c553b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 Mar 2020 19:40:08 +0100 Subject: ARM: dts: stm32: Enable I2C2 on DHCOM PDK2 carrier board The I2C2 is routed out to header X21, enable it to make it available. Add a comment to I2C5, which is routed to header X22 right next to it. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index 06ea8c1a7c56..13b1586d4a8f 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -96,7 +96,19 @@ }; }; -&i2c5 { +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins_a>; i2c-scl-rising-time-ns = <185>; -- cgit v1.2.3-70-g09d2 From 78066055b08096ed3282c027de9d9e137f9a1580 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 26 Mar 2020 23:48:18 -0700 Subject: arm32/64/elf: Add tables to document READ_IMPLIES_EXEC Add tables to document the current behavior of READ_IMPLIES_EXEC in preparation for changing the behavior for both arm64 and arm. Signed-off-by: Kees Cook Signed-off-by: Borislav Petkov Reviewed-by: Jason Gunthorpe Reviewed-by: Catalin Marinas Link: https://lkml.kernel.org/r/20200327064820.12602-5-keescook@chromium.org --- arch/arm/kernel/elf.c | 24 +++++++++++++++++++++--- arch/arm64/include/asm/elf.h | 20 ++++++++++++++++++++ 2 files changed, 41 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index 182422981386..5ccd4aced6cc 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -78,9 +78,27 @@ void elf_set_personality(const struct elf32_hdr *x) EXPORT_SYMBOL(elf_set_personality); /* - * Set READ_IMPLIES_EXEC if: - * - the binary requires an executable stack - * - we're running on a CPU which doesn't support NX. + * An executable for which elf_read_implies_exec() returns TRUE will + * have the READ_IMPLIES_EXEC personality flag set automatically. + * + * The decision process for determining the results are: + * + *              CPU: | lacks NX*  | has NX | + * ELF:              |            |           | + * ---------------------|------------|------------| + * missing PT_GNU_STACK | exec-all   | exec-all  | + * PT_GNU_STACK == RWX  | exec-all   | exec-all  | + * PT_GNU_STACK == RW   | exec-all  | exec-none | + * + * exec-all : all PROT_READ user mappings are executable, except when + * backed by files on a noexec-filesystem. + * exec-none : only PROT_EXEC user mappings are executable. + * + * *this column has no architectural effect: NX markings are ignored by + * hardware, but may have behavioral effects when "wants X" collides with + * "cannot be X" constraints in memory permission flags, as in + * https://lkml.kernel.org/r/20190418055759.GA3155@mellanox.com + * */ int arm_elf_read_implies_exec(int executable_stack) { diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index b618017205a3..986ecf41fc0f 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -96,6 +96,26 @@ */ #define elf_check_arch(x) ((x)->e_machine == EM_AARCH64) +/* + * An executable for which elf_read_implies_exec() returns TRUE will + * have the READ_IMPLIES_EXEC personality flag set automatically. + * + * The decision process for determining the results are: + * + *              CPU*: | arm32    | arm64 | + * ELF:              |            |            | + * ---------------------|------------|------------| + * missing PT_GNU_STACK | exec-all   | exec-all   | + * PT_GNU_STACK == RWX  | exec-all   | exec-all   | + * PT_GNU_STACK == RW   | exec-none | exec-none | + * + * exec-all : all PROT_READ user mappings are executable, except when + * backed by files on a noexec-filesystem. + * exec-none : only PROT_EXEC user mappings are executable. + * + * *all arm64 CPUs support NX, so there is no "lacks NX" column. + * + */ #define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X) #define CORE_DUMP_USE_REGSET -- cgit v1.2.3-70-g09d2 From eaf3f9e61887332d5097dbf0b327b8377546adc5 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 26 Mar 2020 23:48:19 -0700 Subject: arm32/64/elf: Split READ_IMPLIES_EXEC from executable PT_GNU_STACK The READ_IMPLIES_EXEC work-around was designed for old toolchains that lacked the ELF PT_GNU_STACK marking under the assumption that toolchains that couldn't specify executable permission flags for the stack may not know how to do it correctly for any memory region. This logic is sensible for having ancient binaries coexist in a system with possibly NX memory, but was implemented in a way that equated having a PT_GNU_STACK marked executable as being as "broken" as lacking the PT_GNU_STACK marking entirely. Things like unmarked assembly and stack trampolines may cause PT_GNU_STACK to need an executable bit, but they do not imply all mappings must be executable. This confusion has led to situations where modern programs with explicitly marked executable stack are forced into the READ_IMPLIES_EXEC state when no such thing is needed. (And leads to unexpected failures when mmap()ing regions of device driver memory that wish to disallow VM_EXEC[1].) In looking for other reasons for the READ_IMPLIES_EXEC behavior, Jann Horn noted that glibc thread stacks have always been marked RWX (until 2003 when they started tracking the PT_GNU_STACK flag instead[2]). And musl doesn't support executable stacks at all[3]. As such, no breakage for multithreaded applications is expected from this change. This changes arm32 and arm64 compat together, to keep behavior the same. [1] https://lkml.kernel.org/r/20190418055759.GA3155@mellanox.com [2] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=54ee14b3882 [3] https://lkml.kernel.org/r/20190423192534.GN23599@brightrain.aerifal.cx Suggested-by: Hector Marco-Gisbert Signed-off-by: Kees Cook Signed-off-by: Borislav Petkov Reviewed-by: Jason Gunthorpe Reviewed-by: Catalin Marinas Link: https://lkml.kernel.org/r/20200327064820.12602-6-keescook@chromium.org --- arch/arm/kernel/elf.c | 5 +++-- arch/arm64/include/asm/elf.h | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c index 5ccd4aced6cc..254ab7138c85 100644 --- a/arch/arm/kernel/elf.c +++ b/arch/arm/kernel/elf.c @@ -87,12 +87,13 @@ EXPORT_SYMBOL(elf_set_personality); * ELF:              |            |           | * ---------------------|------------|------------| * missing PT_GNU_STACK | exec-all   | exec-all  | - * PT_GNU_STACK == RWX  | exec-all   | exec-all  | + * PT_GNU_STACK == RWX  | exec-all   | exec-stack | * PT_GNU_STACK == RW   | exec-all  | exec-none | * * exec-all : all PROT_READ user mappings are executable, except when * backed by files on a noexec-filesystem. * exec-none : only PROT_EXEC user mappings are executable. + * exec-stack: only the stack and PROT_EXEC user mappings are executable. * * *this column has no architectural effect: NX markings are ignored by * hardware, but may have behavioral effects when "wants X" collides with @@ -102,7 +103,7 @@ EXPORT_SYMBOL(elf_set_personality); */ int arm_elf_read_implies_exec(int executable_stack) { - if (executable_stack != EXSTACK_DISABLE_X) + if (executable_stack == EXSTACK_DEFAULT) return 1; if (cpu_architecture() < CPU_ARCH_ARMv6) return 1; diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index 986ecf41fc0f..0074e9fd6431 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -106,17 +106,18 @@ * ELF:              |            |            | * ---------------------|------------|------------| * missing PT_GNU_STACK | exec-all   | exec-all   | - * PT_GNU_STACK == RWX  | exec-all   | exec-all   | + * PT_GNU_STACK == RWX  | exec-stack | exec-stack | * PT_GNU_STACK == RW   | exec-none | exec-none | * * exec-all : all PROT_READ user mappings are executable, except when * backed by files on a noexec-filesystem. * exec-none : only PROT_EXEC user mappings are executable. + * exec-stack: only the stack and PROT_EXEC user mappings are executable. * * *all arm64 CPUs support NX, so there is no "lacks NX" column. * */ -#define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X) +#define elf_read_implies_exec(ex, stk) (stk == EXSTACK_DEFAULT) #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE -- cgit v1.2.3-70-g09d2 From 4e7573e7a54e1ae3052f1360b676bfeff22bbffb Mon Sep 17 00:00:00 2001 From: Daniele Debernardi Date: Sat, 11 Apr 2020 21:21:18 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add pma8084 regulator nodes The pma8084 replaces the pm8841,pm8941 found in other msm8974 devices. It is used for various things including gpio keys, sdhci, usb, dsi. The voltages are pulled from the vendor source tree. Signed-off-by: Daniele Debernardi Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200411182122.2677248-2-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 184 ++++++++++++++++++++++++ 1 file changed, 184 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index eaa1001d0a46..b6329f24c502 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -2,6 +2,7 @@ #include "qcom-msm8974pro.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" +#include "qcom-pma8084.dtsi" / { model = "Samsung Galaxy S5"; @@ -14,6 +15,189 @@ chosen { stdout-path = "serial0:115200n8"; }; + + smd { + rpm { + rpm_requests { + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + status = "okay"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; + }; + }; + }; }; &soc { -- cgit v1.2.3-70-g09d2 From 9111bbf3a19d463953f9889426314b993d047399 Mon Sep 17 00:00:00 2001 From: Daniele Debernardi Date: Sat, 11 Apr 2020 21:21:19 +0300 Subject: ARM: dts: qcom: msm8974-klte: Remove inherited vreg_boost node The Samsung klte does not have a vreg_boost node. vreg_boost also depends on pm8941-gpio which are not present on the klte. Signed-off-by: Daniele Debernardi Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200411182122.2677248-3-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index b6329f24c502..36ad8ff071ca 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" #include "qcom-pma8084.dtsi" / { @@ -198,6 +196,8 @@ }; }; }; + + /delete-node/ vreg-boost; }; &soc { -- cgit v1.2.3-70-g09d2 From 8513de03928e84dd6b1debe334c4256cbf2d0f6f Mon Sep 17 00:00:00 2001 From: Daniele Debernardi Date: Sat, 11 Apr 2020 21:21:20 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add gpio-keys nodes This introduces the gpio-keys nodes for volume/home keys and the associated pinctrl state. Signed-off-by: Daniele Debernardi Link: https://lore.kernel.org/r/20200411182122.2677248-4-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 36ad8ff071ca..752ab9e99a8c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" #include "qcom-pma8084.dtsi" +#include +#include +#include / { model = "Samsung Galaxy S5"; @@ -205,4 +208,50 @@ status = "ok"; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + home-key { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + }; +}; + +&spmi_bus { + pma8084@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + }; + }; }; -- cgit v1.2.3-70-g09d2 From 8bf7a360a92cc6b2aebc8fa833ebc406ef317c38 Mon Sep 17 00:00:00 2001 From: Daniele Debernardi Date: Sat, 11 Apr 2020 21:21:21 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add sdhci1 node This introduces the eMMC sdhci node and its pinctrl state Signed-off-by: Daniele Debernardi Link: https://lore.kernel.org/r/20200411182122.2677248-5-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 752ab9e99a8c..42fc18804021 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -152,6 +152,9 @@ pma8084_l20: l20 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-system-load = <200000>; }; pma8084_l21: l21 { @@ -240,6 +243,35 @@ debounce-interval = <15>; }; }; + + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; }; &spmi_bus { -- cgit v1.2.3-70-g09d2 From 65876ae91e80d7746e36d3003866aa6f28c56a97 Mon Sep 17 00:00:00 2001 From: Daniele Debernardi Date: Sat, 11 Apr 2020 21:21:22 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add USB node This introduces the usb node which can be used e.g. for USB_ETH Signed-off-by: Daniele Debernardi Link: https://lore.kernel.org/r/20200411182122.2677248-6-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 42fc18804021..df85d90100d9 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -272,6 +272,31 @@ pinctrl-names = "default"; pinctrl-0 = <&sdhc1_pin_a>; }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + /*extcon = <&smbb>, <&usb_id>;*/ + /*vbus-supply = <&chg_otg>;*/ + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + /*extcon = <&smbb>;*/ + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; }; &spmi_bus { -- cgit v1.2.3-70-g09d2 From cd13c72c1853f219e1f5577a107f48b9f9c44fdd Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Tue, 14 Apr 2020 20:22:50 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add max77826 pmic node This introduces the MAX77826 PMIC that powers some pheripherals on the klte, like the touchpad, touchkeys and camera. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200414172250.2363235-4-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 111 ++++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 11 +++ 2 files changed, 122 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index df85d90100d9..d4dc98214225 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -297,6 +297,117 @@ }; }; }; + + pinctrl@fd510000 { + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c@f9928000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; + }; }; &spmi_bus { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 2ea2308d91b3..51f5f904f9eb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -974,6 +974,17 @@ #size-cells = <0>; }; + blsp_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp_i2c8: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; -- cgit v1.2.3-70-g09d2 From ee9a71ad25549d28c26542d93270071e9a269408 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Sun, 19 Apr 2020 15:05:41 +0800 Subject: ARM: samsung: Omit superfluous error message in s3c_adc_probe() In the function s3c_adc_probe(), when get irq failed, the function platform_get_irq() logs an error message, so remove redundant message here. Signed-off-by: Shengju Zhang Signed-off-by: Tang Bin Signed-off-by: Krzysztof Kozlowski --- arch/arm/plat-samsung/adc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 4f7b27239bd4..839bf7d5fee0 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -354,10 +354,8 @@ static int s3c_adc_probe(struct platform_device *pdev) } adc->irq = platform_get_irq(pdev, 1); - if (adc->irq <= 0) { - dev_err(dev, "failed to get adc irq\n"); + if (adc->irq <= 0) return -ENOENT; - } ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); -- cgit v1.2.3-70-g09d2 From 06b29212c3a2467ef9d25876fe82b77fa3d09ac2 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Sun, 19 Apr 2020 15:06:07 +0800 Subject: ARM: samsung: Use devm_platform_ioremap_resource() to simplify code Use devm_platform_ioremap_resource() instead of platform_get_resource() + devm_ioremap_resource(). Signed-off-by: Shengju Zhang Signed-off-by: Tang Bin Signed-off-by: Krzysztof Kozlowski --- arch/arm/plat-samsung/adc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 839bf7d5fee0..55b1925f65d7 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -333,7 +333,6 @@ static int s3c_adc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct adc_device *adc; - struct resource *regs; enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data; int ret; unsigned tmp; @@ -370,8 +369,7 @@ static int s3c_adc_probe(struct platform_device *pdev) return PTR_ERR(adc->clk); } - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - adc->regs = devm_ioremap_resource(dev, regs); + adc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(adc->regs)) return PTR_ERR(adc->regs); -- cgit v1.2.3-70-g09d2 From d85d5247885ef2e8192287b895c2e381fa931b0b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 29 Mar 2020 22:33:14 +0200 Subject: ARM: OMAP2+: drop unnecessary adrl The adrl instruction has been introduced with commit dd31394779aa ("ARM: omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly file was considerably longer. Today adr seems to have enough reach, even when inserting about 60 instructions between the use site and the label. Replace adrl with conventional adr instruction. This allows to build this file using Clang's integrated assembler (which does not support the adrl pseudo instruction). Link: https://github.com/ClangBuiltLinux/linux/issues/430 Signed-off-by: Stefan Agner Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sleep34xx.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index ac1324c6453b..c4e97d35c310 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -72,7 +72,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) stmfd sp!, {lr} @ save registers on stack /* Setup so that we will disable and enable l2 */ mov r1, #0x1 - adrl r3, l2dis_3630_offset @ may be too distant for plain adr + adr r3, l2dis_3630_offset ldr r2, [r3] @ value for offset str r1, [r2, r3] @ write to l2dis_3630 ldmfd sp!, {pc} @ restore regs and return -- cgit v1.2.3-70-g09d2 From c281634c865202e2776b0250678ff93c771947ff Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 3 Apr 2020 11:06:47 +0100 Subject: ARM: compat: remove KERNEL_DS usage in sys_oabi_epoll_ctl() We no longer need to switch to KERNEL_DS mode in sys_oabi_epoll_ctl() as we can use do_epoll_ctl() to avoid the additional copy. Reviewed-by: Christoph Hellwig Signed-off-by: Russell King --- arch/arm/kernel/sys_oabi-compat.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 17bd32b22371..0203e545bbc8 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -253,20 +253,15 @@ asmlinkage long sys_oabi_epoll_ctl(int epfd, int op, int fd, { struct oabi_epoll_event user; struct epoll_event kernel; - mm_segment_t fs; - long ret; - if (op == EPOLL_CTL_DEL) - return sys_epoll_ctl(epfd, op, fd, NULL); - if (copy_from_user(&user, event, sizeof(user))) + if (ep_op_has_event(op) && + copy_from_user(&user, event, sizeof(user))) return -EFAULT; + kernel.events = user.events; kernel.data = user.data; - fs = get_fs(); - set_fs(KERNEL_DS); - ret = sys_epoll_ctl(epfd, op, fd, &kernel); - set_fs(fs); - return ret; + + return do_epoll_ctl(epfd, op, fd, &kernel, false); } asmlinkage long sys_oabi_epoll_wait(int epfd, -- cgit v1.2.3-70-g09d2 From 2e0eb483c058dd013be8e3d0ec1767be531485a2 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Wed, 15 Apr 2020 12:54:18 -0700 Subject: efi/libstub: Move arm-stub to a common file Most of the arm-stub code is written in an architecture independent manner. As a result, RISC-V can reuse most of the arm-stub code. Rename the arm-stub.c to efi-stub.c so that ARM, ARM64 and RISC-V can use it. This patch doesn't introduce any functional changes. Signed-off-by: Atish Patra Reviewed-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20200415195422.19866-2-atish.patra@wdc.com Signed-off-by: Ard Biesheuvel --- arch/arm/Kconfig | 2 +- arch/arm64/Kconfig | 2 +- drivers/firmware/efi/Kconfig | 4 +- drivers/firmware/efi/libstub/Makefile | 12 +- drivers/firmware/efi/libstub/arm-stub.c | 408 -------------------------------- drivers/firmware/efi/libstub/efi-stub.c | 408 ++++++++++++++++++++++++++++++++ 6 files changed, 418 insertions(+), 418 deletions(-) delete mode 100644 drivers/firmware/efi/libstub/arm-stub.c create mode 100644 drivers/firmware/efi/libstub/efi-stub.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 66a04f6f4775..165987aa5bcd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1954,7 +1954,7 @@ config EFI select UCS2_STRING select EFI_PARAMS_FROM_FDT select EFI_STUB - select EFI_ARMSTUB + select EFI_GENERIC_STUB select EFI_RUNTIME_WRAPPERS ---help--- This option provides support for runtime services provided diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 40fb05d96c60..32d818c5ccda 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1785,7 +1785,7 @@ config EFI select EFI_PARAMS_FROM_FDT select EFI_RUNTIME_WRAPPERS select EFI_STUB - select EFI_ARMSTUB + select EFI_GENERIC_STUB default y help This option provides support for runtime services provided diff --git a/drivers/firmware/efi/Kconfig b/drivers/firmware/efi/Kconfig index 613828d3f106..2a2b2b96a1dc 100644 --- a/drivers/firmware/efi/Kconfig +++ b/drivers/firmware/efi/Kconfig @@ -106,12 +106,12 @@ config EFI_PARAMS_FROM_FDT config EFI_RUNTIME_WRAPPERS bool -config EFI_ARMSTUB +config EFI_GENERIC_STUB bool config EFI_ARMSTUB_DTB_LOADER bool "Enable the DTB loader" - depends on EFI_ARMSTUB + depends on EFI_GENERIC_STUB default y help Select this config option to add support for the dtb= command diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index 094eabdecfe6..75cb2c3a1519 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -23,7 +23,7 @@ cflags-$(CONFIG_ARM) := $(subst $(CC_FLAGS_FTRACE),,$(KBUILD_CFLAGS)) \ -fno-builtin -fpic \ $(call cc-option,-mno-single-pic-base) -cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt +cflags-$(CONFIG_EFI_GENERIC_STUB) += -I$(srctree)/scripts/dtc/libfdt KBUILD_CFLAGS := $(cflags-y) -DDISABLE_BRANCH_PROFILING \ -include $(srctree)/drivers/firmware/efi/libstub/hidden.h \ @@ -45,13 +45,13 @@ lib-y := efi-stub-helper.o gop.o secureboot.o tpm.o \ skip_spaces.o lib-cmdline.o lib-ctype.o # include the stub's generic dependencies from lib/ when building for ARM/arm64 -arm-deps-y := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c fdt_empty_tree.c fdt_sw.c +efi-deps-y := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c fdt_empty_tree.c fdt_sw.c $(obj)/lib-%.o: $(srctree)/lib/%.c FORCE $(call if_changed_rule,cc_o_c) -lib-$(CONFIG_EFI_ARMSTUB) += arm-stub.o fdt.o string.o \ - $(patsubst %.c,lib-%.o,$(arm-deps-y)) +lib-$(CONFIG_EFI_GENERIC_STUB) += efi-stub.o fdt.o string.o \ + $(patsubst %.c,lib-%.o,$(efi-deps-y)) lib-$(CONFIG_ARM) += arm32-stub.o lib-$(CONFIG_ARM64) += arm64-stub.o @@ -73,8 +73,8 @@ CFLAGS_arm64-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) # a verification pass to see if any absolute relocations exist in any of the # object files. # -extra-$(CONFIG_EFI_ARMSTUB) := $(lib-y) -lib-$(CONFIG_EFI_ARMSTUB) := $(patsubst %.o,%.stub.o,$(lib-y)) +extra-$(CONFIG_EFI_GENERIC_STUB) := $(lib-y) +lib-$(CONFIG_EFI_GENERIC_STUB) := $(patsubst %.o,%.stub.o,$(lib-y)) STUBCOPY_FLAGS-$(CONFIG_ARM64) += --prefix-alloc-sections=.init \ --prefix-symbols=__efistub_ diff --git a/drivers/firmware/efi/libstub/arm-stub.c b/drivers/firmware/efi/libstub/arm-stub.c deleted file mode 100644 index 99a5cde7c2d8..000000000000 --- a/drivers/firmware/efi/libstub/arm-stub.c +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * EFI stub implementation that is shared by arm and arm64 architectures. - * This should be #included by the EFI stub implementation files. - * - * Copyright (C) 2013,2014 Linaro Limited - * Roy Franz - */ - -#include -#include -#include - -#include "efistub.h" - -/* - * This is the base address at which to start allocating virtual memory ranges - * for UEFI Runtime Services. This is in the low TTBR0 range so that we can use - * any allocation we choose, and eliminate the risk of a conflict after kexec. - * The value chosen is the largest non-zero power of 2 suitable for this purpose - * both on 32-bit and 64-bit ARM CPUs, to maximize the likelihood that it can - * be mapped efficiently. - * Since 32-bit ARM could potentially execute with a 1G/3G user/kernel split, - * map everything below 1 GB. (512 MB is a reasonable upper bound for the - * entire footprint of the UEFI runtime services memory regions) - */ -#define EFI_RT_VIRTUAL_BASE SZ_512M -#define EFI_RT_VIRTUAL_SIZE SZ_512M - -#ifdef CONFIG_ARM64 -# define EFI_RT_VIRTUAL_LIMIT DEFAULT_MAP_WINDOW_64 -#else -# define EFI_RT_VIRTUAL_LIMIT TASK_SIZE -#endif - -static u64 virtmap_base = EFI_RT_VIRTUAL_BASE; -static bool __efistub_global flat_va_mapping; - -static efi_system_table_t *__efistub_global sys_table; - -__pure efi_system_table_t *efi_system_table(void) -{ - return sys_table; -} - -static struct screen_info *setup_graphics(void) -{ - efi_guid_t gop_proto = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID; - efi_status_t status; - unsigned long size; - void **gop_handle = NULL; - struct screen_info *si = NULL; - - size = 0; - status = efi_bs_call(locate_handle, EFI_LOCATE_BY_PROTOCOL, - &gop_proto, NULL, &size, gop_handle); - if (status == EFI_BUFFER_TOO_SMALL) { - si = alloc_screen_info(); - if (!si) - return NULL; - efi_setup_gop(si, &gop_proto, size); - } - return si; -} - -void install_memreserve_table(void) -{ - struct linux_efi_memreserve *rsv; - efi_guid_t memreserve_table_guid = LINUX_EFI_MEMRESERVE_TABLE_GUID; - efi_status_t status; - - status = efi_bs_call(allocate_pool, EFI_LOADER_DATA, sizeof(*rsv), - (void **)&rsv); - if (status != EFI_SUCCESS) { - pr_efi_err("Failed to allocate memreserve entry!\n"); - return; - } - - rsv->next = 0; - rsv->size = 0; - atomic_set(&rsv->count, 0); - - status = efi_bs_call(install_configuration_table, - &memreserve_table_guid, rsv); - if (status != EFI_SUCCESS) - pr_efi_err("Failed to install memreserve config table!\n"); -} - -static unsigned long get_dram_base(void) -{ - efi_status_t status; - unsigned long map_size, buff_size; - unsigned long membase = EFI_ERROR; - struct efi_memory_map map; - efi_memory_desc_t *md; - struct efi_boot_memmap boot_map; - - boot_map.map = (efi_memory_desc_t **)&map.map; - boot_map.map_size = &map_size; - boot_map.desc_size = &map.desc_size; - boot_map.desc_ver = NULL; - boot_map.key_ptr = NULL; - boot_map.buff_size = &buff_size; - - status = efi_get_memory_map(&boot_map); - if (status != EFI_SUCCESS) - return membase; - - map.map_end = map.map + map_size; - - for_each_efi_memory_desc_in_map(&map, md) { - if (md->attribute & EFI_MEMORY_WB) { - if (membase > md->phys_addr) - membase = md->phys_addr; - } - } - - efi_bs_call(free_pool, map.map); - - return membase; -} - -/* - * This function handles the architcture specific differences between arm and - * arm64 regarding where the kernel image must be loaded and any memory that - * must be reserved. On failure it is required to free all - * all allocations it has made. - */ -efi_status_t handle_kernel_image(unsigned long *image_addr, - unsigned long *image_size, - unsigned long *reserve_addr, - unsigned long *reserve_size, - unsigned long dram_base, - efi_loaded_image_t *image); - -asmlinkage void __noreturn efi_enter_kernel(unsigned long entrypoint, - unsigned long fdt_addr, - unsigned long fdt_size); - -/* - * EFI entry point for the arm/arm64 EFI stubs. This is the entrypoint - * that is described in the PE/COFF header. Most of the code is the same - * for both archictectures, with the arch-specific code provided in the - * handle_kernel_image() function. - */ -efi_status_t efi_entry(efi_handle_t handle, efi_system_table_t *sys_table_arg) -{ - efi_loaded_image_t *image; - efi_status_t status; - unsigned long image_addr; - unsigned long image_size = 0; - unsigned long dram_base; - /* addr/point and size pairs for memory management*/ - unsigned long initrd_addr = 0; - unsigned long initrd_size = 0; - unsigned long fdt_addr = 0; /* Original DTB */ - unsigned long fdt_size = 0; - char *cmdline_ptr = NULL; - int cmdline_size = 0; - efi_guid_t loaded_image_proto = LOADED_IMAGE_PROTOCOL_GUID; - unsigned long reserve_addr = 0; - unsigned long reserve_size = 0; - enum efi_secureboot_mode secure_boot; - struct screen_info *si; - efi_properties_table_t *prop_tbl; - unsigned long max_addr; - - sys_table = sys_table_arg; - - /* Check if we were booted by the EFI firmware */ - if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) { - status = EFI_INVALID_PARAMETER; - goto fail; - } - - status = check_platform_features(); - if (status != EFI_SUCCESS) - goto fail; - - /* - * Get a handle to the loaded image protocol. This is used to get - * information about the running image, such as size and the command - * line. - */ - status = sys_table->boottime->handle_protocol(handle, - &loaded_image_proto, (void *)&image); - if (status != EFI_SUCCESS) { - pr_efi_err("Failed to get loaded image protocol\n"); - goto fail; - } - - dram_base = get_dram_base(); - if (dram_base == EFI_ERROR) { - pr_efi_err("Failed to find DRAM base\n"); - status = EFI_LOAD_ERROR; - goto fail; - } - - /* - * Get the command line from EFI, using the LOADED_IMAGE - * protocol. We are going to copy the command line into the - * device tree, so this can be allocated anywhere. - */ - cmdline_ptr = efi_convert_cmdline(image, &cmdline_size, ULONG_MAX); - if (!cmdline_ptr) { - pr_efi_err("getting command line via LOADED_IMAGE_PROTOCOL\n"); - status = EFI_OUT_OF_RESOURCES; - goto fail; - } - - if (IS_ENABLED(CONFIG_CMDLINE_EXTEND) || - IS_ENABLED(CONFIG_CMDLINE_FORCE) || - cmdline_size == 0) - efi_parse_options(CONFIG_CMDLINE); - - if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && cmdline_size > 0) - efi_parse_options(cmdline_ptr); - - pr_efi("Booting Linux Kernel...\n"); - - si = setup_graphics(); - - status = handle_kernel_image(&image_addr, &image_size, - &reserve_addr, - &reserve_size, - dram_base, image); - if (status != EFI_SUCCESS) { - pr_efi_err("Failed to relocate kernel\n"); - goto fail_free_cmdline; - } - - efi_retrieve_tpm2_eventlog(); - - /* Ask the firmware to clear memory on unclean shutdown */ - efi_enable_reset_attack_mitigation(); - - secure_boot = efi_get_secureboot(); - - /* - * Unauthenticated device tree data is a security hazard, so ignore - * 'dtb=' unless UEFI Secure Boot is disabled. We assume that secure - * boot is enabled if we can't determine its state. - */ - if (!IS_ENABLED(CONFIG_EFI_ARMSTUB_DTB_LOADER) || - secure_boot != efi_secureboot_mode_disabled) { - if (strstr(cmdline_ptr, "dtb=")) - pr_efi("Ignoring DTB from command line.\n"); - } else { - status = efi_load_dtb(image, &fdt_addr, &fdt_size); - - if (status != EFI_SUCCESS) { - pr_efi_err("Failed to load device tree!\n"); - goto fail_free_image; - } - } - - if (fdt_addr) { - pr_efi("Using DTB from command line\n"); - } else { - /* Look for a device tree configuration table entry. */ - fdt_addr = (uintptr_t)get_fdt(&fdt_size); - if (fdt_addr) - pr_efi("Using DTB from configuration table\n"); - } - - if (!fdt_addr) - pr_efi("Generating empty DTB\n"); - - if (!noinitrd()) { - max_addr = efi_get_max_initrd_addr(dram_base, image_addr); - status = efi_load_initrd_dev_path(&initrd_addr, &initrd_size, - max_addr); - if (status == EFI_SUCCESS) { - pr_efi("Loaded initrd from LINUX_EFI_INITRD_MEDIA_GUID device path\n"); - } else if (status == EFI_NOT_FOUND) { - status = efi_load_initrd(image, &initrd_addr, &initrd_size, - ULONG_MAX, max_addr); - if (status == EFI_SUCCESS && initrd_size > 0) - pr_efi("Loaded initrd from command line option\n"); - } - if (status != EFI_SUCCESS) - pr_efi_err("Failed to load initrd!\n"); - } - - efi_random_get_seed(); - - /* - * If the NX PE data feature is enabled in the properties table, we - * should take care not to create a virtual mapping that changes the - * relative placement of runtime services code and data regions, as - * they may belong to the same PE/COFF executable image in memory. - * The easiest way to achieve that is to simply use a 1:1 mapping. - */ - prop_tbl = get_efi_config_table(EFI_PROPERTIES_TABLE_GUID); - flat_va_mapping = prop_tbl && - (prop_tbl->memory_protection_attribute & - EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA); - - /* hibernation expects the runtime regions to stay in the same place */ - if (!IS_ENABLED(CONFIG_HIBERNATION) && !nokaslr() && !flat_va_mapping) { - /* - * Randomize the base of the UEFI runtime services region. - * Preserve the 2 MB alignment of the region by taking a - * shift of 21 bit positions into account when scaling - * the headroom value using a 32-bit random value. - */ - static const u64 headroom = EFI_RT_VIRTUAL_LIMIT - - EFI_RT_VIRTUAL_BASE - - EFI_RT_VIRTUAL_SIZE; - u32 rnd; - - status = efi_get_random_bytes(sizeof(rnd), (u8 *)&rnd); - if (status == EFI_SUCCESS) { - virtmap_base = EFI_RT_VIRTUAL_BASE + - (((headroom >> 21) * rnd) >> (32 - 21)); - } - } - - install_memreserve_table(); - - status = allocate_new_fdt_and_exit_boot(handle, &fdt_addr, - efi_get_max_fdt_addr(dram_base), - initrd_addr, initrd_size, - cmdline_ptr, fdt_addr, fdt_size); - if (status != EFI_SUCCESS) - goto fail_free_initrd; - - efi_enter_kernel(image_addr, fdt_addr, fdt_totalsize((void *)fdt_addr)); - /* not reached */ - -fail_free_initrd: - pr_efi_err("Failed to update FDT and exit boot services\n"); - - efi_free(initrd_size, initrd_addr); - efi_free(fdt_size, fdt_addr); - -fail_free_image: - efi_free(image_size, image_addr); - efi_free(reserve_size, reserve_addr); -fail_free_cmdline: - free_screen_info(si); - efi_free(cmdline_size, (unsigned long)cmdline_ptr); -fail: - return status; -} - -/* - * efi_get_virtmap() - create a virtual mapping for the EFI memory map - * - * This function populates the virt_addr fields of all memory region descriptors - * in @memory_map whose EFI_MEMORY_RUNTIME attribute is set. Those descriptors - * are also copied to @runtime_map, and their total count is returned in @count. - */ -void efi_get_virtmap(efi_memory_desc_t *memory_map, unsigned long map_size, - unsigned long desc_size, efi_memory_desc_t *runtime_map, - int *count) -{ - u64 efi_virt_base = virtmap_base; - efi_memory_desc_t *in, *out = runtime_map; - int l; - - for (l = 0; l < map_size; l += desc_size) { - u64 paddr, size; - - in = (void *)memory_map + l; - if (!(in->attribute & EFI_MEMORY_RUNTIME)) - continue; - - paddr = in->phys_addr; - size = in->num_pages * EFI_PAGE_SIZE; - - in->virt_addr = in->phys_addr; - if (novamap()) { - continue; - } - - /* - * Make the mapping compatible with 64k pages: this allows - * a 4k page size kernel to kexec a 64k page size kernel and - * vice versa. - */ - if (!flat_va_mapping) { - - paddr = round_down(in->phys_addr, SZ_64K); - size += in->phys_addr - paddr; - - /* - * Avoid wasting memory on PTEs by choosing a virtual - * base that is compatible with section mappings if this - * region has the appropriate size and physical - * alignment. (Sections are 2 MB on 4k granule kernels) - */ - if (IS_ALIGNED(in->phys_addr, SZ_2M) && size >= SZ_2M) - efi_virt_base = round_up(efi_virt_base, SZ_2M); - else - efi_virt_base = round_up(efi_virt_base, SZ_64K); - - in->virt_addr += efi_virt_base - paddr; - efi_virt_base += size; - } - - memcpy(out, in, desc_size); - out = (void *)out + desc_size; - ++*count; - } -} diff --git a/drivers/firmware/efi/libstub/efi-stub.c b/drivers/firmware/efi/libstub/efi-stub.c new file mode 100644 index 000000000000..99a5cde7c2d8 --- /dev/null +++ b/drivers/firmware/efi/libstub/efi-stub.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * EFI stub implementation that is shared by arm and arm64 architectures. + * This should be #included by the EFI stub implementation files. + * + * Copyright (C) 2013,2014 Linaro Limited + * Roy Franz + */ + +#include +#include +#include + +#include "efistub.h" + +/* + * This is the base address at which to start allocating virtual memory ranges + * for UEFI Runtime Services. This is in the low TTBR0 range so that we can use + * any allocation we choose, and eliminate the risk of a conflict after kexec. + * The value chosen is the largest non-zero power of 2 suitable for this purpose + * both on 32-bit and 64-bit ARM CPUs, to maximize the likelihood that it can + * be mapped efficiently. + * Since 32-bit ARM could potentially execute with a 1G/3G user/kernel split, + * map everything below 1 GB. (512 MB is a reasonable upper bound for the + * entire footprint of the UEFI runtime services memory regions) + */ +#define EFI_RT_VIRTUAL_BASE SZ_512M +#define EFI_RT_VIRTUAL_SIZE SZ_512M + +#ifdef CONFIG_ARM64 +# define EFI_RT_VIRTUAL_LIMIT DEFAULT_MAP_WINDOW_64 +#else +# define EFI_RT_VIRTUAL_LIMIT TASK_SIZE +#endif + +static u64 virtmap_base = EFI_RT_VIRTUAL_BASE; +static bool __efistub_global flat_va_mapping; + +static efi_system_table_t *__efistub_global sys_table; + +__pure efi_system_table_t *efi_system_table(void) +{ + return sys_table; +} + +static struct screen_info *setup_graphics(void) +{ + efi_guid_t gop_proto = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID; + efi_status_t status; + unsigned long size; + void **gop_handle = NULL; + struct screen_info *si = NULL; + + size = 0; + status = efi_bs_call(locate_handle, EFI_LOCATE_BY_PROTOCOL, + &gop_proto, NULL, &size, gop_handle); + if (status == EFI_BUFFER_TOO_SMALL) { + si = alloc_screen_info(); + if (!si) + return NULL; + efi_setup_gop(si, &gop_proto, size); + } + return si; +} + +void install_memreserve_table(void) +{ + struct linux_efi_memreserve *rsv; + efi_guid_t memreserve_table_guid = LINUX_EFI_MEMRESERVE_TABLE_GUID; + efi_status_t status; + + status = efi_bs_call(allocate_pool, EFI_LOADER_DATA, sizeof(*rsv), + (void **)&rsv); + if (status != EFI_SUCCESS) { + pr_efi_err("Failed to allocate memreserve entry!\n"); + return; + } + + rsv->next = 0; + rsv->size = 0; + atomic_set(&rsv->count, 0); + + status = efi_bs_call(install_configuration_table, + &memreserve_table_guid, rsv); + if (status != EFI_SUCCESS) + pr_efi_err("Failed to install memreserve config table!\n"); +} + +static unsigned long get_dram_base(void) +{ + efi_status_t status; + unsigned long map_size, buff_size; + unsigned long membase = EFI_ERROR; + struct efi_memory_map map; + efi_memory_desc_t *md; + struct efi_boot_memmap boot_map; + + boot_map.map = (efi_memory_desc_t **)&map.map; + boot_map.map_size = &map_size; + boot_map.desc_size = &map.desc_size; + boot_map.desc_ver = NULL; + boot_map.key_ptr = NULL; + boot_map.buff_size = &buff_size; + + status = efi_get_memory_map(&boot_map); + if (status != EFI_SUCCESS) + return membase; + + map.map_end = map.map + map_size; + + for_each_efi_memory_desc_in_map(&map, md) { + if (md->attribute & EFI_MEMORY_WB) { + if (membase > md->phys_addr) + membase = md->phys_addr; + } + } + + efi_bs_call(free_pool, map.map); + + return membase; +} + +/* + * This function handles the architcture specific differences between arm and + * arm64 regarding where the kernel image must be loaded and any memory that + * must be reserved. On failure it is required to free all + * all allocations it has made. + */ +efi_status_t handle_kernel_image(unsigned long *image_addr, + unsigned long *image_size, + unsigned long *reserve_addr, + unsigned long *reserve_size, + unsigned long dram_base, + efi_loaded_image_t *image); + +asmlinkage void __noreturn efi_enter_kernel(unsigned long entrypoint, + unsigned long fdt_addr, + unsigned long fdt_size); + +/* + * EFI entry point for the arm/arm64 EFI stubs. This is the entrypoint + * that is described in the PE/COFF header. Most of the code is the same + * for both archictectures, with the arch-specific code provided in the + * handle_kernel_image() function. + */ +efi_status_t efi_entry(efi_handle_t handle, efi_system_table_t *sys_table_arg) +{ + efi_loaded_image_t *image; + efi_status_t status; + unsigned long image_addr; + unsigned long image_size = 0; + unsigned long dram_base; + /* addr/point and size pairs for memory management*/ + unsigned long initrd_addr = 0; + unsigned long initrd_size = 0; + unsigned long fdt_addr = 0; /* Original DTB */ + unsigned long fdt_size = 0; + char *cmdline_ptr = NULL; + int cmdline_size = 0; + efi_guid_t loaded_image_proto = LOADED_IMAGE_PROTOCOL_GUID; + unsigned long reserve_addr = 0; + unsigned long reserve_size = 0; + enum efi_secureboot_mode secure_boot; + struct screen_info *si; + efi_properties_table_t *prop_tbl; + unsigned long max_addr; + + sys_table = sys_table_arg; + + /* Check if we were booted by the EFI firmware */ + if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) { + status = EFI_INVALID_PARAMETER; + goto fail; + } + + status = check_platform_features(); + if (status != EFI_SUCCESS) + goto fail; + + /* + * Get a handle to the loaded image protocol. This is used to get + * information about the running image, such as size and the command + * line. + */ + status = sys_table->boottime->handle_protocol(handle, + &loaded_image_proto, (void *)&image); + if (status != EFI_SUCCESS) { + pr_efi_err("Failed to get loaded image protocol\n"); + goto fail; + } + + dram_base = get_dram_base(); + if (dram_base == EFI_ERROR) { + pr_efi_err("Failed to find DRAM base\n"); + status = EFI_LOAD_ERROR; + goto fail; + } + + /* + * Get the command line from EFI, using the LOADED_IMAGE + * protocol. We are going to copy the command line into the + * device tree, so this can be allocated anywhere. + */ + cmdline_ptr = efi_convert_cmdline(image, &cmdline_size, ULONG_MAX); + if (!cmdline_ptr) { + pr_efi_err("getting command line via LOADED_IMAGE_PROTOCOL\n"); + status = EFI_OUT_OF_RESOURCES; + goto fail; + } + + if (IS_ENABLED(CONFIG_CMDLINE_EXTEND) || + IS_ENABLED(CONFIG_CMDLINE_FORCE) || + cmdline_size == 0) + efi_parse_options(CONFIG_CMDLINE); + + if (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && cmdline_size > 0) + efi_parse_options(cmdline_ptr); + + pr_efi("Booting Linux Kernel...\n"); + + si = setup_graphics(); + + status = handle_kernel_image(&image_addr, &image_size, + &reserve_addr, + &reserve_size, + dram_base, image); + if (status != EFI_SUCCESS) { + pr_efi_err("Failed to relocate kernel\n"); + goto fail_free_cmdline; + } + + efi_retrieve_tpm2_eventlog(); + + /* Ask the firmware to clear memory on unclean shutdown */ + efi_enable_reset_attack_mitigation(); + + secure_boot = efi_get_secureboot(); + + /* + * Unauthenticated device tree data is a security hazard, so ignore + * 'dtb=' unless UEFI Secure Boot is disabled. We assume that secure + * boot is enabled if we can't determine its state. + */ + if (!IS_ENABLED(CONFIG_EFI_ARMSTUB_DTB_LOADER) || + secure_boot != efi_secureboot_mode_disabled) { + if (strstr(cmdline_ptr, "dtb=")) + pr_efi("Ignoring DTB from command line.\n"); + } else { + status = efi_load_dtb(image, &fdt_addr, &fdt_size); + + if (status != EFI_SUCCESS) { + pr_efi_err("Failed to load device tree!\n"); + goto fail_free_image; + } + } + + if (fdt_addr) { + pr_efi("Using DTB from command line\n"); + } else { + /* Look for a device tree configuration table entry. */ + fdt_addr = (uintptr_t)get_fdt(&fdt_size); + if (fdt_addr) + pr_efi("Using DTB from configuration table\n"); + } + + if (!fdt_addr) + pr_efi("Generating empty DTB\n"); + + if (!noinitrd()) { + max_addr = efi_get_max_initrd_addr(dram_base, image_addr); + status = efi_load_initrd_dev_path(&initrd_addr, &initrd_size, + max_addr); + if (status == EFI_SUCCESS) { + pr_efi("Loaded initrd from LINUX_EFI_INITRD_MEDIA_GUID device path\n"); + } else if (status == EFI_NOT_FOUND) { + status = efi_load_initrd(image, &initrd_addr, &initrd_size, + ULONG_MAX, max_addr); + if (status == EFI_SUCCESS && initrd_size > 0) + pr_efi("Loaded initrd from command line option\n"); + } + if (status != EFI_SUCCESS) + pr_efi_err("Failed to load initrd!\n"); + } + + efi_random_get_seed(); + + /* + * If the NX PE data feature is enabled in the properties table, we + * should take care not to create a virtual mapping that changes the + * relative placement of runtime services code and data regions, as + * they may belong to the same PE/COFF executable image in memory. + * The easiest way to achieve that is to simply use a 1:1 mapping. + */ + prop_tbl = get_efi_config_table(EFI_PROPERTIES_TABLE_GUID); + flat_va_mapping = prop_tbl && + (prop_tbl->memory_protection_attribute & + EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA); + + /* hibernation expects the runtime regions to stay in the same place */ + if (!IS_ENABLED(CONFIG_HIBERNATION) && !nokaslr() && !flat_va_mapping) { + /* + * Randomize the base of the UEFI runtime services region. + * Preserve the 2 MB alignment of the region by taking a + * shift of 21 bit positions into account when scaling + * the headroom value using a 32-bit random value. + */ + static const u64 headroom = EFI_RT_VIRTUAL_LIMIT - + EFI_RT_VIRTUAL_BASE - + EFI_RT_VIRTUAL_SIZE; + u32 rnd; + + status = efi_get_random_bytes(sizeof(rnd), (u8 *)&rnd); + if (status == EFI_SUCCESS) { + virtmap_base = EFI_RT_VIRTUAL_BASE + + (((headroom >> 21) * rnd) >> (32 - 21)); + } + } + + install_memreserve_table(); + + status = allocate_new_fdt_and_exit_boot(handle, &fdt_addr, + efi_get_max_fdt_addr(dram_base), + initrd_addr, initrd_size, + cmdline_ptr, fdt_addr, fdt_size); + if (status != EFI_SUCCESS) + goto fail_free_initrd; + + efi_enter_kernel(image_addr, fdt_addr, fdt_totalsize((void *)fdt_addr)); + /* not reached */ + +fail_free_initrd: + pr_efi_err("Failed to update FDT and exit boot services\n"); + + efi_free(initrd_size, initrd_addr); + efi_free(fdt_size, fdt_addr); + +fail_free_image: + efi_free(image_size, image_addr); + efi_free(reserve_size, reserve_addr); +fail_free_cmdline: + free_screen_info(si); + efi_free(cmdline_size, (unsigned long)cmdline_ptr); +fail: + return status; +} + +/* + * efi_get_virtmap() - create a virtual mapping for the EFI memory map + * + * This function populates the virt_addr fields of all memory region descriptors + * in @memory_map whose EFI_MEMORY_RUNTIME attribute is set. Those descriptors + * are also copied to @runtime_map, and their total count is returned in @count. + */ +void efi_get_virtmap(efi_memory_desc_t *memory_map, unsigned long map_size, + unsigned long desc_size, efi_memory_desc_t *runtime_map, + int *count) +{ + u64 efi_virt_base = virtmap_base; + efi_memory_desc_t *in, *out = runtime_map; + int l; + + for (l = 0; l < map_size; l += desc_size) { + u64 paddr, size; + + in = (void *)memory_map + l; + if (!(in->attribute & EFI_MEMORY_RUNTIME)) + continue; + + paddr = in->phys_addr; + size = in->num_pages * EFI_PAGE_SIZE; + + in->virt_addr = in->phys_addr; + if (novamap()) { + continue; + } + + /* + * Make the mapping compatible with 64k pages: this allows + * a 4k page size kernel to kexec a 64k page size kernel and + * vice versa. + */ + if (!flat_va_mapping) { + + paddr = round_down(in->phys_addr, SZ_64K); + size += in->phys_addr - paddr; + + /* + * Avoid wasting memory on PTEs by choosing a virtual + * base that is compatible with section mappings if this + * region has the appropriate size and physical + * alignment. (Sections are 2 MB on 4k granule kernels) + */ + if (IS_ALIGNED(in->phys_addr, SZ_2M) && size >= SZ_2M) + efi_virt_base = round_up(efi_virt_base, SZ_2M); + else + efi_virt_base = round_up(efi_virt_base, SZ_64K); + + in->virt_addr += efi_virt_base - paddr; + efi_virt_base += size; + } + + memcpy(out, in, desc_size); + out = (void *)out + desc_size; + ++*count; + } +} -- cgit v1.2.3-70-g09d2 From dceb213ca4a7a8778786bb2eb49ade722a083fdc Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 26 Mar 2020 10:42:32 -0700 Subject: ARM: vf610: report soc info via soc device The patch adds plumbing to soc device info code necessary to support Vybrid devices. Use case in mind for this is CAAM driver, which utilizes said API. Signed-off-by: Andrey Smirnov Cc: Lucas Stach Cc: Chris Healy Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Tested-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 16 +++++++++++++ arch/arm/mach-imx/mach-vf610.c | 53 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mxc.h | 6 +++++ 3 files changed, 75 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 06f8d64b65af..e3d12b21d6f6 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -172,6 +172,22 @@ struct device * __init imx_soc_device_init(void) ocotp_compat = "fsl,imx7ulp-ocotp"; soc_id = "i.MX7ULP"; break; + case MXC_CPU_VF500: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF500"; + break; + case MXC_CPU_VF510: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF510"; + break; + case MXC_CPU_VF600: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF600"; + break; + case MXC_CPU_VF610: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF610"; + break; default: soc_id = "Unknown"; } diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 9c929b09310c..565dc08412a2 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -3,11 +3,63 @@ * Copyright 2012-2013 Freescale Semiconductor, Inc. */ +#include #include +#include + #include #include #include +#include "common.h" +#include "hardware.h" + +#define MSCM_CPxCOUNT 0x00c +#define MSCM_CPxCFG1 0x014 + +static void __init vf610_detect_cpu(void) +{ + struct device_node *np; + u32 cpxcount, cpxcfg1; + unsigned int cpu_type; + void __iomem *mscm; + + np = of_find_compatible_node(NULL, NULL, "fsl,vf610-mscm-cpucfg"); + if (WARN_ON(!np)) + return; + + mscm = of_iomap(np, 0); + of_node_put(np); + + if (WARN_ON(!mscm)) + return; + + cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT); + cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1); + + iounmap(mscm); + + cpu_type = cpxcount ? MXC_CPU_VF600 : MXC_CPU_VF500; + + if (cpxcfg1) + cpu_type |= MXC_CPU_VFx10; + + mxc_set_cpu_type(cpu_type); +} + +static void __init vf610_init_machine(void) +{ + struct device *parent; + + vf610_detect_cpu(); + + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_default_populate(NULL, NULL, parent); +} + static const char * const vf610_dt_compat[] __initconst = { "fsl,vf500", "fsl,vf510", @@ -20,5 +72,6 @@ static const char * const vf610_dt_compat[] __initconst = { DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, + .init_machine = vf610_init_machine, .dt_compat = vf610_dt_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 2bfd2d59b4a6..48e6d781f15b 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -33,6 +33,12 @@ #define MXC_CPU_IMX7D 0x72 #define MXC_CPU_IMX7ULP 0xff +#define MXC_CPU_VFx10 0x010 +#define MXC_CPU_VF500 0x500 +#define MXC_CPU_VF510 (MXC_CPU_VF500 | MXC_CPU_VFx10) +#define MXC_CPU_VF600 0x600 +#define MXC_CPU_VF610 (MXC_CPU_VF600 | MXC_CPU_VFx10) + #define IMX_DDR_TYPE_LPDDR2 1 #ifndef __ASSEMBLY__ -- cgit v1.2.3-70-g09d2 From 22090f84bc3f8081e0ec180ccaedc85820085376 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 23 Apr 2020 13:44:50 +0200 Subject: efi/libstub: unify EFI call wrappers for non-x86 We have wrappers around EFI calls so that x86 can define special versions for mixed mode, while all other architectures can use the same simple definition that just issues the call directly. In preparation for the arrival of yet another architecture that doesn't need anything special here (RISC-V), let's move the default definition into a shared header. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/efi.h | 8 -------- arch/arm64/include/asm/efi.h | 8 -------- drivers/firmware/efi/libstub/efistub.h | 16 ++++++++++++++++ 3 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index 5ac46e2860bc..9383f236e795 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -50,14 +50,6 @@ void efi_virtmap_unload(void); /* arch specific definitions used by the stub code */ -#define efi_bs_call(func, ...) efi_system_table()->boottime->func(__VA_ARGS__) -#define efi_rt_call(func, ...) efi_system_table()->runtime->func(__VA_ARGS__) -#define efi_is_native() (true) - -#define efi_table_attr(inst, attr) (inst->attr) - -#define efi_call_proto(inst, func, ...) inst->func(inst, ##__VA_ARGS__) - struct screen_info *alloc_screen_info(void); void free_screen_info(struct screen_info *si); diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 45e821222774..d4ab3f73e7a3 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -86,14 +86,6 @@ static inline unsigned long efi_get_max_initrd_addr(unsigned long dram_base, return (image_addr & ~(SZ_1G - 1UL)) + (1UL << (VA_BITS_MIN - 1)); } -#define efi_bs_call(func, ...) efi_system_table()->boottime->func(__VA_ARGS__) -#define efi_rt_call(func, ...) efi_system_table()->runtime->func(__VA_ARGS__) -#define efi_is_native() (true) - -#define efi_table_attr(inst, attr) (inst->attr) - -#define efi_call_proto(inst, func, ...) inst->func(inst, ##__VA_ARGS__) - #define alloc_screen_info(x...) &screen_info static inline void free_screen_info(struct screen_info *si) diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index 7517683b31e9..d9ad8582dbea 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -39,6 +39,22 @@ extern bool __pure novamap(void); extern __pure efi_system_table_t *efi_system_table(void); +#ifndef efi_bs_call +#define efi_bs_call(func, ...) efi_system_table()->boottime->func(__VA_ARGS__) +#endif +#ifndef efi_rt_call +#define efi_rt_call(func, ...) efi_system_table()->runtime->func(__VA_ARGS__) +#endif +#ifndef efi_is_native +#define efi_is_native() (true) +#endif +#ifndef efi_table_attr +#define efi_table_attr(inst, attr) (inst->attr) +#endif +#ifndef efi_call_proto +#define efi_call_proto(inst, func, ...) inst->func(inst, ##__VA_ARGS__) +#endif + #define pr_efi(msg) do { \ if (!is_quiet()) efi_printk("EFI stub: "msg); \ } while (0) -- cgit v1.2.3-70-g09d2 From 420b6d00ca94ce5b6578b1bc12e767ac7a0251ac Mon Sep 17 00:00:00 2001 From: Arvind Sankar Date: Thu, 16 Apr 2020 11:12:25 -0400 Subject: efi/arm: Remove __efistub_global annotation Instead of using __efistub_global to force variables into the .data section, leave them in the .bss but pull the EFI stub's .bss section into .data in the linker script for the compressed kernel. Signed-off-by: Arvind Sankar Reviewed-by: Ard Biesheuvel Link: https://lore.kernel.org/r/20200416151227.3360778-2-nivedita@alum.mit.edu Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/vmlinux.lds.S | 2 +- drivers/firmware/efi/libstub/Makefile | 7 ++++--- drivers/firmware/efi/libstub/efistub.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index b247f399de71..b6793c7932a9 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -78,7 +78,7 @@ SECTIONS * The EFI stub always executes from RAM, and runs strictly before the * decompressor, so we can make an exception for its r/w data, and keep it */ - *(.data.efistub) + *(.data.efistub .bss.efistub) __pecoff_data_end = .; /* diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index 9a712a6e2f87..aa3ab9a4105e 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -101,8 +101,9 @@ quiet_cmd_stubcopy = STUBCPY $@ # # ARM discards the .data section because it disallows r/w data in the -# decompressor. So move our .data to .data.efistub, which is preserved -# explicitly by the decompressor linker script. +# decompressor. So move our .data to .data.efistub and .bss to .bss.efistub, +# which are preserved explicitly by the decompressor linker script. # -STUBCOPY_FLAGS-$(CONFIG_ARM) += --rename-section .data=.data.efistub +STUBCOPY_FLAGS-$(CONFIG_ARM) += --rename-section .data=.data.efistub \ + --rename-section .bss=.bss.efistub,load,alloc STUBCOPY_RELOC-$(CONFIG_ARM) := R_ARM_ABS diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index 2a0698d9dc78..96e25b17c88e 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -25,7 +25,7 @@ #define EFI_ALLOC_ALIGN EFI_PAGE_SIZE #endif -#if defined(CONFIG_ARM) || defined(CONFIG_X86) +#if defined(CONFIG_X86) #define __efistub_global __section(.data) #else #define __efistub_global -- cgit v1.2.3-70-g09d2 From e0d8d4eaccc29959f20de8bef9f1bcce4e952dfc Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sun, 29 Mar 2020 12:42:50 +0200 Subject: ARM: dts: e60k02: add interrupt for PMIC Since the PMIC driver now has IRQ handling, add the GPIO to listen to things like RTC alarm or ADC conversion completion. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/e60k02.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index ce50c4dc6f2a..3af1ab4458ef 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -117,6 +117,8 @@ ricoh619: pmic@32 { compatible = "ricoh,rc5t619"; reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; system-power-controller; regulators { -- cgit v1.2.3-70-g09d2 From 592a8191f05805bc10aa875509bec64d565df931 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 30 Mar 2020 16:46:31 +0530 Subject: arm: dts: ls1021atwr: Add QSPI node properties LS1021A-TWR has one micron "n25q128a13" flash of size 16M. Add QSPI node properties for it. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-twr.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 9b1fe99d55b1..5edf001f6138 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -242,6 +242,20 @@ status = "okay"; }; +&qspi { + status = "okay"; + + n25q128a130: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &sai1 { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From fea89b265f78b639c4845be6b3778a2957eac4bc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Apr 2020 17:15:53 +0200 Subject: ARM: dts: shmobile: Update CMT1 compatible values New compatible values were introduced for the 48-bit CMT devices on SH-Mobile AG5 and R-Mobile A1, and the old "cmt-48"-based values were deprecated. However, the actual DTS files were never updated. See also commits: - 81b604c39997de91 ("dt-bindings: timer: renesas, cmt: Update CMT1 on sh73a0 and r8a7740"), - 8c1afba285a86b9d ("clocksource/drivers/sh_cmt: r8a7740 and sh73a0 SoC-specific match"), - 19d608458f4f3bb3 ("clocksource/drivers/sh_cmt: Document "cmt-48" as deprecated"). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200420151553.22975-1-geert+renesas@glider.be --- arch/arm/boot/dts/r8a7740.dtsi | 2 +- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ebc1ff64f530..014805894ea7 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -83,7 +83,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; + compatible = "renesas,r8a7740-cmt1"; reg = <0xe6138000 0x170>; interrupts = ; clocks = <&mstp3_clks R8A7740_CLK_CMT1>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c134154bcce8..01fd06328420 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -99,7 +99,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; + compatible = "renesas,sh73a0-cmt1"; reg = <0xe6138000 0x200>; interrupts = ; clocks = <&mstp3_clks SH73A0_CLK_CMT1>; -- cgit v1.2.3-70-g09d2 From ae990a1de014396ffc8d0fcc31b6888c9b0ce59a Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 21 Apr 2020 18:35:56 +0900 Subject: ARM: dts: renesas: Fix IOMMU device node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix IOMMU device node names as "iommu@". Fixes: bbb44da0b595 ("ARM: dts: r8a7743: Add IPMMU DT nodes") Fixes: 0dcba3de5835 ("ARM: dts: r8a7745: Add IPMMU DT nodes") Fixes: 350ae49b97c4 ("ARM: dts: r8a7744: Add IPMMU DT nodes") Fixes: 70496727c082 ("ARM: shmobile: r8a7790: Add IPMMU DT nodes") Fixes: f1951852ed17 ("ARM: shmobile: r8a7791: Add IPMMU DT nodes") Fixes: 098cb3a601e6 ("ARM: shmobile: r8a7793: Add IPMMU nodes") Fixes: 1cb2794f6082 ("ARM: shmobile: r8a7794: Add IPMMU DT nodes") Signed-off-by: Yoshihiro Shimoda Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/1587461756-13317-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++------ arch/arm/boot/dts/r8a7744.dtsi | 12 ++++++------ arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++------ arch/arm/boot/dts/r8a7790.dtsi | 12 ++++++------ arch/arm/boot/dts/r8a7791.dtsi | 14 +++++++------- arch/arm/boot/dts/r8a7793.dtsi | 14 +++++++------- arch/arm/boot/dts/r8a7794.dtsi | 12 ++++++------ 7 files changed, 44 insertions(+), 44 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index e8b340bb99bc..fff123753b85 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index def840b8b2d3..5050ac19041d 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 7ab58d8bb740..b0d1fc24e97e 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -302,7 +302,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -312,7 +312,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -321,7 +321,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -331,7 +331,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -340,7 +340,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -350,7 +350,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index e5ef9fd4284a..166d5566229d 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -427,7 +427,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -437,7 +437,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -446,7 +446,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -456,7 +456,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -465,7 +465,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -475,7 +475,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index b2d329a5d8d5..225676fbe312 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -361,7 +361,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -371,7 +371,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -380,7 +380,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -390,7 +390,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -399,7 +399,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -409,7 +409,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -418,7 +418,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index dadbda16161b..1b62a7e06b42 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -336,7 +336,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -346,7 +346,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -355,7 +355,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -365,7 +365,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -374,7 +374,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -384,7 +384,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -393,7 +393,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 2c9e7a1ebfec..8d7f8798628a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -290,7 +290,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -300,7 +300,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -309,7 +309,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -319,7 +319,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -328,7 +328,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -338,7 +338,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; -- cgit v1.2.3-70-g09d2 From 135e7a156ae2c1a7a1f0c1d44bf2b3daece04bbf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Apr 2020 22:40:49 +0100 Subject: ARM: shmobile: r8a7742: Basic SoC support Add minimal support for the RZ/G1H (R8A7742) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1587678050-23468-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/setup-rcar-gen2.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 1ee5cd2840e0..c42ff8c314c8 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -24,6 +24,7 @@ #include "rcar-gen2.h" static const struct of_device_id cpg_matches[] __initconst = { + { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" }, { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" }, { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" }, { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" }, @@ -209,6 +210,7 @@ DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)") MACHINE_END static const char * const rz_g1_boards_compat_dt[] __initconst = { + "renesas,r8a7742", "renesas,r8a7743", "renesas,r8a7744", "renesas,r8a7745", -- cgit v1.2.3-70-g09d2 From dda830431640264b6afcf78424dcefaf4cbc55a4 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 1 Apr 2020 17:03:39 +0200 Subject: ARM: dts: stm32: add cortex-M4 pdds management in Cortex-M4 node Add declarations related to the syscon pdds for deep sleep management. Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index d70fc774e0a4..3a709f333a7f 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1124,6 +1124,11 @@ }; }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "syscon"; + reg = <0x50001014 0x4>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; @@ -1705,6 +1710,7 @@ resets = <&rcc MCU_R>; st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; status = "disabled"; }; }; -- cgit v1.2.3-70-g09d2 From 06a933aaef99ae6338e0da51f9d5016c3b8f8ead Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 23 Jan 2020 17:12:49 +0100 Subject: ARM: dts: stm32: use st,stm32mp15-i2c compatible for stm32mp151 Replace previous st,stm32f7-i2c compatible with st,stm32mp15-i2c for the platform stm32mp151. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3a709f333a7f..baff797c17fb 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -475,7 +475,7 @@ }; i2c1: i2c@40012000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -489,7 +489,7 @@ }; i2c2: i2c@40013000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -503,7 +503,7 @@ }; i2c3: i2c@40014000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -517,7 +517,7 @@ }; i2c5: i2c@40015000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -1486,7 +1486,7 @@ }; i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -1522,7 +1522,7 @@ }; i2c6: i2c@5c009000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; interrupts = , -- cgit v1.2.3-70-g09d2 From ea6318dc5a1d2c4c146d9db92cbef8d9d6619461 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 23 Jan 2020 17:12:50 +0100 Subject: ARM: dts: stm32: add Fast Mode Plus info in I2C nodes of stm32mp151 Add the syscfg-fmp property in each i2c node in order to allow Fast Mode Plus speed if clock-frequency >= 1MHz is indicated. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index baff797c17fb..41fb7b7c4f5b 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -484,6 +484,7 @@ resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; status = "disabled"; }; @@ -498,6 +499,7 @@ resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; status = "disabled"; }; @@ -512,6 +514,7 @@ resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; status = "disabled"; }; @@ -526,6 +529,7 @@ resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; status = "disabled"; }; @@ -1495,6 +1499,7 @@ resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; status = "disabled"; }; @@ -1531,6 +1536,7 @@ resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From e07fec6062865ae4fbc096223fbceac039b18acf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Feb 2020 15:26:29 +0100 Subject: ARM: integrator: Retire LM and IM-PD1 boardfile code We now support probing and populating logical modules and the IM-PD1 example module in particular directly from the device tree using the LM bus driver. Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/Makefile | 3 +- arch/arm/mach-integrator/impd1.c | 475 ------------------------------- arch/arm/mach-integrator/impd1.h | 15 - arch/arm/mach-integrator/integrator_ap.c | 31 -- arch/arm/mach-integrator/lm.c | 96 ------- arch/arm/mach-integrator/lm.h | 24 -- 6 files changed, 1 insertion(+), 643 deletions(-) delete mode 100644 arch/arm/mach-integrator/impd1.c delete mode 100644 arch/arm/mach-integrator/impd1.h delete mode 100644 arch/arm/mach-integrator/lm.c delete mode 100644 arch/arm/mach-integrator/lm.h (limited to 'arch/arm') diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile index 71b97ffe8d32..7857a55c90b0 100644 --- a/arch/arm/mach-integrator/Makefile +++ b/arch/arm/mach-integrator/Makefile @@ -5,7 +5,6 @@ # Object file lists. -obj-y := core.o lm.o +obj-y := core.o obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o -obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c deleted file mode 100644 index 6f875ded8419..000000000000 --- a/arch/arm/mach-integrator/impd1.c +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-integrator/impd1.c - * - * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. - * - * This file provides the core support for the IM-PD1 module. - * - * Module / boot parameters. - * lmid=n impd1.lmid=n - set the logic module position in stack to 'n' - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "lm.h" -#include "impd1.h" - -static int module_id; - -module_param_named(lmid, module_id, int, 0444); -MODULE_PARM_DESC(lmid, "logic module stack position"); - -struct impd1_module { - void __iomem *base; - void __iomem *vic_base; -}; - -void impd1_tweak_control(struct device *dev, u32 mask, u32 val) -{ - struct impd1_module *impd1 = dev_get_drvdata(dev); - u32 cur; - - val &= mask; - cur = readl(impd1->base + IMPD1_CTRL) & ~mask; - writel(cur | val, impd1->base + IMPD1_CTRL); -} - -EXPORT_SYMBOL(impd1_tweak_control); - -/* - * MMC support - */ -static struct mmci_platform_data mmc_data = { - .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, -}; - -/* - * CLCD support - */ -#define PANEL PROSPECTOR - -#define LTM10C209 1 -#define PROSPECTOR 2 -#define SVGA 3 -#define VGA 4 - -#if PANEL == VGA -#define PANELTYPE vga -static struct clcd_panel vga = { - .mode = { - .name = "VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD | TIM2_IPC, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .caps = CLCD_CAP_5551, - .connector = IMPD1_CTRL_DISP_VGA, - .bpp = 16, - .grayscale = 0, -}; - -#elif PANEL == SVGA -#define PANELTYPE svga -static struct clcd_panel svga = { - .mode = { - .name = "SVGA", - .refresh = 0, - .xres = 800, - .yres = 600, - .pixclock = 27778, - .left_margin = 20, - .right_margin = 20, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 164, - .vsync_len = 62, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .connector = IMPD1_CTRL_DISP_VGA, - .caps = CLCD_CAP_5551, - .bpp = 16, - .grayscale = 0, -}; - -#elif PANEL == PROSPECTOR -#define PANELTYPE prospector -static struct clcd_panel prospector = { - .mode = { - .name = "PROSPECTOR", - .refresh = 0, - .xres = 640, - .yres = 480, - .pixclock = 40000, - .left_margin = 33, - .right_margin = 64, - .upper_margin = 36, - .lower_margin = 7, - .hsync_len = 64, - .vsync_len = 25, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .caps = CLCD_CAP_5551, - .fixedtimings = 1, - .connector = IMPD1_CTRL_DISP_LCD, - .bpp = 16, - .grayscale = 0, -}; - -#elif PANEL == LTM10C209 -#define PANELTYPE ltm10c209 -/* - * Untested. - */ -static struct clcd_panel ltm10c209 = { - .mode = { - .name = "LTM10C209", - .refresh = 0, - .xres = 640, - .yres = 480, - .pixclock = 40000, - .left_margin = 20, - .right_margin = 20, - .upper_margin = 19, - .lower_margin = 19, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, - .width = -1, - .height = -1, - .tim2 = TIM2_BCD, - .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), - .caps = CLCD_CAP_5551, - .fixedtimings = 1, - .connector = IMPD1_CTRL_DISP_LCD, - .bpp = 16, - .grayscale = 0, -}; -#endif - -/* - * Disable all display connectors on the interface module. - */ -static void impd1fb_clcd_disable(struct clcd_fb *fb) -{ - impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK, 0); -} - -/* - * Enable the relevant connector on the interface module. - */ -static void impd1fb_clcd_enable(struct clcd_fb *fb) -{ - impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK, - fb->panel->connector | IMPD1_CTRL_DISP_ENABLE); -} - -static int impd1fb_clcd_setup(struct clcd_fb *fb) -{ - unsigned long framebase = fb->dev->res.start + 0x01000000; - unsigned long framesize = SZ_1M; - int ret = 0; - - fb->panel = &PANELTYPE; - - if (!request_mem_region(framebase, framesize, "clcd framebuffer")) { - printk(KERN_ERR "IM-PD1: unable to reserve framebuffer\n"); - return -EBUSY; - } - - fb->fb.screen_base = ioremap(framebase, framesize); - if (!fb->fb.screen_base) { - printk(KERN_ERR "IM-PD1: unable to map framebuffer\n"); - ret = -ENOMEM; - goto free_buffer; - } - - fb->fb.fix.smem_start = framebase; - fb->fb.fix.smem_len = framesize; - - return 0; - - free_buffer: - release_mem_region(framebase, framesize); - return ret; -} - -static int impd1fb_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) -{ - unsigned long start, size; - - start = vma->vm_pgoff + (fb->fb.fix.smem_start >> PAGE_SHIFT); - size = vma->vm_end - vma->vm_start; - - return remap_pfn_range(vma, vma->vm_start, start, size, - vma->vm_page_prot); -} - -static void impd1fb_clcd_remove(struct clcd_fb *fb) -{ - iounmap(fb->fb.screen_base); - release_mem_region(fb->fb.fix.smem_start, fb->fb.fix.smem_len); -} - -static struct clcd_board impd1_clcd_data = { - .name = "IM-PD/1", - .caps = CLCD_CAP_5551 | CLCD_CAP_888, - .check = clcdfb_check, - .decode = clcdfb_decode, - .disable = impd1fb_clcd_disable, - .enable = impd1fb_clcd_enable, - .setup = impd1fb_clcd_setup, - .mmap = impd1fb_clcd_mmap, - .remove = impd1fb_clcd_remove, -}; - -struct impd1_device { - unsigned long offset; - unsigned int irq[2]; - unsigned int id; - void *platform_data; -}; - -static struct impd1_device impd1_devs[] = { - { - .offset = 0x00100000, - .irq = { 1 }, - .id = 0x00141011, - }, { - .offset = 0x00200000, - .irq = { 2 }, - .id = 0x00141011, - }, { - .offset = 0x00300000, - .irq = { 3 }, - .id = 0x00041022, - }, { - .offset = 0x00400000, - .irq = { 4 }, - .id = 0x00041061, - }, { - .offset = 0x00500000, - .irq = { 5 }, - .id = 0x00041061, - }, { - .offset = 0x00600000, - .irq = { 6 }, - .id = 0x00041130, - }, { - .offset = 0x00700000, - .irq = { 7, 8 }, - .id = 0x00041181, - .platform_data = &mmc_data, - }, { - .offset = 0x00800000, - .irq = { 9 }, - .id = 0x00041041, - }, { - .offset = 0x01000000, - .irq = { 11 }, - .id = 0x00041110, - .platform_data = &impd1_clcd_data, - } -}; - -/* - * Valid IRQs: 0 thru 9 and 11, 10 unused. - */ -#define IMPD1_VALID_IRQS 0x00000bffU - -/* - * As this module is bool, it is OK to have this as __ref() - no - * probe calls will be done after the initial system bootup, as devices - * are discovered as part of the machine startup. - */ -static int __ref impd1_probe(struct lm_device *dev) -{ - struct impd1_module *impd1; - int irq_base; - int i; - - if (dev->id != module_id) - return -EINVAL; - - if (!devm_request_mem_region(&dev->dev, dev->resource.start, - SZ_4K, "LM registers")) - return -EBUSY; - - impd1 = devm_kzalloc(&dev->dev, sizeof(struct impd1_module), - GFP_KERNEL); - if (!impd1) - return -ENOMEM; - - impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K); - if (!impd1->base) - return -ENOMEM; - - integrator_impd1_clk_init(impd1->base, dev->id); - - if (!devm_request_mem_region(&dev->dev, - dev->resource.start + 0x03000000, - SZ_4K, "VIC")) - return -EBUSY; - - impd1->vic_base = devm_ioremap(&dev->dev, - dev->resource.start + 0x03000000, - SZ_4K); - if (!impd1->vic_base) - return -ENOMEM; - - irq_base = vic_init_cascaded(impd1->vic_base, dev->irq, - IMPD1_VALID_IRQS, 0); - - lm_set_drvdata(dev, impd1); - - dev_info(&dev->dev, "IM-PD1 found at 0x%08lx\n", - (unsigned long)dev->resource.start); - - for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) { - struct impd1_device *idev = impd1_devs + i; - struct amba_device *d; - unsigned long pc_base; - char devname[32]; - int irq1 = idev->irq[0]; - int irq2 = idev->irq[1]; - - /* Translate IRQs to IM-PD1 local numberspace */ - if (irq1) - irq1 += irq_base; - if (irq2) - irq2 += irq_base; - - pc_base = dev->resource.start + idev->offset; - snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12); - - /* Add GPIO descriptor lookup table for the PL061 block */ - if (idev->offset == 0x00400000) { - struct gpiod_lookup_table *lookup; - char *chipname; - char *mmciname; - - lookup = devm_kzalloc(&dev->dev, - struct_size(lookup, table, 3), - GFP_KERNEL); - chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL); - mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL, - "lm%x:00700", dev->id); - if (!lookup || !chipname || !mmciname) - return -ENOMEM; - - lookup->dev_id = mmciname; - /* - * Offsets on GPIO block 1: - * 3 = MMC WP (write protect) - * 4 = MMC CD (card detect) - * - * Offsets on GPIO block 2: - * 0 = Up key - * 1 = Down key - * 2 = Left key - * 3 = Right key - * 4 = Key lower left - * 5 = Key lower right - */ - /* We need the two MMCI GPIO entries */ - lookup->table[0] = (struct gpiod_lookup) - GPIO_LOOKUP(chipname, 3, "wp", 0); - lookup->table[1] = (struct gpiod_lookup) - GPIO_LOOKUP(chipname, 4, "cd", GPIO_ACTIVE_LOW); - gpiod_add_lookup_table(lookup); - } - - d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K, - irq1, irq2, - idev->platform_data, idev->id, - &dev->resource); - if (IS_ERR(d)) { - dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d)); - continue; - } - } - - return 0; -} - -static int impd1_remove_one(struct device *dev, void *data) -{ - device_unregister(dev); - return 0; -} - -static void impd1_remove(struct lm_device *dev) -{ - device_for_each_child(&dev->dev, NULL, impd1_remove_one); - integrator_impd1_clk_exit(dev->id); - - lm_set_drvdata(dev, NULL); -} - -static struct lm_driver impd1_driver = { - .drv = { - .name = "impd1", - /* - * As we're dropping the probe() function, suppress driver - * binding from sysfs. - */ - .suppress_bind_attrs = true, - }, - .probe = impd1_probe, - .remove = impd1_remove, -}; - -static int __init impd1_init(void) -{ - return lm_driver_register(&impd1_driver); -} - -static void __exit impd1_exit(void) -{ - lm_driver_unregister(&impd1_driver); -} - -module_init(impd1_init); -module_exit(impd1_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Integrator/IM-PD1 logic module core driver"); -MODULE_AUTHOR("Deep Blue Solutions Ltd"); diff --git a/arch/arm/mach-integrator/impd1.h b/arch/arm/mach-integrator/impd1.h deleted file mode 100644 index 36124d34c8f7..000000000000 --- a/arch/arm/mach-integrator/impd1.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define IMPD1_LEDS 0x0c -#define IMPD1_INT 0x10 -#define IMPD1_SW 0x14 -#define IMPD1_CTRL 0x18 - -#define IMPD1_CTRL_DISP_LCD (0 << 0) -#define IMPD1_CTRL_DISP_VGA (1 << 0) -#define IMPD1_CTRL_DISP_LCD1 (2 << 0) -#define IMPD1_CTRL_DISP_ENABLE (1 << 2) -#define IMPD1_CTRL_DISP_MASK (7 << 0) - -struct device; - -void impd1_tweak_control(struct device *dev, u32 mask, u32 val); diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 035069ea2c8b..58b02cbbea72 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -23,7 +23,6 @@ #include "hardware.h" #include "cm.h" #include "common.h" -#include "lm.h" /* Regmap to the AP system controller */ static struct regmap *ap_syscon_map; @@ -174,10 +173,7 @@ static const struct of_device_id ap_syscon_match[] = { static void __init ap_init_of(void) { - u32 sc_dec; struct device_node *syscon; - int ret; - int i; of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); @@ -189,33 +185,6 @@ static void __init ap_init_of(void) pr_crit("could not find Integrator/AP system controller\n"); return; } - - ret = regmap_read(ap_syscon_map, - INTEGRATOR_SC_DEC_OFFSET, - &sc_dec); - if (ret) { - pr_crit("could not read from Integrator/AP syscon\n"); - return; - } - - for (i = 0; i < 4; i++) { - struct lm_device *lmdev; - - if ((sc_dec & (16 << i)) == 0) - continue; - - lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); - if (!lmdev) - continue; - - lmdev->resource.start = 0xc0000000 + 0x10000000 * i; - lmdev->resource.end = lmdev->resource.start + 0x0fffffff; - lmdev->resource.flags = IORESOURCE_MEM; - lmdev->irq = irq_of_parse_and_map(syscon, i); - lmdev->id = i; - - lm_device_register(lmdev); - } } static const char * ap_dt_board_compat[] = { diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c deleted file mode 100644 index 55cd173d1d76..000000000000 --- a/arch/arm/mach-integrator/lm.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-integrator/lm.c - * - * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. - */ -#include -#include -#include -#include - -#include "lm.h" - -#define to_lm_device(d) container_of(d, struct lm_device, dev) -#define to_lm_driver(d) container_of(d, struct lm_driver, drv) - -static int lm_match(struct device *dev, struct device_driver *drv) -{ - return 1; -} - -static int lm_bus_probe(struct device *dev) -{ - struct lm_device *lmdev = to_lm_device(dev); - struct lm_driver *lmdrv = to_lm_driver(dev->driver); - - return lmdrv->probe(lmdev); -} - -static int lm_bus_remove(struct device *dev) -{ - struct lm_device *lmdev = to_lm_device(dev); - struct lm_driver *lmdrv = to_lm_driver(dev->driver); - - if (lmdrv->remove) - lmdrv->remove(lmdev); - return 0; -} - -static struct bus_type lm_bustype = { - .name = "logicmodule", - .match = lm_match, - .probe = lm_bus_probe, - .remove = lm_bus_remove, -// .suspend = lm_bus_suspend, -// .resume = lm_bus_resume, -}; - -static int __init lm_init(void) -{ - return bus_register(&lm_bustype); -} - -postcore_initcall(lm_init); - -int lm_driver_register(struct lm_driver *drv) -{ - drv->drv.bus = &lm_bustype; - return driver_register(&drv->drv); -} - -void lm_driver_unregister(struct lm_driver *drv) -{ - driver_unregister(&drv->drv); -} - -static void lm_device_release(struct device *dev) -{ - struct lm_device *d = to_lm_device(dev); - - kfree(d); -} - -int lm_device_register(struct lm_device *dev) -{ - int ret; - - dev->dev.release = lm_device_release; - dev->dev.bus = &lm_bustype; - - ret = dev_set_name(&dev->dev, "lm%d", dev->id); - if (ret) - return ret; - dev->resource.name = dev_name(&dev->dev); - - ret = request_resource(&iomem_resource, &dev->resource); - if (ret == 0) { - ret = device_register(&dev->dev); - if (ret) - release_resource(&dev->resource); - } - return ret; -} - -EXPORT_SYMBOL(lm_driver_register); -EXPORT_SYMBOL(lm_driver_unregister); diff --git a/arch/arm/mach-integrator/lm.h b/arch/arm/mach-integrator/lm.h deleted file mode 100644 index 172966a699bd..000000000000 --- a/arch/arm/mach-integrator/lm.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -struct lm_device { - struct device dev; - struct resource resource; - unsigned int irq; - unsigned int id; -}; - -struct lm_driver { - struct device_driver drv; - int (*probe)(struct lm_device *); - void (*remove)(struct lm_device *); - int (*suspend)(struct lm_device *, pm_message_t); - int (*resume)(struct lm_device *); -}; - -int lm_driver_register(struct lm_driver *drv); -void lm_driver_unregister(struct lm_driver *drv); - -int lm_device_register(struct lm_device *dev); - -#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev) -#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d) -- cgit v1.2.3-70-g09d2 From d2854bbe5f5c4b4bec8061caf4f2e603d8819446 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Feb 2020 15:27:54 +0100 Subject: ARM: integrator: Add some Kconfig selections The CMA and DMA_CMA Kconfig options need to be selected by the Integrator in order to produce boot console on some Integrator systems. The REGULATOR and REGULATOR_FIXED_VOLTAGE need to be selected in order to boot the system from an external MMC card when using MMCI/PL181 from the device tree probe path. Select these things directly from the Kconfig so we are sure to be able to bring the systems up with console from any device tree. Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/Kconfig | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index fbc35e9db46d..106670c37c94 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -4,6 +4,8 @@ menuconfig ARCH_INTEGRATOR depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 select ARM_AMBA select COMMON_CLK_VERSATILE + select CMA + select DMA_CMA select HAVE_TCM select ICST select MFD_SYSCON @@ -34,14 +36,13 @@ config INTEGRATOR_IMPD1 select ARM_VIC select GPIO_PL061 select GPIOLIB + select REGULATOR + select REGULATOR_FIXED_VOLTAGE help The IM-PD1 is an add-on logic module for the Integrator which allows ARM(R) Ltd PrimeCells to be developed and evaluated. The IM-PD1 can be found on the Integrator/PP2 platform. - To compile this driver as a module, choose M here: the - module will be called impd1. - config INTEGRATOR_CM7TDMI bool "Integrator/CM7TDMI core module" depends on ARCH_INTEGRATOR_AP -- cgit v1.2.3-70-g09d2 From d67ef24adf3c3fbaed62c31551d6e36f24fece16 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Feb 2020 15:15:24 +0100 Subject: ARM: dts: Add devicetree for Integrator/AP with IM-PD1 This adds a device tree for the Integrator/AP with the IM-PD1 logic module mounted, using the new logic module bindings. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/integratorap-im-pd1.dts | 270 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/integratorap.dts | 53 +++++- 3 files changed, 320 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/integratorap-im-pd1.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..22c234e93414 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -237,6 +237,7 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \ hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorap.dtb \ + integratorap-im-pd1.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts new file mode 100644 index 000000000000..1412a1a968fc --- /dev/null +++ b/arch/arm/boot/dts/integratorap-im-pd1.dts @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/AP platform + * with the IM-PD1 example logical module mounted. + */ + +#include "integratorap.dts" + +/ { + model = "ARM Integrator/AP with IM-PD1"; + compatible = "arm,integrator-ap"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + impd1_ram: vram@c2000000 { + /* 1 MB of designated video RAM on the IM-PD1 */ + compatible = "shared-dma-pool"; + reg = <0xc2000000 0x00100000>; + no-map; + }; + }; +}; + +&lm0 { + syscon@0 { + compatible = "arm,im-pd1-syscon", "syscon"; + reg = <0x00000000 0x1000>; + + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + + vco2: clock@04 { + compatible = "arm,impd1-vco2"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x04>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO2"; + }; + }; + + /* Also used for the Smart Card Interface SCI */ + impd1_uartclk: clock@1_4 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV4"; + }; + + /* For the SSP the clock is divided by 64 */ + impd1_sspclk: clock@1_64 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <64>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV64"; + }; + + /* Fixed regulator for the MMC */ + impd1_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Push buttons on the IM-PD1 */ + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; + }; + button@1 { + debounce-interval = <50>; + linux,code = ; + label = "DOWN"; + gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce-interval = <50>; + linux,code = ; + label = "LEFT"; + gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce-interval = <50>; + linux,code = ; + label = "ESC"; + gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + button@5 { + debounce-interval = <50>; + linux,code = ; + label = "ENTER"; + gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; + }; + }; + + + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + uart@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart@200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00200000 0x1000>; + interrupts-extended = <&impd1_vic 2>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@300000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00300000 0x1000>; + interrupts-extended = <&impd1_vic 3>; + clocks = <&impd1_sspclk>, <&sysclk>; + clock-names = "spiclk", "apb_pclk"; + }; + + impd1_gpio0: gpio@400000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 4>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + impd1_gpio1: gpio@500000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00500000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 5>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + rtc@600000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x00600000 0x1000>; + interrupts-extended = <&impd1_vic 6>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + mmc@700000 { + compatible = "arm,pl181", "arm,primecell"; + reg = <0x00700000 0x1000>; + interrupts-extended = <&impd1_vic 7>, + <&impd1_vic 8>; + clocks = <&sysclk>, <&sysclk>; + clock-names = "mclk", "apb_pclk"; + bus-width = <1>; + max-frequency = <515633>; + vmmc-supply = <&impd1_3v3>; + wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; + cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; + }; + + aaci@800000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x00800000 0x1000>; + interrupts-extended = <&impd1_vic 9>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + display@1000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x01000000 0x1000>; + interrupts-extended = <&impd1_vic 11>; + clocks = <&vco1>, <&sysclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; + memory-region = <&impd1_ram>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_vga_dac: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + /* Valid interrupts, 0-9 and 11 */ + valid-mask = <0x00000bff>; + /* LM site 0 has IRQ 9 on the PIC */ + interrupts-extended = <&pic 9>; + }; +}; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 198d66181c50..67d1f9b24a52 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -4,7 +4,9 @@ */ /dts-v1/; -/include/ "integrator.dtsi" +#include "integrator.dtsi" +#include +#include / { model = "ARM Integrator/AP"; @@ -107,9 +109,6 @@ syscon { compatible = "arm,integrator-ap-syscon", "syscon"; reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; /* * SYSCLK clocks PCIv3 bridge, system controller and the @@ -239,4 +238,50 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; }; + + /* + * Logic module bus, we support up to 4 logical modules + * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 + * and use interrupts 9, 10, 11 and 12 respectively. + */ + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + lm0: bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xc0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm1: bus@d0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xd0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xd0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm2: bus@e0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xe0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xe0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm3: bus@f0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xf0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; -- cgit v1.2.3-70-g09d2 From 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Apr 2020 16:44:17 +0100 Subject: ARM: dts: imx6-sr-som: add ethernet PHY configuration Add ethernet PHY configuration ahead of removing the quirk that configures the clocking mode for the PHY. The RGMII delay is already set correctly. Signed-off-by: Russell King Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index 6d7f6b9035bc..b06577808ff4 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -53,10 +53,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &iomuxc { -- cgit v1.2.3-70-g09d2 From dff503ab76b4af30f064d45198e9ff6b35e8655d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:54 +0200 Subject: ARM: dts: stm32: Repair PMIC configuration on AV96 The vdd PMIC buck regulator was misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also add missing Enpirion regulator for the IO voltage into the DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index aba38950f2e9..380ce148520f 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -77,6 +77,17 @@ default-state = "off"; }; }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; }; ðernet0 { @@ -166,8 +177,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; @@ -245,6 +256,7 @@ regulator-name = "vbus_otg"; interrupts = ; interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { @@ -275,7 +287,7 @@ }; &pwr_regulators { - vdd-supply = <&vdd>; + vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; }; -- cgit v1.2.3-70-g09d2 From f3aa3bc3a5841e9da07e0235c3ac386c2deba002 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:55 +0200 Subject: ARM: dts: stm32: Repair PMIC interrupt on AV96 The PMIC interrupt line is connected to PA0 on the DHCOR SoM, fix it. This makes the POWER button on the AV96 working, and also all the other PMIC interrupts. Furthermore, scrub the bogus interrupt-parent props. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 380ce148520f..010b7cdf8926 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -141,7 +141,7 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; @@ -198,7 +198,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; - interrupt-parent = <&pmic>; }; v2v8: ldo2 { @@ -206,7 +205,6 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; interrupts = ; - interrupt-parent = <&pmic>; }; vtt_ddr: ldo3 { @@ -220,7 +218,6 @@ vdd_usb: ldo4 { regulator-name = "vdd_usb"; interrupts = ; - interrupt-parent = <&pmic>; }; vdd_sd: ldo5 { @@ -228,7 +225,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; - interrupt-parent = <&pmic>; regulator-boot-on; }; @@ -237,7 +233,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; interrupts = ; - interrupt-parent = <&pmic>; regulator-enable-ramp-delay = <300000>; }; @@ -249,20 +244,17 @@ bst_out: boost { regulator-name = "bst_out"; interrupts = ; - interrupt-parent = <&pmic>; }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - interrupt-parent = <&pmic>; regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - interrupt-parent = <&pmic>; regulator-active-discharge = <1>; }; }; -- cgit v1.2.3-70-g09d2 From 7354ba62fa1e1af11ef16b84c963a23facf92070 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:56 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for ethernet RGMII on stm32mp15 Add another mux option for DWMAC RGMII, this is used on AV96 board. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index eb85ad19c926..6fce6133d644 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -213,6 +213,57 @@ }; }; + ethernet0_rgmii_pins_c: rgmii-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ -- cgit v1.2.3-70-g09d2 From 3ed6bd31ba31eea5a4cc0ce1fa89c8d9f2134eba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:57 +0200 Subject: ARM: dts: stm32: Repair ethernet operation on AV96 The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 010b7cdf8926..3c9161d0bc2c 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -92,8 +92,8 @@ ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>; -- cgit v1.2.3-70-g09d2 From 010ca9fe500bfe365860b50220ff80541c18f0e1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:58 +0200 Subject: ARM: dts: stm32: Add missing ethernet PHY reset on AV96 Add PHY reset GPIO on AV96 ethernet PHY. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 3c9161d0bc2c..4c31c8f4db7e 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -103,6 +103,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + phy0: ethernet-phy@7 { reg = <7>; }; -- cgit v1.2.3-70-g09d2 From 701f9e65e5d6418a7c051762e87ade39b9dd88dc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:45:59 +0200 Subject: ARM: dts: stm32: Add missing ethernet PHY skews on AV96 The KS9031 PHY supports configurable PHY skews to compensate for the board routing. Fill in the correct values. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 4c31c8f4db7e..8198e22d81e7 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -108,6 +108,20 @@ phy0: ethernet-phy@7 { reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; }; }; }; -- cgit v1.2.3-70-g09d2 From e88cee378719e5f7941c5c2c19a398773ad86092 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:00 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SDMMC pins on stm32mp15 Add another mux option for SDMMC1_D123DIR direction pins, SDMMC2 pins 4..7, and SDMMC3 pins PD5_SDMMC3_D2 and PD0_SDMMC3_CMD, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 99 ++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 6fce6133d644..0f9a6b1325f9 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1084,6 +1084,30 @@ }; }; + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = , /* SDMMC2_D0 */ @@ -1223,6 +1247,27 @@ }; }; + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ @@ -1277,6 +1322,60 @@ }; }; + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = ; /* SPDIF_IN1 */ -- cgit v1.2.3-70-g09d2 From e1ea5c1721ae88f6d886108064f5c679580b6fc5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:01 +0200 Subject: ARM: dts: stm32: Repair SDMMC1 operation on AV96 The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 8198e22d81e7..1219e2b35c50 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -78,6 +78,20 @@ }; }; + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + /* Enpirion EP3A8LQI U2 on the DHCOR */ vdd_io: regulator-buck-io { compatible = "regulator-fixed"; @@ -310,9 +324,9 @@ &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,sig-dir; @@ -320,6 +334,7 @@ st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 611325f681023a6f7f04f60bb2293dfbb7f2acad Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:02 +0200 Subject: ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96 Add DT node describing the eMMC attached to SDMMC2 controller of the STM32MP1 on DHCOR SoM, which is the SoM soldered on AV96. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 1219e2b35c50..811cc4aff2a5 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -338,6 +338,22 @@ status = "okay"; }; +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + &uart4 { /* On Low speed expansion header */ label = "LS-UART1"; -- cgit v1.2.3-70-g09d2 From 76045bc4571043212dbcb59b4f531c97a6ba13ac Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:03 +0200 Subject: ARM: dts: stm32: Add QSPI NOR on AV96 The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 811cc4aff2a5..4043ab6d2ae6 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -21,6 +21,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; }; chosen { @@ -314,6 +315,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; }; +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 84faf29b2d529a10cd71e609ddb237a5af8551a4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:04 +0200 Subject: ARM: dts: stm32: Add configuration EEPROM on AV96 The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 4043ab6d2ae6..3c068dc74103 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -303,6 +303,12 @@ status = "disabled"; }; }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; &iwdg2 { -- cgit v1.2.3-70-g09d2 From 7dd5cbba42c93897d43f9ad21e5e3e8069c21bfc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:05 +0200 Subject: ARM: dts: stm32: Enable WiFi on AV96 The WiFi/Bluetooth SDIO chip is attached to SDMMC3 on AV96, describe it in DT to make it available. Remove WiFi LED and turn it into a regulator, because it is a GPIO controlling the WL_REG_ON input of the WiFi chip. The LED is just an indicator connected to the same line, but not the primary function. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 38 +++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 3c068dc74103..310329a456ed 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -65,13 +65,6 @@ }; led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { label = "blue:bt"; gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; @@ -103,6 +96,17 @@ regulator-boot-on; vin-supply = <&vdd>; }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; ðernet0 { @@ -380,6 +384,26 @@ status = "okay"; }; +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + &uart4 { /* On Low speed expansion header */ label = "LS-UART1"; -- cgit v1.2.3-70-g09d2 From 077e0638fc8384c07d9647b9f73ec0d49b2f910e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:06 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for USART2 pins on stm32mp15 Add mux option for USART2 pins, this is used on AV96 board. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 0f9a6b1325f9..f4bf87bd9b7e 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1389,6 +1389,30 @@ }; }; + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = ; /* USART3_TX */ -- cgit v1.2.3-70-g09d2 From 224771c947640613a822e7c8fa0d6d7d87fbd266 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:07 +0200 Subject: ARM: dts: stm32: Enable Bluetooth on AV96 The WiFi/Bluetooth chip is attached to USART2 on AV96 as well, describe it in DT to make it available. Remove BT LED and turn it into a shutdown GPIO, because the GPIO line controls the BT_REG_ON signal. The LED is just an indicator connected to the same line, but not the primary function. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 310329a456ed..ebf34ae15185 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -21,6 +21,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + serial2 = &usart2; spi0 = &qspi; }; @@ -63,13 +64,6 @@ default-state = "off"; panic-indicator; }; - - led5 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; }; sd_switch: regulator-sd_switch { @@ -419,3 +413,18 @@ pinctrl-0 = <&uart7_pins_a>; status = "okay"; }; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit v1.2.3-70-g09d2 From 0752cc4c66712914396dd4695f5a609ddd6aecf2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:08 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for LTDC pins on stm32mp15 Add new mux option for LTDC pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 74 ++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f4bf87bd9b7e..c3a7402860af 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -662,6 +662,80 @@ }; }; + ltdc_pins_d: ltdc-3 { + pins1 { + pinmux = ; /* LCD_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ltdc_sleep_pins_d: ltdc-sleep-3 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ -- cgit v1.2.3-70-g09d2 From 64e86752d7df5ac8dc83620607da850a20c47a2c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:09 +0200 Subject: ARM: dts: stm32: Add bindings for HDMI video on AV96 Fill in the HDMI video pipeline from AV96 into the DT. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 79 +++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index ebf34ae15185..85116e192b61 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -25,10 +25,28 @@ spi0 = &qspi; }; + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x40000000>; @@ -302,6 +320,50 @@ }; }; + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; + reg-names = "main", "cec", "edid", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + eeprom@53 { compatible = "atmel,24c02"; reg = <0x53>; @@ -314,6 +376,23 @@ status = "okay"; }; +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7513_in>; + }; + }; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; -- cgit v1.2.3-70-g09d2 From dcf185ca8175b3324f8616f848c94d4bf554b76b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:10 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SAI2 pins on stm32mp15 Add new mux option for SAI2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index c3a7402860af..aeddcaadb829 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1028,6 +1028,25 @@ }; }; + sai2a_pins_c: sai2a-4 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_c: sai2a-5 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + }; + }; + sai2b_pins_a: sai2b-0 { pins1 { pinmux = , /* SAI2_SCK_B */ @@ -1065,6 +1084,19 @@ }; }; + sai2b_pins_c: sai2a-4 { + pins1 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_c: sai2a-sleep-5 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + sai4a_pins_a: sai4a-0 { pins { pinmux = ; /* SAI4_SD_A */ -- cgit v1.2.3-70-g09d2 From e027da342772cb31b1e7f67666465c0535c5acb3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:11 +0200 Subject: ARM: dts: stm32: Add bindings for audio on AV96 Fill in the bindings for HDMI audio on AV96, this permits audio playback via attached HDMI device if such device supports it. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 85116e192b61..f04ad8dc6fc6 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -98,6 +98,13 @@ <2900000 0x0>; }; + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + /* Enpirion EP3A8LQI U2 on the DHCOR */ vdd_io: regulator-buck-io { compatible = "regulator-fixed"; @@ -361,6 +368,13 @@ remote-endpoint = <&hdmi_con>; }; }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; }; }; @@ -425,6 +439,31 @@ status = "okay"; }; +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; -- cgit v1.2.3-70-g09d2 From e74ef3823b4db49ae44966ab710d6c6b298ec0b4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:12 +0200 Subject: ARM: dts: stm32: Add bindings for USB on AV96 Fill in the bindings for USB host and gadget on AV96. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index f04ad8dc6fc6..a1b3baf7564d 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -546,3 +546,34 @@ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; }; }; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; -- cgit v1.2.3-70-g09d2 From 878b0ba5c4d299a6cf5438e6b9b9950f875a9819 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 22 Apr 2020 12:46:13 +0200 Subject: ARM: dts: stm32: Rename LEDs to match silkscreen on AV96 The LED labels do not match the silkscreen on the board, fix it. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index a1b3baf7564d..271f38acfeb9 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -55,21 +55,21 @@ led { compatible = "gpio-leds"; led1 { - label = "green:user1"; + label = "green:user0"; gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led2 { - label = "green:user2"; + label = "green:user1"; gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; led3 { - label = "green:user3"; + label = "green:user2"; gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; default-state = "off"; -- cgit v1.2.3-70-g09d2 From 61365ca7b24f1cb106a4c619c94610862bbec778 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 15 Apr 2020 14:14:49 +0200 Subject: backlight: l4f00242t03: Convert to GPIO descriptors This converts the l4f00242t03 backlight driver to use GPIO descriptors and switches the two Freescale i.MX boards over to passing descriptors instead of global GPIO numbers. We use the typical names "enable" and "reset" as found in the device tree bindings for panel GPIOs. This saves a lot of code in the driver and makes it possible to get rid of the platform data header altogether. Signed-off-by: Linus Walleij Reviewed-by: Daniel Thompson Acked-by: Shawn Guo Signed-off-by: Lee Jones --- arch/arm/mach-imx/mach-mx27_3ds.c | 21 +++++++++++----- arch/arm/mach-imx/mach-mx31_3ds.c | 24 +++++++++++++++---- drivers/video/backlight/l4f00242t03.c | 45 ++++++++++++++--------------------- include/linux/spi/l4f00242t03.h | 17 ------------- 4 files changed, 52 insertions(+), 55 deletions(-) delete mode 100644 include/linux/spi/l4f00242t03.h (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 7b8325fb5b41..1da5f07952ac 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -20,8 +21,6 @@ #include #include #include -#include - #include #include @@ -351,9 +350,19 @@ static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { }; /* LCD */ -static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { - .reset_gpio = LCD_RESET, - .data_enable_gpio = LCD_ENABLE, +static struct gpiod_lookup_table mx27_3ds_lcd_gpiod_table = { + .dev_id = "spi0.0", /* Bus 0 chipselect 0 */ + .table = { + /* + * The i.MX27 has the i.MX21 GPIO controller, the GPIOs + * numbered IMX_GPIO_NR(1, 3) and IMX_GPIO_NR(1, 31) + * are in "bank 1" which is subtracted by one in the macro + * so these are actually bank 0 on "imx21-gpio.0". + */ + GPIO_LOOKUP("imx21-gpio.0", 3, "reset", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("imx21-gpio.0", 31, "enable", GPIO_ACTIVE_HIGH), + { }, + }, }; static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { @@ -370,7 +379,6 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { .max_speed_hz = 5000000, .bus_num = 0, .chip_select = 0, /* SS0 */ - .platform_data = &mx27_3ds_lcd_pdata, }, }; @@ -416,6 +424,7 @@ static void __init mx27pdk_late_init(void) if (!otg_mode_host) imx27_add_fsl_usb2_udc(&otg_device_pdata); + gpiod_add_lookup_table(&mx27_3ds_lcd_gpiod_table); mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT); spi_register_board_info(mx27_3ds_spi_devs, ARRAY_SIZE(mx27_3ds_spi_devs)); diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 716d2ad51103..e81386190479 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -10,10 +10,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -160,9 +160,23 @@ static struct mx3fb_platform_data mx3fb_pdata __initdata = { }; /* LCD */ -static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { - .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), - .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), +static struct gpiod_lookup_table mx31_3ds_lcd_gpiod_table = { + .dev_id = "spi0.2", /* Bus 0 chipselect 2 */ + .table = { + /* + * "reset" has IOMUX_TO_GPIO(IOMUX_PIN(88, 28)). + * The macro only shifts 88 to bits 9..16 and then + * mask it and shift it back. The GPIO number is 88. + * 88 is 2*32+24 + */ + GPIO_LOOKUP("imx31-gpio.2", 24, "reset", GPIO_ACTIVE_HIGH), + /* + * Same reasoning as above for + * IOMUX_TO_GPIO(IOMUX_PIN(89, 27), pin 89 is 2*32+25. + */ + GPIO_LOOKUP("imx31-gpio.2", 25, "enable", GPIO_ACTIVE_HIGH), + { }, + }, }; /* @@ -387,7 +401,6 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { .max_speed_hz = 5000000, .bus_num = 0, .chip_select = 2, /* SS2 */ - .platform_data = &mx31_3ds_l4f00242t03_pdata, }, }; @@ -566,6 +579,7 @@ static void __init mx31_3ds_init(void) static void __init mx31_3ds_late(void) { + gpiod_add_lookup_table(&mx31_3ds_lcd_gpiod_table); mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); spi_register_board_info(mx31_3ds_spi_devs, ARRAY_SIZE(mx31_3ds_spi_devs)); diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c index 8554b4aa980c..46f97d1c3d21 100644 --- a/drivers/video/backlight/l4f00242t03.c +++ b/drivers/video/backlight/l4f00242t03.c @@ -14,13 +14,11 @@ #include #include #include -#include +#include #include #include #include - #include -#include struct l4f00242t03_priv { struct spi_device *spi; @@ -28,16 +26,18 @@ struct l4f00242t03_priv { int lcd_state; struct regulator *io_reg; struct regulator *core_reg; + struct gpio_desc *reset; + struct gpio_desc *enable; }; -static void l4f00242t03_reset(unsigned int gpio) +static void l4f00242t03_reset(struct gpio_desc *gpiod) { pr_debug("l4f00242t03_reset.\n"); - gpio_set_value(gpio, 1); + gpiod_set_value(gpiod, 1); mdelay(100); - gpio_set_value(gpio, 0); + gpiod_set_value(gpiod, 0); mdelay(10); /* tRES >= 100us */ - gpio_set_value(gpio, 1); + gpiod_set_value(gpiod, 1); mdelay(20); } @@ -45,7 +45,6 @@ static void l4f00242t03_reset(unsigned int gpio) static void l4f00242t03_lcd_init(struct spi_device *spi) { - struct l4f00242t03_pdata *pdata = dev_get_platdata(&spi->dev); struct l4f00242t03_priv *priv = spi_get_drvdata(spi); const u16 cmd[] = { 0x36, param(0), 0x3A, param(0x60) }; int ret; @@ -76,21 +75,20 @@ static void l4f00242t03_lcd_init(struct spi_device *spi) return; } - l4f00242t03_reset(pdata->reset_gpio); + l4f00242t03_reset(priv->reset); - gpio_set_value(pdata->data_enable_gpio, 1); + gpiod_set_value(priv->enable, 1); msleep(60); spi_write(spi, (const u8 *)cmd, ARRAY_SIZE(cmd) * sizeof(u16)); } static void l4f00242t03_lcd_powerdown(struct spi_device *spi) { - struct l4f00242t03_pdata *pdata = dev_get_platdata(&spi->dev); struct l4f00242t03_priv *priv = spi_get_drvdata(spi); dev_dbg(&spi->dev, "Powering down LCD\n"); - gpio_set_value(pdata->data_enable_gpio, 0); + gpiod_set_value(priv->enable, 0); regulator_disable(priv->io_reg); regulator_disable(priv->core_reg); @@ -168,13 +166,6 @@ static struct lcd_ops l4f_ops = { static int l4f00242t03_probe(struct spi_device *spi) { struct l4f00242t03_priv *priv; - struct l4f00242t03_pdata *pdata = dev_get_platdata(&spi->dev); - int ret; - - if (pdata == NULL) { - dev_err(&spi->dev, "Uninitialized platform data.\n"); - return -EINVAL; - } priv = devm_kzalloc(&spi->dev, sizeof(struct l4f00242t03_priv), GFP_KERNEL); @@ -187,21 +178,21 @@ static int l4f00242t03_probe(struct spi_device *spi) priv->spi = spi; - ret = devm_gpio_request_one(&spi->dev, pdata->reset_gpio, - GPIOF_OUT_INIT_HIGH, "lcd l4f00242t03 reset"); - if (ret) { + priv->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset)) { dev_err(&spi->dev, "Unable to get the lcd l4f00242t03 reset gpio.\n"); - return ret; + return PTR_ERR(priv->reset); } + gpiod_set_consumer_name(priv->reset, "lcd l4f00242t03 reset"); - ret = devm_gpio_request_one(&spi->dev, pdata->data_enable_gpio, - GPIOF_OUT_INIT_LOW, "lcd l4f00242t03 data enable"); - if (ret) { + priv->enable = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(priv->enable)) { dev_err(&spi->dev, "Unable to get the lcd l4f00242t03 data en gpio.\n"); - return ret; + return PTR_ERR(priv->enable); } + gpiod_set_consumer_name(priv->enable, "lcd l4f00242t03 data enable"); priv->io_reg = devm_regulator_get(&spi->dev, "vdd"); if (IS_ERR(priv->io_reg)) { diff --git a/include/linux/spi/l4f00242t03.h b/include/linux/spi/l4f00242t03.h deleted file mode 100644 index 831a5de7a0e2..000000000000 --- a/include/linux/spi/l4f00242t03.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * l4f00242t03.h -- Platform glue for Epson L4F00242T03 LCD - * - * Copyright (c) 2009 Alberto Panizzo - * Based on Marek Vasut work in lms283gf05.h -*/ - -#ifndef _INCLUDE_LINUX_SPI_L4F00242T03_H_ -#define _INCLUDE_LINUX_SPI_L4F00242T03_H_ - -struct l4f00242t03_pdata { - unsigned int reset_gpio; - unsigned int data_enable_gpio; -}; - -#endif /* _INCLUDE_LINUX_SPI_L4F00242T03_H_ */ -- cgit v1.2.3-70-g09d2 From 7ae4a78daacf240a8247cde73337dc4b26d253da Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 22 Apr 2020 14:08:53 +0100 Subject: ARM: 8969/1: decompressor: simplify libfdt builds Copying source files during the build time may not end up with as clean code as expected. lib/fdt*.c simply wrap scripts/dtc/libfdt/fdt*.c, and it works nicely. Let's follow this approach for the arm decompressor, too. Add four wrappers, arch/arm/boot/compressed/fdt*.c and remove the Makefile messes. Another nice thing is we no longer need to maintain the own libfdt_env.h because the decompressor can include . There is a subtle problem when generated files are turned into check-in files. When you are doing a rebuild of an existing object tree with O= option, there exists stale "shipped" copies that the old Makefile implementation created. The build system ends up with compiling the stale generated files because Make searches for prerequisites in the current directory, i.e. $(objtree) first, and then the directory listed in VPATH, i.e. $(srctree). To mend this issue, I added the following code: ifdef building_out_of_srctree $(shell rm -f $(addprefix $(obj)/, fdt_rw.c fdt_ro.c fdt_wip.c fdt.c)) endif This will need to stay for a while because "git bisect" crossing this commit, otherwise, would result in a build error. Signed-off-by: Masahiro Yamada Signed-off-by: Russell King --- arch/arm/boot/compressed/.gitignore | 9 -------- arch/arm/boot/compressed/Makefile | 38 +++++++++++++-------------------- arch/arm/boot/compressed/atags_to_fdt.c | 1 + arch/arm/boot/compressed/fdt.c | 2 ++ arch/arm/boot/compressed/fdt_ro.c | 2 ++ arch/arm/boot/compressed/fdt_rw.c | 2 ++ arch/arm/boot/compressed/fdt_wip.c | 2 ++ arch/arm/boot/compressed/libfdt_env.h | 24 --------------------- 8 files changed, 24 insertions(+), 56 deletions(-) create mode 100644 arch/arm/boot/compressed/fdt.c create mode 100644 arch/arm/boot/compressed/fdt_ro.c create mode 100644 arch/arm/boot/compressed/fdt_rw.c create mode 100644 arch/arm/boot/compressed/fdt_wip.c delete mode 100644 arch/arm/boot/compressed/libfdt_env.h (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore index db05c6ef3e31..60606b0f378d 100644 --- a/arch/arm/boot/compressed/.gitignore +++ b/arch/arm/boot/compressed/.gitignore @@ -7,12 +7,3 @@ hyp-stub.S piggy_data vmlinux vmlinux.lds - -# borrowed libfdt files -fdt.c -fdt.h -fdt_ro.c -fdt_rw.c -fdt_wip.c -libfdt.h -libfdt_internal.h diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 9c11e7490292..00602a6fba04 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -76,29 +76,30 @@ compress-$(CONFIG_KERNEL_LZMA) = lzma compress-$(CONFIG_KERNEL_XZ) = xzkern compress-$(CONFIG_KERNEL_LZ4) = lz4 -# Borrowed libfdt files for the ATAG compatibility mode - -libfdt := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c -libfdt_hdrs := fdt.h libfdt.h libfdt_internal.h - -libfdt_objs := $(addsuffix .o, $(basename $(libfdt))) - -$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/% - $(call cmd,shipped) - -$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \ - $(addprefix $(obj)/,$(libfdt_hdrs)) +libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y) OBJS += $(libfdt_objs) atags_to_fdt.o endif +# -fstack-protector-strong triggers protection checks in this code, +# but it is being used too early to link to meaningful stack_chk logic. +nossp-flags-$(CONFIG_CC_HAS_STACKPROTECTOR_NONE) := -fno-stack-protector +$(foreach o, $(libfdt_objs) atags_to_fdt.o, \ + $(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt $(nossp-flags-y))) + +# These were previously generated C files. When you are building the kernel +# with O=, make sure to remove the stale files in the output tree. Otherwise, +# the build system wrongly compiles the stale ones. +ifdef building_out_of_srctree +$(shell rm -f $(addprefix $(obj)/, fdt_rw.c fdt_ro.c fdt_wip.c fdt.c)) +endif + targets := vmlinux vmlinux.lds piggy_data piggy.o \ lib1funcs.o ashldi3.o bswapsdi2.o \ head.o $(OBJS) -clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S \ - $(libfdt) $(libfdt_hdrs) hyp-stub.S +clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S hyp-stub.S KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING @@ -107,15 +108,6 @@ ORIG_CFLAGS := $(KBUILD_CFLAGS) KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) endif -# -fstack-protector-strong triggers protection checks in this code, -# but it is being used too early to link to meaningful stack_chk logic. -nossp-flags-$(CONFIG_CC_HAS_STACKPROTECTOR_NONE) := -fno-stack-protector -CFLAGS_atags_to_fdt.o := $(nossp-flags-y) -CFLAGS_fdt.o := $(nossp-flags-y) -CFLAGS_fdt_ro.o := $(nossp-flags-y) -CFLAGS_fdt_rw.o := $(nossp-flags-y) -CFLAGS_fdt_wip.o := $(nossp-flags-y) - ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \ -I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN) asflags-y := -DZIMAGE diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index 64c49747f8a3..8452753efebe 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include diff --git a/arch/arm/boot/compressed/fdt.c b/arch/arm/boot/compressed/fdt.c new file mode 100644 index 000000000000..f8ea7a201ab1 --- /dev/null +++ b/arch/arm/boot/compressed/fdt.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/fdt.c" diff --git a/arch/arm/boot/compressed/fdt_ro.c b/arch/arm/boot/compressed/fdt_ro.c new file mode 100644 index 000000000000..93970a4ad5ae --- /dev/null +++ b/arch/arm/boot/compressed/fdt_ro.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/fdt_ro.c" diff --git a/arch/arm/boot/compressed/fdt_rw.c b/arch/arm/boot/compressed/fdt_rw.c new file mode 100644 index 000000000000..f7c6b8b7e01c --- /dev/null +++ b/arch/arm/boot/compressed/fdt_rw.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/fdt_rw.c" diff --git a/arch/arm/boot/compressed/fdt_wip.c b/arch/arm/boot/compressed/fdt_wip.c new file mode 100644 index 000000000000..048d2c7a088d --- /dev/null +++ b/arch/arm/boot/compressed/fdt_wip.c @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "../../../../lib/fdt_wip.c" diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h deleted file mode 100644 index 6a0f1f524466..000000000000 --- a/arch/arm/boot/compressed/libfdt_env.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ARM_LIBFDT_ENV_H -#define _ARM_LIBFDT_ENV_H - -#include -#include -#include -#include - -#define INT32_MAX S32_MAX -#define UINT32_MAX U32_MAX - -typedef __be16 fdt16_t; -typedef __be32 fdt32_t; -typedef __be64 fdt64_t; - -#define fdt16_to_cpu(x) be16_to_cpu(x) -#define cpu_to_fdt16(x) cpu_to_be16(x) -#define fdt32_to_cpu(x) be32_to_cpu(x) -#define cpu_to_fdt32(x) cpu_to_be32(x) -#define fdt64_to_cpu(x) be64_to_cpu(x) -#define cpu_to_fdt64(x) cpu_to_be64(x) - -#endif -- cgit v1.2.3-70-g09d2 From a780e485b5768e78aef087502499714901b68cc4 Mon Sep 17 00:00:00 2001 From: Jian Cai Date: Wed, 29 Apr 2020 01:20:11 +0100 Subject: ARM: 8971/1: replace the sole use of a symbol with its definition ALT_UP_B macro sets symbol up_b_offset via .equ to an expression involving another symbol. The macro gets expanded twice when arch/arm/kernel/sleep.S is assembled, creating a scenario where up_b_offset is set to another expression involving symbols while its current value is based on symbols. LLVM integrated assembler does not allow such cases, and based on the documentation of binutils, "Values that are based on expressions involving other symbols are allowed, but some targets may restrict this to only being done once per assembly", so it may be better to avoid such cases as it is not clearly stated which targets should support or disallow them. The fix in this case is simple, as up_b_offset has only one use, so we can replace the use with the definition and get rid of up_b_offset. Link:https://github.com/ClangBuiltLinux/linux/issues/920 Reviewed-by: Stefan Agner Reviewed-by: Nick Desaulniers Signed-off-by: Jian Cai Signed-off-by: Russell King --- arch/arm/include/asm/assembler.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 99929122dad7..adee13126c62 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -269,10 +269,9 @@ .endif ;\ .popsection #define ALT_UP_B(label) \ - .equ up_b_offset, label - 9998b ;\ .pushsection ".alt.smp.init", "a" ;\ .long 9998b ;\ - W(b) . + up_b_offset ;\ + W(b) . + (label - 9998b) ;\ .popsection #else #define ALT_SMP(instr...) -- cgit v1.2.3-70-g09d2 From 288d3f142bd64abf1f99c6e06109c67811ab94a7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 14 Apr 2020 10:57:18 +0200 Subject: ARM: defconfig: u8500: Enable new drivers for ux500 The new device tree for samsung-skomer and the HREF520 devicetree enables some additional drivers that are not yet selected in the u8500_defconfig: - The GPIO-based I2C bus master driver for some peripherals that do not use the I2C hardware master. - The Novatek NT35510 driver for the Skomer panel. - The Sony ACX424AKP driver for the HREF520 panel. - The GPIO-based backlight driver for Skomer. - The BMA180 driver for the BMA254 accelerometer found in the Skomer. - The new GP2AP002 driver for the GP2AP002S00F proximimty sensor found in the Skomer and Golden devices. Cc: Stephan Gerhold Signed-off-by: Linus Walleij --- arch/arm/configs/u8500_defconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 0fd2726cf1c1..28dd7cf56048 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -72,7 +72,7 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y -CONFIG_I2C_MUX=y +CONFIG_I2C_GPIO=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y @@ -86,11 +86,14 @@ CONFIG_MFD_TC3589X=y CONFIG_REGULATOR_AB8500=y CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y +CONFIG_DRM_PANEL_NOVATEK_NT35510=y CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y +CONFIG_DRM_PANEL_SONY_ACX424AKP=y CONFIG_DRM_LIMA=y CONFIG_DRM_MCDE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_GPIO=y CONFIG_LOGO=y CONFIG_SOUND=y CONFIG_SND=y @@ -121,10 +124,12 @@ CONFIG_HWSPINLOCK=y CONFIG_HSEM_U8500=y CONFIG_IIO=y CONFIG_IIO_SW_TRIGGER=y +CONFIG_BMA180=y CONFIG_IIO_ST_ACCEL_3AXIS=y CONFIG_IIO_ST_GYRO_3AXIS=y CONFIG_INV_MPU6050_I2C=y CONFIG_BH1780=y +CONFIG_GP2AP002=y CONFIG_AK8974=y CONFIG_IIO_ST_MAGN_3AXIS=y CONFIG_IIO_HRTIMER_TRIGGER=y -- cgit v1.2.3-70-g09d2 From 9c8c0f70ec6fdac2398632c723c48277be09b7c0 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 30 Apr 2020 11:07:07 +0200 Subject: ARM: dts: qcom: ipq4019: add MDIO node This patch adds the necessary MDIO interface node to the Qualcomm IPQ4019 DTSI. Built-in QCA8337N switch is managed using it, and since we have a driver for it lets add it. Signed-off-by: Christian Lamparter Signed-off-by: Robert Marko Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Cc: Luka Perkov Signed-off-by: David S. Miller --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bfa9ce4c6e69..b9839f86e703 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -576,5 +576,33 @@ "legacy"; status = "disabled"; }; + + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + }; + }; }; }; -- cgit v1.2.3-70-g09d2 From 07569acbef1d00c48dc4db4f140aab2dbb58df0b Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 3 Apr 2020 10:43:03 +0900 Subject: ARM: dts: uniphier: Add XDMAC node Add external DMA controller support implemented in UniPhier SoCs. This supports for Pro4, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pro4.dtsi | 8 ++++++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 8 ++++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 1c866f0306fc..45b73f948add 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -426,6 +426,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 8f1ae0957f5f..4a388d16633a 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -408,6 +408,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 2f2a24994c69..e36f0df50fd8 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -508,6 +508,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; -- cgit v1.2.3-70-g09d2 From 94a8c115cc5ed8e7afff3bcda243210276a33927 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 3 Apr 2020 10:43:05 +0900 Subject: ARM: dts: uniphier: Add ethernet aliases Add an 'aliases' property for ethernet device. U-Boot performs a fix-up of the MAC address and will overwrite the values from the Linux devicetree for aliased ethernet device. The MAC address can be inherited from U-Boot by adding aliases of ethernet devices. Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld6b-ref.dts | 1 + arch/arm/boot/dts/uniphier-pro4-ace.dts | 1 + arch/arm/boot/dts/uniphier-pro4-ref.dts | 1 + arch/arm/boot/dts/uniphier-pro4-sanji.dts | 1 + arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 1 + arch/arm/boot/dts/uniphier-pxs2-vodka.dts | 1 + 6 files changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts index 60994b6e8b99..079cadc11e6c 100644 --- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -29,6 +29,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts index 92cc48dd86d0..64246fad325c 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ace.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -26,6 +26,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts index 854f2eba3e72..181442c48532 100644 --- a/arch/arm/boot/dts/uniphier-pro4-ref.dts +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts index dda1a2f214a8..5396556dee58 100644 --- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -25,6 +25,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts index e27fd4f2a569..8e9ac579aa9a 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -26,6 +26,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts index 23fe42b7408b..8eacc7bdecb7 100644 --- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -24,6 +24,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { -- cgit v1.2.3-70-g09d2 From 137a1cecb89a024f8c92d71e07e73b14fc4d4161 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 22 Apr 2020 23:36:32 +0900 Subject: ARM: dts: uniphier: add #address-cells and #size-cells to SPI nodes Documentation/devicetree/bindings/spi/spi-uniphier.txt requires #address-cells and #size-cells, but they are missing in actual DT files. Also, 'make ARCH=arm dtbs_check' is really noisy. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4.dtsi | 2 ++ arch/arm/boot/dts/uniphier-pro4.dtsi | 2 ++ arch/arm/boot/dts/uniphier-pro5.dtsi | 4 ++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 4 ++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 2 ++ 5 files changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 06e7400d2940..b52957ccda0d 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 45b73f948add..a53b73ee93e9 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -75,6 +75,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 4a388d16633a..feadb4a378eb 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -160,6 +160,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -171,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index e36f0df50fd8..b0b15c97306b 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -173,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -184,6 +186,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 09992163e1f4..96a766deb8d1 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; -- cgit v1.2.3-70-g09d2 From 96866b1a1d32318b6bbc321a762bf79db1f4686e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 29 Apr 2020 22:56:41 +0100 Subject: ARM: debug-ll: Add support for r8a7742 Enable low-level debugging support for RZ/G1H (R8A7742). RZ/G1H uses SCIFA2 for the debug console. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588197415-13747-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/Kconfig.debug | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index f46e18a77645..26a158e35e2c 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -976,6 +976,13 @@ choice Say Y here if you want kernel low-level debugging support via SCIF4 on Renesas RZ/G1E (R8A7745). + config DEBUG_RCAR_GEN2_SCIFA2 + bool "Kernel low-level debugging messages via SCIFA2 on R8A7742" + depends on ARCH_R8A7742 + help + Say Y here if you want kernel low-level debugging support + via SCIFA2 on Renesas RZ/G1H (R8A7742). + config DEBUG_RMOBILE_SCIFA0 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4" depends on ARCH_R8A73A4 @@ -1577,6 +1584,7 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2 default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4 + default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIFA2 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 @@ -1696,6 +1704,7 @@ config DEBUG_UART_PHYS default 0xe4007000 if DEBUG_HIP04_UART default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1 + default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2 default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4 default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2 default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0 @@ -1737,6 +1746,7 @@ config DEBUG_UART_PHYS DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \ DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \ + DEBUG_RCAR_GEN2_SCIFA2 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ DEBUG_S3C64XX_UART || \ -- cgit v1.2.3-70-g09d2 From 1a90c5ba48c43aeaeccebcd3e092888b670a4bab Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 29 Apr 2020 22:56:39 +0100 Subject: ARM: shmobile: defconfig: Enable r8a7742 SoC Enable recently added r8a7742 (RZ/G1H) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588197415-13747-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index ef3b9d0d6e50..9cf3143025e1 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -179,6 +179,7 @@ CONFIG_ARCH_R7S72100=y CONFIG_ARCH_R7S9210=y CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A7742=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7744=y CONFIG_ARCH_R8A7745=y -- cgit v1.2.3-70-g09d2 From 44b6141ebe936808fc59b386e3e259bef6c9bba6 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 29 Apr 2020 22:56:40 +0100 Subject: ARM: multi_v7_defconfig: Enable r8a7742 SoC Enable recently added r8a7742 (RZ/G1H) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588197415-13747-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f8e45351c3f9..e94699f344d4 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -979,6 +979,7 @@ CONFIG_ARCH_R7S72100=y CONFIG_ARCH_R7S9210=y CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A7742=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7744=y CONFIG_ARCH_R8A7745=y -- cgit v1.2.3-70-g09d2 From 6a52e305f2ac66eed32701e8717c1066d2a3c8ff Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:02 -0700 Subject: ARM: dts: s5pv210: Add helper define for sleep gpio config To simplify writing of sleep gpio configs, add a common helper similar to what is present for other Samsung CPUs. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 7f0c9d447871..609f323d0805 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -18,6 +18,13 @@ #include +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + &pinctrl0 { gpa0: gpa0 { gpio-controller; -- cgit v1.2.3-70-g09d2 From d7d155a7693fcb5e53f2db723cc6586830575a10 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:03 -0700 Subject: ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4G In order to minimize leakage current during sleep, set a config for sleep GPIOs. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-fascinate4g.dts | 243 ++++++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 07a8d9bbe5b8..65f589e2b72a 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -36,3 +36,246 @@ }; }; }; + +&pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + /* Based on vendor kernel v2.6.35.7 */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, PREV, NONE); + PIN_SLP(gpa0-5, PREV, NONE); + PIN_SLP(gpa0-6, PREV, NONE); + PIN_SLP(gpa0-7, PREV, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, DOWN); + PIN_SLP(gpd1-3, INPUT, DOWN); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, INPUT, DOWN); + PIN_SLP(gpg0-1, INPUT, DOWN); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, DOWN); + PIN_SLP(gpg0-4, INPUT, DOWN); + PIN_SLP(gpg0-5, INPUT, DOWN); + PIN_SLP(gpg0-6, INPUT, DOWN); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, PREV, UP); + PIN_SLP(gpg3-1, PREV, UP); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, OUT1, NONE); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, DOWN); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, INPUT, DOWN); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, OUT1, NONE); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT0, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; +}; -- cgit v1.2.3-70-g09d2 From e4e5f695085fe6d1b42565d1ebbeefdd64027e4d Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:04 -0700 Subject: ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy S In order to minimize leakage current during sleep, set a config for sleep GPIOs. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-galaxys.dts | 241 ++++++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index cf161bbfbacf..9bf4a5b95b74 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -52,12 +52,253 @@ }; &pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; + + /* Based on CyanogenMod 3.0.101 kernel */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, OUT0, NONE); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, OUT1, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, NONE); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, NONE); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, OUT0, NONE); + PIN_SLP(gpg0-1, INPUT, NONE); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, NONE); + PIN_SLP(gpg0-4, INPUT, NONE); + PIN_SLP(gpg0-5, INPUT, NONE); + PIN_SLP(gpg0-6, INPUT, NONE); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, OUT1, NONE); + PIN_SLP(gpg3-1, OUT0, NONE); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, UP); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, OUT1, NONE); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, INPUT, DOWN); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT1, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; }; &sdhci0 { -- cgit v1.2.3-70-g09d2 From cf48db69bdfad2930b95fd51d64444e5a7b469ae Mon Sep 17 00:00:00 2001 From: Luke Nelson Date: Thu, 30 Apr 2020 19:02:09 -0700 Subject: bpf, arm: Optimize ALU64 ARSH X using orrpl conditional instruction This patch optimizes the code generated by emit_a32_arsh_r64, which handles the BPF_ALU64 BPF_ARSH BPF_X instruction. The original code uses a conditional B followed by an unconditional ORR. The optimization saves one instruction by removing the B instruction and using a conditional ORR (with an inverted condition). Example of the code generated for BPF_ALU64_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1), before optimization: 34: rsb ip, r2, #32 38: subs r9, r2, #32 3c: lsr lr, r0, r2 40: orr lr, lr, r1, lsl ip 44: bmi 0x4c 48: orr lr, lr, r1, asr r9 4c: asr ip, r1, r2 50: mov r0, lr 54: mov r1, ip and after optimization: 34: rsb ip, r2, #32 38: subs r9, r2, #32 3c: lsr lr, r0, r2 40: orr lr, lr, r1, lsl ip 44: orrpl lr, lr, r1, asr r9 48: asr ip, r1, r2 4c: mov r0, lr 50: mov r1, ip Tested on QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20200501020210.32294-2-luke.r.nels@gmail.com --- arch/arm/net/bpf_jit_32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index bf85d6db4931..48b89211ee5c 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -860,8 +860,8 @@ static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[], emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx); emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx); emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx); - _emit(ARM_COND_MI, ARM_B(0), ctx); - emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx); + _emit(ARM_COND_PL, + ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx); emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx); arm_bpf_put_reg32(dst_lo, ARM_LR, ctx); -- cgit v1.2.3-70-g09d2 From c648c9c7429e979ca081359f39b6902aed92d490 Mon Sep 17 00:00:00 2001 From: Luke Nelson Date: Thu, 30 Apr 2020 19:02:10 -0700 Subject: bpf, arm: Optimize ALU ARSH K using asr immediate instruction This patch adds an optimization that uses the asr immediate instruction for BPF_ALU BPF_ARSH BPF_K, rather than loading the immediate to a temporary register. This is similar to existing code for handling BPF_ALU BPF_{LSH,RSH} BPF_K. This optimization saves two instructions and is more consistent with LSH and RSH. Example of the code generated for BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5) before the optimization: 2c: mov r8, #5 30: mov r9, #0 34: asr r0, r0, r8 and after optimization: 2c: asr r0, r0, #5 Tested on QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang Signed-off-by: Xi Wang Signed-off-by: Luke Nelson Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20200501020210.32294-3-luke.r.nels@gmail.com --- arch/arm/net/bpf_jit_32.c | 10 +++++++--- arch/arm/net/bpf_jit_32.h | 3 +++ 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c index 48b89211ee5c..0207b6ea6e8a 100644 --- a/arch/arm/net/bpf_jit_32.c +++ b/arch/arm/net/bpf_jit_32.c @@ -795,6 +795,9 @@ static inline void emit_a32_alu_i(const s8 dst, const u32 val, case BPF_RSH: emit(ARM_LSR_I(rd, rd, val), ctx); break; + case BPF_ARSH: + emit(ARM_ASR_I(rd, rd, val), ctx); + break; case BPF_NEG: emit(ARM_RSB_I(rd, rd, val), ctx); break; @@ -1408,7 +1411,6 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) case BPF_ALU | BPF_MUL | BPF_X: case BPF_ALU | BPF_LSH | BPF_X: case BPF_ALU | BPF_RSH | BPF_X: - case BPF_ALU | BPF_ARSH | BPF_K: case BPF_ALU | BPF_ARSH | BPF_X: case BPF_ALU64 | BPF_ADD | BPF_K: case BPF_ALU64 | BPF_ADD | BPF_X: @@ -1465,10 +1467,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) case BPF_ALU64 | BPF_MOD | BPF_K: case BPF_ALU64 | BPF_MOD | BPF_X: goto notyet; - /* dst = dst >> imm */ /* dst = dst << imm */ - case BPF_ALU | BPF_RSH | BPF_K: + /* dst = dst >> imm */ + /* dst = dst >> imm (signed) */ case BPF_ALU | BPF_LSH | BPF_K: + case BPF_ALU | BPF_RSH | BPF_K: + case BPF_ALU | BPF_ARSH | BPF_K: if (unlikely(imm > 31)) return -EINVAL; if (imm) diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h index fb67cbc589e0..e0b593a1498d 100644 --- a/arch/arm/net/bpf_jit_32.h +++ b/arch/arm/net/bpf_jit_32.h @@ -94,6 +94,9 @@ #define ARM_INST_LSR_I 0x01a00020 #define ARM_INST_LSR_R 0x01a00030 +#define ARM_INST_ASR_I 0x01a00040 +#define ARM_INST_ASR_R 0x01a00050 + #define ARM_INST_MOV_R 0x01a00000 #define ARM_INST_MOVS_R 0x01b00000 #define ARM_INST_MOV_I 0x03a00000 -- cgit v1.2.3-70-g09d2 From 386c7b372dd8ba9c6706084ade089a1f90551017 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:19 -0700 Subject: ARM: dts: s5pv210: Correct gpi pinctrl node name The node name was gpgi, but the pinctrl driver was registering the pins as just gpi and the "samsung,pins" i2s0 pinctrl entries refer to gpi. The public S5PC110 datasheet also refers to these pins as just gpi, so let's make sure everything is in sync and rename the node to gpi. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 609f323d0805..5e8b66281f01 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -202,7 +202,7 @@ #interrupt-cells = <2>; }; - gpgi: gpgi { + gpi: gpi { gpio-controller; #gpio-cells = <2>; }; -- cgit v1.2.3-70-g09d2 From 869d42e6eba821905e1a0950623aadafe1a6e6d3 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:05 -0700 Subject: ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on Aries SDHCI1 is connected to a BCM4329 WiFi/BT chip which requires power to be kept over suspend. As the surrounding hardware supports this, mark it as such. This fixes WiFi after a suspend/resume cycle. Fixes: 170642468a51 ("ARM: dts: s5pv210: Add initial DTS for Samsung Aries based phones") Cc: Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 8ff70b856334..d419b77201f7 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -454,6 +454,7 @@ pinctrl-names = "default"; cap-sd-highspeed; cap-mmc-highspeed; + keep-power-in-suspend; mmc-pwrseq = <&wifi_pwrseq>; non-removable; -- cgit v1.2.3-70-g09d2 From 09b39f60ee09aca4bebd2f53258814d755628529 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:06 -0700 Subject: ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for Aries The bitbanged GPIO I2C adapters have external pull-ups attached so the internal pulls should be disabled for lower power usage. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index d419b77201f7..f83df426f2b6 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -65,6 +65,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_i2c_pins>; + pmic@66 { compatible = "maxim,max8998"; reg = <0x66>; @@ -314,6 +317,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fg_i2c_pins>; + fuelgauge@36 { compatible = "maxim,max17040"; interrupt-parent = <&vic0>; @@ -438,6 +444,18 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + pmic_i2c_pins: pmic-i2c-pins { + samsung,pins = "gpj4-0", "gpj4-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fg_i2c_pins: fg-i2c-pins { + samsung,pins = "mp05-0", "mp05-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pwm { -- cgit v1.2.3-70-g09d2 From aa2146416dbe2b9529267d6d17e1926fbde5a5b9 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:07 -0700 Subject: ARM: dts: s5pv210: Add WM8994 support to Aries boards Aries boards have a Wolfson WM8994 sound card attached over gpio-i2c. There is currently no ASoC Machine Driver. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 65 ++++++++++++++++++++++++++++++- arch/arm/boot/dts/s5pv210-fascinate4g.dts | 6 +++ 2 files changed, 69 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index f83df426f2b6..7d001c22c532 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -12,6 +12,7 @@ compatible = "samsung,aries", "samsung,s5pv210"; aliases { + i2c4 = &i2c_sound; i2c6 = &i2c_pmic; i2c9 = &i2c_fuel; }; @@ -57,7 +58,55 @@ power-off-delay-us = <500>; }; - i2c_pmic: i2c-gpio-0 { + i2c_sound: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sound_i2c_pins>; + + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + #sound-dai-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clocks MOUT_CLKOUT>; + clock-names = "MCLK1"; + + AVDD2-supply = <&buck3_reg>; + DBVDD-supply = <&buck3_reg>; + CPVDD-supply = <&buck3_reg>; + SPKVDD1-supply = <&buck3_reg>; + SPKVDD2-supply = <&buck3_reg>; + + wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 + 0xa101 0x0100 0x8100 0x0100 0x0100 + 0x0100>; + + wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + + wlf,lineout1-se; + wlf,lineout2-se; + + assigned-clocks = <&clocks MOUT_CLKOUT>; + assigned-clock-rates = <0>; + assigned-clock-parents = <&xusbxti>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_ldo>; + }; + }; + + i2c_pmic: i2c-gpio-2 { compatible = "i2c-gpio"; sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -309,7 +358,7 @@ }; }; - i2c_fuel: i2c-gpio-1 { + i2c_fuel: i2c-gpio-4 { compatible = "i2c-gpio"; sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -405,6 +454,12 @@ samsung,pin-val = <1>; }; + codec_ldo: codec-ldo { + samsung,pins = "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + wlan_gpio_rst: wlan-gpio-rst { samsung,pins = "gpg1-2"; samsung,pin-function = ; @@ -456,6 +511,12 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + sound_i2c_pins: sound-i2c-pins { + samsung,pins = "mp05-2", "mp05-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pwm { diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 65f589e2b72a..5e1b81823a8d 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -279,3 +279,9 @@ PIN_SLP(mp07-7, INPUT, DOWN); }; }; + +&wm8994 { + /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ + wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 + 0x0100 0x8100 0x0100 0x0100 0x0100>; +}; -- cgit v1.2.3-70-g09d2 From 3a4e7635d120dd1856ef8758724e7c6ec9a4d9d1 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:08 -0700 Subject: ARM: dts: s5pv210: Add FSA9480 support to Aries boards The Fairchild FSA9480 is a USB mux connected over i2c-gpio. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 7d001c22c532..6233884713cb 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -14,6 +14,7 @@ aliases { i2c4 = &i2c_sound; i2c6 = &i2c_pmic; + i2c7 = &i2c_musb; i2c9 = &i2c_fuel; }; @@ -358,6 +359,28 @@ }; }; + i2c_musb: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_i2c_pins>; + + fsa9480: musb@25 { + compatible = "fcs,fsa9480"; + reg = <0x25>; + interrupt-parent = <&gph2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_irq>; + }; + }; + i2c_fuel: i2c-gpio-4 { compatible = "i2c-gpio"; sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -480,6 +503,13 @@ samsung,pin-drv = ; }; + musb_irq: musq-irq { + samsung,pins = "gph2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + tf_detect: tf-detect { samsung,pins = "gph3-4"; samsung,pin-function = ; @@ -500,6 +530,12 @@ samsung,pin-drv = ; }; + musb_i2c_pins: musb-i2c-pins { + samsung,pins = "gpj3-4", "gpj3-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + pmic_i2c_pins: pmic-i2c-pins { samsung,pins = "gpj4-0", "gpj4-3"; samsung,pin-pud = ; -- cgit v1.2.3-70-g09d2 From 849994778e485d2185c2e9363e89e3eb5410e10e Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:09 -0700 Subject: ARM: dts: s5pv210: Add touchkey support to Aries boards Aries boards have soft touchkeys, manufactured by Cypress, attached over i2c-gpio. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 58 ++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 6233884713cb..6683ecec905a 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -16,6 +16,7 @@ i2c6 = &i2c_pmic; i2c7 = &i2c_musb; i2c9 = &i2c_fuel; + i2c10 = &i2c_touchkey; }; memory@30000000 { @@ -50,6 +51,18 @@ gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; }; + touchkey_vdd: regulator-fixed-1 { + compatible = "regulator-fixed"; + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_vdd_ena>; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpg1 2 GPIO_ACTIVE_LOW>; @@ -400,6 +413,32 @@ }; }; + i2c_touchkey: i2c-gpio-5 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_i2c_pins>; + + touchkey@20 { + compatible = "cypress,aries-touchkey"; + reg = <0x20>; + vdd-supply = <&touchkey_vdd>; + vcc-supply = <&buck3_reg>; + linux,keycodes = ; + interrupt-parent = <&gpj4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_irq>; + }; + }; + vibrator: pwm-vibrator { compatible = "pwm-vibrator"; pwms = <&pwm 1 44642 0>; @@ -530,6 +569,18 @@ samsung,pin-drv = ; }; + touchkey_i2c_pins: touchkey-i2c-pins { + samsung,pins = "gpj3-0", "gpj3-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_vdd_ena: touchkey-vdd-ena { + samsung,pins = "gpj3-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + musb_i2c_pins: musb-i2c-pins { samsung,pins = "gpj3-4", "gpj3-5"; samsung,pin-pud = ; @@ -542,6 +593,13 @@ samsung,pin-drv = ; }; + touchkey_irq: touchkey-irq { + samsung,pins = "gpj4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + fg_i2c_pins: fg-i2c-pins { samsung,pins = "mp05-0", "mp05-1"; samsung,pin-pud = ; -- cgit v1.2.3-70-g09d2 From ecd7a47382e5a9b290943e72195a4a3669bd3479 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:10 -0700 Subject: ARM: dts: s5pv210: Add panel support to Aries boards Aries boards have an s6e63m0 AMOLED panel connected over i2c-spi. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 68 +++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 6683ecec905a..046366d58aa0 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -200,8 +200,6 @@ regulator-name = "VLCD_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -300,8 +298,6 @@ regulator-name = "VCC_3.0V_LCD"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -454,6 +450,39 @@ offset = <0x681c>; /* PS_HOLD_CONTROL */ value = <0x5200>; }; + + spi_lcd: spi-gpio-0 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_spi_pins>; + + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + spi-cs-high; + spi-max-frequency = <1200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_rst>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + }; }; &fimd { @@ -464,18 +493,13 @@ samsung,invert-vden; samsung,invert-vclk; - display-timings { - timing-0 { - /* 480x800@60Hz */ - clock-frequency = <25628040>; - hactive = <480>; - vactive = <800>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vfront-porch = <28>; - vback-porch = <1>; - vsync-len = <2>; + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; }; }; }; @@ -600,6 +624,12 @@ samsung,pin-drv = ; }; + lcd_spi_pins: spi-lcd-pins { + samsung,pins = "mp01-1", "mp04-1", "mp04-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + fg_i2c_pins: fg-i2c-pins { samsung,pins = "mp05-0", "mp05-1"; samsung,pin-pud = ; @@ -611,6 +641,12 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + panel_rst: panel-rst { + samsung,pins = "mp05-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pwm { -- cgit v1.2.3-70-g09d2 From e619c4ef3839adff77b3c9b7bf30eb23c516c041 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:11 -0700 Subject: ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boards The remaining i2c-gpio adapters that are common to all Aries boards have devices without mainline bindings attachted to them. Add them here for documentation. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 046366d58aa0..a3748705dce8 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -13,10 +13,13 @@ aliases { i2c4 = &i2c_sound; + i2c5 = &i2c_accel; i2c6 = &i2c_pmic; i2c7 = &i2c_musb; i2c9 = &i2c_fuel; i2c10 = &i2c_touchkey; + i2c11 = &i2c_prox; + i2c12 = &i2c_magnetometer; }; memory@30000000 { @@ -120,6 +123,22 @@ }; }; + i2c_accel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_i2c_pins>; + + status = "disabled"; + + /* bma023 accelerometer, no mainline binding */ + }; + i2c_pmic: i2c-gpio-2 { compatible = "i2c-gpio"; sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -435,6 +454,38 @@ }; }; + i2c_prox: i2c-gpio-6 { + compatible = "i2c-gpio"; + sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_i2c_pins>; + + status = "disabled"; + + /* Sharp gp2a prox/light sensor, incomplete mainline binding */ + }; + + i2c_magnetometer: i2c-gpio-7 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&magnetometer_i2c_pins>; + + status = "disabled"; + + /* Yamaha yas529 magnetometer, no mainline binding */ + }; + vibrator: pwm-vibrator { compatible = "pwm-vibrator"; pwms = <&pwm 1 44642 0>; @@ -546,6 +597,12 @@ samsung,pin-pud = ; }; + prox_i2c_pins: gp2a-i2c-pins { + samsung,pins = "gpg0-2", "gpg2-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + wlan_gpio_rst: wlan-gpio-rst { samsung,pins = "gpg1-2"; samsung,pin-function = ; @@ -586,6 +643,12 @@ samsung,pin-pud = ; }; + magnetometer_i2c_pins: yas529-i2c-pins { + samsung,pins = "gpj0-0", "gpj0-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + ts_irq: ts-irq { samsung,pins = "gpj0-5"; samsung,pin-function = ; @@ -611,6 +674,12 @@ samsung,pin-drv = ; }; + accel_i2c_pins: accel-i2c-pins { + samsung,pins = "gpj3-6", "gpj3-7"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + pmic_i2c_pins: pmic-i2c-pins { samsung,pins = "gpj4-0", "gpj4-3"; samsung,pin-pud = ; -- cgit v1.2.3-70-g09d2 From 94f3c8132c30faff0391ec60e2eb72f51474c8c1 Mon Sep 17 00:00:00 2001 From: Paweł Chmiel Date: Fri, 1 May 2020 16:50:12 -0700 Subject: ARM: dts: s5pv210: Add si470x FM radio to Galaxy S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the Silicon Labs si4709 FM radio, which can be found on Galaxy S GT-i9000 (but not on most of other Aries variants). Signed-off-by: Paweł Chmiel Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- arch/arm/boot/dts/s5pv210-galaxys.dts | 47 +++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index a3748705dce8..0fa3de3c985d 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -11,7 +11,7 @@ / { compatible = "samsung,aries", "samsung,s5pv210"; - aliases { + aliases: aliases { i2c4 = &i2c_sound; i2c5 = &i2c_accel; i2c6 = &i2c_pmic; diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index 9bf4a5b95b74..a99fdda25262 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -49,12 +49,59 @@ wakeup-source; }; }; + + i2c_fmradio: i2c-gpio-8 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_i2c_pins>; + + fmradio@10 { + compatible = "silabs,si470x"; + reg = <0x10>; + interrupt-parent = <&gpj2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_irq &fm_rst>; + }; + }; +}; + +&aliases { + i2c8 = &i2c_fmradio; }; &pinctrl0 { pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; + fm_i2c_pins: fm-i2c-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_irq: fm-irq { + samsung,pins = "gpj2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_rst: fm-rst { + samsung,pins = "gpj2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = ; -- cgit v1.2.3-70-g09d2 From 04568cb58a431e51efccd98853ba3a31f758b77f Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:13 -0700 Subject: ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards The enable GPIO for the fixed vibrator regulator shouldn't be pulled in one direction or the other. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 0fa3de3c985d..945259aa5d55 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -52,6 +52,9 @@ regulator-name = "vibrator-en"; enable-active-high; gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctr-0 = <&vibrator_ena>; }; touchkey_vdd: regulator-fixed-1 { @@ -656,6 +659,12 @@ samsung,pin-drv = ; }; + vibrator_ena: vibrator-ena { + samsung,pins = "gpj1-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + touchkey_i2c_pins: touchkey-i2c-pins { samsung,pins = "gpj3-0", "gpj3-1"; samsung,pin-pud = ; -- cgit v1.2.3-70-g09d2 From e39d3a4b23f79097d78fed56613a59281921c606 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:14 -0700 Subject: ARM: dts: s5pv210: Add an ADC node The exynos-adc driver now supports the S5PV210, so add the DT node so that devices can use it. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 2ad642f51fd9..30a0c39a310f 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -159,6 +159,18 @@ }; }; + adc: adc@e1700000 { + compatible = "samsung,s5pv210-adc"; + reg = <0xe1700000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <23>, <24>; + clocks = <&clocks CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + spi0: spi@e1300000 { compatible = "samsung,s5pv210-spi"; reg = <0xe1300000 0x1000>; -- cgit v1.2.3-70-g09d2 From 07297ea732ddb2b731127448f09f066ed6d5637f Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:15 -0700 Subject: ARM: dts: s5pv210: Enable ADC on Aries boards On Aries boards, the ADC is used for things such as jack detection and battery temperature monitoring. It is supplied by LDO4 of max8998, so only enable that regulator when we are actually using the ADC. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 945259aa5d55..9f4694d71203 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -195,7 +195,6 @@ regulator-name = "VADC_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -539,6 +538,12 @@ }; }; +&adc { + vdd-supply = <&ldo4_reg>; + + status = "okay"; +}; + &fimd { pinctrl-names = "default"; pinctrl-0 = <&lcd_clk &lcd_data24>; -- cgit v1.2.3-70-g09d2 From 44a390fb43d37aedf928afc3e2b3ec0902f9c7fc Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:16 -0700 Subject: ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boards The SHDCI controller on Aries devices is a little bit peculiar about the clocks and with a slightly off clock can run into errors such as: mmc2: ADMA error: 0x02000000 mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== mmc2: sdhci: Sys addr: 0x347e4cc4 | Version: 0x00002401 mmc2: sdhci: Blk size: 0x00007004 | Blk cnt: 0x0000fffc mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013 mmc2: sdhci: Present: 0x01fa0000 | Host ctl: 0x00000012 mmc2: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x0000010f mmc2: sdhci: Timeout: 0x0000000a | Int stat: 0x00000003 mmc2: sdhci: Int enab: 0x03ff004b | Sig enab: 0x03ff004b mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000001 mmc2: sdhci: Caps: 0x05e80080 | Caps_1: 0x00000000 mmc2: sdhci: Cmd: 0x0000163a | Max curr: 0x00000000 mmc2: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x00000000 mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc2: sdhci: Host ctl2: 0x00000000 mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x349a3208 mmc2: sdhci: ============================================ mmc2: sdhci: 349a3200: DMA 0x347e4cc0, LEN 0x0004, Attr=0x23 Specifically assign the MMC sclks to be parented from MPLL with specific rates that match the vendor kernel. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 8 ++++++++ arch/arm/boot/dts/s5pv210-galaxys.dts | 4 ++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 9f4694d71203..0bd65401ec65 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -752,6 +752,10 @@ non-removable; status = "okay"; + assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + wlan@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; @@ -768,6 +772,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; &uart0 { diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index a99fdda25262..5d10dd67eacc 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -355,4 +355,8 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; + assigned-clock-rates = <0>, <52000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; -- cgit v1.2.3-70-g09d2 From 18c41a634ebea85d5f34b0483bbecb758ebc8d27 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:17 -0700 Subject: ARM: dts: s5pv210: Correct FIMC definitions The extended mainscaler is only available on FIMC1 and there are minimum pixel alignments that differ from the default. Additionally, the cam-if interface is available on all three while FIMC2 has no rotators. The lcd-wb interface is supported on FIMC1. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 30a0c39a310f..1b0ee884e91d 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -626,7 +626,7 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; + samsung,min-pix-alignment = <16 8>; samsung,cam-if; }; @@ -640,8 +640,10 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; + samsung,min-pix-alignment = <1 1>; samsung,mainscaler-ext; samsung,cam-if; + samsung,lcd-wb; }; fimc2: fimc@fb400000 { @@ -653,9 +655,10 @@ <&clocks SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; + samsung,pix-limits = <1920 8192 1280 1920>; + samsung,min-pix-alignment = <16 8>; + samsung,rotators = <0>; + samsung,cam-if; }; }; -- cgit v1.2.3-70-g09d2 From c9ed436fd69b296001fccaa8469f329be3a12a96 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Fri, 1 May 2020 16:50:18 -0700 Subject: ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boards Make sure that the GPIOs are configured correctly for the interrupt (otherwise it won't fire) and disable the pulls on the DVS GPIOs which are outputs. Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 0bd65401ec65..cf858029292e 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -169,6 +169,9 @@ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; + regulators { ldo2_reg: LDO2 { regulator-name = "VALIVE_1.2V"; @@ -617,6 +620,21 @@ samsung,pin-pud = ; }; + pmic_dvs_pins: pmic-dvs-pins { + samsung,pins = "gph0-3", "gph0-4", "gph0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + pmic_irq: pmic-irq { + samsung,pins = "gph0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + wifi_host_wake: wifi-host-wake { samsung,pins = "gph2-4"; samsung,pin-function = ; -- cgit v1.2.3-70-g09d2 From b64ac044ad949711470213550b53bd06684c5a03 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Thu, 26 Mar 2020 10:53:56 +0100 Subject: ARM: dts: socfgpa: set bridges status to disabled The hps-to-fpga bridges can't be used, when the FPGA is not programmed. Set the default state to disabled and leave enabling them to the board-specific dts files. Although this changes behavior, there are no in-tree users of the bridges, so this won't break anything. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4f3993cc0227..7f0480354ee6 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -531,6 +531,7 @@ reg = <0xff400000 0x100000>; resets = <&rst LWHPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; }; fpga_bridge1: fpga_bridge@ff500000 { @@ -538,6 +539,7 @@ reg = <0xff500000 0x10000>; resets = <&rst HPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; }; fpgamgr0: fpgamgr@ff706000 { -- cgit v1.2.3-70-g09d2 From 29aed3ef6d4985bf8d3ef6505c3e63efc838414e Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Thu, 26 Mar 2020 10:53:57 +0100 Subject: ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7f0480354ee6..c2b54af417a2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -542,6 +542,20 @@ status = "disabled"; }; + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + status = "disabled"; + }; + fpgamgr0: fpgamgr@ff706000 { compatible = "altr,socfpga-fpga-mgr"; reg = <0xff706000 0x1000 -- cgit v1.2.3-70-g09d2 From d1f3f68f55ca6f63e21aee097e075c9163d6e5a3 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 15 Jan 2020 15:29:41 -0600 Subject: ARM: dts: aspeed: ast2500: Add SCU interrupt controller Add a node for the interrupt controller provided by the SCU. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f12ec04d3cbc..f8074f7dbe0b 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -224,6 +224,14 @@ #clock-cells = <1>; #reset-cells = <1>; + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + interrupts = <21>; + interrupt-controller; + }; + p2a: p2a-control@2c { compatible = "aspeed,ast2500-p2a-ctrl"; reg = <0x2c 0x4>; -- cgit v1.2.3-70-g09d2 From f9950ad272051374f15c559ce71934bdfa072ebd Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 15 Jan 2020 15:29:42 -0600 Subject: ARM: dts: aspeed: ast2600: Add SCU interrupt controllers Add nodes for the interrupt controllers provided by the SCU. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 0a29b3b57a9d..525103f45074 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -313,6 +313,22 @@ compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; }; + + scu_ic0: interrupt-controller@560 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic0"; + reg = <0x560 0x4>; + interrupts = ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@570 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic1"; + reg = <0x570 0x4>; + interrupts = ; + interrupt-controller; + }; }; rng: hwrng@1e6e2524 { -- cgit v1.2.3-70-g09d2 From bcee38919fa0ae47c4a80ffc7ee751039fe159bf Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 6 Jan 2020 17:15:01 -0800 Subject: ARM: dts: aspeed: ast2600: Add Video Engine node The AST2600 has Video Engine so add it. Signed-off-by: Jae Hyun Yoo Acked-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 525103f45074..07781b24194d 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -338,6 +338,16 @@ quality = <100>; }; + video: video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = ; + status = "disabled"; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; -- cgit v1.2.3-70-g09d2 From 3dcfff96f17a8e8a9a346f0beff10d75e7ca8edb Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 27 Jan 2020 17:17:28 -0800 Subject: ARM: dts: aspeed: tiogapass: Add IPMB device Adding IPMB devices for facebook tiogapass platform. Signed-off-by: Vijay Khemka Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 5d7cbd9164d4..7e7e67d3b200 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -5,6 +5,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "Facebook TiogaPass BMC"; @@ -368,6 +369,11 @@ &i2c4 { status = "okay"; // BMC Debug Header + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c5 { @@ -449,6 +455,11 @@ &i2c9 { status = "okay"; //USB Debug Connector + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &pwm_tacho { -- cgit v1.2.3-70-g09d2 From d85fa6c6f337e768f25ba362e5d2ebb7769ac8c1 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Mon, 27 Jan 2020 17:18:17 -0800 Subject: ARM: dts: aspeed: tiogapass: Add gpio line names Added GPIO line names for all gpio used in tiogapass platform, these line names will be used by libgpiod to control GPIOs Signed-off-by: Vijay Khemka Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 7e7e67d3b200..6b88c7f26bf7 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -122,6 +122,69 @@ kcs_addr = <0xca2>; }; +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", + /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", + "IRQ_PVDDQ_GHJ_VRHOT_LVT3", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", + "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", + "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", + "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", + "CPU1_PROCHOT_LVT3_ BMC", + /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", + "IRQ_PVCCIN_CPU0_VRHOT_LVC3", + "IRQ_PVCCIN_CPU1_VRHOT_LVC3", + "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", + /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", + "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", + /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", + "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", + "LED_POST_CODE_6","LED_POST_CODE_7", + /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", + "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", + "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", + /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", + "CPU0_THERMTRIP_LATCH_LVT3", + "CPU1_THERMTRIP_LATCH_LVT3","","", + /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", + "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", + "BMC_PWR_DEBUG","RST_RSMRST", + /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", + "POST_CARD_PRES_BMC","PE_BMC_WAKE", + /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", + "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", + "SLT_CFG1", + /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", + "","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","BMC_FAULT","","", + /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","GLOBAL_RST_WARN", + "CPU0_MEMABC_MEMHOT_LVT3_BMC", + "CPU0_MEMDEF_MEMHOT_LVT3_BMC", + "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", + "CPU1_MEMKLM_MEMHOT_LVT3_BMC", + /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", + "","","", + /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", + "","","","", + /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", + "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", + "","POST_COMPLETE", + /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &mac0 { status = "okay"; -- cgit v1.2.3-70-g09d2 From 7f9dad6bdc34782c48935f2108def0ad4eb396a9 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Sun, 2 Feb 2020 08:39:39 -0800 Subject: ARM: dts: aspeed: tacoma: Enable eMMC controller Enabling emmc without enabling its controller doesn't do any good. Enable its controller as well to make it work. Cc: Andrew Jeffery Cc: Joel Stanley Signed-off-by: Guenter Roeck Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index ff49ec76fa7c..47293a5e0c59 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -132,6 +132,10 @@ use-ncsi; }; +&emmc_controller { + status = "okay"; +}; + &emmc { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 4aca6812d25c685934abbf9c02828bedeab903a8 Mon Sep 17 00:00:00 2001 From: Alexander Filippov Date: Thu, 30 May 2019 12:35:44 +0300 Subject: ARM: dts: aspeed: ast2400: Add video engine support Add a node to describe the video engine on AST2400. These changes were copied from aspeed-g5.dtsi Signed-off-by: Alexander Filippov Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 8e04303e8514..82f0213e3a3c 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -219,6 +219,16 @@ reg = <0x1e720000 0x8000>; // 32K }; + video: video@1e700000 { + compatible = "aspeed,ast2400-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + sdmmc: sd-controller@1e740000 { compatible = "aspeed,ast2400-sd-controller"; reg = <0x1e740000 0x100>; -- cgit v1.2.3-70-g09d2 From b19dad68c97ea7de12f8c6367f7cdfcb2cddacb2 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 18 Feb 2020 22:00:52 +1030 Subject: ARM: dts: aspeed: rainier: Enable VUART2 The second VUART is used to expose multiplexed, non-hypervisor consoles. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 6232cd726a7f..61d4140a2601 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -540,6 +540,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; -- cgit v1.2.3-70-g09d2 From 3ad7e45820d0d142161a3d811d659b8c2eb27736 Mon Sep 17 00:00:00 2001 From: Matthew Barth Date: Tue, 25 Feb 2020 14:14:15 -0600 Subject: ARM: dts: aspeed: rainier: Set PCA9552 pin types All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type GPIO. Signed-off-by: Matthew Barth Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 61d4140a2601..521b6e3d24cb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include +#include / { model = "Rainier"; @@ -269,66 +270,82 @@ gpio@0 { reg = <0>; + type = ; }; gpio@1 { reg = <1>; + type = ; }; gpio@2 { reg = <2>; + type = ; }; gpio@3 { reg = <3>; + type = ; }; gpio@4 { reg = <4>; + type = ; }; gpio@5 { reg = <5>; + type = ; }; gpio@6 { reg = <6>; + type = ; }; gpio@7 { reg = <7>; + type = ; }; gpio@8 { reg = <8>; + type = ; }; gpio@9 { reg = <9>; + type = ; }; gpio@10 { reg = <10>; + type = ; }; gpio@11 { reg = <11>; + type = ; }; gpio@12 { reg = <12>; + type = ; }; gpio@13 { reg = <13>; + type = ; }; gpio@14 { reg = <14>; + type = ; }; gpio@15 { reg = <15>; + type = ; }; }; -- cgit v1.2.3-70-g09d2 From d0ba4f581ed52b5d88726c9f1d7fae19eec22479 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 3 Oct 2019 17:24:14 -0500 Subject: ARM: dts: aspeed: tacoma: Add gpio-key definitions Add gpio-keys for various signals on Tacoma. Signed-off-by: Eddie James Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 59 +++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 47293a5e0c59..a972c20af3ed 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -89,6 +89,65 @@ linux,code = <7>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; }; &fmc { -- cgit v1.2.3-70-g09d2 From b2fa526ca27849adb6f6aab5caf505e4dbb93b97 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 22 Aug 2019 20:35:24 +0930 Subject: ARM: dts: aspeed: ast2600evb: Enable FSI master Use the first FSI master. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 4afa8662c4e8..8d0f4656aa05 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -213,3 +213,7 @@ &i2c15 { status = "okay"; }; + +&fsim0 { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 156fbb12f11e3e9a6416d746281a50e72bab0533 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 24 Dec 2019 00:35:54 +1100 Subject: ARM: dts: aspeed: rainier: Add host FSI description This adds the description of the Power CPUs that are attached to the BMC. Without this userspace will see the '/dev/scom66' style layout. Reviewed-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 521b6e3d24cb..89d31de2fb0b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -73,6 +73,88 @@ status = "okay"; }; +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + &ibt { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From fbb6f3e068ecf9247773a5d4604034a2abefa816 Mon Sep 17 00:00:00 2001 From: Matthew Barth Date: Thu, 16 Jan 2020 09:46:38 -0600 Subject: ARM: dts: aspeed: rainier: Remove regulators Regulators will be dynamically configured and monitored from userspace. Signed-off-by: Matthew Barth Reviewed-by: Eddie James Reviewed-by: Jim Wright Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 60 ---------------------------- 1 file changed, 60 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 89d31de2fb0b..f4cad70d8edc 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -485,21 +485,6 @@ &i2c9 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -510,21 +495,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; @@ -534,21 +504,6 @@ &i2c10 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -559,21 +514,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; -- cgit v1.2.3-70-g09d2 From c87f739459cc5f1f7fb11f2b4fac567c72b56001 Mon Sep 17 00:00:00 2001 From: Ben Pai Date: Thu, 20 Feb 2020 13:52:55 +0800 Subject: ARM: dts: aspeed: mihawk: Change the name of leds Change the name of power, fault and rear-id. Remove the two leds. Signed-off-by: Ben Pai Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index f7e935ede919..d1f452a00605 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -120,35 +120,24 @@ leds { compatible = "gpio-leds"; - fault { + front-fault { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; }; - power { + power-button { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; }; - rear-id { + front-id { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; }; - rear-g { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; - }; - - rear-ok { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - }; fan0 { retain-state-shutdown; -- cgit v1.2.3-70-g09d2 From 977f7e0028f1689f93d7f8d793831c4594d50c96 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 24 Mar 2020 16:31:06 +1030 Subject: ARM: dts: aspeed: tacoma: Add GPIOs for FSI GPIO Q7 is no longer used for air/water. It is repurposed on Tacoma to indicate internal FSI (low) vs cabled (high). GPIO B0 controls the muxing of FSI to the cable (low) or internal pins (high). Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index a972c20af3ed..2619dd6e40fc 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -34,12 +34,6 @@ gpio-keys { compatible = "gpio-keys"; - air-water { - label = "air-water"; - gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - checkstop { label = "checkstop"; gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; @@ -205,6 +199,9 @@ #address-cells = <2>; #size-cells = <0>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam@0,0 { reg = <0 0>; #address-cells = <1>; -- cgit v1.2.3-70-g09d2 From c998f40f2ae6a48e93206e2c1ea0691479989611 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 26 Mar 2020 09:17:21 -0500 Subject: ARM: dts: aspeed: ast2600: Set arch timer always-on According to ASPEED, FTTMR010 is not intended to be used in the AST2600. The arch timer should be used, but Linux doesn't enable high-res timers without being assured that the arch timer is always on, so set that property in the devicetree. The FTTMR010 device is described by set to disabled. This fixes highres timer support for AST2600. Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB") Signed-off-by: Eddie James Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 07781b24194d..cb9d104c3ec5 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -65,6 +65,7 @@ ; clocks = <&syscon ASPEED_CLK_HPLL>; arm,cpu-registers-not-fw-configured; + always-on; }; ahb { @@ -394,6 +395,7 @@ <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_APB1>; clock-names = "PCLK"; + status = "disabled"; }; uart1: serial@1e783000 { -- cgit v1.2.3-70-g09d2 From d5ece55c1874a6f29bf610f593e2bdf14a477ff2 Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Thu, 6 Feb 2020 11:02:34 -0600 Subject: ARM: dts: aspeed: witherspoon: Add gpio line names Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler Reviewed-by: Joel Stanley Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 421aa600148b..a0f99e34ac8e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -191,6 +191,40 @@ }; +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","air-water","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","","","", + /*E0-E7*/ "fsi-data","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", + "led-rear-id","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","presence-ps0", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","fsi-trans","","","power-button","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &fmc { status = "okay"; -- cgit v1.2.3-70-g09d2 From 1f2c9d31e4806177aa97819d4ddc83dacd437ba2 Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Fri, 6 Mar 2020 11:02:17 -0600 Subject: ARM: dts: aspeed: romulus: Add gpio line names Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 35 +++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index edfa44fe1f75..fd2e014dae75 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -231,23 +231,52 @@ }; &gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","led-fault","", + "led-identify","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","","fsi-trans","","","led-power","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + nic_func_mode0 { gpio-hog; gpios = ; output-low; - line-name = "nic_func_mode0"; }; nic_func_mode1 { gpio-hog; gpios = ; output-low; - line-name = "nic_func_mode1"; }; seq_cont { gpio-hog; gpios = ; output-low; - line-name = "seq_cont"; }; }; -- cgit v1.2.3-70-g09d2 From fa09a28ca3e966582d6d92ef1536de360c8b194b Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Fri, 6 Mar 2020 11:02:18 -0600 Subject: ARM: dts: aspeed: zaius: Add gpio line names Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler Acked-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 37 ++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index bc60ec291681..4bcc82046362 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -478,32 +478,61 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpioh_unbiased>; + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", + "led-fault", + /*E0-E7*/ "","","","","","","","presence-pcie-e2b", + /*F0-F7*/ "","","","","","","","checkstop", + /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", + /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", + /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", + "","fsi-mux","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","led-hdd-fault","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + line_iso_u146_en { gpio-hog; gpios = ; output-high; - line-name = "iso_u164_en"; }; ncsi_mux_en_n { gpio-hog; gpios = ; output-low; - line-name = "ncsi_mux_en_n"; }; line_bmc_i2c2_sw_rst_n { gpio-hog; gpios = ; output-high; - line-name = "bmc_i2c2_sw_rst_n"; }; line_bmc_i2c5_sw_rst_n { gpio-hog; gpios = ; output-high; - line-name = "bmc_i2c5_sw_rst_n"; }; }; -- cgit v1.2.3-70-g09d2 From 2f68e4e7df6760956a1ae9e5a79fdb32106de52d Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 24 Mar 2020 21:47:11 +1030 Subject: ARM: dts: aspeed: tacoma: Add gpio line names Add names for some of the GPIOs that are used in Tacoma. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 33 +++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 2619dd6e40fc..b7d8b27da161 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -144,6 +144,39 @@ }; }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "fsi-mux","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","presence-ps0","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "led-rear-power","led-rear-id","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &fmc { status = "okay"; flash@0 { -- cgit v1.2.3-70-g09d2 From e9b24b55ca4f140970b78d5e88ff2b1b9751692d Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Fri, 10 Apr 2020 14:17:04 -0500 Subject: ARM: dts: aspeed: rainier: Add gpio line names Name the GPIOs to help userspace work with them. The names describe the functionality the lines provide, not the net or ball name. This makes it easier to share userspace code across different systems and makes the use of the lines more obvious. Signed-off-by: Andrew Geissler Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 34 ++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index f4cad70d8edc..b1eb74de12b8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -65,6 +65,40 @@ }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", + "","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &emmc_controller { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 3208f3a513393aa94c3eaef21c00bbfd003086e1 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 30 Mar 2020 15:17:07 +1030 Subject: ARM: dts: aspeed: rainier: Add VGA reserved memory region The BMC uses reserves the top 16MB of memory for the host to use for VGA or PCIe communication. Reviewed-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index b1eb74de12b8..bdfe342bf7c5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -33,6 +33,11 @@ no-map; reg = <0xB8000000 0x04000000>; /* 64M */ }; + + vga_memory: region@bf000000 { + no-map; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; }; gpio-keys { -- cgit v1.2.3-70-g09d2 From bf6c99f3aeda127efe54b3d2ede2a98a815a90f6 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 30 Mar 2020 16:14:30 -0500 Subject: ARM: dts: aspeed: tacoma: Add iio-hwmon nodes for IIO devices Connect the BMP280 and DPS310 to the hwmon subsystem with iio-hwmon nodes. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index b7d8b27da161..1526127b27af 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -142,6 +142,16 @@ linux,code = <7>; }; }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; }; &gpio0 { -- cgit v1.2.3-70-g09d2 From d2718f5e30d01d5dbc23c189bb670460093ba477 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 2 Apr 2020 23:09:31 +1030 Subject: ARM: dts: aspeed: tacoma: Enable the second VUART Used by some POWER hypervisors. Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 1526127b27af..4069c0d57d1c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -877,6 +877,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; -- cgit v1.2.3-70-g09d2 From 39d8a73c53a21c1e2c643889079652747cd744cd Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 12 Feb 2020 14:30:49 -0600 Subject: ARM: dts: aspeed: tacoma: Add TPM Add the Nuvoton NPCT75X to the appropriate i2c bus. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 4069c0d57d1c..13c4aa02f4de 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -497,6 +497,11 @@ &i2c1 { status = "okay"; + + tpm: tpm@2e { + compatible = "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c2 { -- cgit v1.2.3-70-g09d2 From 6456bc88c90d50568ce3fd5b7d7f6971aa33f2bf Mon Sep 17 00:00:00 2001 From: Ben Pai Date: Thu, 23 Apr 2020 17:52:30 +0800 Subject: ARM: dts: aspeed: mihawk: add aliases for i2c Set the bus id for each mux channel to avoid switching channels multiple times Signed-off-by: Ben Pai Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 293 +++++++++++++++++++++++++++- 1 file changed, 289 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts index d1f452a00605..60e545b6396f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -8,6 +8,52 @@ model = "Mihawk BMC"; compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; + aliases { + i2c215 = &bus6_mux215; + i2c216 = &bus6_mux216; + i2c217 = &bus6_mux217; + i2c218 = &bus6_mux218; + i2c219 = &bus6_mux219; + i2c220 = &bus6_mux220; + i2c221 = &bus6_mux221; + i2c222 = &bus6_mux222; + i2c223 = &bus7_mux223; + i2c224 = &bus7_mux224; + i2c225 = &bus7_mux225; + i2c226 = &bus7_mux226; + i2c227 = &bus7_mux227; + i2c228 = &bus7_mux228; + i2c229 = &bus7_mux229; + i2c230 = &bus7_mux230; + i2c231 = &bus9_mux231; + i2c232 = &bus9_mux232; + i2c233 = &bus9_mux233; + i2c234 = &bus9_mux234; + i2c235 = &bus9_mux235; + i2c236 = &bus9_mux236; + i2c237 = &bus9_mux237; + i2c238 = &bus9_mux238; + i2c239 = &bus10_mux239; + i2c240 = &bus10_mux240; + i2c241 = &bus10_mux241; + i2c242 = &bus10_mux242; + i2c243 = &bus10_mux243; + i2c244 = &bus10_mux244; + i2c245 = &bus10_mux245; + i2c246 = &bus10_mux246; + i2c247 = &bus12_mux247; + i2c248 = &bus12_mux248; + i2c249 = &bus12_mux249; + i2c250 = &bus12_mux250; + i2c251 = &bus13_mux251; + i2c252 = &bus13_mux252; + i2c253 = &bus13_mux253; + i2c254 = &bus13_mux254; + i2c255 = &bus13_mux255; + i2c256 = &bus13_mux256; + i2c257 = &bus13_mux257; + i2c258 = &bus13_mux258; + }; chosen { stdout-path = &uart5; @@ -619,6 +665,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus7_mux223: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus7_mux224: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus7_mux225: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus7_mux226: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus7_mux227: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus7_mux228: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus7_mux229: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus7_mux230: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -633,6 +727,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus6_mux215: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus6_mux216: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus6_mux217: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus6_mux218: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus6_mux219: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus6_mux220: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus6_mux221: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus6_mux222: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -673,6 +815,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux231: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux232: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux233: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux234: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -684,6 +850,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux235: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux236: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux237: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux238: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -714,6 +904,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux239: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux240: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux241: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux242: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -725,6 +939,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux243: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux244: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux245: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux246: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -785,7 +1023,7 @@ interrupt-controller; #interrupt-cells = <2>; - i2c@0 { + bus12_mux247: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -796,7 +1034,7 @@ }; }; - i2c@1 { + bus12_mux248: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -807,7 +1045,7 @@ }; }; - i2c@2 { + bus12_mux249: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -818,7 +1056,7 @@ }; }; - i2c@3 { + bus12_mux250: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -846,6 +1084,53 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + bus13_mux251: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus13_mux252: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus13_mux253: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus13_mux254: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus13_mux255: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus13_mux256: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus13_mux257: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus13_mux258: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; -- cgit v1.2.3-70-g09d2 From 697538bd65ad22a92598b5efded3666d3c59d1cc Mon Sep 17 00:00:00 2001 From: Alexander Filippov Date: Wed, 29 Apr 2020 14:37:11 +0300 Subject: ARM: dts: aspeed: Add YADRO Nicole BMC Nicole is an OpenPower machine with an Aspeed 2500 BMC SoC manufactured by YADRO. Signed-off-by: Alexander Filippov Acked-by: Andrew Jeffery Reviewed-by: Patrick Williams Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts | 326 ++++++++++++++++++++++++++++ 2 files changed, 327 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..6f9fe0f959f2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1347,6 +1347,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mihawk.dtb \ + aspeed-bmc-opp-nicole.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ aspeed-bmc-opp-swift.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts new file mode 100644 index 000000000000..91dced7e7849 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Nicole BMC"; + compatible = "yadro,nicole-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "platform:green:power"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; + }; + + identify { + label = "platform:blue:indicator"; + gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; + }; + + fault { + label = "platform:red:fault"; + gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; + }; + + attention { + label = "platform:yellow:alarm"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c2 { + status = "okay"; + /* CPU0 characterization connector */ +}; + +&i2c3 { + status = "okay"; + /* CLK GEN SI5338 */ +}; + +&i2c4 { + status = "okay"; + /* Voltage regulators for CPU0 */ +}; + +&i2c5 { + status = "okay"; + /* Voltage regulators for CPU1 */ +}; + +&i2c6 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c7 { + status = "okay"; + /* CPLD */ +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", + "func_mode0","func_mode1","func_mode2","","", + /*E0-E7*/ "","ncsi_cfg","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","power-button","","","","","", + /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","software_pwrgood","","","","","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", + "led-power","","","led-identify", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + func_mode0 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode1 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode2 { + gpio-hog; + gpios = ; + output-low; + }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + }; + ncsi_cfg { + gpio-hog; + input; + gpios = ; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" -- cgit v1.2.3-70-g09d2 From 266056d3c61d64744d17bd31484c4c50913fece7 Mon Sep 17 00:00:00 2001 From: Manikandan Elumalai Date: Thu, 2 Apr 2020 19:41:35 +0530 Subject: ARM: dts: aspeed: Adding Facebook Yosemite V2 BMC The Yosemite V2 is a facebook multi-node server platform that host four OCP server. The BMC in the Yosemite V2 platform based on AST2500 SoC. This patch adds linux device tree entry related to Yosemite V2 specific devices connected to BMC SoC. Signed-off-by: Manikandan Elumalai Acked-by: Andrew Jeffery Reviewed-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/aspeed-bmc-facebook-yosemitev2.dts | 231 +++++++++++++++++++++ 2 files changed, 232 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6f9fe0f959f2..0d446e74d6ac 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1339,6 +1339,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts new file mode 100644 index 000000000000..8864e9c312a8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Facebook Yosemitev2 BMC"; + compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; + aliases { + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + iio-hwmon { + // VOLATAGE SENSOR + compatible = "iio-hwmon"; + io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , + <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , + <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , + <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; +&uart1 { + // Host1 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + // Host2 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + +}; + +&uart3 { + // Host3 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + // Host4 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&vuart { + // Virtual UART + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; + mlx,multi-host; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c1 { + //Host1 IPMB bus + status = "okay"; + multi-master; + ipmb1@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + //Host2 IPMB bus + status = "okay"; + multi-master; + ipmb3@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + //Host3 IPMB bus + status = "okay"; + multi-master; + ipmb5@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c7 { + //Host4 IPMB bus + status = "okay"; + multi-master; + ipmb7@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + //FRU EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c9 { + status = "okay"; + tmp421@4e { + //INLET TEMP + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + //OUTLET TEMP + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + //HSC + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c11 { + status = "okay"; + //MEZZ_TEMP_SENSOR + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; +}; + +&i2c12 { + status = "okay"; + //MEZZ_FRU + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&pwm_tacho { + status = "okay"; + //FSC + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; +}; -- cgit v1.2.3-70-g09d2 From 910f65c5561198147bac1d1606892d5790f94a9f Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 15 Jan 2020 15:29:47 -0600 Subject: ARM: dts: aspeed: ast2500: Add XDMA Engine Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g5.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f8074f7dbe0b..284face7de2c 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -262,6 +262,17 @@ interrupts = <0x19>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; -- cgit v1.2.3-70-g09d2 From e7d1ed849fd1660a9b113524461885a0ea1b199c Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 15 Jan 2020 15:29:48 -0600 Subject: ARM: dts: aspeed: ast2600: Add XDMA Engine Add a node for the XDMA engine with all the necessary information. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index cb9d104c3ec5..eb09506510f1 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -339,6 +339,18 @@ quality = <100>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2600-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>; + interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + video: video@1e700000 { compatible = "aspeed,ast2600-video-engine"; reg = <0x1e700000 0x1000>; -- cgit v1.2.3-70-g09d2 From f90fe8d3b242aafe3cf1dd512bff83c704f70558 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 20 Apr 2020 15:26:09 -0500 Subject: ARM: dts: Aspeed: AST2600: Add XDMA PCI-E root control reset The AST2600 XDMA engine requires the PCI-E root control reset be cleared as well, so add a phandle to that syscon reset. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index eb09506510f1..98102968627b 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -343,7 +343,8 @@ compatible = "aspeed,ast2600-xdma"; reg = <0x1e6e7000 0x100>; clocks = <&syscon ASPEED_CLK_GATE_BCLK>; - resets = <&syscon ASPEED_RESET_DEV_XDMA>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; + reset-names = "device", "root-complex"; interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <&scu_ic0 2>; pcie-device = "bmc"; -- cgit v1.2.3-70-g09d2 From fa4c8ec6feaa3237f5d44cb8c6d0aa0dff6e1bcc Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Sat, 11 Apr 2020 11:44:58 +0930 Subject: ARM: dts: aspeed: Change KCS nodes to v2 binding Fixes the following warnings for both g5 and g6 SoCs: arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning (unit_address_vs_reg): /ahb/apb/lpc@1e789000/lpc-bmc@0/kcs1@0: node has a unit name, but no reg property Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 4 ++-- arch/arm/boot/dts/aspeed-g5.dtsi | 24 +++++++++++----------- arch/arm/boot/dts/aspeed-g6.dtsi | 23 +++++++++++---------- 3 files changed, 26 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 6b88c7f26bf7..2d44d9ad4e40 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -113,13 +113,13 @@ &kcs2 { // BMC KCS channel 2 status = "okay"; - kcs_addr = <0xca8>; + aspeed,lpc-io-reg = <0xca8>; }; &kcs3 { // BMC KCS channel 3 status = "okay"; - kcs_addr = <0xca2>; + aspeed,lpc-io-reg = <0xca2>; }; &gpio { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 284face7de2c..de7fd80b022a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -445,22 +445,22 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; - kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; - kcs_chan = <3>; status = "disabled"; }; }; @@ -474,10 +474,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = <8>; - kcs_chan = <4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 98102968627b..9d8d8e18bc90 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -474,22 +474,23 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = ; kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = ; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = ; - kcs_chan = <3>; status = "disabled"; }; }; @@ -503,10 +504,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = ; - kcs_chan = <4>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From eb4cdda7a30b3f9894fd5a58e0201fa57861183f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 3 May 2020 22:46:50 +0100 Subject: ARM: dts: r8a7742: Initial SoC device tree The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC, CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer and the required clock descriptions. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 389 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 389 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi new file mode 100644 index 000000000000..3d3d95678496 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7742 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7742"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU2>; + next-level-cache = <&L2_CA7>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU3>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7742"; + reg = <0 0xe6060000 0 0x250>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7742-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7742-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7742-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; -- cgit v1.2.3-70-g09d2 From 269785eaba09172c5189e30d2202084586aeabdd Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 3 May 2020 22:46:53 +0100 Subject: ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Add support for iWave RZ/G1H Qseven System On Module. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588542414-14826-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21m.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi new file mode 100644 index 000000000000..85aff429d408 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 48ad3c4a334ad1e583f5159f43c3623ecaffc9f9 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 3 May 2020 22:46:54 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588542414-14826-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..ed3376cce638 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -917,6 +917,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r7s9210-rza2mevb.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7742-iwg21d-q7.dtb \ r8a7743-iwg20d-q7.dtb \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts new file mode 100644 index 000000000000..1f5c35c66d91 --- /dev/null +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7742-iwg21m.dtsi" + +/ { + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial2 = &scifa2; + }; + + chosen { + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial2:115200n8"; + }; +}; + +&pfc { + scifa2_pins: scifa2 { + groups = "scifa2_data_c"; + function = "scifa2"; + }; +}; + +&scifa2 { + pinctrl-0 = <&scifa2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 521d6678b9a482058c78a9e6b2384ddc0c3c6392 Mon Sep 17 00:00:00 2001 From: Nick Reitemeyer Date: Thu, 30 Apr 2020 17:02:44 +0200 Subject: ARM: dts: ux500: samsung-golden: Add magnetometer Add the ALPS magnetometer to the Golden phone. Cc: Stephan Gerhold Signed-off-by: Nick Reitemeyer Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200430150245.7935-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 0e9e33f4ca3c..5b499c0b2745 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -24,6 +24,26 @@ stdout-path = &serial2; }; + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + soc { /* External Micro SD card slot */ sdi0_per1@80126000 { @@ -383,6 +403,16 @@ }; }; + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + golden_cfg1 { + pins = "GPIO151", /* COMP_SCL */ + "GPIO152"; /* COMP_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + sdi0 { sd_level_translator_default: sd_level_translator_default { golden_cfg1 { -- cgit v1.2.3-70-g09d2 From 3c278a4749a8a0d1bf8e5235ca289748fdc48b11 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 30 Apr 2020 17:02:45 +0200 Subject: ARM: dts: ux500: samsung-skomer: Add magnetometer Add the ALPS magnetometer to the Skomer phone. Cc: Stephan Gerhold Cc: Nick Reitemeyer Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200430150245.7935-2-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 292ed5286652..c7d4ad34e569 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -140,7 +140,12 @@ pinctrl-0 = <&i2c_gpio_1_default>; #address-cells = <1>; #size-cells = <0>; - /* TODO: this should be used by the ALPS HSCDTD008A compass sensor */ + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; }; soc { -- cgit v1.2.3-70-g09d2 From 2f9306969a76e9e3d531705c53c5a7874928e811 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Thu, 30 Apr 2020 12:16:49 +0200 Subject: ARM: dts: stm32: add sd-uhs properties in SD-card node for stm32mp157c-ed1 The sdmmc1 peripheral is connected on SD-card on STM32MP1-ED1 board. Add the UHS features the controller is able to manage. Those features require a level shifter on the board, and the support of the voltage switch in driver, which is done in Linux v5.7. Signed-off-by: Ludovic Barre Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 0aaae0df5b07..32ccd50b4144 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -319,6 +319,10 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From b5a087139db2aa1f10d79d4b5486386e7493743c Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Thu, 30 Apr 2020 15:02:35 +0200 Subject: ARM: dts: stm32: Enable thermal sensor support on stm32mp15xx-dkx Enable STM32 Digital Thermal Sensor driver for stm32mp15xx-dkx boards. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index fcf50131e5fe..70db923a45f7 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -116,6 +116,10 @@ status = "okay"; }; +&dts { + status = "okay"; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; -- cgit v1.2.3-70-g09d2 From 9b06fc39084e161da84a399b6b5dc524e673f51e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 29 Apr 2020 15:58:10 -0500 Subject: ARM: vexpress: Move vexpress_flags_set() into arch code vexpress_flags_set() is only used by the platform SMP related code and has nothing to do with the vexpress-sysreg MFD driver other than both access the same h/w block. It's also only needed for 32-bit systems and must be built-in for them. Let's move vexpress_flags_set() closer to where it is being used. This will allow for vexpress-sysreg to be built as a module. Cc: Lorenzo Pieralisi Cc: Linus Walleij Reviewed-by: Sudeep Holla Acked-by: Arnd Bergmann Acked-by: Liviu Dudau Acked-by: Lee Jones Signed-off-by: Rob Herring --- arch/arm/mach-vexpress/Kconfig | 1 - arch/arm/mach-vexpress/core.h | 1 + arch/arm/mach-vexpress/dcscb.c | 1 + arch/arm/mach-vexpress/v2m.c | 23 +++++++++++++++++++++++ drivers/mfd/vexpress-sysreg.c | 19 ------------------- include/linux/vexpress.h | 4 ---- 6 files changed, 25 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 726a68085c3b..18951cd20d9d 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -22,7 +22,6 @@ menuconfig ARCH_VEXPRESS select REGULATOR_FIXED_VOLTAGE if REGULATOR select VEXPRESS_CONFIG select VEXPRESS_SYSCFG - select MFD_VEXPRESS_SYSREG help This option enables support for systems using Cortex processor based ARM core and logic (FPGA) tiles on the Versatile Express motherboard, diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index f4a7519084f1..bda78675c55d 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h @@ -1,3 +1,4 @@ bool vexpress_smp_init_ops(void); +void vexpress_flags_set(u32 data); extern const struct smp_operations vexpress_smp_dt_ops; diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c index 46a903c88c6a..a0554d7d04f7 100644 --- a/arch/arm/mach-vexpress/dcscb.c +++ b/arch/arm/mach-vexpress/dcscb.c @@ -20,6 +20,7 @@ #include #include +#include "core.h" #define RST_HOLD0 0x0 #define RST_HOLD1 0x4 diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 95886b3bb9dd..ffe7c7a85ae9 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -1,8 +1,31 @@ // SPDX-License-Identifier: GPL-2.0 +#include +#include #include #include "core.h" +#define SYS_FLAGSSET 0x030 +#define SYS_FLAGSCLR 0x034 + +void vexpress_flags_set(u32 data) +{ + static void __iomem *base; + + if (!base) { + struct device_node *node = of_find_compatible_node(NULL, NULL, + "arm,vexpress-sysreg"); + + base = of_iomap(node, 0); + } + + if (WARN_ON(!base)) + return; + + writel(~0, base + SYS_FLAGSCLR); + writel(data, base + SYS_FLAGSSET); +} + static const char * const v2m_dt_match[] __initconst = { "arm,vexpress", NULL, diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c index c68ff56dbdb1..0b9cc67706c7 100644 --- a/drivers/mfd/vexpress-sysreg.c +++ b/drivers/mfd/vexpress-sysreg.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -42,24 +41,6 @@ #define SYS_MISC_MASTERSITE (1 << 14) -void vexpress_flags_set(u32 data) -{ - static void __iomem *base; - - if (!base) { - struct device_node *node = of_find_compatible_node(NULL, NULL, - "arm,vexpress-sysreg"); - - base = of_iomap(node, 0); - } - - if (WARN_ON(!base)) - return; - - writel(~0, base + SYS_FLAGSCLR); - writel(data, base + SYS_FLAGSSET); -} - /* The sysreg block is just a random collection of various functions... */ static struct syscon_platform_data vexpress_sysreg_sys_id_pdata = { diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h index 0e130b5077a5..2ec7992b054c 100644 --- a/include/linux/vexpress.h +++ b/include/linux/vexpress.h @@ -40,8 +40,4 @@ struct device *vexpress_config_bridge_register(struct device *parent, struct regmap *devm_regmap_init_vexpress_config(struct device *dev); -/* Platform control */ - -void vexpress_flags_set(u32 data); - #endif -- cgit v1.2.3-70-g09d2 From 81134fb541d46d0441ce7fce557eba6c418fcc36 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 29 Apr 2020 15:58:13 -0500 Subject: clk: versatile: Rework kconfig structure CONFIG_COMMON_CLK_VERSATILE doesn't really do anything other than hiding Arm Ltd reference platform clock drivers. It is both selected by the platforms that need it and has a 'depends on' for those platforms. Let's drop the selects and convert CONFIG_COMMON_CLK_VERSATILE into a menuconfig entry. With this make CONFIG_ICST visible. Move the 'select REGMAP_MMIO' to the drivers that require it (SP810 did not). This also has the side effect of enabling CONFIG_ICST for COMPILE_TEST as it was not visible before. Cc: Catalin Marinas Cc: Will Deacon Cc: Liviu Dudau Cc: Lorenzo Pieralisi Cc: Linus Walleij Reviewed-by: Sudeep Holla Reviewed-by: Stephen Boyd Signed-off-by: Rob Herring --- arch/arm/mach-integrator/Kconfig | 1 - arch/arm/mach-realview/Kconfig | 1 - arch/arm/mach-versatile/Kconfig | 1 - arch/arm/mach-vexpress/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - drivers/clk/Makefile | 2 +- drivers/clk/versatile/Kconfig | 22 ++++++++++++---------- 7 files changed, 13 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 982eabc36163..d59ba15a6b69 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -3,7 +3,6 @@ menuconfig ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 select ARM_AMBA - select COMMON_CLK_VERSATILE select HAVE_TCM select ICST select MFD_SYSCON diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 44ebbf9ec673..002404fafc14 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -6,7 +6,6 @@ menuconfig ARCH_REALVIEW select ARM_GIC select ARM_TIMER_SP804 select CLK_SP810 - select COMMON_CLK_VERSATILE select GPIO_PL061 if GPIOLIB select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index f5c275434d6c..d88e7725bf99 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -6,7 +6,6 @@ config ARCH_VERSATILE select ARM_TIMER_SP804 select ARM_VIC select CLKSRC_VERSATILE - select COMMON_CLK_VERSATILE select CPU_ARM926T select ICST select MFD_SYSCON diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 18951cd20d9d..2d1fdec4c230 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -7,7 +7,6 @@ menuconfig ARCH_VEXPRESS select ARM_GIC select ARM_GLOBAL_TIMER select ARM_TIMER_SP804 - select COMMON_CLK_VERSATILE select GPIOLIB select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 5c38dc56b808..25cbb556d863 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -274,7 +274,6 @@ config ARCH_UNIPHIER config ARCH_VEXPRESS bool "ARMv8 software model (Versatile Express)" - select COMMON_CLK_VERSATILE select GPIOLIB select PM select PM_GENERIC_DOMAINS diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f4169cc2fd31..fb30c16e1596 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -114,7 +114,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_U8500) += ux500/ -obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ +obj-y += versatile/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) += x86/ endif diff --git a/drivers/clk/versatile/Kconfig b/drivers/clk/versatile/Kconfig index c2618f1477a2..df0d50bb846c 100644 --- a/drivers/clk/versatile/Kconfig +++ b/drivers/clk/versatile/Kconfig @@ -1,22 +1,22 @@ # SPDX-License-Identifier: GPL-2.0-only -config ICST - bool -config COMMON_CLK_VERSATILE - bool "Clock driver for ARM Reference designs" - depends on ARCH_INTEGRATOR || ARCH_REALVIEW || \ - ARCH_VERSATILE || ARCH_VEXPRESS || ARM64 || \ - COMPILE_TEST +menuconfig COMMON_CLK_VERSATILE + bool "Clock driver for ARM Reference designs" if COMPILE_TEST + default y if ARCH_INTEGRATOR || ARCH_REALVIEW || \ + ARCH_VERSATILE || ARCH_VEXPRESS + +if COMMON_CLK_VERSATILE + +config ICST + bool "Clock driver for ARM Reference designs ICST" select REGMAP_MMIO ---help--- Supports clocking on ARM Reference designs: - Integrator/AP and Integrator/CP - RealView PB1176, EB, PB11MP and PBX - - Versatile Express config CLK_SP810 bool "Clock driver for ARM SP810 System Controller" - depends on COMMON_CLK_VERSATILE default y if ARCH_VEXPRESS ---help--- Supports clock muxing (REFCLK/TIMCLK to TIMERCLKEN0-3) capabilities @@ -24,10 +24,12 @@ config CLK_SP810 config CLK_VEXPRESS_OSC bool "Clock driver for Versatile Express OSC clock generators" - depends on COMMON_CLK_VERSATILE depends on VEXPRESS_CONFIG + select REGMAP_MMIO default y if ARCH_VEXPRESS ---help--- Simple regmap-based driver driving clock generators on Versatile Express platforms hidden behind its configuration infrastructure, commonly known as OSCs. + +endif -- cgit v1.2.3-70-g09d2 From 46ab8238e3e81669c41c698460583636e811018e Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:29 +0300 Subject: ARM: dts: DRA7: Add common IPU and DSP nodes The DRA7xx family of SOCs have two IPUs and upto two DSP processor subsystems in general. The IPU processor subsystem contains dual-core ARM Cortex-M4 processors, while the DSP processor subsystem is based on the TI's standard TMS320C66x DSP CorePac core. The IPUs are very similar to those on OMAP5. Two IPUs and one DSP processor subsystems is the most common configuration. The processor device DT nodes have been added for these processor subsystems, with the internal memories added through 'reg' and 'reg-names' properties. The IPUs only have an L2 RAM, whereas the DSPs have L1P, L1D and L2 RAM memories. NOTE: 1. The nodes do not have any mailboxes, timers or CMA regions assigned, they should be added in the respective board dts files. 2. The nodes haven been disabled by default and the enabling of these nodes is also left to the respective board dts files. Signed-off-by: Suman Anna [t-kristo@ti.com: convert to ti-sysc support from legacy hwmod] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4740989ed9c4..8f4e4941984f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -410,6 +410,42 @@ ti,hwmods = "dmm"; }; + ipu1: ipu@58820000 { + compatible = "ti,dra7-ipu"; + reg = <0x58820000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu1>; + status = "disabled"; + resets = <&prm_ipu 0>, <&prm_ipu 1>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + firmware-name = "dra7-ipu1-fw.xem4"; + }; + + ipu2: ipu@55020000 { + compatible = "ti,dra7-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu2>; + status = "disabled"; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + firmware-name = "dra7-ipu2-fw.xem4"; + }; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x55c 10>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + status = "disabled"; + resets = <&prm_dsp1 0>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + firmware-name = "dra7-dsp1-fw.xe66"; + }; + target-module@40d01000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x40d01000 0x4>, -- cgit v1.2.3-70-g09d2 From 78aae49a23ebe8b5e7a3e2876e4d114d43ac8bbb Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:30 +0300 Subject: ARM: dts: DRA74x: Add DSP2 processor device node The DRA7xx family of SoCs can contain upto two identical DSP processor subsystems. The second DSP processor subsystem is present only on the DRA74x/DRA76x variants. The processor device DT node has therefore been added in disabled state for this processor subsystem in the DRA74x specific DTS file. NOTE: 1. The node does not have any mailboxes, timers or CMA region assigned, they should be added in the respective board dts files. 2. The node should also be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna [t-kristo@ti.com: converted to support ti-sysc from legacy hwmod] Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra74x.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 7b1c61298253..94ba80769001 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -124,6 +124,20 @@ ti,syscon-mmuconfig = <&dsp2_system 0x1>; }; }; + + dsp2: dsp@41000000 { + compatible = "ti,dra7-dsp"; + reg = <0x41000000 0x48000>, + <0x41600000 0x8000>, + <0x41700000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x560 10>; + iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; + status = "disabled"; + resets = <&prm_dsp2 0>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + firmware-name = "dra7-dsp2-fw.xe66"; + }; }; }; -- cgit v1.2.3-70-g09d2 From c6df6557268ad6fee6df4f2ce5e1443f7fcfbd75 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:31 +0300 Subject: ARM: dts: DRA74x: Add aliases for rproc nodes Add aliases for all the IPU and DSP remoteproc processor nodes common to all DRA74x/DRA76x/AM572x/AM574x boards. The aliases uses the stem "rproc". The aliases are defined in the order of the most common processors on the DRA74x family. The aliases can be overridden, if needed, in the respective derivative board dts files. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra74x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 94ba80769001..46d8e7615180 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -29,6 +29,13 @@ }; }; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + rproc3 = &dsp2; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; -- cgit v1.2.3-70-g09d2 From 0ed073c218ee1b4dbf13f89707003cb3a2ee3d94 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:32 +0300 Subject: ARM: dts: DRA72x: Add aliases for rproc nodes Add aliases for all the 3 remote processor nodes common to all DRA72x/DRA71x/AM571x/AM570x boards. The aliases uses the stem "rproc", and are defined in the order of the most common processors on the DRA72x family. The ids are same as DRA74x except for the missing DSP2. The aliases can be overridden, if needed, in the respective derivative board dts files. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index da334489b18f..ae23ec14e8fa 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -10,6 +10,12 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; -- cgit v1.2.3-70-g09d2 From a11a2f73b32d01ac204f861709dc32f6d29ec806 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:33 +0300 Subject: ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files The System Mailboxes 5 and 6 and their corresponding child sub-mailbox (IPC 3.x) nodes are enabled in each of the DRA7xx and AM57xx board dts files individually at present. These mailboxes enable the Remote Processor Messaging (RPMsg) communication stack between the MPU host processor and each of the IPU1, IPU2, DSP1 and DSP2 remote processors. Move these nodes into two common dtsi files - dra7-ipu-dsp-common and dra74-ipu-dsp-common files, which are then included in various board dts files. These files can be used to add all the common configuration properties (except memory data) required by remote processor nodes. The memory pools and the remote processor nodes themselves are to be enabled in the actual board dts files. The first file is to used by platforms using DRA72x/DRA71x/AM571x/AM570x SoCs, and the second file is to be used by platforms using DRA74x/DRA76x/AM572x/AM574x SoCs. The second file includes the first file and contains additional data only applicable for DSP2 remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am571x-idk.dts | 18 +----------------- arch/arm/boot/dts/am572x-idk-common.dtsi | 21 +-------------------- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 21 +-------------------- arch/arm/boot/dts/dra7-evm-common.dtsi | 1 + arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/dra72-evm-common.dtsi | 18 +----------------- arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 12 ++++++++++++ 7 files changed, 38 insertions(+), 74 deletions(-) create mode 100644 arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi create mode 100644 arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 669559c9c95b..98f12231728a 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -10,6 +10,7 @@ #include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" #include "am57xx-idk-common.dtsi" +#include "dra7-ipu-dsp-common.dtsi" / { model = "TI AM5718 IDK"; @@ -148,23 +149,6 @@ load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index ddf123620e96..06f51f5239f0 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -6,6 +6,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra74-ipu-dsp-common.dtsi" / { memory@0 { @@ -146,23 +147,3 @@ status = "okay"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index a813a0cf3ff3..33bb89eee658 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -7,6 +7,7 @@ #include "am5728.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" #include #include @@ -583,23 +584,3 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 23244b5a9942..f89a64cbcd53 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "dra74-ipu-dsp-common.dtsi" #include #include #include diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..478a07e29538 --- /dev/null +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA7xx/AM57xx platforms + */ + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 01558a86af82..c84b63bf0fc8 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "dra72x.dtsi" +#include "dra7-ipu-dsp-common.dtsi" #include #include @@ -583,23 +584,6 @@ rx-num-evt = <32>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; }; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..645063d0df13 --- /dev/null +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms + */ + +#include "dra7-ipu-dsp-common.dtsi" + +&mailbox6 { + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; -- cgit v1.2.3-70-g09d2 From 5e89b39049a6f14f49edbf95ff86290c3109a27a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:34 +0300 Subject: ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes Add the required 'mboxes' property to all the IPU and DSP remote processors (IPU1, IPU2, DSP1 and DSP2) in the two available common dtsi files - dra7-ipu-dsp-common and dra74-ipu-dsp-common dtsi files. The latter file is for platforms having DRA74x/DRA76x/AM572x/AM574x SoCs which do have a DSP2 processor in addition to the other common remote processors. The common data is added to the former file, and the DSP2 only data is added to the latter file. The mailboxes are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the remote processors. Each of the remote processors uses a single sub-mailbox node, the IPUs are assumed to be running in SMP-mode. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 12 ++++++++++++ arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 4 ++++ 2 files changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index 478a07e29538..8a53da1c5f2e 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -19,3 +19,15 @@ status = "okay"; }; }; + +&ipu2 { + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; +}; + +&ipu1 { + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; +}; + +&dsp1 { + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; +}; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index 645063d0df13..6e31c1c27fd4 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -10,3 +10,7 @@ status = "okay"; }; }; + +&dsp2 { + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; +}; -- cgit v1.2.3-70-g09d2 From d329f9f14d6f125d5740049d6806b6e9c005e0ea Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:35 +0300 Subject: ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes The BIOS System Tick timers have been added for all the IPU and DSP remoteproc devices in the DRA7 SoC family. The data is added to the two common dra7-ipu-dsp-common and dra74-ipu-dsp-common dtsi files that are included by all the desired board files. The following timers are chosen, as per the timers used on the current firmware images: IPU2: GPTimer 3 IPU1: GPTimer 11 DSP1: GPTimer 5 DSP2: GPTimer 6 The timers are optional, but are mandatory to support advanced device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, if needed. Each of the IPUs has two Cortex-M4 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 3 +++ arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 1 + 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index 8a53da1c5f2e..23ce3b67faf7 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -22,12 +22,15 @@ &ipu2 { mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + ti,timers = <&timer3>; }; &ipu1 { mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + ti,timers = <&timer11>; }; &dsp1 { mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + ti,timers = <&timer5>; }; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index 6e31c1c27fd4..a546cf740365 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -13,4 +13,5 @@ &dsp2 { mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + ti,timers = <&timer6>; }; -- cgit v1.2.3-70-g09d2 From 371cddbd5f0f30075eb4de6ace719f81f3586a73 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:36 +0300 Subject: ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs The CMA reserved memory nodes have been added for all the IPU and DSP remoteproc devices on DRA7 EVM board. These nodes are assigned to the respective rproc device nodes, and all the IPU and DSP remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 54 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index af06a55d1c5c..7aeb30daf3b8 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -35,6 +35,40 @@ regulator-max-microvolt = <1800000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; @@ -537,3 +571,23 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; -- cgit v1.2.3-70-g09d2 From 791cc4e40f2806f22c5f7ce26adec85ac4f52dc2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:37 +0300 Subject: ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs The CMA reserved memory nodes have been added for both the IPUs and the DSP1 remoteproc devices on DRA72 EVM board. These nodes are assigned to the respective rproc device nodes, and both the IPUs and the DSP1 remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The addresses chosen are the same as the respective processors on the DRA7 EVM board to maintain firmware compatibility between the two boards. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72-evm.dts | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 9adb77585ef1..951152fe206a 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -12,6 +12,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -78,3 +105,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; -- cgit v1.2.3-70-g09d2 From 81fe00fa4e5bcf778d5ea0439a4931de1c259d78 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:38 +0300 Subject: ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs The CMA reserved memory nodes have been added for both the IPUs and the DSP1 remoteproc devices on the DRA72 EVM rev C board, and assigned to the respective rproc device nodes. These match the configuration used on the DRA72 EVM board. Both the CMA nodes and the corresponding rproc nodes are also enabled to enable these processors on the DRA72 EVM rev C board. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra72-evm-revc.dts | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 2bb2e8be6276..6e70858f6313 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -14,6 +14,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -113,3 +140,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; -- cgit v1.2.3-70-g09d2 From f09862d537367eaab1cf52953786992de3aa0c28 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:39 +0300 Subject: ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs The CMA reserved memory nodes have been added for both the IPUs and the DSP1 remoteproc devices on DRA71 EVM board. These nodes are assigned to the respective rproc device nodes, and both the IPUs and the DSP1 remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The addresses chosen are the same as the respective processors on the DRA72 EVM board to maintain firmware compatibility between the two boards. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra71-evm.dts | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index fabeb7704753..a5d275ea7bd3 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -17,6 +17,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { compatible = "regulator-gpio"; @@ -270,3 +297,18 @@ &extcon_usb2 { vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; -- cgit v1.2.3-70-g09d2 From 101a29dd31b15aca958b1b6fa4c8452d56e58f5b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:40 +0300 Subject: ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs The CMA reserved memory nodes have been added for all the IPU and the DSP remoteproc devices on the DRA76 EVM board, and assigned to the respective rproc device nodes. These match the configuration used on the DRA7 EVM board. Both the CMA nodes and the corresponding rproc nodes are also enabled to enable these processors on the DRA76 EVM board. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra76-evm.dts | 54 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index e958cb3d1b31..820a0ece20d4 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -25,6 +25,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vsys_12v0: fixedregulator-vsys12v0 { /* main supply */ compatible = "regulator-fixed"; @@ -548,3 +582,23 @@ data-lanes = <1 2>; }; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; +}; -- cgit v1.2.3-70-g09d2 From 35529cc009967c7fe3cb96da8f2b31bd966f6e14 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:41 +0300 Subject: ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs The CMA reserved memory nodes have been added for all the IPU and DSP remoteproc devices on all the AM57xx BeagleBoard-X15 boards. These nodes are assigned to the respective rproc device nodes, and all the IPU and DSP remote processors are enabled for all these boards. The current CMA pools and sizes are defined statically for each device. The addresses chosen are the same as the respective processors on the DRA7 EVM board to maintain firmware compatibility between the two boards. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index 33bb89eee658..9cfdc29c283d 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -51,6 +51,40 @@ regulator-boot-on; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vdd_3v3: fixedregulator-vdd_3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; @@ -584,3 +618,23 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; -- cgit v1.2.3-70-g09d2 From ac21a4a8f263d155c31f56b23bd056e71e75e7a6 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:42 +0300 Subject: ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs The CMA reserved memory nodes have been added for all the IPU and DSP remoteproc devices in the am572x-idk-common.dtsi file that is common to both the AM572x and AM574x IDK boards. These nodes are assigned to the respective rproc device nodes, and all the IPU and DSP remote processors are enabled. The current CMA pools and sizes are defined statically for each device. The addresses chosen are the same as the respective processors on the AM57xx EVM board to maintain firmware compatibility between the two boards. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am572x-idk-common.dtsi | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi index 06f51f5239f0..37ce2d7c4173 100644 --- a/arch/arm/boot/dts/am572x-idk-common.dtsi +++ b/arch/arm/boot/dts/am572x-idk-common.dtsi @@ -14,6 +14,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + status-leds { compatible = "gpio-leds"; cpu0-led { @@ -147,3 +181,23 @@ status = "okay"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; -- cgit v1.2.3-70-g09d2 From c2a5678e3017437c7c48fda0cbce1ec4136e2573 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:43 +0300 Subject: ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs The CMA reserved memory nodes have been added for both the IPUs and the DSP1 remoteproc devices on the AM571x IDK board. These nodes are assigned to the respective rproc device nodes, and both the IPUs and the DSP1 remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The addresses chosen are the same as the respective processors on the DRA72 EVM board to maintain firmware compatibility between the two boards. The CMA pools and sizes are defined using 64-bit values to support LPAE. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and this will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am571x-idk.dts | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 98f12231728a..62eb2b6ff10b 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -21,6 +21,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + leds { compatible = "gpio-leds"; cpu0-led { @@ -149,6 +176,21 @@ load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + &pcie1_rc { status = "okay"; gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3-70-g09d2 From 1f15980525c6425125678fc97ea8b4b1ee4cb86e Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 24 Apr 2020 18:12:44 +0300 Subject: ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes The watchdog timer information has been added to all the IPU and DSP remote processor device nodes in the DRA7xx/AM57xx SoC families. The data has been added to the two common dra7-ipu-dsp-common and dra74-ipu-dsp-common dtsi files that can be included by all the desired board files. The following timers are chosen as the watchdog timers, as per the usage on the current firmware images: IPU2: GPTimers 4 & 9 (one for each Cortex-M4 core) IPU1: GPTimers 7 & 8 (one for each Cortex-M4 core) DSP1: GPTimer 10 DSP2: GPTimer 13 Each of the IPUs has two Cortex-M4 processors and so uses a timer each for providing watchdog support on that processor irrespective of whether the IPU is running in SMP-mode or non-SMP node. The chosen timers also need to be unique from the ones used by other processors (regular timers or watchdog timers) so that they can be supported simultaneously. The MPU-side drivers will use this data to initialize the watchdog timer(s), and listen for any watchdog triggers. The BIOS-side code on these processors needs to configure/refresh the corresponding timer properly to not throw a watchdog error. The watchdog timers are optional in general, but are mandatory to be added to support watchdog error recovery on a particular processor. These timers can be changed or removed as per the system integration needs, alongside appropriate equivalent changes on the firmware side. Signed-off-by: Angela Stegmaier Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi | 3 +++ arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi | 1 + 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi index 23ce3b67faf7..a25749a1c365 100644 --- a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi @@ -23,14 +23,17 @@ &ipu2 { mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; ti,timers = <&timer3>; + ti,watchdog-timers = <&timer4>, <&timer9>; }; &ipu1 { mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; ti,timers = <&timer11>; + ti,watchdog-timers = <&timer7>, <&timer8>; }; &dsp1 { mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; ti,timers = <&timer5>; + ti,watchdog-timers = <&timer10>; }; diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi index a546cf740365..b1147a4b77f9 100644 --- a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi +++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi @@ -14,4 +14,5 @@ &dsp2 { mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; ti,timers = <&timer6>; + ti,watchdog-timers = <&timer13>; }; -- cgit v1.2.3-70-g09d2 From f9cd51bf6d1c23e1aae8c74a44b4e26d66fa164f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:29:57 +0300 Subject: ARM: dts: omap5: add aes1 entry OMAP5 has AES hardware cryptographic accelerator, add AES1 instance for it. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2ac7f021c284..30391dbc7f8f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -247,6 +247,35 @@ hw-caps-temp-alert; }; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc -- cgit v1.2.3-70-g09d2 From 4b9882ae4d2850e9aec91b73b8bf2cbf21f0bea2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:29:58 +0300 Subject: ARM: dts: omap5: add aes2 entry OMAP5 has AES hardware cryptographic accelerator, add AES2 instance for it. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 30391dbc7f8f..007911685cd9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -276,6 +276,35 @@ }; }; + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc -- cgit v1.2.3-70-g09d2 From bf755817f82ac51dbabd3e2733a2f28a240bd280 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:29:59 +0300 Subject: ARM: dts: omap5: add SHA crypto accelerator node Add the single available SHA crypto accelerator device for OMAP5 SoC. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 007911685cd9..5e74f441c7e5 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -305,6 +305,34 @@ }; }; + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc -- cgit v1.2.3-70-g09d2 From 189a8739cc7235f1a6da141439aa8ece72c9f4d2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:30:00 +0300 Subject: ARM: dts: omap5: add DES crypto accelerator node OMAP5 contains a single DES crypto accelerator instance. Add node for this in DT to enable it. We keep the node disabled for now, as it appears OMAP5 platform is running out of available DMA channels, and DES is the least interesting crypto accelerator available on the device. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f68740abb8aa..55999655a3bc 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1003,6 +1003,7 @@ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a5000 0x000a5000 0x001000>, <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ @@ -1908,6 +1909,36 @@ <0x00001000 0x000a5000 0x00001000>; }; + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + status = "disabled"; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ compatible = "ti,sysc"; status = "disabled"; -- cgit v1.2.3-70-g09d2 From f18e314a6bf1b7bdbc6f5af1d6dbda11bc2dd35b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:30:01 +0300 Subject: ARM: OMAP4: Make L4SEC clock domain SWSUP only Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP4, so do the same change for OMAP4 also. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 6005c4ed3bc6..8285be7c1eab 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -214,7 +214,7 @@ static struct clockdomain l4_secure_44xx_clkdm = { .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4_secure_wkup_sleep_deps, .sleepdep_srcs = l4_secure_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4_per_44xx_clkdm = { -- cgit v1.2.3-70-g09d2 From e88ba436e5615f5bb94deecbbb924227b15bbebb Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 29 Apr 2020 17:30:02 +0300 Subject: ARM: OMAP5: Make L4SEC clock domain SWSUP only Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only') made DRA7 SoC L4SEC clock domain SWSUP only because of power state transition issues detected with HWSUP mode. Based on experimentation similar issue exists on OMAP5, so do the same change for OMAP5 also. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomains54xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c index 3ab41fc89dd3..5611e08018a2 100644 --- a/arch/arm/mach-omap2/clockdomains54xx_data.c +++ b/arch/arm/mach-omap2/clockdomains54xx_data.c @@ -170,7 +170,7 @@ static struct clockdomain l4sec_54xx_clkdm = { .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4sec_wkup_sleep_deps, .sleepdep_srcs = l4sec_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain iva_54xx_clkdm = { -- cgit v1.2.3-70-g09d2 From 38d6d848845ebbbe8f3354a972e815a073bb61f7 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 8 Apr 2020 23:44:07 -0700 Subject: ARM: Remove redundant COMMON_CLK selects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mulitplatform config already selects COMMON_CLK, so selecting it again is not useful. Remove these selects from ARM platforms that are part of the multiplatform build. Reviewed-by: "Andreas Färber" # actions Acked-by: Manivannan Sadhasivam # actions Cc: Russell King Cc: Alexander Shiyan Cc: Lubomir Rintel Cc: Cc: Arnd Bergmann Signed-off-by: Stephen Boyd Reviewed-by: Arnd Bergmann Link: https://lkml.kernel.org/r/20200409064416.83340-2-sboyd@kernel.org --- arch/arm/mach-actions/Kconfig | 1 - arch/arm/mach-clps711x/Kconfig | 1 - arch/arm/mach-mmp/Kconfig | 1 - 3 files changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig index b5e0ac965ec0..00fb4babccdd 100644 --- a/arch/arm/mach-actions/Kconfig +++ b/arch/arm/mach-actions/Kconfig @@ -7,7 +7,6 @@ menuconfig ARCH_ACTIONS select ARM_GLOBAL_TIMER select CACHE_L2X0 select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK - select COMMON_CLK select GENERIC_IRQ_CHIP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index fc9188b54dd6..ba497a2032e9 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -5,7 +5,6 @@ menuconfig ARCH_CLPS711X select AUTO_ZRELADDR select TIMER_OF select CLPS711X_TIMER - select COMMON_CLK select CPU_ARM720T select GENERIC_CLOCKEVENTS select GPIOLIB diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b58a03b18bde..6fe1550f43ec 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -110,7 +110,6 @@ config MACH_MMP_DT depends on ARCH_MULTI_V5 select PINCTRL select PINCTRL_SINGLE - select COMMON_CLK select ARCH_HAS_RESET_CONTROLLER select CPU_MOHAWK help -- cgit v1.2.3-70-g09d2 From e8bd633bc05278ffb4f4ad39050bd9a33acca947 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 8 Apr 2020 23:44:08 -0700 Subject: ARM: Remove redundant CLKDEV_LOOKUP selects These platforms select COMMON_CLK indirectly through use of the ARCH_MULTIPLATFORM config option that they depend on implicitly via some V7/V6/V5 multi platform config option. The COMMON_CLK config option already selects CLKDEV_LOOKUP so it's redundant to have this selected again. Cc: Tony Prisk Cc: Russell King Cc: Cc: Arnd Bergmann Signed-off-by: Stephen Boyd Reviewed-by: Arnd Bergmann Link: https://lkml.kernel.org/r/20200409064416.83340-3-sboyd@kernel.org --- arch/arm/Kconfig | 3 --- arch/arm/mach-vt8500/Kconfig | 1 - 2 files changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 66a04f6f4775..6b56a4bc3b9f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -434,7 +434,6 @@ config ARCH_PXA select ARM_CPU_SUSPEND if PM select AUTO_ZRELADDR select COMMON_CLK - select CLKDEV_LOOKUP select CLKSRC_PXA select CLKSRC_MMIO select TIMER_OF @@ -473,7 +472,6 @@ config ARCH_SA1100 bool "SA1100-based" select ARCH_MTD_XIP select ARCH_SPARSEMEM_ENABLE - select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_PXA select TIMER_OF if OF @@ -494,7 +492,6 @@ config ARCH_SA1100 config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" select ATAGS - select CLKDEV_LOOKUP select CLKSRC_SAMSUNG_PWM select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig index 8841199058ea..d01cdd9ad9c7 100644 --- a/arch/arm/mach-vt8500/Kconfig +++ b/arch/arm/mach-vt8500/Kconfig @@ -2,7 +2,6 @@ config ARCH_VT8500 bool select GPIOLIB - select CLKDEV_LOOKUP select VT8500_TIMER select PINCTRL help -- cgit v1.2.3-70-g09d2 From bbd7ffdbef6888459f301c5889f3b14ada38b913 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 8 Apr 2020 23:44:13 -0700 Subject: clk: Allow the common clk framework to be selectable Enable build testing and configuration control of the common clk framework so that more code coverage and testing can be done on the common clk framework across various architectures. This also nicely removes the requirement that architectures must select the framework when they don't use it in architecture code. There's one snag with doing this, and that's making sure that randconfig builds don't select this option when some architecture or platform implements 'struct clk' outside of the common clk framework. Introduce a new config option 'HAVE_LEGACY_CLK' to indicate those platforms that haven't migrated to the common clk framework and therefore shouldn't be allowed to select this new config option. Also add a note that we hope one day to remove this config entirely. Based on a patch by Mark Brown . Cc: Mark Brown Cc: Geert Uytterhoeven Cc: Mark Salter Cc: Aurelien Jacquiot Cc: Jiaxun Yang Cc: Guan Xuetao Cc: Russell King Cc: Arnd Bergmann Cc: Yoshinori Sato Cc: Rich Felker Cc: Thomas Bogendoerfer Cc: Cc: Cc: Cc: Cc: Link: https://lore.kernel.org/r/1470915049-15249-1-git-send-email-broonie@kernel.org Signed-off-by: Stephen Boyd Link: https://lkml.kernel.org/r/20200409064416.83340-8-sboyd@kernel.org Reviewed-by: Mark Brown Reviewed-by: Arnd Bergmann --- arch/arm/Kconfig | 2 ++ arch/c6x/Kconfig | 1 + arch/m68k/Kconfig.cpu | 2 +- arch/mips/Kconfig | 5 +++-- arch/mips/loongson2ef/Kconfig | 2 +- arch/mips/ralink/Kconfig | 4 ++++ arch/sh/boards/Kconfig | 5 +++++ arch/unicore32/Kconfig | 2 +- drivers/clk/Kconfig | 17 +++++++++++++---- 9 files changed, 31 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b56a4bc3b9f..6e15460cf1f2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -363,6 +363,7 @@ config ARCH_EP93XX select CPU_ARM920T select GENERIC_CLOCKEVENTS select GPIOLIB + select HAVE_LEGACY_CLK help This enables support for the Cirrus EP93xx series of CPUs. @@ -521,6 +522,7 @@ config ARCH_OMAP1 select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_IDE + select HAVE_LEGACY_CLK select IRQ_DOMAIN select NEED_MACH_IO_H if PCCARD select NEED_MACH_MEMORY_H diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig index e65e8d82442a..6444ebfd06a6 100644 --- a/arch/c6x/Kconfig +++ b/arch/c6x/Kconfig @@ -11,6 +11,7 @@ config C6X select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE select CLKDEV_LOOKUP + select HAVE_LEGACY_CLK select GENERIC_ATOMIC64 select GENERIC_IRQ_SHOW select HAVE_ARCH_TRACEHOOK diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 60ac1cd8b96f..bd2d29c22a10 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu @@ -28,7 +28,7 @@ config COLDFIRE select CPU_HAS_NO_MULDIV64 select GENERIC_CSUM select GPIOLIB - select HAVE_CLK + select HAVE_LEGACY_CLK endchoice diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4386bac2c7ac..da7530689a8b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -181,7 +181,7 @@ config AR7 select SYS_SUPPORTS_ZBOOT_UART16550 select GPIOLIB select VLYNQ - select HAVE_CLK + select HAVE_LEGACY_CLK help Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. @@ -296,9 +296,9 @@ config BCM63XX select SYS_HAS_EARLY_PRINTK select SWAP_IO_SPACE select GPIOLIB - select HAVE_CLK select MIPS_L1_CACHE_SHIFT_4 select CLKDEV_LOOKUP + select HAVE_LEGACY_CLK help Support for BCM63XX based boards @@ -419,6 +419,7 @@ config LANTIQ select SWAP_IO_SPACE select BOOT_RAW select CLKDEV_LOOKUP + select HAVE_LEGACY_CLK select USE_OF select PINCTRL select PINCTRL_LANTIQ diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig index 595dd48e1e4d..c9ec43afde73 100644 --- a/arch/mips/loongson2ef/Kconfig +++ b/arch/mips/loongson2ef/Kconfig @@ -46,7 +46,7 @@ config LEMOTE_MACH2F select CSRC_R4K if ! MIPS_EXTERNAL_TIMER select DMA_NONCOHERENT select GENERIC_ISA_DMA_SUPPORT_BROKEN - select HAVE_CLK + select HAVE_LEGACY_CLK select FORCE_PCI select I8259 select IRQ_MIPS_CPU diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 35c2ebd8f094..c10d8b233ab1 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -27,18 +27,22 @@ choice config SOC_RT288X bool "RT288x" select MIPS_L1_CACHE_SHIFT_4 + select HAVE_LEGACY_CLK select HAVE_PCI config SOC_RT305X bool "RT305x" + select HAVE_LEGACY_CLK config SOC_RT3883 bool "RT3883" + select HAVE_LEGACY_CLK select HAVE_PCI config SOC_MT7620 bool "MT7620/8" select CPU_MIPSR2_IRQ_VI + select HAVE_LEGACY_CLK select HAVE_PCI config SOC_MT7621 diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index cee24c308337..fb0ca0c1efe1 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -7,6 +7,11 @@ config SOLUTION_ENGINE config SH_ALPHA_BOARD bool +config SH_CUSTOM_CLK + def_bool y + depends on !SH_DEVICE_TREE + select HAVE_LEGACY_CLK + config SH_DEVICE_TREE bool select OF diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig index 41fe944005f8..11ba1839d198 100644 --- a/arch/unicore32/Kconfig +++ b/arch/unicore32/Kconfig @@ -70,7 +70,7 @@ config ARCH_PUV3 def_bool y select CPU_UCV2 select GENERIC_CLOCKEVENTS - select HAVE_CLK + select HAVE_LEGACY_CLK select GPIOLIB # CONFIGs for ARCH_PUV3 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index bcb257baed06..890bed62196d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -7,8 +7,18 @@ config CLKDEV_LOOKUP config HAVE_CLK_PREPARE bool -config COMMON_CLK +config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated bool + select HAVE_CLK + help + Select this option when the clock API in is implemented + by platform/architecture code. This method is deprecated. Modern + code should select COMMON_CLK instead and not define a custom + 'struct clk'. + +menuconfig COMMON_CLK + bool "Common Clock Framework" + depends on !HAVE_LEGACY_CLK select HAVE_CLK_PREPARE select CLKDEV_LOOKUP select SRCU @@ -20,8 +30,7 @@ config COMMON_CLK Architectures utilizing the common struct clk should select this option. -menu "Common Clock Framework" - depends on COMMON_CLK +if COMMON_CLK config COMMON_CLK_WM831X tristate "Clock driver for WM831x/2x PMICs" @@ -362,4 +371,4 @@ source "drivers/clk/ti/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/zynqmp/Kconfig" -endmenu +endif -- cgit v1.2.3-70-g09d2 From 36dc3b1a7e9dd332d224cc187acdaa9f2023a1f1 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 25 Mar 2020 01:43:33 +0300 Subject: ARM: tegra: Initialize r0 register for firmware wake-up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Downstream kernel of ASUS TF300T sets r0 to #3. There is no explanation in downstream code whether this is really needed and some of T30 downstream kernels have and explicit comment telling that all arguments are ignored by firmware. Let's take a safe side by replicating behavior of the TF300T downstream kernel. This change works fine on Ouya and Nexus 7 devices. Tested-by: Michał Mirosław Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/reset-handler.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 53123ae4ac3b..06ca44b09381 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -98,7 +98,12 @@ ENTRY(tegra_resume_trusted_foundations) reteq lr .arch_extension sec - /* First call after suspend wakes firmware. No arguments required. */ + /* + * First call after suspend wakes firmware. No arguments required + * for some firmware versions. Downstream kernel of ASUS TF300T uses + * r0=3 for the wake-up notification. + */ + mov r0, #3 smc #0 b cpu_resume -- cgit v1.2.3-70-g09d2 From 38743e414e7cc6d23f41276f298ad4781890a89f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 25 Mar 2020 01:43:34 +0300 Subject: ARM: tegra: Do not fully reinitialize L2 on resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ASUS TF300T device may not work properly if firmware is asked to fully re-initialize L2 cache after resume from LP2 suspend. The downstream kernel of TF300T uses different opcode to enable cache after resuming from LP2, this opcode also works fine on Nexus 7 and Ouya devices. Supposedly, this may be needed by an older firmware versions. Reported-by: Michał Mirosław Tested-by: Michał Mirosław Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/pm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index d1e1a61b12cf..6452ebf68d40 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -216,6 +216,8 @@ int tegra_pm_enter_lp2(void) restore_cpu_complex(); cpu_cluster_pm_exit(); + call_firmware_op(prepare_idle, TF_PM_MODE_NONE); + return err; } @@ -391,6 +393,8 @@ static int tegra_suspend_enter(suspend_state_t state) local_fiq_enable(); + call_firmware_op(prepare_idle, TF_PM_MODE_NONE); + return 0; } -- cgit v1.2.3-70-g09d2 From 35509737c8f958944e059d501255a0bf18361ba0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 13 Mar 2020 12:01:04 +0300 Subject: ARM: tegra: Correct PL310 Auxiliary Control Register initialization The PL310 Auxiliary Control Register shouldn't have the "Full line of zero" optimization bit being set before L2 cache is enabled. The L2X0 driver takes care of enabling the optimization by itself. This patch fixes a noisy error message on Tegra20 and Tegra30 telling that cache optimization is erroneously enabled without enabling it for the CPU: L2C-310: enabling full line of zeros but not enabled in Cortex-A9 Cc: Signed-off-by: Dmitry Osipenko Tested-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index f1ce2857a251..b620b0651157 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -107,8 +107,8 @@ static const char * const tegra_dt_board_compat[] = { }; DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") - .l2c_aux_val = 0x3c400001, - .l2c_aux_mask = 0xc20fc3fe, + .l2c_aux_val = 0x3c400000, + .l2c_aux_mask = 0xc20fc3ff, .smp = smp_ops(tegra_smp_ops), .map_io = tegra_map_common_io, .init_early = tegra_init_early, -- cgit v1.2.3-70-g09d2 From d3c32c04adfdb6c646722dc5fde1a3d88f293fd4 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:23 +0300 Subject: ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124 The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index e7bcf7dc4675..9942265ed650 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -398,11 +398,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */ -- cgit v1.2.3-70-g09d2 From 04985d00e2c949f81dfdf4d76de97881690c6613 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:24 +0300 Subject: ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30 PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra30.S | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 9942265ed650..2667bcdb5dc6 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -361,7 +361,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC @@ -371,12 +370,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE - pll_locked r1, r0, CLK_RESET_PLLX_BASE + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ tegra_get_soc_id TEGRA_APB_MISC_BASE, r1 cmp r1, #TEGRA30 beq 1f + pll_locked r1, r0, CLK_RESET_PLLX_BASE + ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass str r1, [r0, #CLK_RESET_PLLP_BASE] -- cgit v1.2.3-70-g09d2 From b9bf73aed99ed3170b37fbbf98557c70a6f19e50 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:27 +0300 Subject: ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index b620b0651157..c011359bcdb4 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -96,6 +96,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available()) platform_device_register_simple("tegra-cpuidle", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { -- cgit v1.2.3-70-g09d2 From ae05ddc9b38076c2e4d4ce7363070a7b611eaa39 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:28 +0300 Subject: ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Set min/max voltage and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-beaver.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 45ef6002b225..a143cac22340 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,9 +1806,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1873,22 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; -- cgit v1.2.3-70-g09d2 From 94ea9681a9f5c7a72ae63c015e44a02530927b61 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:29 +0300 Subject: ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index a143cac22340..6b6fd8a8058f 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -2130,4 +2132,26 @@ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; -- cgit v1.2.3-70-g09d2 From 446937a5056fed6c8bea4306eb0249bd5c50ce5e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 1 Apr 2019 20:23:12 -0700 Subject: ARM: mm: Remove virtual address print from B15 RAC driver We would be trying to print the kernel virtual address of the base register address which is not very useful and is not displayed by default because of pointer restriction. Print the Device Tree node name instead which is what was originally intended. Signed-off-by: Florian Fainelli --- arch/arm/mm/cache-b15-rac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index 3471fc64a3ae..bdc07030997b 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -358,8 +358,7 @@ static int __init b15_rac_init(void) set_bit(RAC_ENABLED, &b15_rac_flags); spin_unlock(&rac_lock); - pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n", - b15_rac_base + RAC_CONFIG0_REG); + pr_info("%pOF: Broadcom Brahma-B15 readahead cache\n", dn); goto out; -- cgit v1.2.3-70-g09d2 From 7d4d46ba051bd706fed1aea1f3996d18a2ad1a62 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 6 May 2020 19:48:40 +0200 Subject: ARM: dts: stm32: bump PSCI to version 1.0 on stm32mp15x Declare PSCI v1.0 support instead of v0.1 as the former is supported by the PSCI firmware stacks stm32mp15x relies on. Signed-off-by: Etienne Carriere Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 41fb7b7c4f5b..36f38a95b4de 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -24,10 +24,8 @@ }; psci { - compatible = "arm,psci"; + compatible = "arm,psci-1.0"; method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; }; intc: interrupt-controller@a0021000 { -- cgit v1.2.3-70-g09d2 From 11b08c46333c7e254b18c636769bb9b8a3a3c3c1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:32 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for I2C2 pins Add another mux option for I2C2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index aeddcaadb829..e6f7634eb349 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -408,6 +408,23 @@ }; }; + i2c2_pins_c: i2c2-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_c: i2c2-sleep-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ -- cgit v1.2.3-70-g09d2 From b1c1fe1d43e372212f577c3dfa56937ed0372085 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:33 +0200 Subject: ARM: dts: stm32: Repair I2C2 operation on AV96 The I2C2 uses different pinmux on AV96, use correct pinmux and also add comments about the I2C being present on the "low-speed" expansion connector X6. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 271f38acfeb9..438c2f70813e 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -164,7 +164,7 @@ }; }; -&i2c1 { +&i2c1 { /* X6 I2C1 */ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins_b>; i2c-scl-rising-time-ns = <185>; @@ -174,9 +174,9 @@ /delete-property/dma-names; }; -&i2c2 { +&i2c2 { /* X6 I2C2 */ pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; + pinctrl-0 = <&i2c2_pins_c>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; -- cgit v1.2.3-70-g09d2 From 39be968cb5a14c68568c0eae77abea0f1b9041ca Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:34 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins Add another mux option for FDCAN1 pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e6f7634eb349..becd81091b56 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -773,6 +773,26 @@ }; }; + m_can1_pins_b: m-can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_b: m_can1-sleep-1 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + pwm1_pins_a: pwm1-0 { pins { pinmux = , /* TIM1_CH1 */ -- cgit v1.2.3-70-g09d2 From b0b3a8b7be1eae4e779e595fe17588d68bb23f76 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:35 +0200 Subject: ARM: dts: stm32: Add bindings for FDCAN1 on AV96 Add FDCAN1 bindings to AV96 DT, the FDCAN1 is present on low-speed expansion connector X6. This is disabled by default to match the 96boards specification though. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 438c2f70813e..b5cee5034e64 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -407,6 +407,13 @@ }; }; +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; -- cgit v1.2.3-70-g09d2 From 099318445981321b690ca4b79920d3ef97e9fe40 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:36 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins Add another mux option for FDCAN2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index becd81091b56..61f3cac56063 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -793,6 +793,26 @@ }; }; + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ + }; + }; + pwm1_pins_a: pwm1-0 { pins { pinmux = , /* TIM1_CH1 */ -- cgit v1.2.3-70-g09d2 From c80b9dacdc6c3ed82d5e1a3f246c03f21853b556 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:37 +0200 Subject: ARM: dts: stm32: Add bindings for FDCAN2 on AV96 Add FDCAN2 bindings to AV96 DT, the FDCAN2 is present on low-speed expansion connector X6. This is disabled by default to match the 96boards specification though. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index b5cee5034e64..2a293ed91c9b 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -414,6 +414,13 @@ status = "disabled"; }; +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; -- cgit v1.2.3-70-g09d2 From d56eb118c37b0a422485d0437977509264729845 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:38 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for ADC pins Add another mux option for ADC pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 61f3cac56063..2570253133fd 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -21,6 +21,13 @@ }; }; + adc12_ain_pins_b: adc12-ain-1 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC2 in2 */ + }; + }; + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = , /* ADC12 in18 */ -- cgit v1.2.3-70-g09d2 From 8f92c7565325ed74f8f1440328c78d1b0085d573 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:39 +0200 Subject: ARM: dts: stm32: Add bindings for ADC on AV96 Add ADC bindings to AV96 DT, the ADC inputs are present on low-speed expansion connector X6. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 2a293ed91c9b..72ca282898eb 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -128,6 +128,27 @@ }; }; +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_c>; -- cgit v1.2.3-70-g09d2 From 5afb13616bafce080a2455831325c3e11bec9ba3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:40 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SPI2 pins Add another mux option for SPI2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 2570253133fd..deb4cf4e2ef0 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1559,6 +1559,21 @@ }; }; + spi2_pins_a: spi2-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ -- cgit v1.2.3-70-g09d2 From f572f485898a3a570acf33be6db7e8f02c303751 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Apr 2020 18:37:41 +0200 Subject: ARM: dts: stm32: Add bindings for SPI2 on AV96 Add SPI2 bindings to AV96 DT, the SPI2 IOs are present on low-speed expansion connector X6. This is disabled by default and can be enabled if something is connected there. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-avenger96.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index 72ca282898eb..a9f3ba9da170 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -551,6 +551,15 @@ }; }; +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + &uart4 { /* On Low speed expansion header */ label = "LS-UART1"; -- cgit v1.2.3-70-g09d2 From 4f0f02cc4b5406a3dc0079722aaa01b31c5783f7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:19 +0200 Subject: ARM: omap2plus: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0 Support for TI AM43x SoCs depends on ARCH_MULTI_V7, which selects ARCH_MULTI_V6_V7. As the latter selects MIGHT_HAVE_CACHE_L2X0, there is no need for SOC_AM43XX to select MIGHT_HAVE_CACHE_L2X0. Signed-off-by: Geert Uytterhoeven Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Acked-by: Arnd Bergmann Acked-by: Tony Lindgren Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dca7d06c0b93..ea23205bf70f 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -66,7 +66,6 @@ config SOC_AM43XX select ARCH_OMAP2PLUS select ARM_GIC select MACH_OMAP_GENERIC - select MIGHT_HAVE_CACHE_L2X0 select HAVE_ARM_SCU select GENERIC_CLOCKEVENTS_BROADCAST select HAVE_ARM_TWD -- cgit v1.2.3-70-g09d2 From 2aaba014b55be46affcae78edff356c5e3389081 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Sat, 2 May 2020 11:24:26 -0700 Subject: crypto: lib/sha1 - remove unnecessary includes of linux/cryptohash.h sounds very generic and important, like it's the header to include if you're doing cryptographic hashing in the kernel. But actually it only includes the library implementation of the SHA-1 compression function (not even the full SHA-1). This should basically never be used anymore; SHA-1 is no longer considered secure, and there are much better ways to do cryptographic hashing in the kernel. Most files that include this header don't actually need it. So in preparation for removing it, remove all these unneeded includes of it. Signed-off-by: Eric Biggers Signed-off-by: Herbert Xu --- arch/arm/crypto/sha1_glue.c | 1 - arch/arm/crypto/sha1_neon_glue.c | 1 - arch/arm/crypto/sha256_glue.c | 1 - arch/arm/crypto/sha256_neon_glue.c | 1 - arch/arm/kernel/armksyms.c | 1 - arch/arm64/crypto/sha256-glue.c | 1 - arch/arm64/crypto/sha512-glue.c | 1 - arch/microblaze/kernel/microblaze_ksyms.c | 1 - arch/mips/cavium-octeon/crypto/octeon-md5.c | 1 - arch/powerpc/crypto/md5-glue.c | 1 - arch/powerpc/crypto/sha1-spe-glue.c | 1 - arch/powerpc/crypto/sha256-spe-glue.c | 1 - arch/sparc/crypto/md5_glue.c | 1 - arch/sparc/crypto/sha1_glue.c | 1 - arch/sparc/crypto/sha256_glue.c | 1 - arch/sparc/crypto/sha512_glue.c | 1 - arch/unicore32/kernel/ksyms.c | 1 - arch/x86/crypto/sha1_ssse3_glue.c | 1 - arch/x86/crypto/sha256_ssse3_glue.c | 1 - arch/x86/crypto/sha512_ssse3_glue.c | 1 - drivers/crypto/atmel-sha.c | 1 - drivers/crypto/chelsio/chcr_algo.c | 1 - drivers/crypto/chelsio/chcr_ipsec.c | 1 - drivers/crypto/omap-sham.c | 1 - fs/f2fs/hash.c | 1 - include/net/tcp.h | 1 - lib/crypto/chacha.c | 1 - net/core/secure_seq.c | 1 - net/ipv6/seg6_hmac.c | 1 - 29 files changed, 29 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c index c80b0ebfd02f..4e954b3f7ecd 100644 --- a/arch/arm/crypto/sha1_glue.c +++ b/arch/arm/crypto/sha1_glue.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/crypto/sha1_neon_glue.c b/arch/arm/crypto/sha1_neon_glue.c index 2c3627334335..0071e5e4411a 100644 --- a/arch/arm/crypto/sha1_neon_glue.c +++ b/arch/arm/crypto/sha1_neon_glue.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c index 215497f011f2..b8a4f79020cf 100644 --- a/arch/arm/crypto/sha256_glue.c +++ b/arch/arm/crypto/sha256_glue.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/crypto/sha256_neon_glue.c b/arch/arm/crypto/sha256_neon_glue.c index 38645e415196..79820b9e2541 100644 --- a/arch/arm/crypto/sha256_neon_glue.c +++ b/arch/arm/crypto/sha256_neon_glue.c @@ -11,7 +11,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 98bdea51089d..82e96ac83684 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c index ddf4a0d85c1c..77bc6e72abae 100644 --- a/arch/arm64/crypto/sha256-glue.c +++ b/arch/arm64/crypto/sha256-glue.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm64/crypto/sha512-glue.c b/arch/arm64/crypto/sha512-glue.c index 78d3083de6b7..370ccb29602f 100644 --- a/arch/arm64/crypto/sha512-glue.c +++ b/arch/arm64/crypto/sha512-glue.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c index 92e12c2c2ec1..51c43ee5e380 100644 --- a/arch/microblaze/kernel/microblaze_ksyms.c +++ b/arch/microblaze/kernel/microblaze_ksyms.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c b/arch/mips/cavium-octeon/crypto/octeon-md5.c index d1ed066e1a17..8c8ea139653e 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-md5.c +++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/crypto/md5-glue.c b/arch/powerpc/crypto/md5-glue.c index 7d1bf2fcf668..c24f605033bd 100644 --- a/arch/powerpc/crypto/md5-glue.c +++ b/arch/powerpc/crypto/md5-glue.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/crypto/sha1-spe-glue.c b/arch/powerpc/crypto/sha1-spe-glue.c index 6379990bd604..cb57be4ada61 100644 --- a/arch/powerpc/crypto/sha1-spe-glue.c +++ b/arch/powerpc/crypto/sha1-spe-glue.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/crypto/sha256-spe-glue.c b/arch/powerpc/crypto/sha256-spe-glue.c index 84939e563b81..ceb0b6c980b3 100644 --- a/arch/powerpc/crypto/sha256-spe-glue.c +++ b/arch/powerpc/crypto/sha256-spe-glue.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/sparc/crypto/md5_glue.c b/arch/sparc/crypto/md5_glue.c index 14f6c15be6ae..111283fe837e 100644 --- a/arch/sparc/crypto/md5_glue.c +++ b/arch/sparc/crypto/md5_glue.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/arch/sparc/crypto/sha1_glue.c b/arch/sparc/crypto/sha1_glue.c index 7c1666304441..dc017782be52 100644 --- a/arch/sparc/crypto/sha1_glue.c +++ b/arch/sparc/crypto/sha1_glue.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/arch/sparc/crypto/sha256_glue.c b/arch/sparc/crypto/sha256_glue.c index f403ce9ba6e4..286bc8ecf15b 100644 --- a/arch/sparc/crypto/sha256_glue.c +++ b/arch/sparc/crypto/sha256_glue.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/arch/sparc/crypto/sha512_glue.c b/arch/sparc/crypto/sha512_glue.c index a3b532e43c07..3b2ca732ff7a 100644 --- a/arch/sparc/crypto/sha512_glue.c +++ b/arch/sparc/crypto/sha512_glue.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include diff --git a/arch/unicore32/kernel/ksyms.c b/arch/unicore32/kernel/ksyms.c index f4b84872d640..731445008932 100644 --- a/arch/unicore32/kernel/ksyms.c +++ b/arch/unicore32/kernel/ksyms.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/crypto/sha1_ssse3_glue.c b/arch/x86/crypto/sha1_ssse3_glue.c index a801ffc10cbb..18200135603f 100644 --- a/arch/x86/crypto/sha1_ssse3_glue.c +++ b/arch/x86/crypto/sha1_ssse3_glue.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c index 6394b5fe8db6..dd06249229e1 100644 --- a/arch/x86/crypto/sha256_ssse3_glue.c +++ b/arch/x86/crypto/sha256_ssse3_glue.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/crypto/sha512_ssse3_glue.c b/arch/x86/crypto/sha512_ssse3_glue.c index 82cc1b3ced1d..b0b05c93409e 100644 --- a/arch/x86/crypto/sha512_ssse3_glue.c +++ b/arch/x86/crypto/sha512_ssse3_glue.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c index e536e2a6bbd8..75ccf41a7cb9 100644 --- a/drivers/crypto/atmel-sha.c +++ b/drivers/crypto/atmel-sha.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c index 5d3000fdd5f4..caf1136e7ef9 100644 --- a/drivers/crypto/chelsio/chcr_algo.c +++ b/drivers/crypto/chelsio/chcr_algo.c @@ -44,7 +44,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/crypto/chelsio/chcr_ipsec.c b/drivers/crypto/chelsio/chcr_ipsec.c index 9fd3b9d1ec2f..25bf6d963066 100644 --- a/drivers/crypto/chelsio/chcr_ipsec.c +++ b/drivers/crypto/chelsio/chcr_ipsec.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c index d600c5b3fdd3..063ad5d03f33 100644 --- a/drivers/crypto/omap-sham.c +++ b/drivers/crypto/omap-sham.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include diff --git a/fs/f2fs/hash.c b/fs/f2fs/hash.c index 5bc4dcd8fc03..8c4ea5003ef8 100644 --- a/fs/f2fs/hash.c +++ b/fs/f2fs/hash.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/include/net/tcp.h b/include/net/tcp.h index 5fa9eacd965a..5948c8e4c9e1 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/lib/crypto/chacha.c b/lib/crypto/chacha.c index 65ead6b0c7e0..4ccbec442469 100644 --- a/lib/crypto/chacha.c +++ b/lib/crypto/chacha.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include diff --git a/net/core/secure_seq.c b/net/core/secure_seq.c index 7b6b1d2c3d10..b5bc680d4755 100644 --- a/net/core/secure_seq.c +++ b/net/core/secure_seq.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include diff --git a/net/ipv6/seg6_hmac.c b/net/ipv6/seg6_hmac.c index ffcfcd2b128f..85dddfe3a2c6 100644 --- a/net/ipv6/seg6_hmac.c +++ b/net/ipv6/seg6_hmac.c @@ -34,7 +34,6 @@ #include #include -#include #include #include #include -- cgit v1.2.3-70-g09d2 From a31a8c9cbc0762b096e0b176ba481a60e54db5bf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 May 2020 20:51:29 +0100 Subject: ARM: dts: r8a7742: Add IRQC support Describe the IRQC interrupt controller in the r8a7742 device tree. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 3d3d95678496..06a4241bafd8 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -226,6 +226,20 @@ #power-domain-cells = <1>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7742", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- cgit v1.2.3-70-g09d2 From b2cb7d8d5f0c63615e38bfae2d632faf33aa8601 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 May 2020 20:51:33 +0100 Subject: ARM: dts: r8a7742: Add [H]SCIF{A|B} support Describe [H]SCIF{A|B} ports in the R8A7742 device tree. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588794695-27852-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 155 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 06a4241bafd8..439ff24e7b3a 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -335,6 +335,36 @@ dma-channels = <15>; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + scifa2: serial@e6c60000 { compatible = "renesas,scifa-r8a7742", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -350,6 +380,131 @@ status = "disabled"; }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + mmcif1: mmc@ee220000 { compatible = "renesas,mmcif-r8a7742", "renesas,sh-mmcif"; -- cgit v1.2.3-70-g09d2 From 7fc3b53a7bd6ebfffd22a75f57175b80fa3df834 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 6 May 2020 20:51:35 +0100 Subject: ARM: dts: r8a7742: Add GPIO nodes Describe GPIO blocks in the R8A7742 device tree. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588794695-27852-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742.dtsi | 90 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 439ff24e7b3a..305d8086a3dd 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -200,6 +200,96 @@ #size-cells = <2>; ranges; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a7742"; reg = <0 0xe6060000 0 0x250>; -- cgit v1.2.3-70-g09d2 From 1ca0c2f612116a7159ab11c36b555910f90db338 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 27 Apr 2020 09:30:19 +0900 Subject: kbuild: remove unused AS assignment $(AS) is not used anywhere in the kernel build, hence commit aa824e0c962b ("kbuild: remove AS variable") killed it. Remove the left-over code in arch/{arm,arm64}/Makefile. Signed-off-by: Masahiro Yamada Reviewed-by: Nathan Chancellor Acked-by: Will Deacon --- arch/arm/Makefile | 2 -- arch/arm64/Makefile | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 7d5cd0f85461..cd28211f1418 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -45,12 +45,10 @@ endif ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) KBUILD_CPPFLAGS += -mbig-endian CHECKFLAGS += -D__ARMEB__ -AS += -EB KBUILD_LDFLAGS += -EB else KBUILD_CPPFLAGS += -mlittle-endian CHECKFLAGS += -D__ARMEL__ -AS += -EL KBUILD_LDFLAGS += -EL endif diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 85e4149cc5d5..d86cc9137539 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -84,7 +84,6 @@ KBUILD_CFLAGS += $(branch-prot-flags-y) ifeq ($(CONFIG_CPU_BIG_ENDIAN), y) KBUILD_CPPFLAGS += -mbig-endian CHECKFLAGS += -D__AARCH64EB__ -AS += -EB # Prefer the baremetal ELF build target, but not all toolchains include # it so fall back to the standard linux version if needed. KBUILD_LDFLAGS += -EB $(call ld-option, -maarch64elfb, -maarch64linuxb) @@ -92,7 +91,6 @@ UTS_MACHINE := aarch64_be else KBUILD_CPPFLAGS += -mlittle-endian CHECKFLAGS += -D__AARCH64EL__ -AS += -EL # Same as above, prefer ELF but fall back to linux target if needed. KBUILD_LDFLAGS += -EL $(call ld-option, -maarch64elf, -maarch64linux) UTS_MACHINE := aarch64 -- cgit v1.2.3-70-g09d2 From 90d0ce39f8b088a3f227acd79d79b5ccf5a091b3 Mon Sep 17 00:00:00 2001 From: Ma Feng Date: Mon, 11 May 2020 20:21:44 +0800 Subject: ARM: omap2: make omap5_erratum_workaround_801819 static Fix sparse warning: arch/arm/mach-omap2/omap-smp.c:75:6: warning: symbol 'omap5_erratum_workaround_801819' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: Ma Feng Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 6a82fce3f822..570a987e6d1a 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -72,7 +72,7 @@ void __iomem *omap4_get_scu_base(void) } #ifdef CONFIG_OMAP5_ERRATA_801819 -void omap5_erratum_workaround_801819(void) +static void omap5_erratum_workaround_801819(void) { u32 acr, revidr; u32 acr_mask; -- cgit v1.2.3-70-g09d2 From d33e3d542b6c09a5cb4fa51d82109b2ca92e89c2 Mon Sep 17 00:00:00 2001 From: Samuel Zou Date: Tue, 12 May 2020 10:41:11 +0800 Subject: ARM: OMAP2+: pm33xx-core: Make am43xx_get_rtc_base_addr static Fix the following sparse warning: arch/arm/mach-omap2/pm33xx-core.c:270:14: warning: symbol 'am43xx_get_rtc_base_addr' was not declared. The am43xx_get_rtc_base_addr has only call site within pm33xx-core.c It should be static Fixes: 8c5a916f4c88 ("ARM: OMAP2+: sleep33/43xx: Add RTC-Mode support") Reported-by: Hulk Robot Signed-off-by: Samuel Zou Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm33xx-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index 5455fc98c60e..58236c7dc83e 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -267,7 +267,7 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) return NULL; } -void __iomem *am43xx_get_rtc_base_addr(void) +static void __iomem *am43xx_get_rtc_base_addr(void) { rtc_oh = omap_hwmod_lookup("rtc"); -- cgit v1.2.3-70-g09d2 From e72e8bf1c9847a12de74f2fd3ea1f5511866526b Mon Sep 17 00:00:00 2001 From: Willy Tarreau Date: Tue, 31 Mar 2020 11:40:32 +0200 Subject: floppy: split the base port from the register in I/O accesses Currently we have architecture-specific fd_inb() and fd_outb() functions or macros, taking just a port which is in fact made of a base address and a register. The base address is FDC-specific and derived from the local or global "fdc" variable through the FD_IOPORT macro used in the base address calculation. This change splits this by explicitly passing the FDC's base address and the register separately to fd_outb() and fd_inb(). It affects the following archs: - x86, alpha, mips, powerpc, parisc, arm, m68k: simple remap of port -> base+reg - sparc32: use of reg only, since the base address was already masked out and the FDC controller is known from a static struct. - sparc64: like x86 for PCI, like sparc32 for 82077 Some archs use inline functions and others macros. This was not unified in order to minimize the number of changes to review. For the same reason checkpatch still spews a few warnings about things that were already there before. The parisc still uses hard-coded register values and could be cleaned up by taking the register definitions. The sparc per-controller inb/outb functions could further be refined to explicitly take an FDC register instead of a port in argument but it was not needed yet and may be cleaned later. Link: https://lore.kernel.org/r/20200331094054.24441-2-w@1wt.eu Cc: Ivan Kokshaysky Cc: Richard Henderson Cc: Matt Turner Cc: Ian Molton Cc: Russell King Cc: Geert Uytterhoeven Cc: Thomas Bogendoerfer Cc: Helge Deller Cc: Benjamin Herrenschmidt Cc: "David S. Miller" Cc: x86@kernel.org Signed-off-by: Willy Tarreau Signed-off-by: Denis Efremov --- arch/alpha/include/asm/floppy.h | 4 ++-- arch/arm/include/asm/floppy.h | 8 ++++---- arch/m68k/include/asm/floppy.h | 12 ++++++------ arch/mips/include/asm/mach-generic/floppy.h | 8 ++++---- arch/mips/include/asm/mach-jazz/floppy.h | 8 ++++---- arch/parisc/include/asm/floppy.h | 12 ++++++------ arch/powerpc/include/asm/floppy.h | 4 ++-- arch/sparc/include/asm/floppy_32.h | 4 ++-- arch/sparc/include/asm/floppy_64.h | 4 ++-- arch/x86/include/asm/floppy.h | 4 ++-- drivers/block/floppy.c | 4 ++-- 11 files changed, 36 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/include/asm/floppy.h b/arch/alpha/include/asm/floppy.h index 942924756cf2..8dfdb3aa1d96 100644 --- a/arch/alpha/include/asm/floppy.h +++ b/arch/alpha/include/asm/floppy.h @@ -11,8 +11,8 @@ #define __ASM_ALPHA_FLOPPY_H -#define fd_inb(port) inb_p(port) -#define fd_outb(value,port) outb_p(value,port) +#define fd_inb(base, reg) inb_p((base) + (reg)) +#define fd_outb(value, base, reg) outb_p(value, (base) + (reg)) #define fd_enable_dma() enable_dma(FLOPPY_DMA) #define fd_disable_dma() disable_dma(FLOPPY_DMA) diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h index 79fa327238e8..e1cb04ed5008 100644 --- a/arch/arm/include/asm/floppy.h +++ b/arch/arm/include/asm/floppy.h @@ -9,20 +9,20 @@ #ifndef __ASM_ARM_FLOPPY_H #define __ASM_ARM_FLOPPY_H -#define fd_outb(val,port) \ +#define fd_outb(val, base, reg) \ do { \ int new_val = (val); \ - if (((port) & 7) == FD_DOR) { \ + if ((reg) == FD_DOR) { \ if (new_val & 0xf0) \ new_val = (new_val & 0x0c) | \ floppy_selects[new_val & 3]; \ else \ new_val &= 0x0c; \ } \ - outb(new_val, (port)); \ + outb(new_val, (base) + (reg)); \ } while(0) -#define fd_inb(port) inb((port)) +#define fd_inb(base, reg) inb((base) + (reg)) #define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\ 0,"floppy",NULL) #define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL) diff --git a/arch/m68k/include/asm/floppy.h b/arch/m68k/include/asm/floppy.h index c3b9ad6732fc..2a6ce29b92aa 100644 --- a/arch/m68k/include/asm/floppy.h +++ b/arch/m68k/include/asm/floppy.h @@ -63,21 +63,21 @@ static __inline__ void release_dma_lock(unsigned long flags) } -static __inline__ unsigned char fd_inb(int port) +static __inline__ unsigned char fd_inb(int base, int reg) { if(MACH_IS_Q40) - return inb_p(port); + return inb_p(base + reg); else if(MACH_IS_SUN3X) - return sun3x_82072_fd_inb(port); + return sun3x_82072_fd_inb(base + reg); return 0; } -static __inline__ void fd_outb(unsigned char value, int port) +static __inline__ void fd_outb(unsigned char value, int base, int reg) { if(MACH_IS_Q40) - outb_p(value, port); + outb_p(value, base + reg); else if(MACH_IS_SUN3X) - sun3x_82072_fd_outb(value, port); + sun3x_82072_fd_outb(value, base + reg); } diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h index 9ec2f6a5200b..e3f446d54827 100644 --- a/arch/mips/include/asm/mach-generic/floppy.h +++ b/arch/mips/include/asm/mach-generic/floppy.h @@ -26,14 +26,14 @@ /* * How to access the FDC's registers. */ -static inline unsigned char fd_inb(unsigned int port) +static inline unsigned char fd_inb(unsigned int base, unsigned int reg) { - return inb_p(port); + return inb_p(base + reg); } -static inline void fd_outb(unsigned char value, unsigned int port) +static inline void fd_outb(unsigned char value, unsigned int base, unsigned int reg) { - outb_p(value, port); + outb_p(value, base + reg); } /* diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h index 4b86c88a03b7..095000c290e5 100644 --- a/arch/mips/include/asm/mach-jazz/floppy.h +++ b/arch/mips/include/asm/mach-jazz/floppy.h @@ -17,19 +17,19 @@ #include #include -static inline unsigned char fd_inb(unsigned int port) +static inline unsigned char fd_inb(unsigned int base, unsigned int reg) { unsigned char c; - c = *(volatile unsigned char *) port; + c = *(volatile unsigned char *) (base + reg); udelay(1); return c; } -static inline void fd_outb(unsigned char value, unsigned int port) +static inline void fd_outb(unsigned char value, unsigned int base, unsigned int reg) { - *(volatile unsigned char *) port = value; + *(volatile unsigned char *) (base + reg) = value; } /* diff --git a/arch/parisc/include/asm/floppy.h b/arch/parisc/include/asm/floppy.h index 09b6f4c1687e..1aebc23b7744 100644 --- a/arch/parisc/include/asm/floppy.h +++ b/arch/parisc/include/asm/floppy.h @@ -29,8 +29,8 @@ #define CSW fd_routine[can_use_virtual_dma & 1] -#define fd_inb(port) readb(port) -#define fd_outb(value, port) writeb(value, port) +#define fd_inb(base, reg) readb((base) + (reg)) +#define fd_outb(value, base, reg) writeb(value, (base) + (reg)) #define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy") #define fd_free_dma() CSW._free_dma(FLOPPY_DMA) @@ -75,19 +75,19 @@ static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs) register char *lptr = virtual_dma_addr; for (lcount = virtual_dma_count; lcount; lcount--) { - st = fd_inb(virtual_dma_port+4) & 0xa0 ; + st = fd_inb(virtual_dma_port, 4) & 0xa0; if (st != 0xa0) break; if (virtual_dma_mode) { - fd_outb(*lptr, virtual_dma_port+5); + fd_outb(*lptr, virtual_dma_port, 5); } else { - *lptr = fd_inb(virtual_dma_port+5); + *lptr = fd_inb(virtual_dma_port, 5); } lptr++; } virtual_dma_count = lcount; virtual_dma_addr = lptr; - st = fd_inb(virtual_dma_port+4); + st = fd_inb(virtual_dma_port, 4); } #ifdef TRACE_FLPY_INT diff --git a/arch/powerpc/include/asm/floppy.h b/arch/powerpc/include/asm/floppy.h index 167c44b58848..ed467eb0c4c8 100644 --- a/arch/powerpc/include/asm/floppy.h +++ b/arch/powerpc/include/asm/floppy.h @@ -13,8 +13,8 @@ #include -#define fd_inb(port) inb_p(port) -#define fd_outb(value,port) outb_p(value,port) +#define fd_inb(base, reg) inb_p((base) + (reg)) +#define fd_outb(value, base, reg) outb_p(value, (base) + (reg)) #define fd_enable_dma() enable_dma(FLOPPY_DMA) #define fd_disable_dma() fd_ops->_disable_dma(FLOPPY_DMA) diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h index b519acf4383d..4d08df4f4deb 100644 --- a/arch/sparc/include/asm/floppy_32.h +++ b/arch/sparc/include/asm/floppy_32.h @@ -59,8 +59,8 @@ struct sun_floppy_ops { static struct sun_floppy_ops sun_fdops; -#define fd_inb(port) sun_fdops.fd_inb(port) -#define fd_outb(value,port) sun_fdops.fd_outb(value,port) +#define fd_inb(base, reg) sun_fdops.fd_inb(reg) +#define fd_outb(value, base, reg) sun_fdops.fd_outb(value, reg) #define fd_enable_dma() sun_fd_enable_dma() #define fd_disable_dma() sun_fd_disable_dma() #define fd_request_dma() (0) /* nothing... */ diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h index 3729fc35ba83..c0cf157e5b15 100644 --- a/arch/sparc/include/asm/floppy_64.h +++ b/arch/sparc/include/asm/floppy_64.h @@ -62,8 +62,8 @@ struct sun_floppy_ops { static struct sun_floppy_ops sun_fdops; -#define fd_inb(port) sun_fdops.fd_inb(port) -#define fd_outb(value,port) sun_fdops.fd_outb(value,port) +#define fd_inb(base, reg) sun_fdops.fd_inb((base) + (reg)) +#define fd_outb(value, base, reg) sun_fdops.fd_outb(value, (base) + (reg)) #define fd_enable_dma() sun_fdops.fd_enable_dma() #define fd_disable_dma() sun_fdops.fd_disable_dma() #define fd_request_dma() (0) /* nothing... */ diff --git a/arch/x86/include/asm/floppy.h b/arch/x86/include/asm/floppy.h index 7ec59edde154..20088cb08f5e 100644 --- a/arch/x86/include/asm/floppy.h +++ b/arch/x86/include/asm/floppy.h @@ -31,8 +31,8 @@ #define CSW fd_routine[can_use_virtual_dma & 1] -#define fd_inb(port) inb_p(port) -#define fd_outb(value, port) outb_p(value, port) +#define fd_inb(base, reg) inb_p((base) + (reg)) +#define fd_outb(value, base, reg) outb_p(value, (base) + (reg)) #define fd_request_dma() CSW._request_dma(FLOPPY_DMA, "floppy") #define fd_free_dma() CSW._free_dma(FLOPPY_DMA) diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index c3daa64cb52c..1cda39098b07 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -595,12 +595,12 @@ static unsigned char in_sector_offset; /* offset within physical sector, static inline unsigned char fdc_inb(int fdc, int reg) { - return fd_inb(fdc_state[fdc].address + reg); + return fd_inb(fdc_state[fdc].address, reg); } static inline void fdc_outb(unsigned char value, int fdc, int reg) { - fd_outb(value, fdc_state[fdc].address + reg); + fd_outb(value, fdc_state[fdc].address, reg); } static inline bool drive_no_geom(int drive) -- cgit v1.2.3-70-g09d2 From 3819ad44025fbc03b32d41070b941acea86e6686 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 8 Apr 2020 23:44:14 -0700 Subject: ARM: mmp: Remove legacy clk code Remove all the legacy clk code that supports a non-common clk framework implementation of 'struct clk' in mach-mmp. This code doesn't look to be compiled anymore given that the MMP is fully supported in the multi-platform config via ARCH_MULTIPLATFORM as of commit 377524dc4d77 ("ARM: mmp: move into ARCH_MULTIPLATFORM"). The ARCH_MULTIPLATFORM config selects COMMON_CLK and therefore the Makefile rule can never actually compile the code in these files. Cc: Lubomir Rintel Cc: Russell King Cc: Cc: Arnd Bergmann Signed-off-by: Stephen Boyd Link: https://lkml.kernel.org/r/20200409064416.83340-9-sboyd@kernel.org Reviewed-by: Arnd Bergmann [sboyd@kernel.org: Squash in a clock.h include removal found by Stephen Rothwell ] --- arch/arm/mach-mmp/Makefile | 6 --- arch/arm/mach-mmp/clock-mmp2.c | 114 --------------------------------------- arch/arm/mach-mmp/clock-pxa168.c | 94 -------------------------------- arch/arm/mach-mmp/clock-pxa910.c | 70 ------------------------ arch/arm/mach-mmp/clock.c | 105 ------------------------------------ arch/arm/mach-mmp/clock.h | 65 ---------------------- arch/arm/mach-mmp/pxa168.c | 1 - arch/arm/mach-mmp/time.c | 1 - 8 files changed, 456 deletions(-) delete mode 100644 arch/arm/mach-mmp/clock-mmp2.c delete mode 100644 arch/arm/mach-mmp/clock-pxa168.c delete mode 100644 arch/arm/mach-mmp/clock-pxa910.c delete mode 100644 arch/arm/mach-mmp/clock.c delete mode 100644 arch/arm/mach-mmp/clock.h (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 7b3a7f979eec..e3758f7e1fe7 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -12,12 +12,6 @@ obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o obj-$(CONFIG_MMP_SRAM) += sram.o -ifeq ($(CONFIG_COMMON_CLK), ) -obj-y += clock.o -obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o -obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o -obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o -endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c deleted file mode 100644 index 7536398bf1c1..000000000000 --- a/arch/arm/mach-mmp/clock-mmp2.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -#include "addr-map.h" - -#include "common.h" -#include "clock.h" - -/* - * APB Clock register offsets for MMP2 - */ -#define APBC_RTC APBC_REG(0x000) -#define APBC_TWSI1 APBC_REG(0x004) -#define APBC_TWSI2 APBC_REG(0x008) -#define APBC_TWSI3 APBC_REG(0x00c) -#define APBC_TWSI4 APBC_REG(0x010) -#define APBC_KPC APBC_REG(0x018) -#define APBC_UART1 APBC_REG(0x02c) -#define APBC_UART2 APBC_REG(0x030) -#define APBC_UART3 APBC_REG(0x034) -#define APBC_GPIO APBC_REG(0x038) -#define APBC_PWM0 APBC_REG(0x03c) -#define APBC_PWM1 APBC_REG(0x040) -#define APBC_PWM2 APBC_REG(0x044) -#define APBC_PWM3 APBC_REG(0x048) -#define APBC_SSP0 APBC_REG(0x04c) -#define APBC_SSP1 APBC_REG(0x050) -#define APBC_SSP2 APBC_REG(0x054) -#define APBC_SSP3 APBC_REG(0x058) -#define APBC_SSP4 APBC_REG(0x05c) -#define APBC_SSP5 APBC_REG(0x060) -#define APBC_TWSI5 APBC_REG(0x07c) -#define APBC_TWSI6 APBC_REG(0x080) -#define APBC_UART4 APBC_REG(0x088) - -#define APMU_USB APMU_REG(0x05c) -#define APMU_NAND APMU_REG(0x060) -#define APMU_SDH0 APMU_REG(0x054) -#define APMU_SDH1 APMU_REG(0x058) -#define APMU_SDH2 APMU_REG(0x0e8) -#define APMU_SDH3 APMU_REG(0x0ec) - -static void sdhc_clk_enable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst |= clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -static void sdhc_clk_disable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst &= ~clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -struct clkops sdhc_clk_ops = { - .enable = sdhc_clk_enable, - .disable = sdhc_clk_disable, -}; - -/* APB peripheral clocks */ -static APBC_CLK(uart1, UART1, 1, 26000000); -static APBC_CLK(uart2, UART2, 1, 26000000); -static APBC_CLK(uart3, UART3, 1, 26000000); -static APBC_CLK(uart4, UART4, 1, 26000000); -static APBC_CLK(twsi1, TWSI1, 0, 26000000); -static APBC_CLK(twsi2, TWSI2, 0, 26000000); -static APBC_CLK(twsi3, TWSI3, 0, 26000000); -static APBC_CLK(twsi4, TWSI4, 0, 26000000); -static APBC_CLK(twsi5, TWSI5, 0, 26000000); -static APBC_CLK(twsi6, TWSI6, 0, 26000000); -static APBC_CLK(gpio, GPIO, 0, 26000000); - -static APMU_CLK(nand, NAND, 0xbf, 100000000); -static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); - -static struct clk_lookup mmp2_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), - INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), - INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), - INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL), - INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), -}; - -void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys) -{ - clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); -} diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c deleted file mode 100644 index 2d4a5d96a1ff..000000000000 --- a/arch/arm/mach-mmp/clock-pxa168.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -#include "addr-map.h" - -#include "common.h" -#include "clock.h" - -/* - * APB clock register offsets for PXA168 - */ -#define APBC_UART1 APBC_REG(0x000) -#define APBC_UART2 APBC_REG(0x004) -#define APBC_GPIO APBC_REG(0x008) -#define APBC_PWM1 APBC_REG(0x00c) -#define APBC_PWM2 APBC_REG(0x010) -#define APBC_PWM3 APBC_REG(0x014) -#define APBC_PWM4 APBC_REG(0x018) -#define APBC_RTC APBC_REG(0x028) -#define APBC_TWSI0 APBC_REG(0x02c) -#define APBC_KPC APBC_REG(0x030) -#define APBC_TWSI1 APBC_REG(0x06c) -#define APBC_UART3 APBC_REG(0x070) -#define APBC_SSP1 APBC_REG(0x81c) -#define APBC_SSP2 APBC_REG(0x820) -#define APBC_SSP3 APBC_REG(0x84c) -#define APBC_SSP4 APBC_REG(0x858) -#define APBC_SSP5 APBC_REG(0x85c) - -#define APMU_NAND APMU_REG(0x060) -#define APMU_LCD APMU_REG(0x04c) -#define APMU_ETH APMU_REG(0x0fc) -#define APMU_USB APMU_REG(0x05c) - -/* APB peripheral clocks */ -static APBC_CLK(uart1, UART1, 1, 14745600); -static APBC_CLK(uart2, UART2, 1, 14745600); -static APBC_CLK(uart3, UART3, 1, 14745600); -static APBC_CLK(twsi0, TWSI0, 1, 33000000); -static APBC_CLK(twsi1, TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PWM1, 1, 13000000); -static APBC_CLK(pwm2, PWM2, 1, 13000000); -static APBC_CLK(pwm3, PWM3, 1, 13000000); -static APBC_CLK(pwm4, PWM4, 1, 13000000); -static APBC_CLK(ssp1, SSP1, 4, 0); -static APBC_CLK(ssp2, SSP2, 4, 0); -static APBC_CLK(ssp3, SSP3, 4, 0); -static APBC_CLK(ssp4, SSP4, 4, 0); -static APBC_CLK(ssp5, SSP5, 4, 0); -static APBC_CLK(gpio, GPIO, 0, 13000000); -static APBC_CLK(keypad, KPC, 0, 32000); -static APBC_CLK(rtc, RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(lcd, LCD, 0x7f, 312000000); -static APMU_CLK(eth, ETH, 0x09, 0); -static APMU_CLK(usb, USB, 0x12, 0); - -/* device and clock bindings */ -static struct clk_lookup pxa168_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), - INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), - INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), - INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), - INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), - INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), - INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL), - INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), - INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), - INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - -void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys) -{ - clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); -} diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c deleted file mode 100644 index 3cd83ff91bb0..000000000000 --- a/arch/arm/mach-mmp/clock-pxa910.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -#include "addr-map.h" - -#include "common.h" -#include "clock.h" - -/* - * APB Clock register offsets for PXA910 - */ -#define APBC_UART0 APBC_REG(0x000) -#define APBC_UART1 APBC_REG(0x004) -#define APBC_GPIO APBC_REG(0x008) -#define APBC_PWM1 APBC_REG(0x00c) -#define APBC_PWM2 APBC_REG(0x010) -#define APBC_PWM3 APBC_REG(0x014) -#define APBC_PWM4 APBC_REG(0x018) -#define APBC_SSP1 APBC_REG(0x01c) -#define APBC_SSP2 APBC_REG(0x020) -#define APBC_RTC APBC_REG(0x028) -#define APBC_TWSI0 APBC_REG(0x02c) -#define APBC_KPC APBC_REG(0x030) -#define APBC_SSP3 APBC_REG(0x04c) -#define APBC_TWSI1 APBC_REG(0x06c) - -#define APMU_NAND APMU_REG(0x060) -#define APMU_USB APMU_REG(0x05c) - -static APBC_CLK(uart1, UART0, 1, 14745600); -static APBC_CLK(uart2, UART1, 1, 14745600); -static APBC_CLK(twsi0, TWSI0, 1, 33000000); -static APBC_CLK(twsi1, TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PWM1, 1, 13000000); -static APBC_CLK(pwm2, PWM2, 1, 13000000); -static APBC_CLK(pwm3, PWM3, 1, 13000000); -static APBC_CLK(pwm4, PWM4, 1, 13000000); -static APBC_CLK(gpio, GPIO, 0, 13000000); -static APBC_CLK(rtc, RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(u2o, USB, 0x1b, 480000000); - -/* device and clock bindings */ -static struct clk_lookup pxa910_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL), - INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - -void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, - phys_addr_t apbc_phys, phys_addr_t apbcp_phys) -{ - clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); -} diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c deleted file mode 100644 index 291fe41e3547..000000000000 --- a/arch/arm/mach-mmp/clock.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/clock.c - */ - -#include -#include -#include -#include -#include -#include - -#include "regs-apbc.h" -#include "clock.h" - -static void apbc_clk_enable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); - __raw_writel(clk_rst, clk->clk_rst); -} - -static void apbc_clk_disable(struct clk *clk) -{ - __raw_writel(0, clk->clk_rst); -} - -struct clkops apbc_clk_ops = { - .enable = apbc_clk_enable, - .disable = apbc_clk_disable, -}; - -static void apmu_clk_enable(struct clk *clk) -{ - __raw_writel(clk->enable_val, clk->clk_rst); -} - -static void apmu_clk_disable(struct clk *clk) -{ - __raw_writel(0, clk->clk_rst); -} - -struct clkops apmu_clk_ops = { - .enable = apmu_clk_enable, - .disable = apmu_clk_disable, -}; - -static DEFINE_SPINLOCK(clocks_lock); - -int clk_enable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - if (clk->enabled++ == 0) - clk->ops->enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - if (!clk) - return; - - WARN_ON(clk->enabled == 0); - - spin_lock_irqsave(&clocks_lock, flags); - if (--clk->enabled == 0) - clk->ops->disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long rate; - - if (clk->ops->getrate) - rate = clk->ops->getrate(clk); - else - rate = clk->rate; - - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (clk->ops->setrate) { - spin_lock_irqsave(&clocks_lock, flags); - ret = clk->ops->setrate(clk, rate); - spin_unlock_irqrestore(&clocks_lock, flags); - } - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h deleted file mode 100644 index 0256c894fa11..000000000000 --- a/arch/arm/mach-mmp/clock.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -struct clkops { - void (*enable)(struct clk *); - void (*disable)(struct clk *); - unsigned long (*getrate)(struct clk *); - int (*setrate)(struct clk *, unsigned long); -}; - -struct clk { - const struct clkops *ops; - - void __iomem *clk_rst; /* clock reset control register */ - int fnclksel; /* functional clock select (APBC) */ - uint32_t enable_val; /* value for clock enable (APMU) */ - unsigned long rate; - int enabled; -}; - -extern struct clkops apbc_clk_ops; -extern struct clkops apmu_clk_ops; - -#define APBC_CLK(_name, _reg, _fnclksel, _rate) \ -struct clk clk_##_name = { \ - .clk_rst = APBC_##_reg, \ - .fnclksel = _fnclksel, \ - .rate = _rate, \ - .ops = &apbc_clk_ops, \ -} - -#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ -struct clk clk_##_name = { \ - .clk_rst = APBC_##_reg, \ - .fnclksel = _fnclksel, \ - .rate = _rate, \ - .ops = _ops, \ -} - -#define APMU_CLK(_name, _reg, _eval, _rate) \ -struct clk clk_##_name = { \ - .clk_rst = APMU_##_reg, \ - .enable_val = _eval, \ - .rate = _rate, \ - .ops = &apmu_clk_ops, \ -} - -#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ -struct clk clk_##_name = { \ - .clk_rst = APMU_##_reg, \ - .enable_val = _eval, \ - .rate = _rate, \ - .ops = _ops, \ -} - -#define INIT_CLKREG(_clk, _devname, _conname) \ - { \ - .clk = _clk, \ - .dev_id = _devname, \ - .con_id = _conname, \ - } - -extern struct clk clk_pxa168_gpio; -extern struct clk clk_pxa168_timers; diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index b642e900727a..1e9389245d0e 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -19,7 +19,6 @@ #include #include "addr-map.h" -#include "clock.h" #include "common.h" #include #include "devices.h" diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 049a65f47b42..41b2e8abc9e6 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -34,7 +34,6 @@ #include "regs-apbc.h" #include "irqs.h" #include -#include "clock.h" #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE -- cgit v1.2.3-70-g09d2 From 957743b79b1ebb710f5498b61a212cebc302e685 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Apr 2020 08:22:35 -0700 Subject: ARM: dts: imx6qdl-gw552x: add USB OTG support The GW552x-B board revision adds USB OTG support. Enable the device-tree node and configure the OTG_ID pin. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index dc646b72b59a..bb3597132c62 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -258,6 +258,14 @@ status = "okay"; }; +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -359,6 +367,12 @@ >; }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 -- cgit v1.2.3-70-g09d2 From d06cfe3f123c50449a0c3ece21bc16668289c50f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 29 Apr 2020 15:58:21 -0500 Subject: bus: vexpress-config: Merge vexpress-syscfg into vexpress-config The only thing that vexpress-syscfg does is provide a regmap to vexpress-config bus child devices. There's little reason to have 2 components for this. The current structure with initcall ordering requirements makes turning these components into modules more difficult. So let's start to simplify things and merge vexpress-syscfg into vexpress-config. There's no functional change in this commit and it's still separate components until subsequent commits. Cc: Lorenzo Pieralisi Cc: Linus Walleij Cc: Arnd Bergmann Reviewed-by: Sudeep Holla Acked-by: Greg Kroah-Hartman Acked-by: Liviu Dudau Signed-off-by: Rob Herring --- arch/arm/mach-vexpress/Kconfig | 1 - drivers/bus/vexpress-config.c | 283 +++++++++++++++++++++++++++++++++++++++-- drivers/misc/Kconfig | 9 -- drivers/misc/Makefile | 1 - drivers/misc/vexpress-syscfg.c | 280 ---------------------------------------- include/linux/vexpress.h | 17 --- 6 files changed, 274 insertions(+), 317 deletions(-) delete mode 100644 drivers/misc/vexpress-syscfg.c (limited to 'arch/arm') diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 2d1fdec4c230..065e12991663 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -20,7 +20,6 @@ menuconfig ARCH_VEXPRESS select REGULATOR if MMC_ARMMMCI select REGULATOR_FIXED_VOLTAGE if REGULATOR select VEXPRESS_CONFIG - select VEXPRESS_SYSCFG help This option enables support for systems using Cortex processor based ARM core and logic (FPGA) tiles on the Versatile Express motherboard, diff --git a/drivers/bus/vexpress-config.c b/drivers/bus/vexpress-config.c index ff70575b2db6..43f5beac9811 100644 --- a/drivers/bus/vexpress-config.c +++ b/drivers/bus/vexpress-config.c @@ -6,10 +6,48 @@ #include #include +#include #include +#include #include +#include +#include #include +#define SYS_CFGDATA 0x0 + +#define SYS_CFGCTRL 0x4 +#define SYS_CFGCTRL_START (1 << 31) +#define SYS_CFGCTRL_WRITE (1 << 30) +#define SYS_CFGCTRL_DCC(n) (((n) & 0xf) << 26) +#define SYS_CFGCTRL_FUNC(n) (((n) & 0x3f) << 20) +#define SYS_CFGCTRL_SITE(n) (((n) & 0x3) << 16) +#define SYS_CFGCTRL_POSITION(n) (((n) & 0xf) << 12) +#define SYS_CFGCTRL_DEVICE(n) (((n) & 0xfff) << 0) + +#define SYS_CFGSTAT 0x8 +#define SYS_CFGSTAT_ERR (1 << 1) +#define SYS_CFGSTAT_COMPLETE (1 << 0) + + +struct vexpress_syscfg { + struct device *dev; + void __iomem *base; + struct list_head funcs; +}; + +struct vexpress_syscfg_func { + struct list_head list; + struct vexpress_syscfg *syscfg; + struct regmap *regmap; + int num_templates; + u32 template[]; /* Keep it last! */ +}; + +struct vexpress_config_bridge_ops { + struct regmap * (*regmap_init)(struct device *dev, void *context); + void (*regmap_exit)(struct regmap *regmap, void *context); +}; struct vexpress_config_bridge { struct vexpress_config_bridge_ops *ops; @@ -27,17 +65,12 @@ void vexpress_config_set_master(u32 site) vexpress_config_site_master = site; } -u32 vexpress_config_get_master(void) -{ - return vexpress_config_site_master; -} - -void vexpress_config_lock(void *arg) +static void vexpress_config_lock(void *arg) { mutex_lock(&vexpress_config_mutex); } -void vexpress_config_unlock(void *arg) +static void vexpress_config_unlock(void *arg) { mutex_unlock(&vexpress_config_mutex); } @@ -59,7 +92,7 @@ static void vexpress_config_find_prop(struct device_node *node, } } -int vexpress_config_get_topo(struct device_node *node, u32 *site, +static int vexpress_config_get_topo(struct device_node *node, u32 *site, u32 *position, u32 *dcc) { vexpress_config_find_prop(node, "arm,vexpress,site", site); @@ -113,7 +146,7 @@ struct regmap *devm_regmap_init_vexpress_config(struct device *dev) } EXPORT_SYMBOL_GPL(devm_regmap_init_vexpress_config); -struct device *vexpress_config_bridge_register(struct device *parent, +static struct device *vexpress_config_bridge_register(struct device *parent, struct vexpress_config_bridge_ops *ops, void *context) { struct device *dev; @@ -201,3 +234,235 @@ static int __init vexpress_config_init(void) } postcore_initcall(vexpress_config_init); +static int vexpress_syscfg_exec(struct vexpress_syscfg_func *func, + int index, bool write, u32 *data) +{ + struct vexpress_syscfg *syscfg = func->syscfg; + u32 command, status; + int tries; + long timeout; + + if (WARN_ON(index >= func->num_templates)) + return -EINVAL; + + command = readl(syscfg->base + SYS_CFGCTRL); + if (WARN_ON(command & SYS_CFGCTRL_START)) + return -EBUSY; + + command = func->template[index]; + command |= SYS_CFGCTRL_START; + command |= write ? SYS_CFGCTRL_WRITE : 0; + + /* Use a canary for reads */ + if (!write) + *data = 0xdeadbeef; + + dev_dbg(syscfg->dev, "func %p, command %x, data %x\n", + func, command, *data); + writel(*data, syscfg->base + SYS_CFGDATA); + writel(0, syscfg->base + SYS_CFGSTAT); + writel(command, syscfg->base + SYS_CFGCTRL); + mb(); + + /* The operation can take ages... Go to sleep, 100us initially */ + tries = 100; + timeout = 100; + do { + if (!irqs_disabled()) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(usecs_to_jiffies(timeout)); + if (signal_pending(current)) + return -EINTR; + } else { + udelay(timeout); + } + + status = readl(syscfg->base + SYS_CFGSTAT); + if (status & SYS_CFGSTAT_ERR) + return -EFAULT; + + if (timeout > 20) + timeout -= 20; + } while (--tries && !(status & SYS_CFGSTAT_COMPLETE)); + if (WARN_ON_ONCE(!tries)) + return -ETIMEDOUT; + + if (!write) { + *data = readl(syscfg->base + SYS_CFGDATA); + dev_dbg(syscfg->dev, "func %p, read data %x\n", func, *data); + } + + return 0; +} + +static int vexpress_syscfg_read(void *context, unsigned int index, + unsigned int *val) +{ + struct vexpress_syscfg_func *func = context; + + return vexpress_syscfg_exec(func, index, false, val); +} + +static int vexpress_syscfg_write(void *context, unsigned int index, + unsigned int val) +{ + struct vexpress_syscfg_func *func = context; + + return vexpress_syscfg_exec(func, index, true, &val); +} + +static struct regmap_config vexpress_syscfg_regmap_config = { + .lock = vexpress_config_lock, + .unlock = vexpress_config_unlock, + .reg_bits = 32, + .val_bits = 32, + .reg_read = vexpress_syscfg_read, + .reg_write = vexpress_syscfg_write, + .reg_format_endian = REGMAP_ENDIAN_LITTLE, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + + +static struct regmap *vexpress_syscfg_regmap_init(struct device *dev, + void *context) +{ + int err; + struct vexpress_syscfg *syscfg = context; + struct vexpress_syscfg_func *func; + struct property *prop; + const __be32 *val = NULL; + __be32 energy_quirk[4]; + int num; + u32 site, position, dcc; + int i; + + err = vexpress_config_get_topo(dev->of_node, &site, + &position, &dcc); + if (err) + return ERR_PTR(err); + + prop = of_find_property(dev->of_node, + "arm,vexpress-sysreg,func", NULL); + if (!prop) + return ERR_PTR(-EINVAL); + + num = prop->length / sizeof(u32) / 2; + val = prop->value; + + /* + * "arm,vexpress-energy" function used to be described + * by its first device only, now it requires both + */ + if (num == 1 && of_device_is_compatible(dev->of_node, + "arm,vexpress-energy")) { + num = 2; + energy_quirk[0] = *val; + energy_quirk[2] = *val++; + energy_quirk[1] = *val; + energy_quirk[3] = cpu_to_be32(be32_to_cpup(val) + 1); + val = energy_quirk; + } + + func = kzalloc(struct_size(func, template, num), GFP_KERNEL); + if (!func) + return ERR_PTR(-ENOMEM); + + func->syscfg = syscfg; + func->num_templates = num; + + for (i = 0; i < num; i++) { + u32 function, device; + + function = be32_to_cpup(val++); + device = be32_to_cpup(val++); + + dev_dbg(dev, "func %p: %u/%u/%u/%u/%u\n", + func, site, position, dcc, + function, device); + + func->template[i] = SYS_CFGCTRL_DCC(dcc); + func->template[i] |= SYS_CFGCTRL_SITE(site); + func->template[i] |= SYS_CFGCTRL_POSITION(position); + func->template[i] |= SYS_CFGCTRL_FUNC(function); + func->template[i] |= SYS_CFGCTRL_DEVICE(device); + } + + vexpress_syscfg_regmap_config.max_register = num - 1; + + func->regmap = regmap_init(dev, NULL, func, + &vexpress_syscfg_regmap_config); + + if (IS_ERR(func->regmap)) { + void *err = func->regmap; + + kfree(func); + return err; + } + + list_add(&func->list, &syscfg->funcs); + + return func->regmap; +} + +static void vexpress_syscfg_regmap_exit(struct regmap *regmap, void *context) +{ + struct vexpress_syscfg *syscfg = context; + struct vexpress_syscfg_func *func, *tmp; + + regmap_exit(regmap); + + list_for_each_entry_safe(func, tmp, &syscfg->funcs, list) { + if (func->regmap == regmap) { + list_del(&syscfg->funcs); + kfree(func); + break; + } + } +} + +static struct vexpress_config_bridge_ops vexpress_syscfg_bridge_ops = { + .regmap_init = vexpress_syscfg_regmap_init, + .regmap_exit = vexpress_syscfg_regmap_exit, +}; + + +static int vexpress_syscfg_probe(struct platform_device *pdev) +{ + struct vexpress_syscfg *syscfg; + struct resource *res; + struct device *bridge; + + syscfg = devm_kzalloc(&pdev->dev, sizeof(*syscfg), GFP_KERNEL); + if (!syscfg) + return -ENOMEM; + syscfg->dev = &pdev->dev; + INIT_LIST_HEAD(&syscfg->funcs); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + syscfg->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(syscfg->base)) + return PTR_ERR(syscfg->base); + + /* Must use dev.parent (MFD), as that's where DT phandle points at... */ + bridge = vexpress_config_bridge_register(pdev->dev.parent, + &vexpress_syscfg_bridge_ops, syscfg); + + return PTR_ERR_OR_ZERO(bridge); +} + +static const struct platform_device_id vexpress_syscfg_id_table[] = { + { "vexpress-syscfg", }, + {}, +}; + +static struct platform_driver vexpress_syscfg_driver = { + .driver.name = "vexpress-syscfg", + .id_table = vexpress_syscfg_id_table, + .probe = vexpress_syscfg_probe, +}; + +static int __init vexpress_syscfg_init(void) +{ + return platform_driver_register(&vexpress_syscfg_driver); +} +core_initcall(vexpress_syscfg_init); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 99e151475d8f..edd5dd5ebfdc 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -423,15 +423,6 @@ config SRAM config SRAM_EXEC bool -config VEXPRESS_SYSCFG - bool "Versatile Express System Configuration driver" - depends on VEXPRESS_CONFIG - default y - help - ARM Ltd. Versatile Express uses specialised platform configuration - bus. System Configuration interface is one of the possible means - of generating transactions on this bus. - config PCI_ENDPOINT_TEST depends on PCI select CRC32 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 9abf2923d831..c7bd01ac6291 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_SRAM_EXEC) += sram-exec.o obj-y += mic/ obj-$(CONFIG_GENWQE) += genwqe/ obj-$(CONFIG_ECHO) += echo/ -obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o obj-$(CONFIG_CXL_BASE) += cxl/ obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o obj-$(CONFIG_OCXL) += ocxl/ diff --git a/drivers/misc/vexpress-syscfg.c b/drivers/misc/vexpress-syscfg.c deleted file mode 100644 index a431787c0898..000000000000 --- a/drivers/misc/vexpress-syscfg.c +++ /dev/null @@ -1,280 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * - * Copyright (C) 2014 ARM Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#define SYS_CFGDATA 0x0 - -#define SYS_CFGCTRL 0x4 -#define SYS_CFGCTRL_START (1 << 31) -#define SYS_CFGCTRL_WRITE (1 << 30) -#define SYS_CFGCTRL_DCC(n) (((n) & 0xf) << 26) -#define SYS_CFGCTRL_FUNC(n) (((n) & 0x3f) << 20) -#define SYS_CFGCTRL_SITE(n) (((n) & 0x3) << 16) -#define SYS_CFGCTRL_POSITION(n) (((n) & 0xf) << 12) -#define SYS_CFGCTRL_DEVICE(n) (((n) & 0xfff) << 0) - -#define SYS_CFGSTAT 0x8 -#define SYS_CFGSTAT_ERR (1 << 1) -#define SYS_CFGSTAT_COMPLETE (1 << 0) - - -struct vexpress_syscfg { - struct device *dev; - void __iomem *base; - struct list_head funcs; -}; - -struct vexpress_syscfg_func { - struct list_head list; - struct vexpress_syscfg *syscfg; - struct regmap *regmap; - int num_templates; - u32 template[]; /* Keep it last! */ -}; - - -static int vexpress_syscfg_exec(struct vexpress_syscfg_func *func, - int index, bool write, u32 *data) -{ - struct vexpress_syscfg *syscfg = func->syscfg; - u32 command, status; - int tries; - long timeout; - - if (WARN_ON(index >= func->num_templates)) - return -EINVAL; - - command = readl(syscfg->base + SYS_CFGCTRL); - if (WARN_ON(command & SYS_CFGCTRL_START)) - return -EBUSY; - - command = func->template[index]; - command |= SYS_CFGCTRL_START; - command |= write ? SYS_CFGCTRL_WRITE : 0; - - /* Use a canary for reads */ - if (!write) - *data = 0xdeadbeef; - - dev_dbg(syscfg->dev, "func %p, command %x, data %x\n", - func, command, *data); - writel(*data, syscfg->base + SYS_CFGDATA); - writel(0, syscfg->base + SYS_CFGSTAT); - writel(command, syscfg->base + SYS_CFGCTRL); - mb(); - - /* The operation can take ages... Go to sleep, 100us initially */ - tries = 100; - timeout = 100; - do { - if (!irqs_disabled()) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(usecs_to_jiffies(timeout)); - if (signal_pending(current)) - return -EINTR; - } else { - udelay(timeout); - } - - status = readl(syscfg->base + SYS_CFGSTAT); - if (status & SYS_CFGSTAT_ERR) - return -EFAULT; - - if (timeout > 20) - timeout -= 20; - } while (--tries && !(status & SYS_CFGSTAT_COMPLETE)); - if (WARN_ON_ONCE(!tries)) - return -ETIMEDOUT; - - if (!write) { - *data = readl(syscfg->base + SYS_CFGDATA); - dev_dbg(syscfg->dev, "func %p, read data %x\n", func, *data); - } - - return 0; -} - -static int vexpress_syscfg_read(void *context, unsigned int index, - unsigned int *val) -{ - struct vexpress_syscfg_func *func = context; - - return vexpress_syscfg_exec(func, index, false, val); -} - -static int vexpress_syscfg_write(void *context, unsigned int index, - unsigned int val) -{ - struct vexpress_syscfg_func *func = context; - - return vexpress_syscfg_exec(func, index, true, &val); -} - -static struct regmap_config vexpress_syscfg_regmap_config = { - .lock = vexpress_config_lock, - .unlock = vexpress_config_unlock, - .reg_bits = 32, - .val_bits = 32, - .reg_read = vexpress_syscfg_read, - .reg_write = vexpress_syscfg_write, - .reg_format_endian = REGMAP_ENDIAN_LITTLE, - .val_format_endian = REGMAP_ENDIAN_LITTLE, -}; - - -static struct regmap *vexpress_syscfg_regmap_init(struct device *dev, - void *context) -{ - int err; - struct vexpress_syscfg *syscfg = context; - struct vexpress_syscfg_func *func; - struct property *prop; - const __be32 *val = NULL; - __be32 energy_quirk[4]; - int num; - u32 site, position, dcc; - int i; - - err = vexpress_config_get_topo(dev->of_node, &site, - &position, &dcc); - if (err) - return ERR_PTR(err); - - prop = of_find_property(dev->of_node, - "arm,vexpress-sysreg,func", NULL); - if (!prop) - return ERR_PTR(-EINVAL); - - num = prop->length / sizeof(u32) / 2; - val = prop->value; - - /* - * "arm,vexpress-energy" function used to be described - * by its first device only, now it requires both - */ - if (num == 1 && of_device_is_compatible(dev->of_node, - "arm,vexpress-energy")) { - num = 2; - energy_quirk[0] = *val; - energy_quirk[2] = *val++; - energy_quirk[1] = *val; - energy_quirk[3] = cpu_to_be32(be32_to_cpup(val) + 1); - val = energy_quirk; - } - - func = kzalloc(struct_size(func, template, num), GFP_KERNEL); - if (!func) - return ERR_PTR(-ENOMEM); - - func->syscfg = syscfg; - func->num_templates = num; - - for (i = 0; i < num; i++) { - u32 function, device; - - function = be32_to_cpup(val++); - device = be32_to_cpup(val++); - - dev_dbg(dev, "func %p: %u/%u/%u/%u/%u\n", - func, site, position, dcc, - function, device); - - func->template[i] = SYS_CFGCTRL_DCC(dcc); - func->template[i] |= SYS_CFGCTRL_SITE(site); - func->template[i] |= SYS_CFGCTRL_POSITION(position); - func->template[i] |= SYS_CFGCTRL_FUNC(function); - func->template[i] |= SYS_CFGCTRL_DEVICE(device); - } - - vexpress_syscfg_regmap_config.max_register = num - 1; - - func->regmap = regmap_init(dev, NULL, func, - &vexpress_syscfg_regmap_config); - - if (IS_ERR(func->regmap)) { - void *err = func->regmap; - - kfree(func); - return err; - } - - list_add(&func->list, &syscfg->funcs); - - return func->regmap; -} - -static void vexpress_syscfg_regmap_exit(struct regmap *regmap, void *context) -{ - struct vexpress_syscfg *syscfg = context; - struct vexpress_syscfg_func *func, *tmp; - - regmap_exit(regmap); - - list_for_each_entry_safe(func, tmp, &syscfg->funcs, list) { - if (func->regmap == regmap) { - list_del(&syscfg->funcs); - kfree(func); - break; - } - } -} - -static struct vexpress_config_bridge_ops vexpress_syscfg_bridge_ops = { - .regmap_init = vexpress_syscfg_regmap_init, - .regmap_exit = vexpress_syscfg_regmap_exit, -}; - - -static int vexpress_syscfg_probe(struct platform_device *pdev) -{ - struct vexpress_syscfg *syscfg; - struct resource *res; - struct device *bridge; - - syscfg = devm_kzalloc(&pdev->dev, sizeof(*syscfg), GFP_KERNEL); - if (!syscfg) - return -ENOMEM; - syscfg->dev = &pdev->dev; - INIT_LIST_HEAD(&syscfg->funcs); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - syscfg->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(syscfg->base)) - return PTR_ERR(syscfg->base); - - /* Must use dev.parent (MFD), as that's where DT phandle points at... */ - bridge = vexpress_config_bridge_register(pdev->dev.parent, - &vexpress_syscfg_bridge_ops, syscfg); - - return PTR_ERR_OR_ZERO(bridge); -} - -static const struct platform_device_id vexpress_syscfg_id_table[] = { - { "vexpress-syscfg", }, - {}, -}; - -static struct platform_driver vexpress_syscfg_driver = { - .driver.name = "vexpress-syscfg", - .id_table = vexpress_syscfg_id_table, - .probe = vexpress_syscfg_probe, -}; - -static int __init vexpress_syscfg_init(void) -{ - return platform_driver_register(&vexpress_syscfg_driver); -} -core_initcall(vexpress_syscfg_init); diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h index 2ec7992b054c..65096c792d57 100644 --- a/include/linux/vexpress.h +++ b/include/linux/vexpress.h @@ -18,23 +18,6 @@ /* Config infrastructure */ void vexpress_config_set_master(u32 site); -u32 vexpress_config_get_master(void); - -void vexpress_config_lock(void *arg); -void vexpress_config_unlock(void *arg); - -int vexpress_config_get_topo(struct device_node *node, u32 *site, - u32 *position, u32 *dcc); - -/* Config bridge API */ - -struct vexpress_config_bridge_ops { - struct regmap * (*regmap_init)(struct device *dev, void *context); - void (*regmap_exit)(struct regmap *regmap, void *context); -}; - -struct device *vexpress_config_bridge_register(struct device *parent, - struct vexpress_config_bridge_ops *ops, void *context); /* Config regmap API */ -- cgit v1.2.3-70-g09d2 From 848685c25da99d871bbd87369f3c3d6eead661ac Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 29 Apr 2020 15:58:25 -0500 Subject: ARM: vexpress: Don't select VEXPRESS_CONFIG CONFIG_VEXPRESS_CONFIG has 'default y if ARCH_VEXPRESS', so selecting is unnecessary. Selecting it also prevents setting CONFIG_VEXPRESS_CONFIG to a module. Cc: Lorenzo Pieralisi Cc: Linus Walleij Reviewed-by: Sudeep Holla Acked-by: Liviu Dudau Signed-off-by: Rob Herring --- arch/arm/mach-vexpress/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 065e12991663..8391a5b3cd78 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -19,7 +19,6 @@ menuconfig ARCH_VEXPRESS select POWER_SUPPLY select REGULATOR if MMC_ARMMMCI select REGULATOR_FIXED_VOLTAGE if REGULATOR - select VEXPRESS_CONFIG help This option enables support for systems using Cortex processor based ARM core and logic (FPGA) tiles on the Versatile Express motherboard, -- cgit v1.2.3-70-g09d2 From 498a7014989dfdd9a47864b55704dc829ed0dc90 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sun, 3 May 2020 21:12:11 +0530 Subject: ARM: dts: stm32: Add missing pinctrl entries for STM32MP15 These pinctrl definitions will be used by Stinger96/IoTBox boards from Shiratech. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index deb4cf4e2ef0..7eb858732d6d 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1598,6 +1598,30 @@ }; }; + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = ; /* USART3_TX */ @@ -1637,6 +1661,19 @@ }; }; + uart4_pins_c: uart4-2 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1652,6 +1689,19 @@ }; }; + uart7_pins_b: uart7-1 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -1726,4 +1776,18 @@ bias-disable; }; }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; }; -- cgit v1.2.3-70-g09d2 From aaac4bd35a8339cf217a0928c8762fc2250fdb81 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sun, 3 May 2020 21:12:13 +0530 Subject: ARM: dts: stm32: Add Stinger96 board support Stinger96 is a 96Boards IoT Extended edition board designed and manufactured by Shiratech solutions based on STM32MP1 SoC. Following are the features of this board: * 256MB DDR * 125MB NAND Flash * Onboard BG96 modem * 1x uSD * 2x USB (1 available as external connector and another connected to BG96) * 1x SPI * 1x PCM * 2x UART (apart from serial console) * 2x I2C (apart from one connected to PMIC) Following peripherals are tested and known to work: * BG96 modem * 1x I2C (LS-I2C0) * 1x SPI * 1x UART (LS-UART0) * USB (Only Gadget mode) * uSD More information about this board can be found in Shiratech website: https://www.shiratech-solutions.com/products/stinger96/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-stinger96.dts | 12 + arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 342 +++++++++++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-stinger96.dts create mode 100644 arch/arm/boot/dts/stm32mp157a-stinger96.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f43467b02bcd..966b81dfffd6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/stm32mp157a-stinger96.dts new file mode 100644 index 000000000000..249a53877512 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A Stinger96 board"; + compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi new file mode 100644 index 000000000000..58275bcf9e26 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &spi4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + led { + compatible = "gpio-leds"; + + led1 { + label = "green:user1"; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +/* Only headless mode is supported */ +&gpu { + status = "disabled"; +}; + +/* LS-I2C0 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <1000>; + i2c-scl-falling-time-ns = <300>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v2v9: ldo2 { + regulator-name = "v2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + broken-cd; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +/* LS-SPI0 */ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* BG96 */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* LS-UART0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_c>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* Debug console */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_b>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; -- cgit v1.2.3-70-g09d2 From f0c2df217c809e367be2004e8e34bbcf3533cb1f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sun, 3 May 2020 21:12:15 +0530 Subject: ARM: dts: stm32: Add IoT Box board support IoT Box is an IoT gateway device based on Stinger96 board powered by STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This device makes use of Stinger96 board by having it as a base board with one additional mezzanine on top. Following are the features exposed by this device in addition to the Stinger96 board: * WiFi/BT * CCS811 VOC sensor * 2x Digital microphones IM69D130 * 12x WS2812B LEDs Following peripherals are tested and known to work: * WiFi/BT * CCS811 More information about this device can be found in Shiratech website: https://www.shiratech-solutions.com/products/iot-box/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-iot-box.dts | 68 +++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157a-iot-box.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 966b81dfffd6..455ec6eb6303 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dk1.dtb \ + stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ stm32mp157c-dk2.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts new file mode 100644 index 000000000000..70f394b4d3c0 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A IoT Box"; + compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c2 { + ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; +}; + +/* WiFi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <1>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&uart4 { + /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ + /delete-property/st,hw-flow-ctrl; + cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + }; +}; -- cgit v1.2.3-70-g09d2 From 87cabf9405cbfba439d59fa5d956e4c5e76a061c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 13 May 2020 20:10:17 +0200 Subject: ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2 Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1 key is polled because it's IRQ line conflicts with ethernet IRQ, the rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake up sources. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index 13b1586d4a8f..e5036c9b9e92 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -4,6 +4,7 @@ */ #include "stm32mp157c-dhcom-som.dtsi" +#include #include / { @@ -46,6 +47,48 @@ regulator-boot-on; }; + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #size-cells = <0>; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with touchscreen and ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = ; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #size-cells = <0>; + + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-2 { + label = "TA3-GPIO-C"; + linux,code = ; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = ; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + panel { compatible = "edt,etm0700g0edh6"; backlight = <&display_bl>; -- cgit v1.2.3-70-g09d2 From 81d5fc7197984c793ae90c5516657fe8902b3f18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 13 May 2020 20:10:18 +0200 Subject: ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2 Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5 GPIO-E may conflict with touchscreen interrupt, hence LED5 must be disabled when using the DH 560-200 display unit with touchscreen. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index e5036c9b9e92..b380268750f3 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -89,6 +89,34 @@ }; }; + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + panel { compatible = "edt,etm0700g0edh6"; backlight = <&display_bl>; -- cgit v1.2.3-70-g09d2 From 604536dc58379d918e455bdbe6194e68b5aa4f1f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 13 May 2020 20:10:19 +0200 Subject: ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2 The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx variant. Split the SoC-independent parts of the SoM and PDK2 into the stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example of adding STM32MP157C variant of the SoM into a PDK2 carrier board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 348 +----------------------- arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi | 364 -------------------------- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 337 ++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 361 +++++++++++++++++++++++++ 4 files changed, 712 insertions(+), 698 deletions(-) delete mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index b380268750f3..197aa98d49e2 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -1,243 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2019 Marek Vasut + * Copyright (C) 2019-2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 + * DHCOR PCB number: 587-200 or newer + * PDK2 PCB number: 516-400 or newer */ +/dts-v1/; -#include "stm32mp157c-dhcom-som.dtsi" -#include -#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" / { - model = "STMicroelectronics STM32MP157C DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp157c-dhcom-pdk2", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #size-cells = <0>; - poll-interval = <20>; - - /* - * The EXTi IRQ line 3 is shared with touchscreen and ethernet, - * so mark this as polled GPIO key. - */ - button-0 { - label = "TA1-GPIO-A"; - linux,code = ; - gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #size-cells = <0>; - - button-1 { - label = "TA2-GPIO-B"; - linux,code = ; - gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-2 { - label = "TA3-GPIO-C"; - linux,code = ; - gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-3 { - label = "TA4-GPIO-D"; - linux,code = ; - gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - label = "green:led5"; - gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - label = "green:led6"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "green:led7"; - gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "green:led8"; - gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - sound { - compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; - dais = <&sai2a_port &sai2b_port>; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&i2c2 { /* Header X22 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&i2c5 { /* Header X21 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <&v3v3>; - VDDIO-supply = <&vdd>; - - sgtl5000_port: port { - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - - sgtl5000_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - }; - - }; - - polytouch@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpiog>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - linux,wakeup; - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_sleep_pins_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; + model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; }; &m_can1 { @@ -246,103 +26,3 @@ pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; }; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&sgtl5000_tx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&sgtl5000_rx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi deleted file mode 100644 index f97e0d2ecf17..000000000000 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2019 Marek Vasut - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include -#include - -/ { - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; -}; - -&adc { - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <0>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <1>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "okay"; - - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - touchscreen@49 { - compatible = "ti,tsc2004"; - reg = <0x49>; - vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: mx66l51235l@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - broken-cd; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..7c4bd615b311 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + ethernet0 = ðernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #size-cells = <0>; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with touchscreen and ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = ; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #size-cells = <0>; + + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-2 { + label = "TA3-GPIO-C"; + linux,code = ; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = ; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + sound { + compatible = "audio-graph-card"; + routing = + "MIC_IN", "Capture", + "Capture", "Mic Bias", + "Playback", "HP_OUT"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <&v3v3>; + VDDIO-supply = <&vdd>; + + sgtl5000_port: port { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + }; + + }; + + polytouch@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpiog>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + linux,wakeup; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&sgtl5000_tx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&sgtl5000_rx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm2: pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi new file mode 100644 index 000000000000..ba905196fb54 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include +#include + +/ { + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <1>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "okay"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + vio-supply = <&v3v3>; + interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: mx66l51235l@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; + broken-cd; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From 7e76f82acd9e12fe7765d5d8c200b37787c994e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 13 May 2020 20:10:20 +0200 Subject: ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top of an Avenger96 reference board. The DHCOR SoM can be populated with any STM32MP15xx. Split the DTs to reflect this such that the common SoM and Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example implementation of STM32MP157A SoM and Avenger96 board is separated into stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for the sake of backward naming compatibility. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Manivannan Sadhasivam Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157a-avenger96.dts | 618 +-------------------- arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts | 38 ++ arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 401 +++++++++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi | 23 + arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 209 +++++++ 6 files changed, 675 insertions(+), 615 deletions(-) create mode 100644 arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 455ec6eb6303..ad3786c9d6fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1029,6 +1029,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32mp157a-avenger96.dtb \ + stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts index a9f3ba9da170..8a6eaca994d1 100644 --- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts @@ -2,622 +2,10 @@ /* * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut */ /dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - serial2 = &usart2; - spi0 = &qspi; - }; - - /* XTal Q1 */ - cec_clock: clk-cec-fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7513_out>; - }; - }; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user0"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user1"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user2"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-AV96-HDMI"; - dais = <&sai2a_port>; - status = "okay"; - }; - - /* Enpirion EP3A8LQI U2 on the DHCOR */ - vdd_io: regulator-buck-io { - compatible = "regulator-fixed"; - regulator-name = "buck-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&i2c1 { /* X6 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { /* X6 I2C2 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_c>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - hdmi-transmitter@3d { - compatible = "adi,adv7513"; - reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; - reg-names = "main", "cec", "edid", "packet"; - clocks = <&cec_clock>; - clock-names = "cec"; - - avdd-supply = <&v3v3>; - dvdd-supply = <&v3v3>; - pvdd-supply = <&v3v3>; - dvdd-3v-supply = <&v3v3>; - bgvdd-supply = <&v3v3>; - - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - - status = "okay"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7513_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - - port@2 { - reg = <2>; - adv7513_i2s0: endpoint { - remote-endpoint = <&sai2a_endpoint>; - }; - }; - }; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_d>; - pinctrl-1 = <<dc_sleep_pins_d>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&adv7513_in>; - }; - }; -}; - -&m_can1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_b>; - pinctrl-1 = <&m_can1_sleep_pins_b>; - status = "disabled"; -}; - -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "disabled"; -}; - -&pwr_regulators { - vdd-supply = <&vdd_io>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x200000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_c>; - pinctrl-1 = <&sai2a_sleep_pins_c>; - clock-names = "pclk", "x8k", "x11k"; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&adv7513_i2s0>; - format = "i2s"; - mclk-fs = <256>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; - bus-width = <8>; - mmc-ddr-1_8v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd_io>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_b>; - pinctrl-1 = <&sdmmc3_b4_od_pins_b>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - cs-gpios = <&gpioi 0 0>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -/* Bluetooth */ -&usart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - st,hw-flow-ctrl; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - status = "okay"; - vbus-supply = <&vbus_otg>; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; +/* This DT is here only for backward compatibility */ +#include "stm32mp157a-dhcor-avenger96.dts" diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 000000000000..2e3c9fbb4eb3 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 000000000000..930202742a3f --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &qspi; + }; + + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user0"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user1"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user2"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&i2c1 { /* X6 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { /* X6 I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; + reg-names = "main", "cec", "edid", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi new file mode 100644 index 000000000000..75172314d7af --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/ { + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi new file mode 100644 index 000000000000..04fbb324a541 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From c8ffd8bcdd28296a198f237cc595148a8d4adfbe Mon Sep 17 00:00:00 2001 From: Miklos Szeredi Date: Thu, 14 May 2020 16:44:25 +0200 Subject: vfs: add faccessat2 syscall POSIX defines faccessat() as having a fourth "flags" argument, while the linux syscall doesn't have it. Glibc tries to emulate AT_EACCESS and AT_SYMLINK_NOFOLLOW, but AT_EACCESS emulation is broken. Add a new faccessat(2) syscall with the added flags argument and implement both flags. The value of AT_EACCESS is defined in glibc headers to be the same as AT_REMOVEDIR. Use this value for the kernel interface as well, together with the explanatory comment. Also add AT_EMPTY_PATH support, which is not documented by POSIX, but can be useful and is trivial to implement. Signed-off-by: Miklos Szeredi --- arch/alpha/kernel/syscalls/syscall.tbl | 1 + arch/arm/tools/syscall.tbl | 1 + arch/arm64/include/asm/unistd.h | 2 +- arch/arm64/include/asm/unistd32.h | 2 ++ arch/ia64/kernel/syscalls/syscall.tbl | 1 + arch/m68k/kernel/syscalls/syscall.tbl | 1 + arch/microblaze/kernel/syscalls/syscall.tbl | 1 + arch/mips/kernel/syscalls/syscall_n32.tbl | 1 + arch/mips/kernel/syscalls/syscall_n64.tbl | 1 + arch/mips/kernel/syscalls/syscall_o32.tbl | 1 + arch/parisc/kernel/syscalls/syscall.tbl | 1 + arch/powerpc/kernel/syscalls/syscall.tbl | 1 + arch/s390/kernel/syscalls/syscall.tbl | 1 + arch/sh/kernel/syscalls/syscall.tbl | 1 + arch/sparc/kernel/syscalls/syscall.tbl | 1 + arch/x86/entry/syscalls/syscall_32.tbl | 1 + arch/x86/entry/syscalls/syscall_64.tbl | 1 + arch/xtensa/kernel/syscalls/syscall.tbl | 1 + fs/internal.h | 1 - fs/open.c | 34 ++++++++++++++++++++++------- include/linux/syscalls.h | 6 +++-- include/uapi/asm-generic/unistd.h | 4 +++- include/uapi/linux/fcntl.h | 10 +++++++++ 23 files changed, 62 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index 36d42da7466a..5ddd128d4b7a 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -477,3 +477,4 @@ # 545 reserved for clone3 547 common openat2 sys_openat2 548 common pidfd_getfd sys_pidfd_getfd +549 common faccessat2 sys_faccessat2 diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 4d1cf74a2caa..d5cae5ffede0 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -451,3 +451,4 @@ 435 common clone3 sys_clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index 803039d504de..3b859596840d 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -38,7 +38,7 @@ #define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE + 5) #define __ARM_NR_COMPAT_END (__ARM_NR_COMPAT_BASE + 0x800) -#define __NR_compat_syscalls 439 +#define __NR_compat_syscalls 440 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index c1c61635f89c..6d95d0c8bf2f 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -883,6 +883,8 @@ __SYSCALL(__NR_clone3, sys_clone3) __SYSCALL(__NR_openat2, sys_openat2) #define __NR_pidfd_getfd 438 __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) +#define __NR_faccessat2 439 +__SYSCALL(__NR_faccessat2, sys_faccessat2) /* * Please add new compat syscalls above this comment and update diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index 042911e670b8..49e325b604b3 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -358,3 +358,4 @@ # 435 reserved for clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index f4f49fcb76d0..f71b1bbcc198 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -437,3 +437,4 @@ 435 common clone3 __sys_clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl b/arch/microblaze/kernel/syscalls/syscall.tbl index 4c67b11f9c9e..edacc4561f2b 100644 --- a/arch/microblaze/kernel/syscalls/syscall.tbl +++ b/arch/microblaze/kernel/syscalls/syscall.tbl @@ -443,3 +443,4 @@ 435 common clone3 sys_clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/mips/kernel/syscalls/syscall_n32.tbl b/arch/mips/kernel/syscalls/syscall_n32.tbl index 1f9e8ad636cc..f777141f5256 100644 --- a/arch/mips/kernel/syscalls/syscall_n32.tbl +++ b/arch/mips/kernel/syscalls/syscall_n32.tbl @@ -376,3 +376,4 @@ 435 n32 clone3 __sys_clone3 437 n32 openat2 sys_openat2 438 n32 pidfd_getfd sys_pidfd_getfd +439 n32 faccessat2 sys_faccessat2 diff --git a/arch/mips/kernel/syscalls/syscall_n64.tbl b/arch/mips/kernel/syscalls/syscall_n64.tbl index c0b9d802dbf6..da8c76394e17 100644 --- a/arch/mips/kernel/syscalls/syscall_n64.tbl +++ b/arch/mips/kernel/syscalls/syscall_n64.tbl @@ -352,3 +352,4 @@ 435 n64 clone3 __sys_clone3 437 n64 openat2 sys_openat2 438 n64 pidfd_getfd sys_pidfd_getfd +439 n64 faccessat2 sys_faccessat2 diff --git a/arch/mips/kernel/syscalls/syscall_o32.tbl b/arch/mips/kernel/syscalls/syscall_o32.tbl index ac586774c980..13280625d312 100644 --- a/arch/mips/kernel/syscalls/syscall_o32.tbl +++ b/arch/mips/kernel/syscalls/syscall_o32.tbl @@ -425,3 +425,4 @@ 435 o32 clone3 __sys_clone3 437 o32 openat2 sys_openat2 438 o32 pidfd_getfd sys_pidfd_getfd +439 o32 faccessat2 sys_faccessat2 diff --git a/arch/parisc/kernel/syscalls/syscall.tbl b/arch/parisc/kernel/syscalls/syscall.tbl index 52a15f5cd130..5a758fa6ec52 100644 --- a/arch/parisc/kernel/syscalls/syscall.tbl +++ b/arch/parisc/kernel/syscalls/syscall.tbl @@ -435,3 +435,4 @@ 435 common clone3 sys_clone3_wrapper 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl b/arch/powerpc/kernel/syscalls/syscall.tbl index 220ae11555f2..f833a3190822 100644 --- a/arch/powerpc/kernel/syscalls/syscall.tbl +++ b/arch/powerpc/kernel/syscalls/syscall.tbl @@ -527,3 +527,4 @@ 435 spu clone3 sys_ni_syscall 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/s390/kernel/syscalls/syscall.tbl b/arch/s390/kernel/syscalls/syscall.tbl index bd7bd3581a0f..bfdcb7633957 100644 --- a/arch/s390/kernel/syscalls/syscall.tbl +++ b/arch/s390/kernel/syscalls/syscall.tbl @@ -440,3 +440,4 @@ 435 common clone3 sys_clone3 sys_clone3 437 common openat2 sys_openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 sys_faccessat2 diff --git a/arch/sh/kernel/syscalls/syscall.tbl b/arch/sh/kernel/syscalls/syscall.tbl index c7a30fcd135f..acc35daa1b79 100644 --- a/arch/sh/kernel/syscalls/syscall.tbl +++ b/arch/sh/kernel/syscalls/syscall.tbl @@ -440,3 +440,4 @@ # 435 reserved for clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/sparc/kernel/syscalls/syscall.tbl b/arch/sparc/kernel/syscalls/syscall.tbl index f13615ecdecc..8004a276cb74 100644 --- a/arch/sparc/kernel/syscalls/syscall.tbl +++ b/arch/sparc/kernel/syscalls/syscall.tbl @@ -483,3 +483,4 @@ # 435 reserved for clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index 54581ac671b4..d8f8a1a69ed1 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -442,3 +442,4 @@ 435 i386 clone3 sys_clone3 437 i386 openat2 sys_openat2 438 i386 pidfd_getfd sys_pidfd_getfd +439 i386 faccessat2 sys_faccessat2 diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index 37b844f839bc..78847b32e137 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -359,6 +359,7 @@ 435 common clone3 sys_clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 # # x32-specific system call numbers start at 512 to avoid cache impact diff --git a/arch/xtensa/kernel/syscalls/syscall.tbl b/arch/xtensa/kernel/syscalls/syscall.tbl index 85a9ab1bc04d..69d0d73876b3 100644 --- a/arch/xtensa/kernel/syscalls/syscall.tbl +++ b/arch/xtensa/kernel/syscalls/syscall.tbl @@ -408,3 +408,4 @@ 435 common clone3 sys_clone3 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd +439 common faccessat2 sys_faccessat2 diff --git a/fs/internal.h b/fs/internal.h index aa5d45524e87..0d467e32dd7e 100644 --- a/fs/internal.h +++ b/fs/internal.h @@ -126,7 +126,6 @@ extern struct open_how build_open_how(int flags, umode_t mode); extern int build_open_flags(const struct open_how *how, struct open_flags *op); long do_sys_ftruncate(unsigned int fd, loff_t length, int small); -long do_faccessat(int dfd, const char __user *filename, int mode); int do_fchmodat(int dfd, const char __user *filename, umode_t mode); int do_fchownat(int dfd, const char __user *filename, uid_t user, gid_t group, int flag); diff --git a/fs/open.c b/fs/open.c index 0ea3cd1a1250..e62b1db06638 100644 --- a/fs/open.c +++ b/fs/open.c @@ -394,20 +394,30 @@ static const struct cred *access_override_creds(void) return old_cred; } -long do_faccessat(int dfd, const char __user *filename, int mode) +long do_faccessat(int dfd, const char __user *filename, int mode, int flags) { struct path path; struct inode *inode; int res; unsigned int lookup_flags = LOOKUP_FOLLOW; - const struct cred *old_cred; + const struct cred *old_cred = NULL; if (mode & ~S_IRWXO) /* where's F_OK, X_OK, W_OK, R_OK? */ return -EINVAL; - old_cred = access_override_creds(); - if (!old_cred) - return -ENOMEM; + if (flags & ~(AT_EACCESS | AT_SYMLINK_NOFOLLOW | AT_EMPTY_PATH)) + return -EINVAL; + + if (flags & AT_SYMLINK_NOFOLLOW) + lookup_flags &= ~LOOKUP_FOLLOW; + if (flags & AT_EMPTY_PATH) + lookup_flags |= LOOKUP_EMPTY; + + if (!(flags & AT_EACCESS)) { + old_cred = access_override_creds(); + if (!old_cred) + return -ENOMEM; + } retry: res = user_path_at(dfd, filename, lookup_flags, &path); @@ -450,18 +460,26 @@ out_path_release: goto retry; } out: - revert_creds(old_cred); + if (old_cred) + revert_creds(old_cred); + return res; } SYSCALL_DEFINE3(faccessat, int, dfd, const char __user *, filename, int, mode) { - return do_faccessat(dfd, filename, mode); + return do_faccessat(dfd, filename, mode, 0); +} + +SYSCALL_DEFINE4(faccessat2, int, dfd, const char __user *, filename, int, mode, + int, flags) +{ + return do_faccessat(dfd, filename, mode, flags); } SYSCALL_DEFINE2(access, const char __user *, filename, int, mode) { - return do_faccessat(AT_FDCWD, filename, mode); + return do_faccessat(AT_FDCWD, filename, mode, 0); } int ksys_chdir(const char __user *filename) diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 1815065d52f3..7c354c2955f5 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -428,6 +428,8 @@ asmlinkage long sys_ftruncate64(unsigned int fd, loff_t length); #endif asmlinkage long sys_fallocate(int fd, int mode, loff_t offset, loff_t len); asmlinkage long sys_faccessat(int dfd, const char __user *filename, int mode); +asmlinkage long sys_faccessat2(int dfd, const char __user *filename, int mode, + int flags); asmlinkage long sys_chdir(const char __user *filename); asmlinkage long sys_fchdir(unsigned int fd); asmlinkage long sys_chroot(const char __user *filename); @@ -1333,11 +1335,11 @@ static inline int ksys_chmod(const char __user *filename, umode_t mode) return do_fchmodat(AT_FDCWD, filename, mode); } -extern long do_faccessat(int dfd, const char __user *filename, int mode); +long do_faccessat(int dfd, const char __user *filename, int mode, int flags); static inline long ksys_access(const char __user *filename, int mode) { - return do_faccessat(AT_FDCWD, filename, mode); + return do_faccessat(AT_FDCWD, filename, mode, 0); } extern int do_fchownat(int dfd, const char __user *filename, uid_t user, diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h index 3a3201e4618e..f4a01305d9a6 100644 --- a/include/uapi/asm-generic/unistd.h +++ b/include/uapi/asm-generic/unistd.h @@ -855,9 +855,11 @@ __SYSCALL(__NR_clone3, sys_clone3) __SYSCALL(__NR_openat2, sys_openat2) #define __NR_pidfd_getfd 438 __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) +#define __NR_faccessat2 439 +__SYSCALL(__NR_faccessat2, sys_faccessat2) #undef __NR_syscalls -#define __NR_syscalls 439 +#define __NR_syscalls 440 /* * 32 bit systems traditionally used different diff --git a/include/uapi/linux/fcntl.h b/include/uapi/linux/fcntl.h index ca88b7bce553..2f86b2ad6d7e 100644 --- a/include/uapi/linux/fcntl.h +++ b/include/uapi/linux/fcntl.h @@ -84,10 +84,20 @@ #define DN_ATTRIB 0x00000020 /* File changed attibutes */ #define DN_MULTISHOT 0x80000000 /* Don't remove notifier */ +/* + * The constants AT_REMOVEDIR and AT_EACCESS have the same value. AT_EACCESS is + * meaningful only to faccessat, while AT_REMOVEDIR is meaningful only to + * unlinkat. The two functions do completely different things and therefore, + * the flags can be allowed to overlap. For example, passing AT_REMOVEDIR to + * faccessat would be undefined behavior and thus treating it equivalent to + * AT_EACCESS is valid undefined behavior. + */ #define AT_FDCWD -100 /* Special value used to indicate openat should use the current working directory. */ #define AT_SYMLINK_NOFOLLOW 0x100 /* Do not follow symbolic links. */ +#define AT_EACCESS 0x200 /* Test access permitted for + effective IDs, not real IDs. */ #define AT_REMOVEDIR 0x200 /* Remove directory instead of unlinking file. */ #define AT_SYMLINK_FOLLOW 0x400 /* Follow symbolic links. */ -- cgit v1.2.3-70-g09d2 From f1f2212eaddf4857728167ce9e582e530183cf4b Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:07 +0000 Subject: ARM: dts: at91: sama5d2: Fix the label numbering for flexcom functions The sama5d2 SoC has the following IPs: [uart0, uart4], {spi0, spi1}, {i2c0, i2c1}. Label the flexcom functions in order: flx0: uart5, spi2, i2c2 flx1: uart6, spi3, i2c3 flx2: uart7, spi4, i2c4 flx3: uart8, spi5, i2c5 flx4: uart9, spi6, i2c6 Some boards respected this scheme, others not. Fix the ones that didn't. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-2-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-kizbox3-hs.dts | 4 ++-- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 8 ++++---- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 20 ++++++++++---------- arch/arm/boot/dts/at91-sama5d2_icp.dts | 8 ++++---- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 2 +- 5 files changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 8734e7f8939e..0da1f0557eaf 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -283,7 +283,7 @@ &flx3 { status = "okay"; - uart6: serial@200 { + uart8: serial@200 { status = "okay"; }; }; @@ -291,7 +291,7 @@ &flx4 { status = "okay"; - i2c2: i2c@600 { + i2c6: i2c@600 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index 299e74d23184..d7a6c972bdac 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -28,7 +28,7 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - serial6 = &uart6; + serial6 = &uart8; }; chosen { @@ -207,7 +207,7 @@ }; }; - pinctrl_flx4_default: flx4_i2c2_default { + pinctrl_flx4_default: flx4_i2c6_default { pinmux = , //DATA ; //CLK bias-disable; @@ -324,7 +324,7 @@ atmel,flexcom-mode = ; status = "disabled"; - uart6: serial@200 { + uart8: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x400>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; @@ -350,7 +350,7 @@ atmel,flexcom-mode = ; status = "disabled"; - i2c2: i2c@600 { + i2c6: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index b0853bf7901c..d215243fe163 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -21,7 +21,7 @@ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ i2c1 = &i2c1; - i2c2 = &i2c2; + i2c2 = &i2c3; }; chosen { @@ -125,7 +125,7 @@ atmel,flexcom-mode = ; status = "okay"; - i2c2: i2c@600 { + i2c3: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; @@ -178,7 +178,7 @@ atmel,flexcom-mode = ; status = "disabled"; - uart7: serial@200 { + uart8: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; @@ -190,7 +190,7 @@ status = "disabled"; /* Conflict with isc. */ }; - spi2: spi@400 { + spi5: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; @@ -207,7 +207,7 @@ atmel,flexcom-mode = ; status = "okay"; - uart6: serial@200 { + uart9: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; @@ -216,10 +216,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <32>; - status = "disabled"; /* Conflict with spi3 and i2c3. */ + status = "disabled"; /* Conflict with spi6 and i2c6. */ }; - spi3: spi@400 { + spi6: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; @@ -228,10 +228,10 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; atmel,fifo-size = <16>; - status = "okay"; /* Conflict with uart6 and i2c3. */ + status = "okay"; /* Conflict with uart5 and i2c6. */ }; - i2c3: i2c@600 { + i2c6: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; @@ -243,7 +243,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <16>; - status = "disabled"; /* Conflict with uart6 and spi3. */ + status = "disabled"; /* Conflict with uart5 and spi6. */ }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index cc9fa700eafb..1d9556dbbd63 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -22,7 +22,7 @@ serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ serial1 = &uart1; /* mikro BUS 3 */ serial3 = &uart3; /* mikro BUS 2 */ - serial5 = &uart5; /* flx2 */ + serial5 = &uart7; /* flx2 */ i2c0 = &i2c0; i2c1 = &i2c1; }; @@ -159,7 +159,7 @@ atmel,flexcom-mode = ; status = "okay"; - uart5: serial@200 { + uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; @@ -184,7 +184,7 @@ atmel,flexcom-mode = ; status = "okay"; - spi3: spi@400 { + spi5: spi@400 { compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; @@ -201,7 +201,7 @@ atmel,flexcom-mode = ; status = "okay"; - i2c2: i2c@600 { + i2c6: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index e0c6cff1a312..0666708b05f9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -377,7 +377,7 @@ atmel,flexcom-mode = ; status = "okay"; - i2c2: i2c@600 { + i2c6: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; -- cgit v1.2.3-70-g09d2 From 91fa03c9e33e3ae8eb6959dc3d0f0b853a004f2c Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:07 +0000 Subject: ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsi The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 14 ---------- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 20 --------------- arch/arm/boot/dts/at91-sama5d2_icp.dts | 8 ------ arch/arm/boot/dts/at91-sama5d2_xplained.dts | 8 ------ arch/arm/boot/dts/sama5d2.dtsi | 40 +++++++++++++++++++++++++++++ 5 files changed, 40 insertions(+), 50 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index d7a6c972bdac..ee6f036aa008 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -351,22 +351,8 @@ status = "disabled"; i2c6: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index d215243fe163..5f4a7c8725f3 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -208,41 +208,21 @@ status = "okay"; uart9: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <32>; status = "disabled"; /* Conflict with spi6 and i2c6. */ }; spi6: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "spi_clk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; - atmel,fifo-size = <16>; status = "okay"; /* Conflict with uart5 and i2c6. */ }; i2c6: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; status = "disabled"; /* Conflict with uart5 and spi6. */ }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 1d9556dbbd63..7216a794f4f6 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -202,17 +202,9 @@ status = "okay"; i2c6: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; status = "okay"; mcp16502@5b { diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 0666708b05f9..a5046f8257ad 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -378,20 +378,12 @@ status = "okay"; i2c6: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx4_default>; pinctrl-1 = <&pinctrl_flx4_gpio>; sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; - atmel,fifo-size = <16>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index ab550d69db91..5c31e4068eb5 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -814,6 +814,46 @@ #size-cells = <1>; ranges = <0x0 0xfc018000 0x800>; status = "disabled"; + + uart9: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi6: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; trng@fc01c000 { -- cgit v1.2.3-70-g09d2 From 445a9d6e562a656f6f9bd4acfd5d55bd415f206e Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:08 +0000 Subject: ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsi The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 13 ------------- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 13 +------------ arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 ------ arch/arm/boot/dts/sama5d2.dtsi | 29 +++++++++++++++++++++++++++++ 4 files changed, 30 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index ee6f036aa008..4351a8d32225 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -325,21 +325,8 @@ status = "disabled"; uart8: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 5f4a7c8725f3..abbf14e29d85 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -179,26 +179,15 @@ status = "disabled"; uart8: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; status = "disabled"; /* Conflict with isc. */ }; spi5: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <16>; status = "disabled"; /* Conflict with isc. */ }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 7216a794f4f6..8a4336e12a60 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -185,14 +185,8 @@ status = "okay"; spi5: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; - atmel,fifo-size = <16>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5c31e4068eb5..5e84cde8226a 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -804,6 +804,35 @@ #size-cells = <1>; ranges = <0x0 0xfc014000 0x800>; status = "disabled"; + + uart8: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx4: flexcom@fc018000 { -- cgit v1.2.3-70-g09d2 From 0afa4365266ab36c5751ff3136d95b5cae070467 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:08 +0000 Subject: ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsi The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 12 ------------ arch/arm/boot/dts/sama5d2.dtsi | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 8a4336e12a60..23f413afb333 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -160,18 +160,6 @@ status = "okay"; uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(15))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(16))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx2_default>; pinctrl-names = "default"; atmel,use-dma-rx; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5e84cde8226a..89064225e9aa 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -794,6 +794,24 @@ #size-cells = <1>; ranges = <0x0 0xfc010000 0x800>; status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; flx3: flexcom@fc014000 { -- cgit v1.2.3-70-g09d2 From 96f63ffdbc38e1b61e768a47b9c52f42f4c7b846 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:09 +0000 Subject: ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsi The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 7 ------- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 12 ------------ arch/arm/boot/dts/sama5d2.dtsi | 29 +++++++++++++++++++++++++++++ 3 files changed, 29 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index abbf14e29d85..a0deff15fb9a 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -126,20 +126,13 @@ status = "okay"; i2c3: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; dma-names = "tx", "rx"; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; - atmel,fifo-size = <16>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index bea3d60b9722..a06700e53e4c 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -36,18 +36,6 @@ atmel,flexcom-mode = ; uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx1_default>; pinctrl-names = "default"; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 89064225e9aa..79ed7bd02df6 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -645,6 +645,35 @@ #size-cells = <1>; ranges = <0x0 0xf8038000 0x800>; status = "disabled"; + + uart6: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; securam: sram@f8044000 { -- cgit v1.2.3-70-g09d2 From 56cd4b9e8c67fa60244aea013cc3846f9d8c498b Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:10 +0000 Subject: ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsi The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. There is a single functional change in this patch. With the move of the flx0 uart5 definition in the SoC dtsi, the uart5 from at91-sama5d27_wlsom1_ek.dts inherits the following optional property: atmel,fifo-size = <32>; This particular change was tested by Codrin. Signed-off-by: Tudor Ambarus Tested-by: Codrin Ciubotariu Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 13 --------- arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts | 12 -------- arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 ---- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 7 ----- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 7 +---- arch/arm/boot/dts/sama5d2.dtsi | 40 +++++++++++++++++++++++++++ 6 files changed, 41 insertions(+), 44 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index 4351a8d32225..7c3076e245ef 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -299,21 +299,8 @@ status = "disabled"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index 6b8461278950..6b38fa3f5568 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -77,18 +77,6 @@ status = "okay"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-names = "default"; atmel,use-dma-rx; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 23f413afb333..4a01ab8e7e70 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -105,15 +105,9 @@ status = "okay"; spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "spi_clk"; cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; - atmel,fifo-size = <16>; status = "okay"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 32435ce1dab2..8ad3a9c6c536 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -191,20 +191,13 @@ status = "okay"; i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-1 = <&pinctrl_flx0_gpio>; sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>; - atmel,fifo-size = <16>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index a5046f8257ad..da4442715ea5 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -327,14 +327,9 @@ status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 79ed7bd02df6..acb91908bd74 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -635,6 +635,46 @@ #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; status = "disabled"; + + uart5: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "spi_clk"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx1: flexcom@f8038000 { -- cgit v1.2.3-70-g09d2 From 4b098033279ef20f3a05de1cfc64ad6b9699688f Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:11 +0000 Subject: ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UART The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs. Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index acb91908bd74..dde969a140b4 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -701,6 +701,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(14))>; dma-names = "tx", "rx"; + atmel,fifo-size = <32>; status = "disabled"; }; @@ -879,6 +880,7 @@ AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(16))>; dma-names = "tx", "rx"; + atmel,fifo-size = <32>; status = "disabled"; }; }; -- cgit v1.2.3-70-g09d2 From ddcdaeb88242ca9b2a3ded2c6cb1d664e0ce24a3 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:12 +0000 Subject: ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functions Spare boards of duplicating the DMA bindings. Describe the flx4 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 2 ++ arch/arm/boot/dts/sama5d2.dtsi | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index a0deff15fb9a..6ad66d034305 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -190,12 +190,14 @@ status = "okay"; uart9: serial@200 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; status = "disabled"; /* Conflict with spi6 and i2c6. */ }; spi6: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; status = "okay"; /* Conflict with uart5 and i2c6. */ diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index dde969a140b4..66aa8d6502d3 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -939,6 +939,15 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; atmel,fifo-size = <32>; status = "disabled"; }; @@ -949,6 +958,15 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; atmel,fifo-size = <16>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From b793f1661777dddbd8f99554c24df247906c29bc Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:12 +0000 Subject: ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI function Spare boards of duplicating the DMA bindings. Describe the flx3 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 + arch/arm/boot/dts/at91-sama5d2_icp.dts | 1 + arch/arm/boot/dts/sama5d2.dtsi | 9 +++++++++ 3 files changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 6ad66d034305..1aa8b79d618b 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -179,6 +179,7 @@ }; spi5: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; status = "disabled"; /* Conflict with isc. */ diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 4a01ab8e7e70..559d8ae93af9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -167,6 +167,7 @@ status = "okay"; spi5: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; status = "okay"; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 66aa8d6502d3..5a0162915ae7 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -919,6 +919,15 @@ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; atmel,fifo-size = <16>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From 1a6508a2ed9a9a7925c999683eb872cd0ed2a7bd Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:13 +0000 Subject: ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C function Spare boards of duplicating the DMA bindings. Describe the flx1 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 - arch/arm/boot/dts/sama5d2.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 1aa8b79d618b..0e159f879c15 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -127,7 +127,6 @@ i2c3: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5a0162915ae7..855846c74a32 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -712,6 +712,15 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; atmel,fifo-size = <16>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From 466fb89be5916af18ba5ea636fc1f7489a71e276 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:14 +0000 Subject: ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functions Spare boards of duplicating the DMA bindings. Describe the flx0 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 1 + arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 1 - arch/arm/boot/dts/sama5d2.dtsi | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 559d8ae93af9..8d19925fc09e 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -105,6 +105,7 @@ status = "okay"; spi2: spi@400 { + dmas = <0>, <0>; cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 8ad3a9c6c536..0e0341c83aa5 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -192,7 +192,6 @@ i2c2: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-1 = <&pinctrl_flx0_gpio>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 855846c74a32..5bba8024f485 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -661,6 +661,15 @@ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; atmel,fifo-size = <16>; status = "disabled"; }; @@ -672,6 +681,15 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; atmel,fifo-size = <16>; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From 6e57359dd660ac1be632c8ae583e502faea6aa7e Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:15 +0000 Subject: ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsi Device aliases are board-specific, if needed one should define them in board dts rather than in the SoC dtsi. If an alias from the SoC dtsi is addressed by a driver that does not use any of the of_alias*() methods, we can drop it. This is the case for the i2s aliases, drop them. tcb aliases point to nodes that are not enabled in any of the sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any board using that alias is already broken, so get rid of the tcb aliases too. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2.dtsi | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 5bba8024f485..38371db376b3 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -21,10 +21,6 @@ aliases { serial0 = &uart1; serial1 = &uart3; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2s0 = &i2s0; - i2s1 = &i2s1; }; cpus { -- cgit v1.2.3-70-g09d2 From 6b9a3584c7ed635641e0379df03a17943505d423 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:15 +0000 Subject: ARM: dts: at91: sama5d2: Add missing flexcom definitions Describe all the flexcom functions for all the flexcom nodes. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-13-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2.dtsi | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 38371db376b3..c0a3ca8f9bf7 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -719,6 +719,25 @@ status = "disabled"; }; + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + i2c3: i2c@600 { compatible = "atmel,sama5d2-i2c"; reg = <0x600 0x200>; @@ -906,6 +925,45 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx3: flexcom@fc014000 { @@ -954,6 +1012,27 @@ atmel,fifo-size = <16>; status = "disabled"; }; + + i2c5: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; flx4: flexcom@fc018000 { -- cgit v1.2.3-70-g09d2 From c85273fd1452a6de5cfaac93821a243990364108 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:16 +0000 Subject: ARM: dts: at91: sama5d2_xplained: Add alias for DBGU The aliases should be defined in the board dts rather than in the SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define the alias for the Serial DBGU in the board dts file. sama5d2 boards use the "serial0" alias for the Serial DBGU, do the same for sama5d2_xplained. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-15-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index da4442715ea5..01ffbddd4ab8 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -16,6 +16,10 @@ model = "Atmel SAMA5D2 Xplained"; compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + aliases { + serial0 = &uart1; /* DBGU */ + }; + chosen { stdout-path = "serial0:115200n8"; }; -- cgit v1.2.3-70-g09d2 From dbe5bbdb28b4fca61584806301a021d57b4f1433 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:17 +0000 Subject: ARM: dts: at91: sama5d2_ptc_ek: Add comments to describe the aliases Indicate which i2c alias is for which connector on the board. Specify that serial0 is for DBGU. This eases tester's life. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-17-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 0e0341c83aa5..45c671a2bcf2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -18,9 +18,9 @@ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; + serial0 = &uart0; /* DBGU */ + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ i2c2 = &i2c2; }; -- cgit v1.2.3-70-g09d2 From bd1f49e7792b1ca6e8c538942294309881150632 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 14 May 2020 05:03:17 +0000 Subject: ARM: dts: at91: sama5d2_xplained: Describe the flx0 I2C function Users can choose which flexcom function to use. Describe the I2C Flexcom0 function. Add alias for the i2c2 node in order to not rely on probe order for the i2c device numbering. The sama5d2 SoC has two dedicated i2c buses and five flexcoms that can function as i2c. The i2c0 and i2c1 aliases are kept for the dedicated i2c buses, the i2c flexcom functions can be numbered in order starting from i2c2. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200514050301.147442-16-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 01ffbddd4ab8..77e5d4f5a102 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -18,6 +18,7 @@ aliases { serial0 = &uart1; /* DBGU */ + i2c2 = &i2c2; /* XPRO EXT2 */ }; chosen { @@ -336,6 +337,20 @@ pinctrl-0 = <&pinctrl_flx0_default>; status = "okay"; }; + + i2c2: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>; + i2c-sda-hold-time-ns = <350>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ + }; }; shdwc@f8048010 { @@ -523,6 +538,12 @@ bias-disable; }; + pinctrl_i2c2_gpio: i2c2_gpio { + pinmux = , + ; + bias-disable; + }; + pinctrl_i2s0_default: i2s0_default { pinmux = , , -- cgit v1.2.3-70-g09d2 From c5a28380257327bb7b89974919a3695047277ba5 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 15 May 2020 17:00:01 +0300 Subject: ARM: dts: at91: Configure I2C SCL gpio as open drain The SCL gpio pin used by I2C bus for recovery needs to be configured as open drain. Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl") Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl") Fixes: 8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl") Signed-off-by: Codrin Ciubotariu Link: https://lore.kernel.org/r/20200515140001.287932-1-codrin.ciubotariu@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++--- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 8 ++++---- arch/arm/boot/dts/sama5d3.dtsi | 6 +++--- arch/arm/boot/dts/sama5d4.dtsi | 6 +++--- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 45c671a2bcf2..c894c7c788a9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -182,7 +182,7 @@ pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -196,7 +196,7 @@ pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-1 = <&pinctrl_flx0_gpio>; sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; }; @@ -226,7 +226,7 @@ pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PC7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@50 { diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 77e5d4f5a102..851b8587068b 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -190,7 +190,7 @@ pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-sda-hold-time-ns = <350>; status = "okay"; @@ -344,7 +344,7 @@ pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-sda-hold-time-ns = <350>; i2c-analog-filter; i2c-digital-filter; @@ -397,7 +397,7 @@ pinctrl-0 = <&pinctrl_flx4_default>; pinctrl-1 = <&pinctrl_flx4_gpio>; sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; @@ -414,7 +414,7 @@ i2c-digital-filter-width-ns = <35>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@54 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index f3ce561b46ab..c53e48445e4d 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -163,7 +163,7 @@ pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; @@ -181,7 +181,7 @@ pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioC 27 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; @@ -367,7 +367,7 @@ pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 19 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index c9c0316b5b0e..fff679734c9c 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -462,7 +462,7 @@ pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; @@ -484,7 +484,7 @@ pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioE 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; @@ -529,7 +529,7 @@ pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; -- cgit v1.2.3-70-g09d2 From 9bffcf42c6700114d4a602370a66816c1ebd2798 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:45:34 +0200 Subject: ARM/time: Replace by The ARM time code is not a clock provider, and just needs to call of_clk_init(). Hence it can include instead of . Link: https://lore.kernel.org/r/20200505154536.4099-2-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Reviewed-by: Stephen Boyd Signed-off-by: Arnd Bergmann --- arch/arm/kernel/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index dddc7ebf4db4..09b149b09c43 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -8,7 +8,6 @@ * This file contains the ARM-specific time handling details: * reading the RTC at bootup, etc... */ -#include #include #include #include @@ -17,6 +16,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3-70-g09d2 From 1c2f05e72adef5ace094b686aa9069b5b206be74 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:45:35 +0200 Subject: ARM: mediatek: Replace by The Mediatek platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include instead of . Link: https://lore.kernel.org/r/20200505154536.4099-3-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Reviewed-by: Stephen Boyd Signed-off-by: Arnd Bergmann --- arch/arm/mach-mediatek/mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c index f6f102fa9e23..e6e9f93a1f01 100644 --- a/arch/arm/mach-mediatek/mediatek.c +++ b/arch/arm/mach-mediatek/mediatek.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include -- cgit v1.2.3-70-g09d2 From b5bb63177d38cfa295a9c74962519fcddca94876 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:45:36 +0200 Subject: ARM: mmp: Replace by The Marvell MMP platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include instead of . Link: https://lore.kernel.org/r/20200505154536.4099-4-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Reviewed-by: Stephen Boyd Acked-by: Lubomir Rintel Signed-off-by: Arnd Bergmann --- arch/arm/mach-mmp/mmp-dt.c | 2 +- arch/arm/mach-mmp/mmp2-dt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c index 91214996acec..3f43c0867dca 100644 --- a/arch/arm/mach-mmp/mmp-dt.c +++ b/arch/arm/mach-mmp/mmp-dt.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c index 510c762ddc48..34a5fe4b3949 100644 --- a/arch/arm/mach-mmp/mmp2-dt.c +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.2.3-70-g09d2 From 4c8a2bd23115e9871a82c92b465c6625bdd25808 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:08 +0200 Subject: ARM: arch timer: Drop unneeded select GENERIC_CLOCKEVENTS The ARM Architected timer is available on ARMv7 SoCs only. As both ARCH_MULTIPLATFORM and ARM_SINGLE_ARMV7M select GENERIC_CLOCKEVENTS, there is no need for HAVE_ARM_ARCH_TIMER to select GENERIC_CLOCKEVENTS. Link: https://lore.kernel.org/r/20200505150722.1575-2-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d2dfb9919aea..d5cd71213128 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1246,7 +1246,6 @@ config HAVE_ARM_ARCH_TIMER bool "Architected timer support" depends on CPU_V7 select ARM_ARCH_TIMER - select GENERIC_CLOCKEVENTS help This option enables support for the ARM architected timer -- cgit v1.2.3-70-g09d2 From 4039a44c9ee9ce09fe0ca480788b89071ee6c585 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:09 +0200 Subject: ARM: actions: Drop unneeded select of COMMON_CLK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Support for Actions Semi SoCs depends on ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM. As the latter selects COMMON_CLK, there is no need for ARCH_ACTIONS to select COMMON_CLK. Link: https://lore.kernel.org/r/20200505150722.1575-3-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Andreas Färber Cc: Manivannan Sadhasivam Acked-by: Arnd Bergmann Reviewed-by: Andreas Färber Signed-off-by: Arnd Bergmann --- arch/arm/mach-actions/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig index b5e0ac965ec0..00fb4babccdd 100644 --- a/arch/arm/mach-actions/Kconfig +++ b/arch/arm/mach-actions/Kconfig @@ -7,7 +7,6 @@ menuconfig ARCH_ACTIONS select ARM_GLOBAL_TIMER select CACHE_L2X0 select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK - select COMMON_CLK select GENERIC_IRQ_CHIP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP -- cgit v1.2.3-70-g09d2 From 84ce0141031a80864083448ba919046393ca0eb4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:10 +0200 Subject: ARM: alpine: Drop unneeded select of HAVE_SMP Support for Annapurna Labs Alpine platforms depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for ARCH_ALPINE to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-4-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Tsahee Zidenberg Cc: Antoine Tenart Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/mach-alpine/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig index bc04c91294cf..6a68a162385b 100644 --- a/arch/arm/mach-alpine/Kconfig +++ b/arch/arm/mach-alpine/Kconfig @@ -7,7 +7,6 @@ config ARCH_ALPINE select ARM_GIC select GENERIC_IRQ_CHIP select HAVE_ARM_ARCH_TIMER - select HAVE_SMP select MFD_SYSCON select FORCE_PCI select PCI_HOST_GENERIC -- cgit v1.2.3-70-g09d2 From 80454a9908d70f76c44b28f3ec2af61aea16e0c1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:11 +0200 Subject: ARM: asm9260: Drop unneeded select of GENERIC_CLOCKEVENTS Support for the Alphascale ASM9260 platform depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects GENERIC_CLOCKEVENTS, there is no need for MACH_ASM9260 to select GENERIC_CLOCKEVENTS. Link: https://lore.kernel.org/r/20200505150722.1575-5-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Oleksij Rempel Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/mach-asm9260/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig index e42dbaa53bc6..a2e1d0aaf252 100644 --- a/arch/arm/mach-asm9260/Kconfig +++ b/arch/arm/mach-asm9260/Kconfig @@ -4,6 +4,5 @@ config MACH_ASM9260 depends on ARCH_MULTI_V5 select CPU_ARM926T select ASM9260_TIMER - select GENERIC_CLOCKEVENTS help Support for Alphascale ASM9260 based platform. -- cgit v1.2.3-70-g09d2 From 9fdba09a039e9a045e6c7cd0342ff646ad8f81ff Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:12 +0200 Subject: ARM: aspeed: Drop unneeded select of HAVE_SMP Support for the 6th generation Aspeed SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_ASPEED_G6 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-6-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Joel Stanley Cc: Andrew Jeffery Acked-by: Arnd Bergmann Reviewed-by: Andrew Jeffery Signed-off-by: Arnd Bergmann --- arch/arm/mach-aspeed/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index e8d6e9957d65..ea96d11b8502 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -39,7 +39,6 @@ config MACH_ASPEED_G6 select PINCTRL_ASPEED_G6 select ARM_GIC select HAVE_ARM_ARCH_TIMER - select HAVE_SMP help Say yes if you intend to run on an Aspeed ast2600 or similar sixth generation Aspeed BMCs. -- cgit v1.2.3-70-g09d2 From b8c5a80689bae8c13029bde2cc605b7011a09dfe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:13 +0200 Subject: ARM: berlin: Drop unneeded select of HAVE_SMP Support for Marvell Berlin SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_BERLIN_BG2 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-7-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Jisheng Zhang Cc: Sebastian Hesselbarth Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/mach-berlin/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig index 5b1f61fd7878..01861fa72c97 100644 --- a/arch/arm/mach-berlin/Kconfig +++ b/arch/arm/mach-berlin/Kconfig @@ -19,7 +19,6 @@ config MACH_BERLIN_BG2 select CPU_PJ4B select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_SMP select PINCTRL_BERLIN_BG2 config MACH_BERLIN_BG2CD -- cgit v1.2.3-70-g09d2 From 022dacdd278da6d3746c8f62ce293c67aaa7b6fc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:14 +0200 Subject: ARM: clps711x: Drop unneeded select of multi-platform selected options Support for Cirrus Logic EP721x/EP731x-based SoCs depends on ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM. As the latter selects AUTO_ZRELADDR, TIMER_OF, COMMON_CLK, GENERIC_CLOCKEVENTS, and USE_OF, there is no need for ARCH_CLPS711X to select any of them. Link: https://lore.kernel.org/r/20200505150722.1575-8-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Alexander Shiyan Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/mach-clps711x/Kconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index fc9188b54dd6..314de9477b84 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -2,15 +2,10 @@ menuconfig ARCH_CLPS711X bool "Cirrus Logic EP721x/EP731x-based" depends on ARCH_MULTI_V4T - select AUTO_ZRELADDR - select TIMER_OF select CLPS711X_TIMER - select COMMON_CLK select CPU_ARM720T - select GENERIC_CLOCKEVENTS select GPIOLIB select MFD_SYSCON select OF_IRQ - select USE_OF help Select this if you use ARMv4T Cirrus Logic chips. -- cgit v1.2.3-70-g09d2 From 671ae272850484844b0897bf1c2f01a52a284dc7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:15 +0200 Subject: ARM: davinci: Drop unneeded select of TIMER_OF Support for TI DaVinci SoCs depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects TIMER_OF, there is no need for MACH_DA8XX_DT to select TIMER_OF. Link: https://lore.kernel.org/r/20200505150722.1575-9-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Sekhar Nori Cc: Bartosz Golaszewski Acked-by: Arnd Bergmann Acked-by: Sekhar Nori Signed-off-by: Arnd Bergmann --- arch/arm/mach-davinci/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 02b180ad7245..d028d38a44bf 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -64,7 +64,6 @@ config MACH_DA8XX_DT default y depends on ARCH_DAVINCI_DA850 select PINCTRL - select TIMER_OF help Say y here to include support for TI DaVinci DA850 based using Flattened Device Tree. More information at Documentation/devicetree -- cgit v1.2.3-70-g09d2 From 1942cf1cb5e233a9223c1ad1ea05aa26bce7a51c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:17 +0200 Subject: ARM: mmp: Drop unneeded select of COMMON_CLK Support for Marvell MMP ARMv5 platforms depends on ARCH_MULTI_V5, and thus on ARCH_MULTIPLATFORM. As the latter selects COMMON_CLK, there is no need for MACH_MMP_DT to select COMMON_CLK. Link: https://lore.kernel.org/r/20200505150722.1575-11-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Lubomir Rintel Acked-by: Arnd Bergmann Acked-by: Lubomir Rintel Signed-off-by: Arnd Bergmann --- arch/arm/mach-mmp/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b58a03b18bde..6fe1550f43ec 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -110,7 +110,6 @@ config MACH_MMP_DT depends on ARCH_MULTI_V5 select PINCTRL select PINCTRL_SINGLE - select COMMON_CLK select ARCH_HAS_RESET_CONTROLLER select CPU_MOHAWK help -- cgit v1.2.3-70-g09d2 From c5b18873f5b956bd46d42effbffb1b929788190a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:18 +0200 Subject: ARM: mvebu: Drop unneeded select of HAVE_SMP Support for Marvell Armada 375, 380, 385, and 39x SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for MACH_ARMADA_375, MACH_ARMADA_38X, and MACH_ARMADA_39X to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-12-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth Acked-by: Arnd Bergmann Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/mach-mvebu/Kconfig | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 7a5629b9bede..34dbeaab94b0 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -47,7 +47,6 @@ config MACH_ARMADA_375 select ARMADA_375_CLK select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP - select HAVE_SMP select MACH_MVEBU_V7 select PINCTRL_ARMADA_375 help @@ -66,7 +65,6 @@ config MACH_ARMADA_38X select ARMADA_38X_CLK select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP - select HAVE_SMP select MACH_MVEBU_V7 select PINCTRL_ARMADA_38X help @@ -82,7 +80,6 @@ config MACH_ARMADA_39X select CACHE_L2X0 select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP - select HAVE_SMP select MACH_MVEBU_V7 select PINCTRL_ARMADA_39X help -- cgit v1.2.3-70-g09d2 From 9fe2b45889db54fdfa9080f826e08e3bdcf0e18d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:20 +0200 Subject: ARM: prima2: Drop unneeded select of HAVE_SMP Support for CSR SiRF SoCs depends on ARCH_MULTI_V7. As the latter selects HAVE_SMP, there is no need for ARCH_ATLAS7 to select HAVE_SMP. Link: https://lore.kernel.org/r/20200505150722.1575-14-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Barry Song Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/mach-prima2/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 6f66785fab01..ea077f66372d 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -30,7 +30,6 @@ config ARCH_ATLAS7 select ARM_GIC select ATLAS7_TIMER select HAVE_ARM_SCU if SMP - select HAVE_SMP help Support for CSR SiRFSoC ARM Cortex A7 Platform -- cgit v1.2.3-70-g09d2 From 9d281a4f6fd61341da2fd08bf0b9449ed72b40e3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 5 May 2020 17:07:22 +0200 Subject: ARM: socfpga: Drop unneeded select of PCI_DOMAINS_GENERIC Support for Altera SOCFPGA systems depends on ARCH_MULTI_V7, and thus on ARCH_MULTIPLATFORM. As the latter selects PCI_DOMAINS_GENERIC, there is no need for ARCH_SOCFPGA to select PCI_DOMAINS_GENERIC. Link: https://lore.kernel.org/r/20200505150722.1575-16-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Cc: Dinh Nguyen Acked-by: Arnd Bergmann Acked-by: Dinh Nguyen Signed-off-by: Arnd Bergmann --- arch/arm/mach-socfpga/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 22af5e308db6..c3bb68d57cea 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,7 +11,6 @@ menuconfig ARCH_SOCFPGA select HAVE_ARM_SCU select HAVE_ARM_TWD if SMP select MFD_SYSCON - select PCI_DOMAINS_GENERIC if PCI select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- cgit v1.2.3-70-g09d2 From 1f6ed224594653556adbd8392e03ef0e168c1d48 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 24 Jul 2019 17:00:59 +0800 Subject: arm: dts: mt7623: add Mali-450 device node Add a node for Mali-450. Signed-off-by: Sean Wang Signed-off-by: Ryder Lee Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index f76b4a3c34b9..3a6b856e5b74 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2017-2018 MediaTek Inc. * Author: John Crispin * Sean Wang + * Ryder Lee * */ @@ -733,6 +734,30 @@ #reset-cells = <1>; }; + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", -- cgit v1.2.3-70-g09d2 From 189881af810d452b592ee958db43eb4c57df9803 Mon Sep 17 00:00:00 2001 From: Min Guo Date: Wed, 11 Dec 2019 09:54:42 +0800 Subject: arm: dts: mt2701: Add usb2 device nodes Add musb nodes and usb2 phy nodes for MT2701 Signed-off-by: Min Guo Link: https://lore.kernel.org/r/20191211015446.11477-3-min.guo@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701-evb.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/mt2701.dtsi | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts index 88f8fd22302a..d1535f385f36 100644 --- a/arch/arm/boot/dts/mt2701-evb.dts +++ b/arch/arm/boot/dts/mt2701-evb.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "mt2701.dtsi" / { @@ -61,6 +62,15 @@ >; default-brightness-level = <9>; }; + + usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &auxadc { @@ -230,3 +240,14 @@ &uart0 { status = "okay"; }; + +&usb2 { + status = "okay"; + usb-role-switch; + connector{ + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_vbus>; + }; +}; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 2093b38d6e6d..39b3a2f4bef4 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -671,6 +671,39 @@ }; }; + usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy0: usb-phy@11210000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@1a1c4800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; -- cgit v1.2.3-70-g09d2 From c589d6da965e395ce4e6ba47fb382b1c47c50fe3 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 29 Apr 2020 07:30:35 +0300 Subject: ARM: dts: marvell: drop i2c timeout-ms property The timeout-ms property for i2c master nodes is undocumented, and as never been supported. Drop it. Signed-off-by: Baruch Siach Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-xp.dtsi | 2 -- arch/arm/boot/dts/armada-375.dtsi | 2 -- arch/arm/boot/dts/armada-38x.dtsi | 2 -- arch/arm/boot/dts/armada-39x.dtsi | 4 ---- arch/arm/boot/dts/dove.dtsi | 1 - 5 files changed, 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index c15f5e92f97f..0b8c2a64b36f 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -114,7 +114,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <31>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -124,7 +123,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <32>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 2932a29ae272..9805e507c695 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -236,7 +236,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -247,7 +246,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index e038abc0c6b4..348116501aa2 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -153,7 +153,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -164,7 +163,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index b1b86934c688..e0b7c2099831 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -108,7 +108,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -119,7 +118,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -130,7 +128,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -141,7 +138,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3081b04e8c08..a551fabae851 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -175,7 +175,6 @@ #size-cells = <0>; interrupts = <11>; clock-frequency = <400000>; - timeout-ms = <1000>; clocks = <&core_clk 0>; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 2bf399defde86792b272a617500d891ef234eb4f Mon Sep 17 00:00:00 2001 From: Pawel Dembicki Date: Wed, 22 Apr 2020 17:00:06 +0200 Subject: ARM: dts: kirkwood: Add Check Point L-50 board This patch adds dts for the Check Point L-50 from 600/1100 series routers. Specification: -CPU: Marvell Kirkwood 88F6821 1200MHz -RAM: 512MB -Flash: NAND 512MB -WiFi: mPCIe card based on Atheros AR9287 b/g/n -WAN: 1 Gigabit Port (Marvell 88E1116R PHY) -LAN: 9 Gigabit Ports (2x Marvell 88E6171(5+4)) -USB: 2x USB2.0 -Express card slot -SD card slot -Serial console: RJ-45 115200 8n1 -Unsupported DSL Reviewed-by: Andrew Lunn Signed-off-by: Pawel Dembicki Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-l-50.dts | 438 ++++++++++++++++++++++++++++++++++++ 2 files changed, 439 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-l-50.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e8dd99201397..eba030b3ba69 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -279,6 +279,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ kirkwood-km_kirkwood.dtb \ + kirkwood-l-50.dtb \ kirkwood-laplug.dtb \ kirkwood-linkstation-lsqvl.dtb \ kirkwood-linkstation-lsvl.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts new file mode 100644 index 000000000000..0d81c43a6a73 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-l-50.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Check Point L-50 Board Description + * Copyright 2020 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Check Point L-50"; + compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_button29: pmx_button29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led38: pmx_led38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio1 14 9>; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + gpio2: gpio-expander@20{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x20>; + + gpio-controller; + }; + + /* Three GPIOs from 0x21 exp. are undescribed in dts: + * 1: DSL module reset (active low) + * 5: mPCIE reset (active low) + * 6: Express card reset (active low) + */ + gpio3: gpio-expander@21{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x21>; + + gpio-controller; + }; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_green { + label = "l-50:green:status"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + status_red { + label = "l-50:red:status"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + wifi { + label = "l-50:green:wifi"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + internet_green { + label = "l-50:green:internet"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + + internet_red { + label = "l-50:red:internet"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + usb1_green { + label = "l-50:green:usb1"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port3>; + }; + + usb1_red { + label = "l-50:red:usb1"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + usb2_green { + label = "l-50:green:usb2"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + + usb2_red { + label = "l-50:red:usb2"; + gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb2_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + usb1_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb1_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + mpcie_pwr { + compatible = "regulator-fixed"; + regulator-name = "mpcie_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + express_card_pwr { + compatible = "regulator-fixed"; + regulator-name = "express_card_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory_defaults { + label = "factory_defaults"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy8: ethernet-phy@8 { + reg = <0x08>; + }; + + switch0: switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan6"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan7"; + }; + + switch0port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch1port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <ð1port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + switch@11 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11>; + dsa,member = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan8"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "dmz"; + }; + + switch1port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "dsl"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy8>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000c0000>; + }; + + partition@a0000 { + label = "bootldr-env"; + reg = <0x000c0000 0x00040000>; + }; + + partition@100000 { + label = "kernel-1"; + reg = <0x00100000 0x00800000>; + }; + + partition@900000 { + label = "rootfs-1"; + reg = <0x00900000 0x07100000>; + }; + + partition@7a00000 { + label = "kernel-2"; + reg = <0x07a00000 0x00800000>; + }; + + partition@8200000 { + label = "rootfs-2"; + reg = <0x08200000 0x07100000>; + }; + + partition@f300000 { + label = "default_sw"; + reg = <0x0f300000 0x07900000>; + }; + + partition@16c00000 { + label = "logs"; + reg = <0x16c00000 0x01800000>; + }; + + partition@18400000 { + label = "preset_cfg"; + reg = <0x18400000 0x00100000>; + }; + + partition@18500000 { + label = "adsl"; + reg = <0x18500000 0x00100000>; + }; + + partition@18600000 { + label = "storage"; + reg = <0x18600000 0x07a00000>; + }; +}; + +&rtc { + status = "disabled"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port3: port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 1383d42cffa68c03d886ae846b3e3f6e3bbd784c Mon Sep 17 00:00:00 2001 From: "Brian J. Tarricone" Date: Sat, 25 Apr 2020 12:28:20 -0700 Subject: ARM: dts: kirkwood: ReadyNAS NV+v2: Add LCD panel The NV+ v2 has a WH1602 LCD panel (which is just a rebranded HD44780), similar to the Netgear RN104, just with different GPIO assignments. Signed-off-by: Brian J. Tarricone Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 8cc8550242ef..b13aee570804 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -113,6 +113,20 @@ }; }; + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio1 1 GPIO_ACTIVE_HIGH>, + <&gpio1 3 GPIO_ACTIVE_HIGH>, + <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup -- cgit v1.2.3-70-g09d2 From bb5cce12ac717c7462217cd493ed701d12d6dbce Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 May 2020 11:29:58 +0100 Subject: arm64: dts: fvp/juno: Fix node address fields The Arm Ltd. boards were using an outdated address convention in the DT node names, by separating the high from the low 32-bits of an address by a comma. Remove the comma from the node name suffix to be DT spec compliant. Link: https://lore.kernel.org/r/20200513103016.130417-3-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 10 +++++----- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 4 ++-- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 6 +++--- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 5c183483ec3b..8010cdcdb37a 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -31,7 +31,7 @@ #interrupt-cells = <1>; ranges; - nor_flash: flash@0,00000000 { + nor_flash: flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; @@ -41,13 +41,13 @@ }; }; - psram@1,00000000 { + psram@100000000 { compatible = "arm,vexpress-psram", "mtd-ram"; reg = <1 0x00000000 0x02000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -59,14 +59,14 @@ vddvario-supply = <&v2m_fixed_3v3>; }; - usb@2,03000000 { + usb@203000000 { compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; port1-otg; }; - iofpga@3,00000000 { + iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 12f039fa3dad..e26b492795c5 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -151,7 +151,7 @@ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -178,7 +178,7 @@ clock-output-names = "v2m:refclk32khz"; }; - iofpga@3,00000000 { + iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index e3983ded3c3c..d5cefddde08c 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -103,7 +103,7 @@ }; }; - flash@0,00000000 { + flash@0 { /* 2 * 32MiB NOR Flash memory mounted on CS0 */ compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>; @@ -120,7 +120,7 @@ }; }; - ethernet@2,00000000 { + ethernet@200000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; interrupts = <3>; @@ -133,7 +133,7 @@ vddvario-supply = <&mb_fixed_3v3>; }; - iofpga@3,00000000 { + iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 60703b5763c6..350cbf17e8b4 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -9,7 +9,7 @@ motherboard { arm,v2m-memory-map = "rs2"; - iofpga@3,00000000 { + iofpga@300000000 { virtio-p9@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index e333c8d2d0e4..d1bfa62ca073 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -17,14 +17,14 @@ #interrupt-cells = <1>; ranges; - flash@0,00000000 { + flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -51,7 +51,7 @@ clock-output-names = "v2m:refclk32khz"; }; - iofpga@3,00000000 { + iofpga@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-70-g09d2 From d9258898ad49cbb46caffe23af0d4f0b766e67a2 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 May 2020 11:30:00 +0100 Subject: arm64: dts: vexpress: Move fixed devices out of bus node The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/refclk32khz missing or empty reg/ranges property Move the fixed clocks, the fixed regulator, the leds and the config bus subtree to the root node, since they do not depend on any busses. Link: https://lore.kernel.org/r/20200513103016.130417-5-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 308 ++++++++++++++++---------------- 1 file changed, 154 insertions(+), 154 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 8010cdcdb37a..d4d88ce996a5 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -19,6 +19,160 @@ */ / { + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + bus@8000000 { motherboard { model = "V2M-P1"; @@ -282,160 +436,6 @@ }; }; }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; }; }; }; -- cgit v1.2.3-70-g09d2 From 4908471e1ed767504ccfe3561e3a72c7458b1138 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 16 May 2020 23:29:13 +0200 Subject: ARM: dts: ux500: Add touchscreen to the Skomer This adds touchscreen support to the Ux500 Samsung GT-S7710 "Skomer" mobile phone. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200516212913.485365-1-linus.walleij@linaro.org --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 32 +++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index c7d4ad34e569..8edef161613a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -367,7 +367,28 @@ pinctrl-0 = <&i2c3_c_2_default>; pinctrl-1 = <&i2c3_c_2_sleep>; - /* TODO: this should be used by the Cypress TMA140 touchscreen */ + /* Cypress CY8CTMA140 touchscreen */ + touchscreen@20 { + compatible = "cypress,cy8ctma140"; + clock-frequency = <400000>; + reg = <0x20>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-max-pressure = <255>; + + /* GPIO218 for IRQ */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + /* VDD is "digital supply" nominally 1.71-3.6V */ + vdd-supply = <&ab8500_ldo_aux2_reg>; + /* VCPIN is "analog supply", 2.7-3.6 V */ + vcpin-supply = <&ab8500_ldo_aux2_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tma140_skomer_default>; + }; }; mcde@a0350000 { @@ -562,6 +583,15 @@ }; }; }; + /* Interrupt line for the Cypress TMA140 touchscreen */ + touchscreen { + tma140_skomer_default: tma140_skomer { + skomer_cfg1 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; }; &ab8505_gpio { -- cgit v1.2.3-70-g09d2 From 88d801aec6e971c15a0bfb4d46d02476dde9e8aa Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 18 May 2020 11:49:21 +0000 Subject: ARM: dts: at91: sama5d2_xplained: Add aliases for the dedicated I2C IPs The sama5d2 SoC has two dedicated I2C IPs that are enabled on sama5d2_xplained. Add alias for the i2c devices to not rely on probe order for the i2c device numbering. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200518114802.253660-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 851b8587068b..a927165ea7c2 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -18,6 +18,8 @@ aliases { serial0 = &uart1; /* DBGU */ + i2c0 = &i2c0; + i2c1 = &i2c1; i2c2 = &i2c2; /* XPRO EXT2 */ }; -- cgit v1.2.3-70-g09d2 From 608f1b6cf366a3d429dab08c67117a9699c982c1 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 May 2020 11:30:09 +0100 Subject: arm64: dts: fvp/juno: Fix serial node names The UARTs for all Arm Ltd. boards were using "uart" as their node name stub. Replace that with the required "serial" string, to comply with the PL011 DT binding. Link: https://lore.kernel.org/r/20200513103016.130417-14-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 8 ++++---- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 8 ++++---- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index d4d88ce996a5..f4a65d693f15 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -316,7 +316,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -324,7 +324,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -332,7 +332,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -340,7 +340,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 63efb88595d4..e226c5e080c2 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -189,7 +189,7 @@ reg = <0x010000 0x1000>; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -197,7 +197,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -205,7 +205,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -213,7 +213,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 2b34661d426c..ee860d539395 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -729,7 +729,7 @@ }; }; - soc_uart0: uart@7ff80000 { + soc_uart0: serial@7ff80000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x7ff80000 0x0 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index f61e313ab1a4..b81651b1890a 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -158,7 +158,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -166,7 +166,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -174,7 +174,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -182,7 +182,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; -- cgit v1.2.3-70-g09d2 From 9d0a36ddcc523e8c64781ac4b38cae8410736c56 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 May 2020 11:30:11 +0100 Subject: arm64: dts: fvp/juno: Fix bus node names Most Arm Ltd. boards are employing a layered bus structure, to map the hardware design (SoC, motherboard, IOFPGA) and structure the DTs. The "simple-bus" nodes only allow a limited set of node names. Switch to use *-bus to be binding compliant. This relies on a pending dt-schema.git fix for now: https://github.com/devicetree-org/dt-schema/pull/38 Link: https://lore.kernel.org/r/20200513103016.130417-16-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 4 ++-- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 2 +- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 4 ++-- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 4 ++-- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 4 ++-- 6 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index f4a65d693f15..f5c8f07b4918 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -174,7 +174,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { model = "V2M-P1"; arm,hbi = <0x190>; arm,vexpress,site = <0>; @@ -220,7 +220,7 @@ port1-otg; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index e226c5e080c2..05ae893d1b2e 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -178,7 +178,7 @@ interrupts = <15>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index ee860d539395..bd4e0b15f9c8 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -828,7 +828,7 @@ <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; }; - site2: tlx@60000000 { + site2: tlx-bus@60000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index f3279327a665..eeee51f1251b 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -92,7 +92,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { compatible = "arm,vexpress,v2p-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; @@ -133,7 +133,7 @@ vddvario-supply = <&mb_fixed_3v3>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 350cbf17e8b4..b917d9d3f1c4 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -6,10 +6,10 @@ */ / { bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs2"; - iofpga@300000000 { + iofpga-bus@300000000 { virtio-p9@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index b81651b1890a..001a0a3c7f66 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -77,7 +77,7 @@ }; bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ @@ -98,7 +98,7 @@ interrupts = <15>; }; - iofpga@300000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-70-g09d2 From 3b42c06061cde145c9b4feb933d9d416c94e05d0 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 13 May 2020 11:30:13 +0100 Subject: arm64: dts: vexpress: Fix VExpress LED names The common LED binding wants the LED node names to start with led- and then have just a single number. Changing the naming for the 8 user LEDs from using user to led-. Also there is no default-trigger named "mmc0" in the kernel, so use the more generic "disk-activity". Link: https://lore.kernel.org/r/20200513103016.130417-18-andre.przywara@arm.com Signed-off-by: Andre Przywara Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index f5c8f07b4918..e6308fb76183 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -51,49 +51,49 @@ leds { compatible = "gpio-leds"; - user1 { + led-1 { label = "v2m:green:user1"; gpios = <&v2m_led_gpios 0 0>; linux,default-trigger = "heartbeat"; }; - user2 { + led-2 { label = "v2m:green:user2"; gpios = <&v2m_led_gpios 1 0>; linux,default-trigger = "disk-activity"; }; - user3 { + led-3 { label = "v2m:green:user3"; gpios = <&v2m_led_gpios 2 0>; linux,default-trigger = "cpu0"; }; - user4 { + led-4 { label = "v2m:green:user4"; gpios = <&v2m_led_gpios 3 0>; linux,default-trigger = "cpu1"; }; - user5 { + led-5 { label = "v2m:green:user5"; gpios = <&v2m_led_gpios 4 0>; linux,default-trigger = "cpu2"; }; - user6 { + led-6 { label = "v2m:green:user6"; gpios = <&v2m_led_gpios 5 0>; linux,default-trigger = "cpu3"; }; - user7 { + led-7 { label = "v2m:green:user7"; gpios = <&v2m_led_gpios 6 0>; linux,default-trigger = "cpu4"; }; - user8 { + led-8 { label = "v2m:green:user8"; gpios = <&v2m_led_gpios 7 0>; linux,default-trigger = "cpu5"; -- cgit v1.2.3-70-g09d2 From f0344b33546cee3ea887d41e07900226dec6a23a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 28 Apr 2020 16:49:32 +0200 Subject: ARM: dts: rockchip: rename and label gpio-led subnodes Current dts files with 'gpio-led' nodes were manually verified. In order to automate this process leds-gpio.txt has been converted to yaml. With this conversion a check for pattern properties was added. A test with the command below gives a screen full of warnings like: arch/arm/boot/dts/rk3188-radxarock.dt.yaml: gpio-leds: 'blue', 'green', 'sleep' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Fix these errors with help of the following rules: 1: Add nodename in the preferred form. 2: Always add a label that ends with '_led' to prevent conflicts with other labels such as 'power' and 'mmc' 3: If leds need pinctrl add a label that ends with '_led_pin' also to prevent conflicts with other labels. patternProperties: # The first form is preferred, but fall back to just 'led' # anywhere in the node name to at least catch some child nodes. "(^led-[0-9a-f]$|led)": make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/leds/ leds-gpio.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200428144933.10953-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 2 +- arch/arm/boot/dts/rk3066a-mk808.dts | 2 +- arch/arm/boot/dts/rk3188-radxarock.dts | 6 +++--- arch/arm/boot/dts/rk3229-xms6.dts | 2 +- arch/arm/boot/dts/rk3288-firefly-reload.dts | 12 ++++++------ arch/arm/boot/dts/rk3288-firefly.dtsi | 12 ++++++------ arch/arm/boot/dts/rk3288-miqi.dts | 2 +- arch/arm/boot/dts/rk3288-phycore-som.dtsi | 6 +++--- arch/arm/boot/dts/rk3288-rock2-square.dts | 4 ++-- arch/arm/boot/dts/rk3288-tinker.dtsi | 6 +++--- 10 files changed, 27 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 2ff9f152d29b..7154b827ea2f 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -16,7 +16,7 @@ leds: gpio-leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; label = "kylin:red:led"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 365eff621113..eed9e60cffa2 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -22,7 +22,7 @@ gpio-leds { compatible = "gpio-leds"; - blue { + blue_led: led-0 { label = "mk808:blue:power"; gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index c9a7f5409960..b0fef82c0a71 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -33,19 +33,19 @@ gpio-leds { compatible = "gpio-leds"; - green { + green_led: led-0 { label = "rock:green:user1"; gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blue { + blue_led: led-1 { label = "rock:blue:user2"; gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sleep { + sleep_led: led-2 { label = "rock:red:power"; gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts index 679fc2b00e5a..9252a735c450 100644 --- a/arch/arm/boot/dts/rk3229-xms6.dts +++ b/arch/arm/boot/dts/rk3229-xms6.dts @@ -33,7 +33,7 @@ power-led { compatible = "gpio-leds"; - blue { + blue_led: led-0 { gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 8c38bda21a7c..9a4a9749c405 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -45,20 +45,20 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:blue:power"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; panic-indicator; }; - work { + work_led: led-1 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; }; @@ -334,11 +334,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 5e0a19004e46..e5c4fd4ea67e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -62,20 +62,20 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; - power { + power_led: led-1 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:green:power"; linux,default-trigger = "default-on"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; }; }; @@ -429,11 +429,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index c41d012c8850..213c9eb84f76 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -30,7 +30,7 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; label = "miqi:green:user"; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi index 77a47b9b756d..e43887c9635f 100644 --- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi @@ -36,9 +36,9 @@ leds: user-leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led>; + pinctrl-0 = <&user_led_pin>; - user { + user_led: led-0 { label = "green_led"; gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -372,7 +372,7 @@ }; leds { - user_led: user-led { + user_led_pin: user-led-pin { rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; }; }; diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index cdcdc921ee09..3cca4d0f9b09 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -41,13 +41,13 @@ gpio-leds { compatible = "gpio-leds"; - heartbeat { + heartbeat_led: led-0 { gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; label = "rock2:green:state1"; linux,default-trigger = "heartbeat"; }; - mmc { + mmc_led: led-1 { gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; label = "rock2:blue:state2"; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index acfaa12ec239..90e9be443fe6 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -46,17 +46,17 @@ gpio-leds { compatible = "gpio-leds"; - act-led { + act_led: led-0 { gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - heartbeat-led { + heartbeat_led: led-1 { gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - pwr-led { + pwr_led: led-2 { gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; -- cgit v1.2.3-70-g09d2 From 439062737bc06232761196f07046872d0ce3f3d6 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 3 Apr 2020 20:01:56 +0200 Subject: ARM: dts: rockchip: remove identical #include from rk3288.dtsi There are 2 identical '#include' for 'rk3288-power.h', so remove one of them. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200403180159.13387-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 0cd88774db95..2e1edd85f04a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -7,7 +7,6 @@ #include #include #include -#include #include / { -- cgit v1.2.3-70-g09d2 From 6067ec2c7ffacab4689ddfed3df74a467d112efe Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Mon, 6 Apr 2020 13:50:04 +0000 Subject: ARM: dts: enable WLAN for Mecer Xtreme Mini S6 The Mecer Xtreme Mini S6 features a wireless module, based on a Realtek 8723BS, which provides WLAN and Bluetooth connectivity via SDIO and UART interfaces respectively. Define a simple MMC power sequence that declares the GPIO pins connected to the module's WLAN Disable and Bluetooth Disable pins as active low reset signals, because both signals must be deasserted for WLAN radio operation. Configure the host's SDIO interface for High Speed mode with 1.8v I/O signalling and IRQ detection over a 4-bit wide bus. Signed-off-by: Justin Swartz Link: https://lore.kernel.org/r/20200406135006.23759-1-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3229-xms6.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts index 9252a735c450..727734d6da9b 100644 --- a/arch/arm/boot/dts/rk3229-xms6.dts +++ b/arch/arm/boot/dts/rk3229-xms6.dts @@ -39,6 +39,12 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 29 GPIO_ACTIVE_LOW>; + }; + vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -202,6 +208,16 @@ status = "okay"; }; +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + vqmmc-supply = <&vccio_1v8>; + status = "okay"; +}; + &sdmmc { cap-mmc-highspeed; disable-wp; -- cgit v1.2.3-70-g09d2 From 2dd579fc969882c0036433a74446ba5e57ffab2d Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Mon, 6 Apr 2020 13:50:05 +0000 Subject: ARM: dts: remove disable-wp from rk3229-xms6 emmc Remove the disable-wp attribute from &emmc as it is, according to Documentation/devicetree/bindings/mmc/mmc-controller.yaml: "Not used in combination with eMMC or SDIO." Suggested-by: Johan Jonker Signed-off-by: Justin Swartz Link: https://lore.kernel.org/r/20200406135006.23759-2-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3229-xms6.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts index 727734d6da9b..96c9372a89ee 100644 --- a/arch/arm/boot/dts/rk3229-xms6.dts +++ b/arch/arm/boot/dts/rk3229-xms6.dts @@ -137,7 +137,6 @@ &emmc { cap-mmc-highspeed; - disable-wp; non-removable; status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 54b1a4e070330c3fba5becfb0b619bf360bc2657 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sun, 19 Apr 2020 12:51:33 +0000 Subject: ARM: dts: rockchip: add rga node for rk322x Add a node to define the presence of RGA, a 2D raster graphic acceleration unit. Signed-off-by: Justin Swartz Link: https://lore.kernel.org/r/20200419125134.29923-2-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 06172ebbf0ce..b37ba72d32ca 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -615,6 +615,16 @@ status = "disabled"; }; + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + iep_mmu: iommu@20070800 { compatible = "rockchip,iommu"; reg = <0x20070800 0x100>; -- cgit v1.2.3-70-g09d2 From 0697e5e06ea0d96e2d1508104ff3b13e4dddc4bb Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Tue, 12 May 2020 18:11:19 +0100 Subject: ARM: 8974/1: use SPARSMEM_STATIC when SPARSEMEM is enabled The commit 3e347261a80b5 ("[PATCH] sparsemem extreme implementation") made SPARSMEM_EXTREME the default option for configurations that enable SPARSEMEM. For ARM systems with handful of memory banks SPARSEMEM_EXTREME is an overkill. Ensure that SPARSMEM_STATIC is enabled in the configurations that use SPARSEMEM. Fixes: 3e347261a80b5 ("[PATCH] sparsemem extreme implementation") Acked-by: Florian Fainelli Signed-off-by: Mike Rapoport Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 66a04f6f4775..c88a48d622fc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1517,6 +1517,7 @@ config ARCH_HAS_HOLES_MEMORYMODEL config ARCH_SPARSEMEM_ENABLE bool + select SPARSEMEM_STATIC config ARCH_SPARSEMEM_DEFAULT def_bool ARCH_SPARSEMEM_ENABLE -- cgit v1.2.3-70-g09d2 From cdcb07e45a911a5be9d38bb1aff1f6de019503b2 Mon Sep 17 00:00:00 2001 From: Vincent Whitchurch Date: Thu, 14 May 2020 11:36:42 +0100 Subject: ARM: 8975/1: module: fix handling of unwind init sections Unwind information for init sections is placed in .ARM.exidx.init.text and .ARM.extab.init.text. The module core doesn't know that these are init sections so they are allocated along with the core sections, and if the core and init sections get allocated in different memory regions (which is possible with CONFIG_ARM_MODULE_PLTS=y) and they can't reach each other, relocation fails: final section addresses: ... 0x7f800000 .init.text .. 0xcbb54078 .ARM.exidx.init.text .. section 16 reloc 0 sym '': relocation 42 out of range (0xcbb54078 -> 0x7f800000) Fix this by informing the module core that these sections are init sections, and by removing the init unwind tables before the module core frees the init sections. Signed-off-by: Vincent Whitchurch Signed-off-by: Russell King --- arch/arm/kernel/module.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index deef17f34bd2..af0a8500a24e 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -55,6 +55,13 @@ void *module_alloc(unsigned long size) } #endif +bool module_init_section(const char *name) +{ + return strstarts(name, ".init") || + strstarts(name, ".ARM.extab.init") || + strstarts(name, ".ARM.exidx.init"); +} + bool module_exit_section(const char *name) { return strstarts(name, ".exit") || @@ -409,8 +416,17 @@ module_arch_cleanup(struct module *mod) #ifdef CONFIG_ARM_UNWIND int i; - for (i = 0; i < ARM_SEC_MAX; i++) - if (mod->arch.unwind[i]) - unwind_table_del(mod->arch.unwind[i]); + for (i = 0; i < ARM_SEC_MAX; i++) { + unwind_table_del(mod->arch.unwind[i]); + mod->arch.unwind[i] = NULL; + } +#endif +} + +void __weak module_arch_freeing_init(struct module *mod) +{ +#ifdef CONFIG_ARM_UNWIND + unwind_table_del(mod->arch.unwind[ARM_SEC_INIT]); + mod->arch.unwind[ARM_SEC_INIT] = NULL; #endif } -- cgit v1.2.3-70-g09d2 From 691cbe5ba5f77f3759f3491b971a96f9998dcd9d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Apr 2020 18:21:31 +0200 Subject: ARM: decompressor: move headroom variable out of LC0 Before breaking up LC0 into different pieces, move out the variable that is already place-relative (given that it subtracts 'restart' in the expression) and so its value does not need to be added to the runtime address of the LC0 symbol itself. Signed-off-by: Ard Biesheuvel Reviewed-by: Geert Uytterhoeven Reviewed-by: Nicolas Pitre --- arch/arm/boot/compressed/head.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index cabdd8f4a248..42b8d67beab6 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -287,7 +287,7 @@ not_angel: */ mov r0, pc cmp r0, r4 - ldrcc r0, LC0+28 + ldrcc r0, .Lheadroom addcc r0, r0, pc cmpcc r4, r0 orrcc r4, r4, #1 @ remember we skipped cache_on @@ -664,9 +664,11 @@ LC0: .word LC0 @ r1 .word _got_start @ r11 .word _got_end @ ip .word .L_user_stack_end @ sp - .word _end - restart + 16384 + 1024*1024 .size LC0, . - LC0 +.Lheadroom: + .word _end - restart + 16384 + 1024*1024 + .Linflated_image_size_offset: .long (input_data_end - 4) - . -- cgit v1.2.3-70-g09d2 From 161e04a5bae58a65d2b13642845f250888a845a1 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Apr 2020 18:21:32 +0200 Subject: ARM: decompressor: split off _edata and stack base into separate object In preparation of moving the handling of the LC0 object to a later stage in the decompressor startup code, move out _edata and the initial value of the stack pointer, which are needed earlier than the remaining contents of LC0. Signed-off-by: Ard Biesheuvel Reviewed-by: Geert Uytterhoeven Reviewed-by: Nicolas Pitre --- arch/arm/boot/compressed/head.S | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 42b8d67beab6..5d712e2c0001 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -293,22 +293,20 @@ not_angel: orrcc r4, r4, #1 @ remember we skipped cache_on blcs cache_on -restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r6, r11, r12} - ldr sp, [r0, #24] +restart: adr r0, LC1 + ldr sp, [r0] + ldr r6, [r0, #4] + add sp, sp, r0 + add r6, r6, r0 - /* - * We might be running at a different address. We need - * to fix up various pointers. - */ + adr r0, LC0 + ldmia r0, {r1, r2, r3, r11, r12} sub r0, r0, r1 @ calculate the delta offset - add r6, r6, r0 @ _edata get_inflated_image_size r9, r10, lr #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ - add sp, sp, r0 add r10, sp, #0x10000 #else /* @@ -660,12 +658,15 @@ not_relocated: mov r0, #0 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 - .word _edata @ r6 .word _got_start @ r11 .word _got_end @ ip - .word .L_user_stack_end @ sp .size LC0, . - LC0 + .type LC1, #object +LC1: .word .L_user_stack_end - LC1 @ sp + .word _edata - LC1 @ r6 + .size LC1, . - LC1 + .Lheadroom: .word _end - restart + 16384 + 1024*1024 -- cgit v1.2.3-70-g09d2 From f1f012b033e6651cd5c5b43d1722976cf6baf973 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Apr 2020 18:21:33 +0200 Subject: ARM: decompressor: defer loading of the contents of the LC0 structure The remaining contents of LC0 are only used after the point in the decompressor startup code where we enter via 'wont_overwrite'. So move the loading of the LC0 structure after it. This will allow us to jump to wont_overwrite directly from the EFI stub, and execute the decompressor in place at the offset it was loaded by the UEFI firmware. Signed-off-by: Ard Biesheuvel Reviewed-by: Geert Uytterhoeven Reviewed-by: Nicolas Pitre --- arch/arm/boot/compressed/head.S | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 5d712e2c0001..ce442ec5028a 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -299,10 +299,6 @@ restart: adr r0, LC1 add sp, sp, r0 add r6, r6, r0 - adr r0, LC0 - ldmia r0, {r1, r2, r3, r11, r12} - sub r0, r0, r1 @ calculate the delta offset - get_inflated_image_size r9, r10, lr #ifndef CONFIG_ZBOOT_ROM @@ -320,9 +316,6 @@ restart: adr r0, LC1 mov r5, #0 @ init dtb size to 0 #ifdef CONFIG_ARM_APPENDED_DTB /* - * r0 = delta - * r2 = BSS start - * r3 = BSS end * r4 = final kernel address (possibly with LSB set) * r5 = appended dtb size (still unknown) * r6 = _edata @@ -330,8 +323,6 @@ restart: adr r0, LC1 * r8 = atags/device tree pointer * r9 = size of decompressed image * r10 = end of this image, including bss/stack/malloc space if non XIP - * r11 = GOT start - * r12 = GOT end * sp = stack pointer * * if there are device trees (dtb) appended to zImage, advance r10 so that the @@ -379,7 +370,6 @@ restart: adr r0, LC1 /* temporarily relocate the stack past the DTB work space */ add sp, sp, r5 - stmfd sp!, {r0-r3, ip, lr} mov r0, r8 mov r1, r6 mov r2, r5 @@ -398,7 +388,6 @@ restart: adr r0, LC1 mov r2, r5 bleq atags_to_fdt - ldmfd sp!, {r0-r3, ip, lr} sub sp, sp, r5 #endif @@ -535,6 +524,10 @@ dtb_check_done: mov pc, r0 wont_overwrite: + adr r0, LC0 + ldmia r0, {r1, r2, r3, r11, r12} + sub r0, r0, r1 @ calculate the delta offset + /* * If delta is zero, we are running at the address we were linked at. * r0 = delta -- cgit v1.2.3-70-g09d2 From 35d57d1215ed0da3349180275b845f0c2ee62d08 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Apr 2020 18:21:34 +0200 Subject: ARM: decompressor: move GOT into .data for EFI enabled builds We will be running the decompressor in place after a future patch, instead of copying it around first. This means we no longer have to disable and re-enable the MMU and caches either. However, this means we will be loaded with the restricted permissions set by the UEFI firmware, which means that we have to move the GOT table into the data section in order for the contents to be writable by the code itself. Signed-off-by: Ard Biesheuvel Reviewed-by: Nicolas Pitre --- arch/arm/boot/compressed/vmlinux.lds.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index b247f399de71..d0619ec05705 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -63,9 +63,11 @@ SECTIONS _etext = .; .got.plt : { *(.got.plt) } +#ifndef CONFIG_EFI_STUB _got_start = .; .got : { *(.got) } _got_end = .; +#endif /* ensure the zImage file size is always a multiple of 64 bits */ /* (without a dummy byte, ld just ignores the empty section) */ @@ -74,6 +76,9 @@ SECTIONS #ifdef CONFIG_EFI_STUB .data : ALIGN(4096) { __pecoff_data_start = .; + _got_start = .; + *(.got) + _got_end = .; /* * The EFI stub always executes from RAM, and runs strictly before the * decompressor, so we can make an exception for its r/w data, and keep it -- cgit v1.2.3-70-g09d2 From d0f9ca9be11f25ef4151195eab7ea36d136084f6 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 13 Apr 2020 18:21:35 +0200 Subject: ARM: decompressor: run decompressor in place if loaded via UEFI The decompressor can load from anywhere in memory, and the only reason the EFI stub code relocates it is to ensure it appears within the first 128 MiB of memory, so that the uncompressed kernel ends up at the right offset in memory. We can short circuit this, and simply jump into the decompressor startup code at the point where it knows where the base of memory lives. This also means there is no need to disable the MMU and caches, create new page tables and re-enable them. Signed-off-by: Ard Biesheuvel Reviewed-by: Nicolas Pitre --- arch/arm/boot/compressed/head.S | 39 ++++++++++----------------- drivers/firmware/efi/libstub/arm32-stub.c | 45 +++++-------------------------- 2 files changed, 20 insertions(+), 64 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index ce442ec5028a..c79db44ba128 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1430,37 +1430,26 @@ reloc_code_end: #ifdef CONFIG_EFI_STUB ENTRY(efi_enter_kernel) - mov r7, r0 @ preserve image base - mov r4, r1 @ preserve DT pointer + mov r4, r0 @ preserve image base + mov r8, r1 @ preserve DT pointer - mov r0, r4 @ DT start - add r1, r4, r2 @ DT end - bl cache_clean_flush + mrc p15, 0, r0, c1, c0, 0 @ read SCTLR + tst r0, #0x1 @ MMU enabled? + orreq r4, r4, #1 @ set LSB if not - mov r0, r7 @ relocated zImage - ldr r1, =_edata @ size of zImage - add r1, r1, r0 @ end of zImage + mov r0, r8 @ DT start + add r1, r8, r2 @ DT end bl cache_clean_flush - @ The PE/COFF loader might not have cleaned the code we are - @ running beyond the PoU, and so calling cache_off below from - @ inside the PE/COFF loader allocated region is unsafe unless - @ we explicitly clean it to the PoC. - adr r0, call_cache_fn @ region of code we will - adr r1, 0f @ run with MMU off - bl cache_clean_flush - bl cache_off + adr r0, 0f @ switch to our stack + ldr sp, [r0] + add sp, sp, r0 - @ Set parameters for booting zImage according to boot protocol - @ put FDT address in r2, it was returned by efi_entry() - @ r1 is the machine type, and r0 needs to be 0 - mov r0, #0 - mov r1, #0xFFFFFFFF - mov r2, r4 - add r7, r7, #(__efi_start - start) - mov pc, r7 @ no mode switch + mov r5, #0 @ appended DTB size + mov r7, #0xFFFFFFFF @ machine ID + b wont_overwrite ENDPROC(efi_enter_kernel) -0: +0: .long .L_user_stack_end - . #endif .align diff --git a/drivers/firmware/efi/libstub/arm32-stub.c b/drivers/firmware/efi/libstub/arm32-stub.c index 7826553af2ba..0050d811bf20 100644 --- a/drivers/firmware/efi/libstub/arm32-stub.c +++ b/drivers/firmware/efi/libstub/arm32-stub.c @@ -199,14 +199,8 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, unsigned long kernel_base; efi_status_t status; - /* - * Verify that the DRAM base address is compatible with the ARM - * boot protocol, which determines the base of DRAM by masking - * off the low 27 bits of the address at which the zImage is - * loaded. These assumptions are made by the decompressor, - * before any memory map is available. - */ - kernel_base = round_up(dram_base, SZ_128M); + /* use a 16 MiB aligned base for the decompressed kernel */ + kernel_base = round_up(dram_base, SZ_16M) + TEXT_OFFSET; /* * Note that some platforms (notably, the Raspberry Pi 2) put @@ -215,41 +209,14 @@ efi_status_t handle_kernel_image(unsigned long *image_addr, * base of the kernel image is only partially used at the moment. * (Up to 5 pages are used for the swapper page tables) */ - kernel_base += TEXT_OFFSET - 5 * PAGE_SIZE; - - status = reserve_kernel_base(kernel_base, reserve_addr, reserve_size); + status = reserve_kernel_base(kernel_base - 5 * PAGE_SIZE, reserve_addr, + reserve_size); if (status != EFI_SUCCESS) { pr_efi_err("Unable to allocate memory for uncompressed kernel.\n"); return status; } - /* - * Relocate the zImage, so that it appears in the lowest 128 MB - * memory window. - */ - *image_addr = (unsigned long)image->image_base; - *image_size = image->image_size; - status = efi_relocate_kernel(image_addr, *image_size, *image_size, - kernel_base + MAX_UNCOMP_KERNEL_SIZE, 0, 0); - if (status != EFI_SUCCESS) { - pr_efi_err("Failed to relocate kernel.\n"); - efi_free(*reserve_size, *reserve_addr); - *reserve_size = 0; - return status; - } - - /* - * Check to see if we were able to allocate memory low enough - * in memory. The kernel determines the base of DRAM from the - * address at which the zImage is loaded. - */ - if (*image_addr + *image_size > dram_base + ZIMAGE_OFFSET_LIMIT) { - pr_efi_err("Failed to relocate kernel, no low memory available.\n"); - efi_free(*reserve_size, *reserve_addr); - *reserve_size = 0; - efi_free(*image_size, *image_addr); - *image_size = 0; - return EFI_LOAD_ERROR; - } + *image_addr = kernel_base; + *image_size = 0; return EFI_SUCCESS; } -- cgit v1.2.3-70-g09d2 From e69b4e1a7577c169e9f52edf977401734a6a29eb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: OMAP2+: Add omap_init_time_of() This allows us to move the SoCs to probe system timers one SoC at at time. As arch/arm/mach-omap2/timer.c will be eventually gone, let's just add omap_init_time_of() to board-generic.c directly. Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-generic.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index ff992f8895ee..c6f7dcf13a15 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,13 @@ static void __init __maybe_unused omap_generic_init(void) omap_soc_device_init(); } +/* Clocks are needed early, see drivers/clocksource for the rest */ +void __init __maybe_unused omap_init_time_of(void) +{ + omap_clk_init(); + timer_probe(); +} + #ifdef CONFIG_SOC_OMAP2420 static const char *const omap242x_boards_compat[] __initconst = { "ti,omap2420", -- cgit v1.2.3-70-g09d2 From e20ef23dd6937c38df2cfddf15270668153c8177 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for am335x We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Cc: devicetree@vger.kernel.org Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 6 ++---- arch/arm/boot/dts/am33xx.dtsi | 20 ++++++++++++++++++++ arch/arm/mach-omap2/board-generic.c | 2 +- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 2 -- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 10 ---------- 5 files changed, 23 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 5ed7f3c58c0f..7ff11d6bf0f2 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -330,9 +330,8 @@ }; }; - target-module@31000 { /* 0x44e31000, ap 25 40.0 */ + timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; @@ -1117,9 +1116,8 @@ }; }; - target-module@40000 { /* 0x48040000, ap 22 1e.0 */ + timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index a35f5052d76f..3b177c9c4412 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -619,3 +619,23 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index c6f7dcf13a15..cce9523eaa77 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -236,7 +236,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") .init_early = am33xx_init_early, .init_machine = omap_generic_init, .init_late = am33xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = am33xx_boards_compat, .restart = am33xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index dca5a3a7b97c..99c633338488 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -367,12 +367,10 @@ struct omap_hwmod am33xx_timer2_hwmod = { static void omap_hwmod_am33xx_clkctrl(void) { - CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex0_hwmod, AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET); CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index c64b735c8acc..3cf9c4c90b18 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -265,14 +265,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -/* l4 wkup -> timer1 */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_timer1_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__emif, &am33xx_mpu__l3_main, @@ -291,9 +283,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, - &am33xx_l4_wkup__timer1, &am33xx_l4_wkup__rtc, - &am33xx_l4_ls__timer2, &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, NULL, -- cgit v1.2.3-70-g09d2 From 545a95582e80a2c66527dbf7f0ae495902fc083a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for am437x We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Cc: devicetree@vger.kernel.org Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 20 ++++++++ arch/arm/boot/dts/am437x-l4.dtsi | 7 +-- arch/arm/mach-omap2/board-generic.c | 2 +- .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 2 - .../omap_hwmod_33xx_43xx_interconnect_data.c | 8 --- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 60 ---------------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 45 ---------------- 7 files changed, 23 insertions(+), 121 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index dba87bfaf33e..b4861f70f178 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -553,3 +553,23 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 49c6a872052e..0d0f9fe4a882 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -328,9 +328,8 @@ }; }; - target-module@31000 { /* 0x44e31000, ap 24 40.0 */ + timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; @@ -450,7 +449,6 @@ target-module@86000 { /* 0x44e86000, ap 40 70.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x86000 0x4>, <0x86004 0x4>; reg-names = "rev", "sysc"; @@ -868,9 +866,8 @@ }; }; - target-module@40000 { /* 0x48040000, ap 18 1e.0 */ + timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index cce9523eaa77..fa299e09730d 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -308,7 +308,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .init_late = am43xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = am43_boards_compat, .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index fa2ff41f84b9..5f4ab24dd60d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -44,8 +44,6 @@ extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod; extern struct omap_hwmod am33xx_gpmc_hwmod; extern struct omap_hwmod am33xx_rtc_hwmod; -extern struct omap_hwmod am33xx_timer1_hwmod; -extern struct omap_hwmod am33xx_timer2_hwmod; extern struct omap_hwmod_class am33xx_emif_hwmod_class; extern struct omap_hwmod_class am33xx_l4_hwmod_class; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 0ebbfbb4fb1c..b389d6589c32 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -106,14 +106,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .user = OCP_USER_MPU, }; -/* l4 per -> timer2 */ -struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_timer2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l3 main -> ocmc */ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { .master = &am33xx_l3_main_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 99c633338488..4b3cd590fb52 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -307,64 +307,6 @@ struct omap_hwmod am33xx_rtc_hwmod = { }, }; -/* 'timer 2-7' class */ -static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSC_HAS_RESET_STATUS, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -struct omap_hwmod_class am33xx_timer_hwmod_class = { - .name = "timer", - .sysc = &am33xx_timer_sysc, -}; - -/* timer1 1ms */ -static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { - .name = "timer", - .sysc = &am33xx_timer1ms_sysc, -}; - -struct omap_hwmod am33xx_timer1_hwmod = { - .name = "timer1", - .class = &am33xx_timer1ms_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "timer1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -struct omap_hwmod am33xx_timer2_hwmod = { - .name = "timer2", - .class = &am33xx_timer_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "timer2_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - static void omap_hwmod_am33xx_clkctrl(void) { CLKCTRL(am33xx_smartreflex0_hwmod, @@ -397,12 +339,10 @@ void omap_hwmod_am33xx_reg(void) static void omap_hwmod_am43xx_clkctrl(void) { - CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex0_hwmod, AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET); CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET); CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index d2203f44af88..3f338732ee6c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -85,34 +85,6 @@ static struct omap_hwmod am43xx_control_hwmod = { }, }; -static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x4, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am43xx_synctimer_hwmod_class = { - .name = "synctimer", - .sysc = &am43xx_synctimer_sysc, -}; - -static struct omap_hwmod am43xx_synctimer_hwmod = { - .name = "counter_32k", - .class = &am43xx_synctimer_hwmod_class, - .clkdm_name = "l4_wkup_aon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "synctimer_32kclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - - static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, @@ -206,20 +178,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_timer1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_synctimer_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { .master = &am33xx_l3_s_hwmod, .slave = &am43xx_usb_otg_ss0_hwmod, @@ -235,7 +193,6 @@ static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { }; static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l4_wkup__synctimer, &am33xx_mpu__l3_main, &am33xx_mpu__prcm, &am33xx_l3_s__l4_ls, @@ -252,8 +209,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_wkup__control, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, - &am43xx_l4_wkup__timer1, - &am33xx_l4_ls__timer2, &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, &am43xx_l3_s__usbotgss0, -- cgit v1.2.3-70-g09d2 From 14b1925a721992d781f5e9d28db26b85174e3927 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for omap4 We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Cc: devicetree@vger.kernel.org Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 4 +- arch/arm/boot/dts/omap4.dtsi | 10 ++++ arch/arm/mach-omap2/board-generic.c | 2 +- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 90 ------------------------------ 4 files changed, 12 insertions(+), 94 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index ef59e4e97d7c..fcc52121ff09 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -974,7 +974,6 @@ target-module@4000 { /* 0x4a304000, ap 17 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4004 0x4>; reg-names = "rev", "sysc"; @@ -1139,9 +1138,8 @@ }; }; - target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ + timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>, <0x8014 0x4>; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 763bdea8c829..6c2b07f0704d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -655,3 +655,13 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index fa299e09730d..4818fd429f98 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -261,7 +261,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_late = omap4430_init_late, - .init_time = omap4_local_timer_init, + .init_time = omap_init_time_of, .dt_compat = omap4_boards_compat, .restart = omap44xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 33f6596c03f7..de13c46b984f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -231,39 +231,6 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { * usim */ -/* - * 'counter' class - * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock - */ - -static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0004, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_counter_hwmod_class = { - .name = "counter", - .sysc = &omap44xx_counter_sysc, -}; - -/* counter_32k */ -static struct omap_hwmod omap44xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap44xx_counter_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "sys_32k_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, - }, - }, -}; - /* * 'ctrl_module' class * attila core control module + core pad control module + wkup pad control @@ -672,45 +639,6 @@ static struct omap_hwmod omap44xx_sl2if_hwmod = { }, }; -/* - * 'timer' class - * general purpose timer module with accurate 1ms tick - * This class contains several variants: ['timer_1ms', 'timer'] - */ - -static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | - SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | - SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap44xx_timer_1ms_sysc, -}; - -/* timer1 */ -static struct omap_hwmod omap44xx_timer1_hwmod = { - .name = "timer1", - .class = &omap44xx_timer_1ms_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .main_clk = "dmt1_clk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_host_fs' class * full-speed usb host controller @@ -1063,14 +991,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_counter_32k_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> ctrl_module_core */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { .master = &omap44xx_l4_cfg_hwmod, @@ -1199,14 +1119,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { - .master = &omap44xx_l4_wkup_hwmod, - .slave = &omap44xx_timer1_hwmod, - .clk = "l4_wkup_clk_mux_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_host_fs */ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { .master = &omap44xx_l4_cfg_hwmod, @@ -1273,7 +1185,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_cfg__l4_wkup, &omap44xx_mpu__mpu_private, &omap44xx_l4_cfg__ocp_wp_noc, - &omap44xx_l4_wkup__counter_32k, &omap44xx_l4_cfg__ctrl_module_core, &omap44xx_l4_cfg__ctrl_module_pad_core, &omap44xx_l4_wkup__ctrl_module_wkup, @@ -1290,7 +1201,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_wkup__prm, &omap44xx_l4_wkup__scrm, /* &omap44xx_l3_main_2__sl2if, */ - &omap44xx_l4_wkup__timer1, /* &omap44xx_l4_cfg__usb_host_fs, */ &omap44xx_l4_cfg__usb_host_hs, &omap44xx_l4_cfg__usb_tll_hs, -- cgit v1.2.3-70-g09d2 From 036a3d42bb8f28ae3cdd7c9570135c243724fbd6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for omap5 and dra7 We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Note that similar to omap_init_time_of(), we now need to call omap_clk_init() also from omap5_realtime_timer_init(). Cc: devicetree@vger.kernel.org Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 7 +- arch/arm/boot/dts/dra7.dtsi | 10 ++ arch/arm/boot/dts/omap5-l4.dtsi | 4 +- arch/arm/boot/dts/omap5.dtsi | 10 ++ arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 89 --------------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 176 ----------------------------- arch/arm/mach-omap2/timer.c | 17 +-- 7 files changed, 23 insertions(+), 290 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 2119a78e9c15..fc728c606eef 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -1143,7 +1143,6 @@ target-module@32000 { /* 0x48032000, ap 5 3e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; @@ -1171,7 +1170,6 @@ target-module@34000 { /* 0x48034000, ap 7 46.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; @@ -1199,7 +1197,6 @@ target-module@36000 { /* 0x48036000, ap 9 4e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; @@ -4295,7 +4292,6 @@ target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -4430,9 +4426,8 @@ }; }; - target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4740989ed9c4..ad4401b0f270 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1044,3 +1044,13 @@ reg = <0x1c00 0x60>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f68740abb8aa..a7e718c4ccea 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -2150,7 +2150,6 @@ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -2336,9 +2335,8 @@ }; }; - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2ac7f021c284..e30a556f7c18 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -581,3 +581,13 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 08f34f4732fd..4cb194ac7a7e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -193,39 +193,6 @@ static struct omap_hwmod omap54xx_mpu_private_hwmod = { }, }; -/* - * 'counter' class - * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock - */ - -static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap54xx_counter_hwmod_class = { - .name = "counter", - .sysc = &omap54xx_counter_sysc, -}; - -/* counter_32k */ -static struct omap_hwmod omap54xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap54xx_counter_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, - }, - }, -}; - /* * 'emif' class * external memory interface no1 (wrapper) @@ -299,44 +266,6 @@ static struct omap_hwmod omap54xx_mpu_hwmod = { }, }; - -/* - * 'timer' class - * general purpose timer module with accurate 1ms tick - * This class contains several variants: ['timer_1ms', 'timer'] - */ - -static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &omap54xx_timer_1ms_sysc, -}; - -/* timer1 */ -static struct omap_hwmod omap54xx_timer1_hwmod = { - .name = "timer1", - .class = &omap54xx_timer_1ms_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "timer1_gfclk_mux", - .flags = HWMOD_SET_DEFAULT_CLOCKACT, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, - .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_host_hs' class * high-speed multi-port usb host controller @@ -666,14 +595,6 @@ static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { - .master = &omap54xx_l4_wkup_hwmod, - .slave = &omap54xx_counter_32k_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* mpu -> emif1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { .master = &omap54xx_mpu_hwmod, @@ -698,14 +619,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { - .master = &omap54xx_l4_wkup_hwmod, - .slave = &omap54xx_timer1_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> usb_host_hs */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { .master = &omap54xx_l4_cfg_hwmod, @@ -747,11 +660,9 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_2__l4_per, &omap54xx_l3_main_1__l4_wkup, &omap54xx_mpu__mpu_private, - &omap54xx_l4_wkup__counter_32k, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, &omap54xx_l4_cfg__mpu, - &omap54xx_l4_wkup__timer1, &omap54xx_l4_cfg__usb_host_hs, &omap54xx_l4_cfg__usb_tll_hs, &omap54xx_l4_cfg__usb_otg_ss, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e95668bdbc3f..07b7458deae4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -221,40 +221,6 @@ static struct omap_hwmod dra7xx_bb2d_hwmod = { }, }; -/* - * 'counter' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_counter_hwmod_class = { - .name = "counter", - .sysc = &dra7xx_counter_sysc, -}; - -/* counter_32k */ -static struct omap_hwmod dra7xx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &dra7xx_counter_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkupaon_iclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, - }, - }, -}; - /* * 'ctrl_module' class * @@ -525,103 +491,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { }, }; -/* - * 'timer' class - * - * This class contains several variants: ['timer_1ms', 'timer_secure', - * 'timer'] - */ - -static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { - .name = "timer", - .sysc = &dra7xx_timer_1ms_sysc, -}; - -static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | - SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class dra7xx_timer_hwmod_class = { - .name = "timer", - .sysc = &dra7xx_timer_sysc, -}; - -/* timer1 */ -static struct omap_hwmod dra7xx_timer1_hwmod = { - .name = "timer1", - .class = &dra7xx_timer_1ms_hwmod_class, - .clkdm_name = "wkupaon_clkdm", - .main_clk = "timer1_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer2 */ -static struct omap_hwmod dra7xx_timer2_hwmod = { - .name = "timer2", - .class = &dra7xx_timer_1ms_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer2_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer3 */ -static struct omap_hwmod dra7xx_timer3_hwmod = { - .name = "timer3", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer3_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* timer4 */ -static struct omap_hwmod dra7xx_timer4_hwmod = { - .name = "timer4", - .class = &dra7xx_timer_hwmod_class, - .clkdm_name = "l4per_clkdm", - .main_clk = "timer4_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'usb_otg_ss' class * @@ -864,14 +733,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> counter_32k */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_counter_32k_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> ctrl_module_wkup */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .master = &dra7xx_l4_wkup_hwmod, @@ -952,38 +813,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { - .master = &dra7xx_l4_wkup_hwmod, - .slave = &dra7xx_timer1_hwmod, - .clk = "wkupaon_iclk_mux", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer3 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer3_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4_per1 -> timer4 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { - .master = &dra7xx_l4_per1_hwmod, - .slave = &dra7xx_timer4_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_per3 -> usb_otg_ss1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { .master = &dra7xx_l4_per3_hwmod, @@ -1062,7 +891,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__l4_wkup, &dra7xx_l4_per2__atl, &dra7xx_l3_main_1__bb2d, - &dra7xx_l4_wkup__counter_32k, &dra7xx_l4_wkup__ctrl_module_wkup, &dra7xx_l3_main_1__gpmc, &dra7xx_l4_cfg__mpu, @@ -1072,10 +900,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_cfg__pciess2, &dra7xx_l3_main_1__qspi, &dra7xx_l4_cfg__sata, - &dra7xx_l4_wkup__timer1, - &dra7xx_l4_per1__timer2, - &dra7xx_l4_per1__timer3, - &dra7xx_l4_per1__timer4, &dra7xx_l4_per3__usb_otg_ss1, &dra7xx_l4_per3__usb_otg_ss2, &dra7xx_l4_per3__usb_otg_ss3, diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 8b09cdacc30d..662a31004b91 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -576,21 +576,6 @@ void __init omap3_gptimer_timer_init(void) } #endif -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ - defined(CONFIG_SOC_DRA7XX) -static void __init omap4_sync32k_timer_init(void) -{ - __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", - 0, NULL, NULL, false); -} - -void __init omap4_local_timer_init(void) -{ - omap4_sync32k_timer_init(); - timer_probe(); -} -#endif - #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) /* @@ -708,7 +693,7 @@ sysclk1_based: void __init omap5_realtime_timer_init(void) { - omap4_sync32k_timer_init(); + omap_clk_init(); realtime_counter_init(); timer_probe(); -- cgit v1.2.3-70-g09d2 From e428e250fde683ad3a658f8476f0914714e7eb6f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for omap3 We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Adam Ford Cc: Andreas Kemnade Cc: Grygorii Strashko Cc: "H. Nikolaus Schaller" Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517.dtsi | 24 ++++- arch/arm/boot/dts/omap3-beagle.dts | 33 +++++++ arch/arm/boot/dts/omap3-devkit8000.dts | 33 +++++++ arch/arm/boot/dts/omap3.dtsi | 134 +++++++++++++++++++++----- arch/arm/mach-omap2/board-generic.c | 10 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 146 +---------------------------- 6 files changed, 205 insertions(+), 175 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index e0b5a00e2078..dc8927f14b6c 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -169,5 +169,25 @@ status = "disabled"; }; -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +#include "am35xx-clocks.dtsi" +#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 4ed3f93f5841..dfa158647d91 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -304,6 +304,39 @@ phys = <0 &hsusb2_phy>; }; +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 162d0726b008..c2995a280729 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -14,3 +14,36 @@ display2 = &tv0; }; }; + +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 634ea16a711e..1296d0643943 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -193,10 +193,23 @@ }; }; - counter32k: counter@48320000 { - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; + target-module@48320000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48320000 0x4>, + <0x48320004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48320000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; }; intc: interrupt-controller@48200000 { @@ -637,19 +650,63 @@ dma-names = "rx"; }; - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48318000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48318000 0x4>, + <0x48318010 0x4>, + <0x48318014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48318000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&gpt1_fck>; + clock-names = "fck"; + interrupts = <37>; + ti,timer-alwon; + }; }; - timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@49032000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49032000 0x4>, + <0x49032010 0x4>, + <0x49032014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49032000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@49034000 { @@ -723,13 +780,34 @@ ti,timer-pwm; }; - timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; + timer12_target: target-module@48304000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48304000 0x4>, + <0x48304010 0x4>, + <0x48304014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt12_fck>, <&gpt12_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48304000 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <95>; + ti,timer-alwon; + ti,timer-secure; + }; }; usbhstll: usbhstll@48062000 { @@ -886,4 +964,14 @@ }; }; -/include/ "omap3xxx-clocks.dtsi" +#include "omap3xxx-clocks.dtsi" + +/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&omap_32k_fck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 4818fd429f98..a10a74e95385 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -114,7 +114,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = n900_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -132,7 +132,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap3_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -149,7 +149,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .init_early = omap3630_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap36xx_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -166,7 +166,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .init_early = omap3430_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap3_secure_sync32k_timer_init, + .init_time = omap_init_time_of, .dt_compat = omap3_gp_boards_compat, .restart = omap3xxx_restart, MACHINE_END @@ -182,7 +182,7 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)") .init_early = am35xx_init_early, .init_machine = omap_generic_init, .init_late = omap3_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = am3517_boards_compat, .restart = omap3xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 3c8d2b6e887a..ca02f91237e3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -147,36 +147,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { .sysc = &omap3xxx_timer_sysc, }; -/* timer1 */ -static struct omap_hwmod omap3xxx_timer1_hwmod = { - .name = "timer1", - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - -/* timer2 */ -static struct omap_hwmod omap3xxx_timer2_hwmod = { - .name = "timer2", - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* timer3 */ static struct omap_hwmod omap3xxx_timer3_hwmod = { .name = "timer3", @@ -312,21 +282,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = { .flags = HWMOD_SET_DEFAULT_CLOCKACT, }; -/* timer12 */ -static struct omap_hwmod omap3xxx_timer12_hwmod = { - .name = "timer12", - .main_clk = "gpt12_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, - }, - }, - .class = &omap3xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* * 'wd_timer' class * 32-bit watchdog upward counter that generates a pulse on the reset pin on @@ -1524,38 +1479,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = { .class = &omap3xxx_sad2d_class, }; -/* - * '32K sync counter' class - * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock - */ -static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0004, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { - .name = "counter", - .sysc = &omap3xxx_counter_sysc, -}; - -static struct omap_hwmod omap3xxx_counter_32k_hwmod = { - .name = "counter_32k", - .class = &omap3xxx_counter_hwmod_class, - .clkdm_name = "wkup_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "wkup_32k_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, - }, - }, -}; - /* * 'gpmc' class * general purpose memory controller @@ -1868,25 +1791,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - - -/* l4_per -> timer2 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { - .master = &omap3xxx_l4_per_hwmod, - .slave = &omap3xxx_timer2_hwmod, - .clk = "gpt2_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - - /* l4_per -> timer3 */ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { .master = &omap3xxx_l4_per_hwmod, @@ -1965,15 +1869,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l4_core -> timer12 */ -static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { - .master = &omap3xxx_l4_sec_hwmod, - .slave = &omap3xxx_timer12_hwmod, - .clk = "gpt12_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { @@ -2325,16 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; -/* l4_wkup -> 32ksync_counter */ - - -static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { - .master = &omap3xxx_l4_wkup_hwmod, - .slave = &omap3xxx_counter_32k_hwmod, - .clk = "omap_32ksync_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* am35xx has Davinci MDIO & EMAC */ static struct omap_hwmod_class am35xx_mdio_class = { .name = "davinci_mdio", @@ -2551,8 +2436,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3_l4_core__i2c2, &omap3_l4_core__i2c3, &omap3xxx_l4_wkup__l4_sec, - &omap3xxx_l4_wkup__timer1, - &omap3xxx_l4_per__timer2, &omap3xxx_l4_per__timer3, &omap3xxx_l4_per__timer4, &omap3xxx_l4_per__timer5, @@ -2580,27 +2463,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__mcspi2, &omap34xx_l4_core__mcspi3, &omap34xx_l4_core__mcspi4, - &omap3xxx_l4_wkup__counter_32k, &omap3xxx_l3_main__gpmc, NULL, }; -/* GP-only hwmod links */ -static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - -static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - -static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { - &omap3xxx_l4_sec__timer12, - NULL, -}; - /* crypto hwmod links */ static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__sham, @@ -2774,7 +2640,7 @@ static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, int __init omap3xxx_hwmod_init(void) { int r; - struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; + struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL; struct omap_hwmod_ocp_if **h_aes = NULL; struct device_node *bus; unsigned int rev; @@ -2797,18 +2663,15 @@ int __init omap3xxx_hwmod_init(void) rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { h = omap34xx_hwmod_ocp_ifs; - h_gp = omap34xx_gp_hwmod_ocp_ifs; h_sham = omap34xx_sham_hwmod_ocp_ifs; h_aes = omap34xx_aes_hwmod_ocp_ifs; } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { h = am35xx_hwmod_ocp_ifs; - h_gp = am35xx_gp_hwmod_ocp_ifs; h_sham = am35xx_sham_hwmod_ocp_ifs; h_aes = am35xx_aes_hwmod_ocp_ifs; } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) { h = omap36xx_hwmod_ocp_ifs; - h_gp = omap36xx_gp_hwmod_ocp_ifs; h_sham = omap36xx_sham_hwmod_ocp_ifs; h_aes = omap36xx_aes_hwmod_ocp_ifs; } else { @@ -2820,13 +2683,6 @@ int __init omap3xxx_hwmod_init(void) if (r < 0) return r; - /* Register GP-only hwmod links. */ - if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { - r = omap_hwmod_register_links(h_gp); - if (r < 0) - return r; - } - /* * Register crypto hwmod links only if they are not disabled in DT. * If DT information is missing, enable them only for GP devices. -- cgit v1.2.3-70-g09d2 From 83bd18b46600a37d977e811dca1334e09a6e03eb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for ti81xx We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Note that for ti81xx, also timer1 is of type 2 unlike on am335x where timer1 is type1 while the rest of the timers are type 2. Cc: devicetree@vger.kernel.org Cc: Brian Hutchinson Cc: Graeme Smecher Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 74 +++++++++++++++++++++++----- arch/arm/boot/dts/dm816x.dtsi | 78 +++++++++++++++++++++++++----- arch/arm/mach-omap2/board-generic.c | 4 +- arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 74 ---------------------------- 4 files changed, 130 insertions(+), 100 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 44ed5a798164..a172cf5cf29c 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -308,14 +308,30 @@ ti,hwmods = "mcspi4"; }; - timer1: timer@2e000 { - compatible = "ti,dm814-timer"; - reg = <0x2e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@2e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer1_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; }; uart1: uart@20000 { @@ -348,13 +364,29 @@ dma-names = "tx", "rx"; }; - timer2: timer@40000 { - compatible = "ti,dm814-timer"; - reg = <0x40000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; + timer2_target: target-module@40000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer2_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm814-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; }; timer3: timer@42000 { @@ -735,3 +767,23 @@ }; #include "dm814x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 2a4934b60ded..3551a64963f8 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -440,23 +440,55 @@ dma-names = "tx", "rx"; }; - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; + timer1_target: target-module@4802e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4802e000 0x4>, + <0x4802e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + }; }; - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; + timer2_target: target-module@48040000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48040000 0x4>, + <0x48040010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48040000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + }; }; timer3: timer@48042000 { @@ -642,3 +674,23 @@ }; #include "dm816x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index a10a74e95385..eeb3f97af520 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -201,7 +201,7 @@ DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)") .init_early = ti814x_init_early, .init_machine = omap_generic_init, .init_late = ti81xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = ti814x_boards_compat, .restart = ti81xx_restart, MACHINE_END @@ -218,7 +218,7 @@ DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)") .init_early = ti816x_init_early, .init_machine = omap_generic_init, .init_late = ti81xx_init_late, - .init_time = omap3_gptimer_timer_init, + .init_time = omap_init_time_of, .dt_compat = ti816x_boards_compat, .restart = ti81xx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 6a9f1ad9d413..50fb699b163f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -690,76 +690,6 @@ static struct omap_hwmod_class dm816x_timer_hwmod_class = { .sysc = &dm816x_timer_sysc, }; -static struct omap_hwmod dm814x_timer1_hwmod = { - .name = "timer1", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer1_fck", - .class = &dm816x_timer_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm814x_timer1_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm816x_timer1_hwmod = { - .name = "timer1", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer1_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .class = &dm816x_timer_hwmod_class, -}; - -static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm816x_timer1_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm814x_timer2_hwmod = { - .name = "timer2", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer2_fck", - .class = &dm816x_timer_hwmod_class, - .flags = HWMOD_NO_IDLEST, -}; - -static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm814x_timer2_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod dm816x_timer2_hwmod = { - .name = "timer2", - .clkdm_name = "alwon_l3s_clkdm", - .main_clk = "timer2_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .class = &dm816x_timer_hwmod_class, -}; - -static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { - .master = &dm81xx_l4_ls_hwmod, - .slave = &dm816x_timer2_hwmod, - .clk = "sysclk6_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod dm816x_timer3_hwmod = { .name = "timer3", .clkdm_name = "alwon_l3s_clkdm", @@ -1288,8 +1218,6 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { &dm814x_l4_ls__mmc1, &dm814x_l4_ls__mmc2, &ti81xx_l4_ls__rtc, - &dm814x_l4_ls__timer1, - &dm814x_l4_ls__timer2, &dm81xx_alwon_l3_slow__gpmc, &dm814x_default_l3_slow__usbss, &dm814x_alwon_l3_med__mmc3, @@ -1318,8 +1246,6 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_ls__elm, &ti81xx_l4_ls__rtc, &dm816x_l4_ls__mmc1, - &dm816x_l4_ls__timer1, - &dm816x_l4_ls__timer2, &dm816x_l4_ls__timer3, &dm816x_l4_ls__timer4, &dm816x_l4_ls__timer5, -- cgit v1.2.3-70-g09d2 From 64dbc3d55d60fd115e058e9f1689542daa37356c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: dts: Configure system timers for omap2 We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2.dtsi | 31 ++++++++-- arch/arm/boot/dts/omap2420.dtsi | 68 ++++++++++++++++++---- arch/arm/boot/dts/omap2430.dtsi | 68 ++++++++++++++++++---- arch/arm/mach-omap2/board-generic.c | 4 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 20 ------- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 19 ------ .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c | 8 --- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 47 --------------- arch/arm/mach-omap2/omap_hwmod_common_data.h | 3 - 9 files changed, 140 insertions(+), 128 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 0e453fec2e3a..8a5cb44bfe2f 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -201,11 +201,32 @@ clock-frequency = <48000000>; }; - timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4802a000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@4802a000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x4802a000 0x4>, + <0x4802a010 0x4>, + <0x4802a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802a000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@48078000 { diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index aba542d63d6d..6c5c7c0e8b94 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -68,10 +68,23 @@ }; }; - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -194,12 +207,33 @@ }; }; - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48028000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48028000 0x4>, + <0x48028010 0x4>, + <0x48028014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48028000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; wd_timer2: wdt@48022000 { @@ -218,5 +252,15 @@ compatible = "ti,omap2420-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2420-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2420-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 15ef7593be12..6a1f5bb3c06a 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -81,10 +81,23 @@ }; }; - counter32k: counter@20000 { - compatible = "ti,omap-counter32k"; - reg = <0x20000 0x20>; - ti,hwmods = "counter_32k"; + target-module@20000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -277,12 +290,33 @@ }; }; - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@49018000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49018000 0x4>, + <0x49018010 0x4>, + <0x49018014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49018000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; mcspi3: spi@480b8000 { @@ -321,5 +355,15 @@ compatible = "ti,omap2430-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2430-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2430-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index eeb3f97af520..cafeb822bab7 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -50,7 +50,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") .map_io = omap242x_map_io, .init_early = omap2420_init_early, .init_machine = omap_generic_init, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap242x_boards_compat, .restart = omap2xxx_restart, MACHINE_END @@ -67,7 +67,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") .map_io = omap243x_map_io, .init_early = omap2430_init_early, .init_machine = omap_generic_init, - .init_time = omap_init_time, + .init_time = omap_init_time_of, .dt_compat = omap243x_boards_compat, .restart = omap2xxx_restart, MACHINE_END diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index b14442cf6179..558fae4375ba 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -264,14 +264,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, @@ -352,15 +344,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; - -/* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_counter_32k_hwmod, - .clk = "sync_32k_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, @@ -382,8 +365,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2420_l4_core__i2c2, &omap2420_l3__iva, &omap2420_l3__dsp, - &omap2420_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, &omap2xxx_l4_core__timer3, &omap2xxx_l4_core__timer4, &omap2xxx_l4_core__timer5, @@ -411,7 +392,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__sham, &omap2xxx_l4_core__aes, &omap2420_l4_core__hdq1w, - &omap2420_l4_wkup__counter_32k, &omap2420_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 41a37c74f9a6..c93200801b34 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -436,14 +436,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_wkup -> timer1 */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_timer1_hwmod, - .clk = "gpt1_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { .master = &omap2xxx_l4_wkup_hwmod, @@ -548,14 +540,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, }; -/* l4_wkup -> 32ksync_counter */ -static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { - .master = &omap2xxx_l4_wkup_hwmod, - .slave = &omap2xxx_counter_32k_hwmod, - .clk = "sync_32k_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { .master = &omap2xxx_l3_main_hwmod, .slave = &omap2xxx_gpmc_hwmod, @@ -581,8 +565,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__mcspi2, &omap2430_l4_core__mcspi3, &omap2430_l3__iva, - &omap2430_l4_wkup__timer1, - &omap2xxx_l4_core__timer2, &omap2xxx_l4_core__timer3, &omap2xxx_l4_core__timer4, &omap2xxx_l4_core__timer5, @@ -613,7 +595,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { &omap2xxx_l4_core__rng, &omap2xxx_l4_core__sham, &omap2xxx_l4_core__aes, - &omap2430_l4_wkup__counter_32k, &omap2430_l3__gpmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c index eef96adea411..518e877bb2a1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c @@ -95,14 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_core -> timer2 */ -struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = { - .master = &omap2xxx_l4_core_hwmod, - .slave = &omap2xxx_timer2_hwmod, - .clk = "gpt2_ick", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_core -> timer3 */ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = { .master = &omap2xxx_l4_core_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c index a445704d43d9..9156f2bfbc8d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c @@ -195,36 +195,6 @@ struct omap_hwmod omap2xxx_iva_hwmod = { .class = &iva_hwmod_class, }; -/* timer1 */ -struct omap_hwmod omap2xxx_timer1_hwmod = { - .name = "timer1", - .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, - .class = &omap2xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - -/* timer2 */ -struct omap_hwmod omap2xxx_timer2_hwmod = { - .name = "timer2", - .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, - .class = &omap2xxx_timer_hwmod_class, - .flags = HWMOD_SET_DEFAULT_CLOCKACT, -}; - /* timer3 */ struct omap_hwmod omap2xxx_timer3_hwmod = { .name = "timer3", @@ -595,23 +565,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = { .class = &omap2xxx_mcspi_class, }; -static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { - .name = "counter", -}; - -struct omap_hwmod omap2xxx_counter_32k_hwmod = { - .name = "counter_32k", - .main_clk = "func_32k_ck", - .prcm = { - .omap2 = { - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, - }, - }, - .class = &omap2xxx_counter_hwmod_class, -}; - /* gpmc */ struct omap_hwmod omap2xxx_gpmc_hwmod = { .name = "gpmc", diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h index c85cb8b5831c..0045e6680a63 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h @@ -21,8 +21,6 @@ extern struct omap_hwmod omap2xxx_l4_core_hwmod; extern struct omap_hwmod omap2xxx_l4_wkup_hwmod; extern struct omap_hwmod omap2xxx_mpu_hwmod; extern struct omap_hwmod omap2xxx_iva_hwmod; -extern struct omap_hwmod omap2xxx_timer1_hwmod; -extern struct omap_hwmod omap2xxx_timer2_hwmod; extern struct omap_hwmod omap2xxx_timer3_hwmod; extern struct omap_hwmod omap2xxx_timer4_hwmod; extern struct omap_hwmod omap2xxx_timer5_hwmod; @@ -47,7 +45,6 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod; extern struct omap_hwmod omap2xxx_gpio4_hwmod; extern struct omap_hwmod omap2xxx_mcspi1_hwmod; extern struct omap_hwmod omap2xxx_mcspi2_hwmod; -extern struct omap_hwmod omap2xxx_counter_32k_hwmod; extern struct omap_hwmod omap2xxx_gpmc_hwmod; extern struct omap_hwmod omap2xxx_rng_hwmod; extern struct omap_hwmod omap2xxx_sham_hwmod; -- cgit v1.2.3-70-g09d2 From 2ee04b88547ab4c46aa2a258efd0f91fc705b6d6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 7 May 2020 09:59:31 -0700 Subject: ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter With dmtimer and 32k counter being initialized based on devicetree data, we can just drop the old timer code. This still leaves the omap5 and dra7 realtime_counter_init() that depend on the smc calls and control module platform code for the dra7 quirk init. Cc: Grygorii Strashko Cc: Keerthy Cc: Lokesh Vutla Cc: Rob Herring Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 4 +- arch/arm/mach-omap2/common.h | 7 + arch/arm/mach-omap2/timer.c | 551 ------------------------------------------- 3 files changed, 10 insertions(+), 552 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 5017a3be0ff0..07616d346557 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -7,7 +7,7 @@ ccflags-y := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-omap/include # Common support -obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \ +obj-y := id.o io.o control.o devices.o fb.o pm.o \ common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ omap_device.o omap-headsmp.o sram.o @@ -16,6 +16,8 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ clock-common = clock.o secure-common = omap-smc.o omap-secure.o +obj-$(CONFIG_SOC_HAS_REALTIME_COUNTER) += timer.o + obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 75d729943958..49926eced5f1 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -111,7 +111,14 @@ static inline int omap_l2_cache_init(void) #define OMAP_L2C_AUX_CTRL 0 #define omap4_l2c310_write_sec NULL #endif + +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER extern void omap5_realtime_timer_init(void); +#else +static inline void omap5_realtime_timer_init(void) +{ +} +#endif void omap2420_init_early(void); void omap2430_init_early(void); diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 662a31004b91..2d4ea386fc38 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -26,34 +26,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include -#include -#include -#include #include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "omap_hwmod.h" -#include "omap_device.h" -#include -#include #include "soc.h" #include "common.h" #include "control.h" -#include "powerdomain.h" #include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 @@ -61,294 +39,12 @@ #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 -/* Clockevent code */ - -static struct omap_dm_timer clkev; -static struct clock_event_device clockevent_gpt; - -/* Clockevent hwmod for am335x and am437x suspend */ -static struct omap_hwmod *clockevent_gpt_hwmod; - -/* Clockesource hwmod for am437x suspend */ -static struct omap_hwmod *clocksource_gpt_hwmod; - -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; void set_cntfreq(void) { omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); } -#endif - -static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_gpt; - - __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); - - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static int omap2_gp_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, - 0xffffffff - cycles, OMAP_TIMER_POSTED); - - return 0; -} - -static int omap2_gp_timer_shutdown(struct clock_event_device *evt) -{ - __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); - return 0; -} - -static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) -{ - u32 period; - - __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); - - period = clkev.rate / HZ; - period -= 1; - /* Looks like we need to first set the load value separately */ - __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, - OMAP_TIMER_POSTED); - __omap_dm_timer_load_start(&clkev, - OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, - 0xffffffff - period, OMAP_TIMER_POSTED); - return 0; -} - -static void omap_clkevt_idle(struct clock_event_device *unused) -{ - if (!clockevent_gpt_hwmod) - return; - - omap_hwmod_idle(clockevent_gpt_hwmod); -} - -static void omap_clkevt_unidle(struct clock_event_device *unused) -{ - if (!clockevent_gpt_hwmod) - return; - - omap_hwmod_enable(clockevent_gpt_hwmod); - __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); -} - -static struct clock_event_device clockevent_gpt = { - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = omap2_gp_timer_set_next_event, - .set_state_shutdown = omap2_gp_timer_shutdown, - .set_state_periodic = omap2_gp_timer_set_periodic, - .set_state_oneshot = omap2_gp_timer_shutdown, - .tick_resume = omap2_gp_timer_shutdown, -}; - -static const struct of_device_id omap_timer_match[] __initconst = { - { .compatible = "ti,omap2420-timer", }, - { .compatible = "ti,omap3430-timer", }, - { .compatible = "ti,omap4430-timer", }, - { .compatible = "ti,omap5430-timer", }, - { .compatible = "ti,dm814-timer", }, - { .compatible = "ti,dm816-timer", }, - { .compatible = "ti,am335x-timer", }, - { .compatible = "ti,am335x-timer-1ms", }, - { } -}; - -static int omap_timer_add_disabled_property(struct device_node *np) -{ - struct property *prop; - - prop = kzalloc(sizeof(*prop), GFP_KERNEL); - if (!prop) - return -ENOMEM; - - prop->name = "status"; - prop->value = "disabled"; - prop->length = strlen(prop->value); - - return of_add_property(np, prop); -} - -static int omap_timer_update_dt(struct device_node *np) -{ - int error = 0; - - if (!of_device_is_compatible(np, "ti,omap-counter32k")) { - error = omap_timer_add_disabled_property(np); - if (error) - return error; - } - - /* No parent interconnect target module configured? */ - if (of_get_property(np, "ti,hwmods", NULL)) - return error; - - /* Tag parent interconnect target module disabled */ - error = omap_timer_add_disabled_property(np->parent); - if (error) - return error; - - return 0; -} - -/** - * omap_get_timer_dt - get a timer using device-tree - * @match - device-tree match structure for matching a device type - * @property - optional timer property to match - * - * Helper function to get a timer during early boot using device-tree for use - * as kernel system timer. Optionally, the property argument can be used to - * select a timer with a specific property. Once a timer is found then mark - * the timer node in device-tree as disabled, to prevent the kernel from - * registering this timer as a platform device and so no one else can use it. - */ -static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, - const char *property) -{ - struct device_node *np; - int error; - - for_each_matching_node(np, match) { - if (!of_device_is_available(np)) - continue; - - if (property && !of_get_property(np, property, NULL)) - continue; - - if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || - of_get_property(np, "ti,timer-dsp", NULL) || - of_get_property(np, "ti,timer-pwm", NULL) || - of_get_property(np, "ti,timer-secure", NULL))) - continue; - - error = omap_timer_update_dt(np); - WARN(error, "%s: Could not update dt: %i\n", __func__, error); - - return np; - } - - return NULL; -} - -/** - * omap_dmtimer_init - initialisation function when device tree is used - * - * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" - * cannot be used by the kernel as they are reserved. Therefore, to prevent the - * kernel registering these devices remove them dynamically from the device - * tree on boot. - */ -static void __init omap_dmtimer_init(void) -{ - struct device_node *np; - - if (!cpu_is_omap34xx() && !soc_is_dra7xx()) - return; - - /* If we are a secure device, remove any secure timer nodes */ - if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { - np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); - of_node_put(np); - } -} - -/** - * omap_dm_timer_get_errata - get errata flags for a timer - * - * Get the timer errata flags that are specific to the OMAP device being used. - */ -static u32 __init omap_dm_timer_get_errata(void) -{ - if (cpu_is_omap24xx()) - return 0; - - return OMAP_TIMER_ERRATA_I103_I767; -} - -static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, - const char *fck_source, - const char *property, - const char **timer_name, - int posted) -{ - const char *oh_name = NULL; - struct device_node *np; - struct omap_hwmod *oh; - struct clk *src; - int r = 0; - - np = omap_get_timer_dt(omap_timer_match, property); - if (!np) - return -ENODEV; - - of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); - if (!oh_name) { - of_property_read_string_index(np->parent, "ti,hwmods", 0, - &oh_name); - if (!oh_name) - return -ENODEV; - } - - timer->irq = irq_of_parse_and_map(np, 0); - if (!timer->irq) - return -ENXIO; - - timer->io_base = of_iomap(np, 0); - - timer->fclk = of_clk_get_by_name(np, "fck"); - - of_node_put(np); - - oh = omap_hwmod_lookup(oh_name); - if (!oh) - return -ENODEV; - - *timer_name = oh->name; - - if (!timer->io_base) - return -ENXIO; - - omap_hwmod_setup_one(oh_name); - - /* After the dmtimer is using hwmod these clocks won't be needed */ - if (IS_ERR_OR_NULL(timer->fclk)) - timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); - if (IS_ERR(timer->fclk)) - return PTR_ERR(timer->fclk); - - src = clk_get(NULL, fck_source); - if (IS_ERR(src)) - return PTR_ERR(src); - - WARN(clk_set_parent(timer->fclk, src) < 0, - "Cannot set timer parent clock, no PLL clock driver?"); - - clk_put(src); - - omap_hwmod_enable(oh); - __omap_dm_timer_init_regs(timer); - - if (posted) - __omap_dm_timer_enable_posted(timer); - - /* Check that the intended posted configuration matches the actual */ - if (posted != timer->posted) - return -EINVAL; - - timer->rate = clk_get_rate(timer->fclk); - timer->reserved = 1; - - return r; -} #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) void tick_broadcast(const struct cpumask *mask) @@ -356,226 +52,6 @@ void tick_broadcast(const struct cpumask *mask) } #endif -static void __init omap2_gp_clockevent_init(int gptimer_id, - const char *fck_source, - const char *property) -{ - int res; - - clkev.id = gptimer_id; - clkev.errata = omap_dm_timer_get_errata(); - - /* - * For clock-event timers we never read the timer counter and - * so we are not impacted by errata i103 and i767. Therefore, - * we can safely ignore this errata for clock-event timers. - */ - __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); - - res = omap_dm_timer_init_one(&clkev, fck_source, property, - &clockevent_gpt.name, OMAP_TIMER_POSTED); - BUG_ON(res); - - if (request_irq(clkev.irq, omap2_gp_timer_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "gp_timer", &clkev)) - pr_err("Failed to request irq %d (gp_timer)\n", clkev.irq); - - __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); - - clockevent_gpt.cpumask = cpu_possible_mask; - clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); - clockevents_config_and_register(&clockevent_gpt, clkev.rate, - 3, /* Timer internal resynch latency */ - 0xffffffff); - - if (soc_is_am33xx() || soc_is_am43xx()) { - clockevent_gpt.suspend = omap_clkevt_idle; - clockevent_gpt.resume = omap_clkevt_unidle; - - clockevent_gpt_hwmod = - omap_hwmod_lookup(clockevent_gpt.name); - } - - pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, - clkev.rate); -} - -/* Clocksource code */ -static struct omap_dm_timer clksrc; -static bool use_gptimer_clksrc __initdata; - -/* - * clocksource - */ -static u64 clocksource_read_cycles(struct clocksource *cs) -{ - return (u64)__omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_NONPOSTED); -} - -static struct clocksource clocksource_gpt = { - .rating = 300, - .read = clocksource_read_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static u64 notrace dmtimer_read_sched_clock(void) -{ - if (clksrc.reserved) - return __omap_dm_timer_read_counter(&clksrc, - OMAP_TIMER_NONPOSTED); - - return 0; -} - -static const struct of_device_id omap_counter_match[] __initconst = { - { .compatible = "ti,omap-counter32k", }, - { } -}; - -/* Setup free-running counter for clocksource */ -static int __init __maybe_unused omap2_sync32k_clocksource_init(void) -{ - int ret; - struct device_node *np = NULL; - struct omap_hwmod *oh; - const char *oh_name = "counter_32k"; - - /* - * See if the 32kHz counter is supported. - */ - np = omap_get_timer_dt(omap_counter_match, NULL); - if (!np) - return -ENODEV; - - of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name); - if (!oh_name) { - of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); - if (!oh_name) - return -ENODEV; - } - - /* - * First check hwmod data is available for sync32k counter - */ - oh = omap_hwmod_lookup(oh_name); - if (!oh || oh->slaves_cnt == 0) - return -ENODEV; - - omap_hwmod_setup_one(oh_name); - - ret = omap_hwmod_enable(oh); - if (ret) { - pr_warn("%s: failed to enable counter_32k module (%d)\n", - __func__, ret); - return ret; - } - - return ret; -} - -static unsigned int omap2_gptimer_clksrc_load; - -static void omap2_gptimer_clksrc_suspend(struct clocksource *unused) -{ - omap2_gptimer_clksrc_load = - __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED); - - omap_hwmod_idle(clocksource_gpt_hwmod); -} - -static void omap2_gptimer_clksrc_resume(struct clocksource *unused) -{ - omap_hwmod_enable(clocksource_gpt_hwmod); - - __omap_dm_timer_load_start(&clksrc, - OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, - omap2_gptimer_clksrc_load, - OMAP_TIMER_NONPOSTED); -} - -static void __init omap2_gptimer_clocksource_init(int gptimer_id, - const char *fck_source, - const char *property) -{ - int res; - - clksrc.id = gptimer_id; - clksrc.errata = omap_dm_timer_get_errata(); - - res = omap_dm_timer_init_one(&clksrc, fck_source, property, - &clocksource_gpt.name, - OMAP_TIMER_NONPOSTED); - - if (soc_is_am43xx()) { - clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend; - clocksource_gpt.resume = omap2_gptimer_clksrc_resume; - - clocksource_gpt_hwmod = - omap_hwmod_lookup(clocksource_gpt.name); - } - - BUG_ON(res); - - __omap_dm_timer_load_start(&clksrc, - OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, - OMAP_TIMER_NONPOSTED); - sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); - - if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) - pr_err("Could not register clocksource %s\n", - clocksource_gpt.name); - else - pr_info("OMAP clocksource: %s at %lu Hz\n", - clocksource_gpt.name, clksrc.rate); -} - -static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, - const char *clkev_prop, int clksrc_nr, const char *clksrc_src, - const char *clksrc_prop, bool gptimer) -{ - omap_clk_init(); - omap_dmtimer_init(); - omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); - - /* Enable the use of clocksource="gp_timer" kernel parameter */ - if (clksrc_nr && (use_gptimer_clksrc || gptimer)) - omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, - clksrc_prop); - else - omap2_sync32k_clocksource_init(); -} - -void __init omap_init_time(void) -{ - __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", - 2, "timer_sys_ck", NULL, false); - - timer_probe(); -} - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) -void __init omap3_secure_sync32k_timer_init(void) -{ - __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", - 2, "timer_sys_ck", NULL, false); - - timer_probe(); -} -#endif /* CONFIG_ARCH_OMAP3 */ - -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ - defined(CONFIG_SOC_AM43XX) -void __init omap3_gptimer_timer_init(void) -{ - __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, - 1, "timer_sys_ck", "ti,timer-alwon", true); - if (of_have_populated_dt()) - timer_probe(); -} -#endif - #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) /* @@ -589,7 +65,6 @@ void __init omap3_gptimer_timer_init(void) */ static void __init realtime_counter_init(void) { -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER void __iomem *base; static struct clk *sys_clk; unsigned long rate; @@ -688,7 +163,6 @@ sysclk1_based: set_cntfreq(); iounmap(base); -#endif } void __init omap5_realtime_timer_init(void) @@ -699,28 +173,3 @@ void __init omap5_realtime_timer_init(void) timer_probe(); } #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ - -/** - * omap2_override_clocksource - clocksource override with user configuration - * - * Allows user to override default clocksource, using kernel parameter - * clocksource="gp_timer" (For all OMAP2PLUS architectures) - * - * Note that, here we are using same standard kernel parameter "clocksource=", - * and not introducing any OMAP specific interface. - */ -static int __init omap2_override_clocksource(char *str) -{ - if (!str) - return 0; - /* - * For OMAP architecture, we only have two options - * - sync_32k (default) - * - gp_timer (sys_clk based) - */ - if (!strcmp(str, "gp_timer")) - use_gptimer_clksrc = true; - - return 0; -} -early_param("clocksource", omap2_override_clocksource); -- cgit v1.2.3-70-g09d2 From 9530dcf1082da23438ee557291c07d475128f63a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 4 May 2020 21:51:05 +0200 Subject: ARM: dts: meson: add the gadget mode properties to the USB0 controller Testing with a USB RNDIS connection and iperf3 gives the following results: - From the host computer to the device at ~250Mbit/s - From the device to the host computer at ~76Mbit/s Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200504195105.2909711-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 5d198309058a..ae89deaa8c9c 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -229,6 +229,9 @@ interrupts = ; phys = <&usb0_phy>; phy-names = "usb2-phy"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <500>; + g-tx-fifo-size = <256 192 128 128 128>; dr_mode = "host"; status = "disabled"; }; -- cgit v1.2.3-70-g09d2 From f5a7382d6f176e29e4fd9d733b93d5b93771a7e4 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 15 May 2020 22:25:20 +0200 Subject: ARM: dts: meson8m2: Use the Meson8m2 specific USB2 PHY compatible Use the Meson8m2 specific USB2 PHY compatible string. The 3.10 vendor kernel has at least one known difference between Meson8 and Meson8m2: Meson8m2 sets the ACA_ENABLE bit while Meson8 doesn't. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200515202520.1487514-1-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8m2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 5bde7f502007..ca749cc3cc65 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -64,6 +64,14 @@ compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&usb0_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; -- cgit v1.2.3-70-g09d2 From b632506c5af22a9a7c63674fc605d24cf94d585b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 12 May 2020 23:51:47 +0200 Subject: ARM: dts: meson: Add the Ethernet "timing-adjustment" clock Add the "timing-adjusment" clock now that we now that this is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay no the MAC side (if needed). Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b.dtsi | 5 +++-- arch/arm/boot/dts/meson8m2.dtsi | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index e34b039b9357..ba36168b9c1b 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -425,8 +425,9 @@ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index ca749cc3cc65..2397ba06d608 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -30,8 +30,9 @@ 0xc1108140 0x8>; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; }; -- cgit v1.2.3-70-g09d2 From 005231128e9e97461e81fa32421957a7664317ca Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 12 May 2020 23:51:48 +0200 Subject: ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" Let the PHY generate the RX and TX delay on the Odroid-C1 and MXIII Plus. Previously we did not know that these boards used an RX delay. We assumed that setting the TX delay on the MAC side It turns out that these boards also require an RX delay of 2ns (verified on Odroid-C1, but the u-boot code uses the same setup on both boards). Ethernet only worked because u-boot added this RX delay on the MAC side. The 4ns TX delay was also wrong and the result of using an unsupported RGMII TX clock divider setting. This has been fixed in the driver with commit bd6f48546b9cb7 ("net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). Switch to phy-mode "rgmii-id" to let the PHY side handle all the delays, (as recommended by the Ethernet maintainers anyways) to correctly describe the need for a 2ns RX as well as 2ns TX delay on these boards. This fixes the Ethernet performance on Odroid-C1 where there was a huge amount of packet loss when transmitting data due to the incorrect TX delay. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20200512215148.540322-3-martin.blumenstingl@googlemail.com --- arch/arm/boot/dts/meson8b-odroidc1.dts | 3 +-- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index a2a47804fc4a..cb21ac9f517c 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -202,9 +202,8 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; - phy-mode = "rgmii"; phy-handle = <ð_phy>; - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; nvmem-cells = <ðernet_mac_address>; nvmem-cell-names = "mac-address"; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index d54477b1001c..cc498191ddd1 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -69,9 +69,7 @@ pinctrl-names = "default"; phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; mdio { compatible = "snps,dwmac-mdio"; -- cgit v1.2.3-70-g09d2 From 16d6b91a4b2a817ab0b8e224cffa0c838b16a8df Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 1 May 2020 17:37:47 -0300 Subject: ARM: dts: imx50: Remove unused iomuxc-gpr node The iomuxc-gpr node is not used and causes the following dtc warning with W=1: arch/arm/boot/dts/imx50.dtsi:286.28-289.6: Warning (unique_unit_address): /soc/bus@50000000/iomuxc@53fa8000: duplicate unit-address (also used in node /soc/bus@50000000/iomuxc-gpr@53fa8000) Remove the node to fix the warning. Signed-off-by: Fabio Estevam Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index d325658901c5..339294df0399 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -288,11 +288,6 @@ reg = <0x53fa8000 0x4000>; }; - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx50-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; -- cgit v1.2.3-70-g09d2 From 5b4bf802427e3f49b9bca5e02ec7154e4d3d63ad Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 7 May 2020 22:43:39 +0200 Subject: ARM: imx_v6_v7_defconfig: extend RN5T618 PMIC family support There are new drivers for functionality of that family (RTC and ADC), so enable them, since they are used by various i.MX6 boards. Signed-off-by: Andreas Kemnade Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 5a20d12d62bd..87e6400c436b 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -395,6 +395,7 @@ CONFIG_RTC_DRV_DA9063=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_MXC_V2=y +CONFIG_RTC_DRV_RC5T619=y CONFIG_RTC_DRV_SNVS=y CONFIG_DMADEVICES=y CONFIG_FSL_EDMA=y @@ -408,6 +409,7 @@ CONFIG_COMMON_CLK_PWM=y CONFIG_IIO=y CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y +CONFIG_RN5T618_ADC=y CONFIG_VF610_ADC=y CONFIG_SENSORS_ISL29018=y CONFIG_MAG3110=y -- cgit v1.2.3-70-g09d2 From 64d7bf58e72be362ce2f2682e1250dcf2e61a1e6 Mon Sep 17 00:00:00 2001 From: Ma Feng Date: Mon, 11 May 2020 20:36:04 +0800 Subject: ARM: imx: pcm037: make pcm970_sja1000_platform_data static Fix sparse warning: arch/arm/mach-imx/mach-pcm037.c:407:30: warning: symbol 'pcm970_sja1000_platform_data' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: Ma Feng Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-pcm037.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index bd9443fa6edc..c7d23e9d4f8b 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c @@ -404,7 +404,7 @@ static struct resource pcm970_sja1000_resources[] = { }, }; -struct sja1000_platform_data pcm970_sja1000_platform_data = { +static struct sja1000_platform_data pcm970_sja1000_platform_data = { .osc_freq = 16000000, .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, .cdr = CDR_CBP, -- cgit v1.2.3-70-g09d2 From 905d3d25c18a44f9e69fa5b1c2a6467df0471fe2 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 May 2020 10:25:06 +0800 Subject: ARM: dts: imx51: Add src node interrupt Interrupt is a required property according to SRC binding, add it for SRC node. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 92fbb90bec57..3f1e913d5ab8 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -442,6 +442,7 @@ src: src@73fd0000 { compatible = "fsl,imx51-src"; reg = <0x73fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; -- cgit v1.2.3-70-g09d2 From 012d1c246f1f821762404196f04591411fc17e22 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 May 2020 10:25:07 +0800 Subject: ARM: dts: imx53: Add src node interrupt Interrupt is a required property according to SRC binding, add it for SRC node. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 8536f59f59e6..0d06dbdd932c 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -591,6 +591,7 @@ src: src@53fd0000 { compatible = "fsl,imx53-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; -- cgit v1.2.3-70-g09d2 From 9e72702a3d9a967edac02d8e937bce2b68b77814 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 12 May 2020 13:59:37 -0700 Subject: ARM: dts: imx6qdl-gw560x: add lsm9ds1 iio imu/magn support Add one node for the accel/gyro i2c device and another for the separate magnetometer device in the lsm9ds1. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index e8e36dfd0a6b..69ca70d3baa8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -295,6 +295,15 @@ VDDIO-supply = <®_3p3v>; }; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + }; + tca8418: keypad@34 { compatible = "ti,tca8418"; pinctrl-names = "default"; @@ -389,6 +398,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -609,6 +628,12 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ @@ -616,6 +641,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ -- cgit v1.2.3-70-g09d2 From c8756cbad816954be912ba32277ccd55fe7acc01 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 12 May 2020 13:59:56 -0700 Subject: ARM: dts: imx6qdl-gw5904: add lsm9ds1 iio imu/magn support Add one node for the accel/gyro i2c device and another for the separate magnetometer device in the lsm9ds1. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 6d21cc6a9d4b..76d6cf57f1c3 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -248,6 +248,15 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + ltc3676: pmic@3c { compatible = "lltc,ltc3676"; reg = <0x3c>; @@ -320,6 +329,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -501,6 +520,18 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ -- cgit v1.2.3-70-g09d2 From d40edafe80569c5b4d8893c1cdd1060c54ef433c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 12 May 2020 14:54:15 -0700 Subject: ARM: dts: imx6qdl-gw5910: add support for bcm4330-bt The Sterling-LWB has a BCM4330 which has a UART based bluetooth HCI. Add support for binding to the bcm_hci driver to take care of handling the shutdown gpio and loading firmware. Because the shutdown gpio is more of an enable than a regulator go ahead and replace the regulator with a shutdown-gpio. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 30fe47ff64a4..b850f8f62970 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -83,19 +83,6 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; - - reg_bt: regulator-bt { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_bt>; - compatible = "regulator-fixed"; - regulator-name = "bt"; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; @@ -231,9 +218,14 @@ /* Sterling-LWB Bluetooth */ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; + pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; }; /* GPS */ @@ -288,6 +280,12 @@ >; }; + pinctrl_bten: btengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + >; + }; + pinctrl_ecspi3: escpi3grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 @@ -393,12 +391,6 @@ >; }; - pinctrl_reg_bt: regbtgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - >; - }; - pinctrl_reg_wl: regwlgrp { fsl,pins = < MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 -- cgit v1.2.3-70-g09d2 From 4792ff641cc8993606013d27d84cda59d8cc76c5 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 12 May 2020 15:02:34 -0700 Subject: ARM: dts: imx6qdl-gw5910: fix wlan regulator Connect the wl_reg regulator to usdhc2 such that it can be enabled and disabled as needed. There is no need for this to be always-on. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index b850f8f62970..0857de505192 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -81,7 +81,6 @@ enable-active-high; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; @@ -251,7 +250,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_wl>; non-removable; bus-width = <4>; status = "okay"; -- cgit v1.2.3-70-g09d2 From d8a6511d988a80dc7b1a83bcc213c6340def3590 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 14 May 2020 09:08:47 +0800 Subject: ARM: dts: imx6qdl: Use nvmem interface to get fuse data Although ocotp clock is always ON for i.MX6QDL, OCOTP can be accessed directly, but since i.MX6QDL nvmem interface is supported, and fsl,tempmon-data is deprecated, use it instead of getting fuse data by reading ocotp directly, this makes all i.MX6 SoCs aligned. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 47982889d774..0ddb4dfc9b9b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -74,7 +74,8 @@ interrupt-parent = <&gpc>; interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; #thermal-sensor-cells = <0>; }; @@ -1171,6 +1172,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; tzasc@21d0000 { /* TZASC1 */ -- cgit v1.2.3-70-g09d2 From d7e1c2b081b08dbcd8717613407dd9f99f3b9c0f Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 14 May 2020 09:08:48 +0800 Subject: ARM: dts: imx6sl: Use nvmem interface to get fuse data Although ocotp clock is always ON for i.MX6SL, OCOTP can be accessed directly, but since i.MX6SL nvmem interface is supported, and fsl,tempmon-data is deprecated, use it instead of getting fuse data by reading ocotp directly, this makes all i.MX6 SoCs aligned. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 8230b45057a1..fcb84fe0e032 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -98,7 +98,8 @@ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gpc>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; }; @@ -961,6 +962,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; audmux: audmux@21d8000 { -- cgit v1.2.3-70-g09d2 From fbf40f4e64ba7eb814aa02b6c4c76a032f877ad6 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Fri, 15 May 2020 13:41:51 +0200 Subject: ARM: dts: imx7d-pinfunc: add input mux for ENET2 mdio Add the missing input mux for ENET2 mdio. Without this setting, it is not possible to read the MDIO answers back from the PHY. Signed-off-by: Steffen Trumtrar Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h index 08ca1608fdb1..69f2c1ec8254 100644 --- a/arch/arm/boot/dts/imx7d-pinfunc.h +++ b/arch/arm/boot/dts/imx7d-pinfunc.h @@ -592,7 +592,7 @@ #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 -- cgit v1.2.3-70-g09d2 From eb998547a0bd8663245400ca197e28945bd289fe Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 18 May 2020 20:39:53 +0800 Subject: ARM: dts: imx: make src node name generic Node name should be generic, use "reset-controller" instead of "src" for i.MX6/i.MX7 SoCs src nodes. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- arch/arm/boot/dts/imx6sl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- arch/arm/boot/dts/imx6ul.dtsi | 2 +- arch/arm/boot/dts/imx7s.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 0ddb4dfc9b9b..3b442b4493bd 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -858,7 +858,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index fcb84fe0e032..911d8cf77f2c 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -678,7 +678,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index d6f831731460..e03133740078 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -754,7 +754,7 @@ interrupts = ; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 2ccf67c4ac1a..35e730167960 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -676,7 +676,7 @@ interrupts = ; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 76e3ffbbbfbf..8bac49137692 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -624,7 +624,7 @@ clock-names = "ckil", "osc"; }; - src: src@30390000 { + src: reset-controller@30390000 { compatible = "fsl,imx7d-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = ; -- cgit v1.2.3-70-g09d2 From 1ebc662f5da64aae9a2ad6ca2133ad233ec0682d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 18 May 2020 20:54:19 +0800 Subject: ARM: dts: imx50: Add src node interrupt Interrupt is a required property according to SRC binding, add it for SRC node. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 339294df0399..74f49b4aed1a 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -331,6 +331,7 @@ src: src@53fd0000 { compatible = "fsl,imx50-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; -- cgit v1.2.3-70-g09d2 From 6a3153e1e0b7d514dcec2833a6b3d7946864508d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 18 May 2020 20:54:20 +0800 Subject: ARM: dts: imx5: make src node name generic Node name should be generic, use "reset-controller" instead of "src" for i.MX5 SoCs src nodes. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 2 +- arch/arm/boot/dts/imx53.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 74f49b4aed1a..1f4ecbca5225 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -328,7 +328,7 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx50-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; interrupts = <75>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 3f1e913d5ab8..d3583aad8323 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -439,7 +439,7 @@ status = "disabled"; }; - src: src@73fd0000 { + src: reset-controller@73fd0000 { compatible = "fsl,imx51-src"; reg = <0x73fd0000 0x4000>; interrupts = <75>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 0d06dbdd932c..afa57bf7b0ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -588,7 +588,7 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx53-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; interrupts = <75>; -- cgit v1.2.3-70-g09d2 From 103515d91832bb837159c37f0cb69d59d68a1dc2 Mon Sep 17 00:00:00 2001 From: Ricardo Cañuelo Date: Thu, 14 May 2020 16:36:10 +0200 Subject: ARM: dts: imx53-cx9020: Group port definitions for the dvi-converter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the port definitions of the dvi-converter in a 'ports' node to make it compliant with the ti,tfp410 binding. Signed-off-by: Ricardo Cañuelo Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-cx9020.dts | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts index 0a475c234054..cfb18849a92b 100644 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ b/arch/arm/boot/dts/imx53-cx9020.dts @@ -59,23 +59,26 @@ }; dvi-converter { - #address-cells = <1>; - #size-cells = <0>; compatible = "ti,tfp410"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; - tfp410_in: endpoint { - remote-endpoint = <&display0_out>; + tfp410_in: endpoint { + remote-endpoint = <&display0_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; }; }; }; -- cgit v1.2.3-70-g09d2 From d2199b34871b859d33cd08398af5f1530241cb4e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 20 May 2020 13:51:27 +0800 Subject: ARM: imx: use device_initcall for imx_soc_device_init This is preparation to move imx_soc_device_init to drivers/soc/imx/ There is no reason to must put dt devices under /sys/devices/soc0, they could also be under /sys/devices/platform, so we could pass NULL as parent when calling of_platform_default_populate. Following soc-imx8.c soc-imx-scu.c using device_initcall, need to change return type to int type for imx_soc_device_init. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 1 - arch/arm/mach-imx/cpu.c | 21 ++++++++++++++------- arch/arm/mach-imx/mach-imx6q.c | 8 +------- arch/arm/mach-imx/mach-imx6sl.c | 8 +------- arch/arm/mach-imx/mach-imx6sx.c | 8 +------- arch/arm/mach-imx/mach-imx6ul.c | 8 +------- arch/arm/mach-imx/mach-imx7d.c | 6 ------ arch/arm/mach-imx/mach-imx7ulp.c | 2 +- arch/arm/mach-imx/mach-vf610.c | 8 +------- 9 files changed, 20 insertions(+), 50 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 5aa5796cff0e..72c3fcc32910 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -49,7 +49,6 @@ void imx_aips_allow_unprivileged_access(const char *compat); int mxc_device_init(void); void imx_set_soc_revision(unsigned int rev); void imx_init_revision_from_anatop(void); -struct device *imx_soc_device_init(void); void imx6_enable_rbc(bool enable); void imx_gpc_check_dt(void); void imx_gpc_set_arm_power_in_lpm(bool power_off); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index e3d12b21d6f6..75ffcba9f878 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -83,7 +83,7 @@ void __init imx_aips_allow_unprivileged_access( } } -struct device * __init imx_soc_device_init(void) +static int __init imx_soc_device_init(void) { struct soc_device_attribute *soc_dev_attr; const char *ocotp_compat = NULL; @@ -97,7 +97,7 @@ struct device * __init imx_soc_device_init(void) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) - return NULL; + return -ENOMEM; soc_dev_attr->family = "Freescale i.MX"; @@ -224,18 +224,24 @@ struct device * __init imx_soc_device_init(void) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", (imx_soc_revision >> 4) & 0xf, imx_soc_revision & 0xf); - if (!soc_dev_attr->revision) + if (!soc_dev_attr->revision) { + ret = -ENOMEM; goto free_soc; + } soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); - if (!soc_dev_attr->serial_number) + if (!soc_dev_attr->serial_number) { + ret = -ENOMEM; goto free_rev; + } soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) + if (IS_ERR(soc_dev)) { + ret = PTR_ERR(soc_dev); goto free_serial_number; + } - return soc_device_to_device(soc_dev); + return 0; free_serial_number: kfree(soc_dev_attr->serial_number); @@ -243,5 +249,6 @@ free_rev: kfree(soc_dev_attr->revision); free_soc: kfree(soc_dev_attr); - return NULL; + return ret; } +device_initcall(imx_soc_device_init); diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 284bce1112d2..85c084a716ab 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -245,21 +245,15 @@ static void __init imx6q_axi_init(void) static void __init imx6q_init_machine(void) { - struct device *parent; - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - imx6q_enet_phy_init(); - of_platform_default_populate(NULL, NULL, parent); + of_platform_default_populate(NULL, NULL, NULL); imx_anatop_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index e27a6889cc56..f6e87363d605 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -45,13 +45,7 @@ static void __init imx6sl_init_late(void) static void __init imx6sl_init_machine(void) { - struct device *parent; - - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - - of_platform_default_populate(NULL, NULL, parent); + of_platform_default_populate(NULL, NULL, NULL); if (cpu_is_imx6sl()) imx6sl_fec_init(); diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index d5310bf307ff..781e2a94fdd7 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -63,13 +63,7 @@ static inline void imx6sx_enet_init(void) static void __init imx6sx_init_machine(void) { - struct device *parent; - - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - - of_platform_default_populate(NULL, NULL, parent); + of_platform_default_populate(NULL, NULL, NULL); imx6sx_enet_init(); imx_anatop_init(); diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 3b0e16ccd59d..e018e716735f 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -55,13 +55,7 @@ static inline void imx6ul_enet_init(void) static void __init imx6ul_init_machine(void) { - struct device *parent; - - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - - of_platform_default_populate(NULL, NULL, parent); + of_platform_default_populate(NULL, NULL, NULL); imx6ul_enet_init(); imx_anatop_init(); imx6ul_pm_init(); diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index ebb27592a9f7..879c35929a13 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -78,12 +78,6 @@ static inline void imx7d_enet_init(void) static void __init imx7d_init_machine(void) { - struct device *parent; - - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - imx_anatop_init(); imx7d_enet_init(); } diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 11ac71aaf965..128cf4c92aab 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -57,7 +57,7 @@ static void __init imx7ulp_init_machine(void) mxc_set_cpu_type(MXC_CPU_IMX7ULP); imx7ulp_set_revision(); - of_platform_default_populate(NULL, NULL, imx_soc_device_init()); + of_platform_default_populate(NULL, NULL, NULL); } static const char *const imx7ulp_dt_compat[] __initconst = { diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 565dc08412a2..208ff640698d 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -49,15 +49,9 @@ static void __init vf610_detect_cpu(void) static void __init vf610_init_machine(void) { - struct device *parent; - vf610_detect_cpu(); - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - - of_platform_default_populate(NULL, NULL, parent); + of_platform_default_populate(NULL, NULL, NULL); } static const char * const vf610_dt_compat[] __initconst = { -- cgit v1.2.3-70-g09d2 From f72130c6b62e45df18ca7568d13f5402c2f58115 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 20 May 2020 13:51:28 +0800 Subject: ARM: imx: move cpu definitions into a header The soc device register code will be moved to drivers/soc/imx/, the code needs the cpu type definitions. So let's move the cpu type definitions to a header. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mxc.h | 28 +--------------------------- include/soc/imx/cpu.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 27 deletions(-) create mode 100644 include/soc/imx/cpu.h (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 48e6d781f15b..fe2d0f5abfcc 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -8,41 +8,15 @@ #define __ASM_ARCH_MXC_H__ #include +#include #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #error "Do not include directly." #endif -#define MXC_CPU_MX1 1 -#define MXC_CPU_MX21 21 -#define MXC_CPU_MX25 25 -#define MXC_CPU_MX27 27 -#define MXC_CPU_MX31 31 -#define MXC_CPU_MX35 35 -#define MXC_CPU_MX51 51 -#define MXC_CPU_MX53 53 -#define MXC_CPU_IMX6SL 0x60 -#define MXC_CPU_IMX6DL 0x61 -#define MXC_CPU_IMX6SX 0x62 -#define MXC_CPU_IMX6Q 0x63 -#define MXC_CPU_IMX6UL 0x64 -#define MXC_CPU_IMX6ULL 0x65 -/* virtual cpu id for i.mx6ulz */ -#define MXC_CPU_IMX6ULZ 0x6b -#define MXC_CPU_IMX6SLL 0x67 -#define MXC_CPU_IMX7D 0x72 -#define MXC_CPU_IMX7ULP 0xff - -#define MXC_CPU_VFx10 0x010 -#define MXC_CPU_VF500 0x500 -#define MXC_CPU_VF510 (MXC_CPU_VF500 | MXC_CPU_VFx10) -#define MXC_CPU_VF600 0x600 -#define MXC_CPU_VF610 (MXC_CPU_VF600 | MXC_CPU_VFx10) - #define IMX_DDR_TYPE_LPDDR2 1 #ifndef __ASSEMBLY__ -extern unsigned int __mxc_cpu_type; #ifdef CONFIG_SOC_IMX6SL static inline bool cpu_is_imx6sl(void) diff --git a/include/soc/imx/cpu.h b/include/soc/imx/cpu.h new file mode 100644 index 000000000000..42d6aeb951fa --- /dev/null +++ b/include/soc/imx/cpu.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __IMX_CPU_H__ +#define __IMX_CPU_H__ + +#define MXC_CPU_MX1 1 +#define MXC_CPU_MX21 21 +#define MXC_CPU_MX25 25 +#define MXC_CPU_MX27 27 +#define MXC_CPU_MX31 31 +#define MXC_CPU_MX35 35 +#define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 +#define MXC_CPU_IMX6SL 0x60 +#define MXC_CPU_IMX6DL 0x61 +#define MXC_CPU_IMX6SX 0x62 +#define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX6UL 0x64 +#define MXC_CPU_IMX6ULL 0x65 +/* virtual cpu id for i.mx6ulz */ +#define MXC_CPU_IMX6ULZ 0x6b +#define MXC_CPU_IMX6SLL 0x67 +#define MXC_CPU_IMX7D 0x72 +#define MXC_CPU_IMX7ULP 0xff + +#define MXC_CPU_VFx10 0x010 +#define MXC_CPU_VF500 0x500 +#define MXC_CPU_VF510 (MXC_CPU_VF500 | MXC_CPU_VFx10) +#define MXC_CPU_VF600 0x600 +#define MXC_CPU_VF610 (MXC_CPU_VF600 | MXC_CPU_VFx10) + +#ifndef __ASSEMBLY__ +extern unsigned int __mxc_cpu_type; +#endif + +#endif -- cgit v1.2.3-70-g09d2 From 52102a3ba6a617449f4b057880d73be93310a7c7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 20 May 2020 13:51:29 +0800 Subject: soc: imx: move cpu code to drivers/soc/imx Move the soc device register code to drivers/soc/imx to align with i.MX8. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/cpu.c | 182 ------------------------------------------- drivers/soc/imx/Makefile | 3 + drivers/soc/imx/soc-imx.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 195 insertions(+), 182 deletions(-) create mode 100644 drivers/soc/imx/soc-imx.c (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 75ffcba9f878..65c7224f5250 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,25 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include #include #include #include #include -#include -#include -#include #include "hardware.h" #include "common.h" -#define OCOTP_UID_H 0x420 -#define OCOTP_UID_L 0x410 - -#define OCOTP_ULP_UID_1 0x4b0 -#define OCOTP_ULP_UID_2 0x4c0 -#define OCOTP_ULP_UID_3 0x4d0 -#define OCOTP_ULP_UID_4 0x4e0 - unsigned int __mxc_cpu_type; static unsigned int imx_soc_revision; @@ -82,173 +70,3 @@ void __init imx_aips_allow_unprivileged_access( imx_set_aips(aips_base_addr); } } - -static int __init imx_soc_device_init(void) -{ - struct soc_device_attribute *soc_dev_attr; - const char *ocotp_compat = NULL; - struct soc_device *soc_dev; - struct device_node *root; - struct regmap *ocotp = NULL; - const char *soc_id; - u64 soc_uid = 0; - u32 val; - int ret; - - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return -ENOMEM; - - soc_dev_attr->family = "Freescale i.MX"; - - root = of_find_node_by_path("/"); - ret = of_property_read_string(root, "model", &soc_dev_attr->machine); - of_node_put(root); - if (ret) - goto free_soc; - - switch (__mxc_cpu_type) { - case MXC_CPU_MX1: - soc_id = "i.MX1"; - break; - case MXC_CPU_MX21: - soc_id = "i.MX21"; - break; - case MXC_CPU_MX25: - soc_id = "i.MX25"; - break; - case MXC_CPU_MX27: - soc_id = "i.MX27"; - break; - case MXC_CPU_MX31: - soc_id = "i.MX31"; - break; - case MXC_CPU_MX35: - soc_id = "i.MX35"; - break; - case MXC_CPU_MX51: - soc_id = "i.MX51"; - break; - case MXC_CPU_MX53: - soc_id = "i.MX53"; - break; - case MXC_CPU_IMX6SL: - ocotp_compat = "fsl,imx6sl-ocotp"; - soc_id = "i.MX6SL"; - break; - case MXC_CPU_IMX6DL: - ocotp_compat = "fsl,imx6q-ocotp"; - soc_id = "i.MX6DL"; - break; - case MXC_CPU_IMX6SX: - ocotp_compat = "fsl,imx6sx-ocotp"; - soc_id = "i.MX6SX"; - break; - case MXC_CPU_IMX6Q: - ocotp_compat = "fsl,imx6q-ocotp"; - soc_id = "i.MX6Q"; - break; - case MXC_CPU_IMX6UL: - ocotp_compat = "fsl,imx6ul-ocotp"; - soc_id = "i.MX6UL"; - break; - case MXC_CPU_IMX6ULL: - ocotp_compat = "fsl,imx6ull-ocotp"; - soc_id = "i.MX6ULL"; - break; - case MXC_CPU_IMX6ULZ: - ocotp_compat = "fsl,imx6ull-ocotp"; - soc_id = "i.MX6ULZ"; - break; - case MXC_CPU_IMX6SLL: - ocotp_compat = "fsl,imx6sll-ocotp"; - soc_id = "i.MX6SLL"; - break; - case MXC_CPU_IMX7D: - ocotp_compat = "fsl,imx7d-ocotp"; - soc_id = "i.MX7D"; - break; - case MXC_CPU_IMX7ULP: - ocotp_compat = "fsl,imx7ulp-ocotp"; - soc_id = "i.MX7ULP"; - break; - case MXC_CPU_VF500: - ocotp_compat = "fsl,vf610-ocotp"; - soc_id = "VF500"; - break; - case MXC_CPU_VF510: - ocotp_compat = "fsl,vf610-ocotp"; - soc_id = "VF510"; - break; - case MXC_CPU_VF600: - ocotp_compat = "fsl,vf610-ocotp"; - soc_id = "VF600"; - break; - case MXC_CPU_VF610: - ocotp_compat = "fsl,vf610-ocotp"; - soc_id = "VF610"; - break; - default: - soc_id = "Unknown"; - } - soc_dev_attr->soc_id = soc_id; - - if (ocotp_compat) { - ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat); - if (IS_ERR(ocotp)) - pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat); - } - - if (!IS_ERR_OR_NULL(ocotp)) { - if (__mxc_cpu_type == MXC_CPU_IMX7ULP) { - regmap_read(ocotp, OCOTP_ULP_UID_4, &val); - soc_uid = val & 0xffff; - regmap_read(ocotp, OCOTP_ULP_UID_3, &val); - soc_uid <<= 16; - soc_uid |= val & 0xffff; - regmap_read(ocotp, OCOTP_ULP_UID_2, &val); - soc_uid <<= 16; - soc_uid |= val & 0xffff; - regmap_read(ocotp, OCOTP_ULP_UID_1, &val); - soc_uid <<= 16; - soc_uid |= val & 0xffff; - } else { - regmap_read(ocotp, OCOTP_UID_H, &val); - soc_uid = val; - regmap_read(ocotp, OCOTP_UID_L, &val); - soc_uid <<= 32; - soc_uid |= val; - } - } - - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", - (imx_soc_revision >> 4) & 0xf, - imx_soc_revision & 0xf); - if (!soc_dev_attr->revision) { - ret = -ENOMEM; - goto free_soc; - } - - soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); - if (!soc_dev_attr->serial_number) { - ret = -ENOMEM; - goto free_rev; - } - - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - ret = PTR_ERR(soc_dev); - goto free_serial_number; - } - - return 0; - -free_serial_number: - kfree(soc_dev_attr->serial_number); -free_rev: - kfree(soc_dev_attr->revision); -free_soc: - kfree(soc_dev_attr); - return ret; -} -device_initcall(imx_soc_device_init); diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 103e2c93c342..446143241fe7 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_ARM),y) +obj-$(CONFIG_ARCH_MXC) += soc-imx.o +endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o diff --git a/drivers/soc/imx/soc-imx.c b/drivers/soc/imx/soc-imx.c new file mode 100644 index 000000000000..fec3d672b606 --- /dev/null +++ b/drivers/soc/imx/soc-imx.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define OCOTP_UID_H 0x420 +#define OCOTP_UID_L 0x410 + +#define OCOTP_ULP_UID_1 0x4b0 +#define OCOTP_ULP_UID_2 0x4c0 +#define OCOTP_ULP_UID_3 0x4d0 +#define OCOTP_ULP_UID_4 0x4e0 + +static int __init imx_soc_device_init(void) +{ + struct soc_device_attribute *soc_dev_attr; + const char *ocotp_compat = NULL; + struct soc_device *soc_dev; + struct device_node *root; + struct regmap *ocotp = NULL; + const char *soc_id; + u64 soc_uid = 0; + u32 val; + int ret; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Freescale i.MX"; + + root = of_find_node_by_path("/"); + ret = of_property_read_string(root, "model", &soc_dev_attr->machine); + of_node_put(root); + if (ret) + goto free_soc; + + switch (__mxc_cpu_type) { + case MXC_CPU_MX1: + soc_id = "i.MX1"; + break; + case MXC_CPU_MX21: + soc_id = "i.MX21"; + break; + case MXC_CPU_MX25: + soc_id = "i.MX25"; + break; + case MXC_CPU_MX27: + soc_id = "i.MX27"; + break; + case MXC_CPU_MX31: + soc_id = "i.MX31"; + break; + case MXC_CPU_MX35: + soc_id = "i.MX35"; + break; + case MXC_CPU_MX51: + soc_id = "i.MX51"; + break; + case MXC_CPU_MX53: + soc_id = "i.MX53"; + break; + case MXC_CPU_IMX6SL: + ocotp_compat = "fsl,imx6sl-ocotp"; + soc_id = "i.MX6SL"; + break; + case MXC_CPU_IMX6DL: + ocotp_compat = "fsl,imx6q-ocotp"; + soc_id = "i.MX6DL"; + break; + case MXC_CPU_IMX6SX: + ocotp_compat = "fsl,imx6sx-ocotp"; + soc_id = "i.MX6SX"; + break; + case MXC_CPU_IMX6Q: + ocotp_compat = "fsl,imx6q-ocotp"; + soc_id = "i.MX6Q"; + break; + case MXC_CPU_IMX6UL: + ocotp_compat = "fsl,imx6ul-ocotp"; + soc_id = "i.MX6UL"; + break; + case MXC_CPU_IMX6ULL: + ocotp_compat = "fsl,imx6ull-ocotp"; + soc_id = "i.MX6ULL"; + break; + case MXC_CPU_IMX6ULZ: + ocotp_compat = "fsl,imx6ull-ocotp"; + soc_id = "i.MX6ULZ"; + break; + case MXC_CPU_IMX6SLL: + ocotp_compat = "fsl,imx6sll-ocotp"; + soc_id = "i.MX6SLL"; + break; + case MXC_CPU_IMX7D: + ocotp_compat = "fsl,imx7d-ocotp"; + soc_id = "i.MX7D"; + break; + case MXC_CPU_IMX7ULP: + ocotp_compat = "fsl,imx7ulp-ocotp"; + soc_id = "i.MX7ULP"; + break; + case MXC_CPU_VF500: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF500"; + break; + case MXC_CPU_VF510: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF510"; + break; + case MXC_CPU_VF600: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF600"; + break; + case MXC_CPU_VF610: + ocotp_compat = "fsl,vf610-ocotp"; + soc_id = "VF610"; + break; + default: + soc_id = "Unknown"; + } + soc_dev_attr->soc_id = soc_id; + + if (ocotp_compat) { + ocotp = syscon_regmap_lookup_by_compatible(ocotp_compat); + if (IS_ERR(ocotp)) + pr_err("%s: failed to find %s regmap!\n", __func__, ocotp_compat); + } + + if (!IS_ERR_OR_NULL(ocotp)) { + if (__mxc_cpu_type == MXC_CPU_IMX7ULP) { + regmap_read(ocotp, OCOTP_ULP_UID_4, &val); + soc_uid = val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_3, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_2, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + regmap_read(ocotp, OCOTP_ULP_UID_1, &val); + soc_uid <<= 16; + soc_uid |= val & 0xffff; + } else { + regmap_read(ocotp, OCOTP_UID_H, &val); + soc_uid = val; + regmap_read(ocotp, OCOTP_UID_L, &val); + soc_uid <<= 32; + soc_uid |= val; + } + } + + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", + (imx_get_soc_revision() >> 4) & 0xf, + imx_get_soc_revision() & 0xf); + if (!soc_dev_attr->revision) { + ret = -ENOMEM; + goto free_soc; + } + + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + if (!soc_dev_attr->serial_number) { + ret = -ENOMEM; + goto free_rev; + } + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + ret = PTR_ERR(soc_dev); + goto free_serial_number; + } + + return 0; + +free_serial_number: + kfree(soc_dev_attr->serial_number); +free_rev: + kfree(soc_dev_attr->revision); +free_soc: + kfree(soc_dev_attr); + return ret; +} +device_initcall(imx_soc_device_init); -- cgit v1.2.3-70-g09d2 From 6656e163535530098f85651e5987f0a68705875b Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:43 +0200 Subject: ARM: dts: kirkwood: Fix interrupt controller node name The current ones makes validation unhappy: kirkwood-lsxhl.dt.yaml: main-interrupt-ctrl@20200: $nodename:0: 'main-interrupt-ctrl@20200' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/kirkwood.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 2161e23bd98e..6c8d94beae78 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -228,7 +228,7 @@ reg = <0x20128 0x4>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; -- cgit v1.2.3-70-g09d2 From a857caa9d95b8645a38113db79e37b6bcefd35c8 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:44 +0200 Subject: ARM: dts: dove: Fix interrupt controller node name The current ones makes validation unhappy: dove-d3plug.dt.yaml: main-interrupt-ctrl@20200: $nodename:0: 'main-interrupt-ctrl@20200' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/dove.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index a551fabae851..89e0bdaf3a85 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -247,7 +247,7 @@ marvell,#interrupts = <5>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; -- cgit v1.2.3-70-g09d2 From 4fade3403e5a8f1750a444023d9ed175e2960a37 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:45 +0200 Subject: ARM: dts: pxa168: Add missing address/size cells to i2c nodes This makes the nodes compatible with the generic i2c binding without the board DTS files having to supply the necessary properties themselves. Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/pxa168.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 9a9e38245e88..fb92fcf231cd 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -119,6 +119,8 @@ twsi1: i2c@d4011000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; clocks = <&soc_clocks PXA168_CLK_TWSI0>; @@ -129,6 +131,8 @@ twsi2: i2c@d4025000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4025000 0x1000>; interrupts = <58>; clocks = <&soc_clocks PXA168_CLK_TWSI1>; -- cgit v1.2.3-70-g09d2 From 51d6bba66113f7da02f2c0b645c721f1ba6b98eb Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:46 +0200 Subject: ARM: dts: pxa168: Fix the gpio interrupt cell number gpio-pxa uses two cell to encode the interrupt source: the pin number and the trigger type. Adjust the device node accordingly. Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/pxa168.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index fb92fcf231cd..550cd372d7c9 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -97,7 +97,7 @@ resets = <&soc_clocks PXA168_CLK_GPIO>; interrupt-names = "gpio_mux"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { -- cgit v1.2.3-70-g09d2 From 55d26c38442e8f23491085b5cebddd352dea9e9a Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:47 +0200 Subject: ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property This way the device tree validator learns that each cell of the property constitutes a separate item. Otherwise it gets unnecessairly upset: pxa300-raumfeld-speaker-s.dt.yaml: gpio@40e00000: interrupts: [[8, 9, 10]] is too short Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Reviewed-by: Robert Jarzmik Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/pxa3xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index c237a0e4b12a..d19674812cd2 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -170,7 +170,7 @@ clocks = <&clks CLK_GPIO>; gpio-ranges = <&pinctrl 0 0 128>; interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; + interrupts = <8>, <9>, <10>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; -- cgit v1.2.3-70-g09d2 From c911cadfab50a67beff9cb036c3de9f8c81ff976 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:48 +0200 Subject: ARM: dts: pxa910: Fix the gpio interrupt cell number gpio-pxa uses two cell to encode the interrupt source: the pin number and the trigger type. Adjust the device node accordingly. Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/pxa910.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index 587a5e7f0702..f59f593acff4 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -109,7 +109,7 @@ clocks = <&soc_clocks PXA910_CLK_GPIO>; resets = <&soc_clocks PXA910_CLK_GPIO>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { -- cgit v1.2.3-70-g09d2 From 2e7167d17bcdc9968e0a103f7cb01b2820f86345 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:49 +0200 Subject: ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property This way the device tree validator learns that each cell of the property constitutes a separate item. Otherwise it gets unnecessairly upset: pxa168-aspenite.dt.yaml: rtc@d4010000: interrupts: [[5, 6]] is too short pxa910-dkb.dt.yaml: rtc@d4010000: interrupts: [[5, 6]] is too short Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/pxa168.dtsi | 2 +- arch/arm/boot/dts/pxa910.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 550cd372d7c9..4fe7735c7c58 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -143,7 +143,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA168_CLK_RTC>; resets = <&soc_clocks PXA168_CLK_RTC>; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index f59f593acff4..352a39357810 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -155,7 +155,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA910_CLK_RTC>; resets = <&soc_clocks PXA910_CLK_RTC>; -- cgit v1.2.3-70-g09d2 From 4989fd577d0720c334ddbd01748a21a9adc7d197 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:50 +0200 Subject: ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property This way the device tree validator learns that each cell of the property constitutes a separate item. Otherwise it gets unnecessairly upset: mmp3-dell-ariel.dt.yaml: rtc@d4010000: interrupts: [[1, 0]] is too short Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mmp2.dtsi | 2 +- arch/arm/boot/dts/mmp3.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index da10567b5aca..4306f3a6742b 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -364,7 +364,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&intcmux5>; clocks = <&soc_clocks MMP2_CLK_RTC>; diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 9b5087a95e73..3ac5e4e86e56 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -474,7 +474,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&rtc_mux>; clocks = <&soc_clocks MMP2_CLK_RTC>; -- cgit v1.2.3-70-g09d2 From 7df3a1ee12ebccd13c4b2d0def7b0403216db4f0 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:51 +0200 Subject: ARM: dts: mmp3: Fix L2 cache controller node name The current one makes validation unhappy: mmp3-dell-ariel.dt.yaml: l2-cache-controller@d0020000: $nodename:0: 'l2-cache-controller@d0020000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mmp3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 3ac5e4e86e56..531e1d85d5fa 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -523,7 +523,7 @@ }; }; - l2: l2-cache-controller@d0020000 { + l2: cache-controller@d0020000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xd0020000 0x1000>; cache-unified; -- cgit v1.2.3-70-g09d2 From bbbea1f2a9b16c7f85e94e4c2d90eee005cfae61 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:52 +0200 Subject: ARM: dts: mmp3: Fix USB & USB PHY node names There are better generic ones and the validation is going to complain: mmp3-dell-ariel.dt.yaml: hsic@f0001000: $nodename:0: 'hsic@f0001000' does not match '^usb(@.*)?' mmp3-dell-ariel.dt.yaml: hsic@f0002000: $nodename:0: 'hsic@f0002000' does not match '^usb(@.*)?' ... Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mmp3.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index 531e1d85d5fa..a4d8d846f81a 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -183,14 +183,14 @@ mrvl,intc-nr-irqs = <5>; }; - usb_otg_phy0: usb-otg-phy@d4207000 { + usb_otg_phy0: usb-phy@d4207000 { compatible = "marvell,mmp3-usb-phy"; reg = <0xd4207000 0x40>; #phy-cells = <0>; status = "disabled"; }; - usb_otg0: usb-otg@d4208000 { + usb_otg0: usb@d4208000 { compatible = "marvell,pxau2o-ehci"; reg = <0xd4208000 0x200>; interrupts = ; @@ -201,7 +201,7 @@ status = "disabled"; }; - hsic_phy0: hsic-phy@f0001800 { + hsic_phy0: usb-phy@f0001800 { compatible = "marvell,mmp3-hsic-phy", "usb-nop-xceiv"; reg = <0xf0001800 0x40>; @@ -209,7 +209,7 @@ status = "disabled"; }; - hsic0: hsic@f0001000 { + hsic0: usb@f0001000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0001000 0x200>; interrupts = ; @@ -223,7 +223,7 @@ status = "disabled"; }; - hsic_phy1: hsic-phy@f0002800 { + hsic_phy1: usb-phy@f0002800 { compatible = "marvell,mmp3-hsic-phy", "usb-nop-xceiv"; reg = <0xf0002800 0x40>; @@ -231,7 +231,7 @@ status = "disabled"; }; - hsic1: hsic@f0002000 { + hsic1: usb@f0002000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0002000 0x200>; interrupts = ; -- cgit v1.2.3-70-g09d2 From dd95b542b74c774598a4ef2f61cd914c99028ccc Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:53 +0200 Subject: ARM: dts: berlin*: Fix up the SDHCI node names The node name preferred by mmc-controller.yaml binding spec is "mmc": berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab0000: $nodename:0: 'sdhci@ab0000' does not match '^mmc(@.*)?$' berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab0800: $nodename:0: 'sdhci@ab0800' does not match '^mmc(@.*)?$' berlin2-sony-nsz-gs7.dt.yaml: sdhci@ab1000: $nodename:0: 'sdhci@ab1000' does not match '^mmc(@.*)?$' berlin2cd-google-chromecast.dt.yaml: sdhci@ab0000: $nodename:0: 'sdhci@ab0000' does not match '^mmc(@.*)?$' berlin2cd-valve-steamlink.dt.yaml: sdhci@ab0000: $nodename:0: 'sdhci@ab0000' does not match '^mmc(@.*)?$' berlin2q-marvell-dmp.dt.yaml: sdhci@ab0000: $nodename:0: 'sdhci@ab0000' does not match '^mmc(@.*)?$' berlin2q-marvell-dmp.dt.yaml: sdhci@ab0800: $nodename:0: 'sdhci@ab0800' does not match '^mmc(@.*)?$' berlin2q-marvell-dmp.dt.yaml: sdhci@ab1000: $nodename:0: 'sdhci@ab1000' does not match '^mmc(@.*)?$' Signed-off-by: Lubomir Rintel Reviewed-by: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/berlin2.dtsi | 6 +++--- arch/arm/boot/dts/berlin2cd.dtsi | 2 +- arch/arm/boot/dts/berlin2q.dtsi | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index d2f7d984bba5..3ab3cd250da7 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -77,7 +77,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; @@ -86,7 +86,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; @@ -95,7 +95,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index e5c1f4213ff9..7cf3e6302d75 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -62,7 +62,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 99d6872a6dfc..c44a32e873f4 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -122,7 +122,7 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -131,7 +131,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -140,7 +140,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; -- cgit v1.2.3-70-g09d2 From ed365a4a84a016077d4c07796c75971e45edbbb8 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 19 Apr 2020 19:11:54 +0200 Subject: ARM: dts: mmp3: Add the fifth SD HCI There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add it to the device tree. Signed-off-by: Lubomir Rintel Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mmp3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index a4d8d846f81a..ae264af12c28 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -281,6 +281,16 @@ status = "disabled"; }; + mmc5: mmc@d4217000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4217000 0x120>; + clocks = <&soc_clocks MMP3_CLK_SDH4>; + clock-names = "io"; + interrupt-parent = <&hsi1_mux>; + interrupts = <0>; + status = "disabled"; + }; + camera0: camera@d420a000 { compatible = "marvell,mmp2-ccic"; reg = <0xd420a000 0x800>; -- cgit v1.2.3-70-g09d2 From 6e99d3213b10ee18428d6d20715ad6c0e89ead4d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sat, 23 May 2020 11:01:57 +0200 Subject: efi/libstub: Add missing prototype for PE/COFF entry point Fix a missing prototype warning by adding a forward declaration for the PE/COFF entrypoint, and while at it, align the function name between the x86 and ARM versions of the stub. Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/efi-header.S | 2 +- arch/arm64/kernel/efi-entry.S | 2 +- arch/arm64/kernel/efi-header.S | 2 +- drivers/firmware/efi/libstub/efi-stub.c | 3 ++- drivers/firmware/efi/libstub/efistub.h | 3 +++ 5 files changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/efi-header.S b/arch/arm/boot/compressed/efi-header.S index 62286da318e7..c0e7a745103e 100644 --- a/arch/arm/boot/compressed/efi-header.S +++ b/arch/arm/boot/compressed/efi-header.S @@ -60,7 +60,7 @@ optional_header: .long __pecoff_code_size @ SizeOfCode .long __pecoff_data_size @ SizeOfInitializedData .long 0 @ SizeOfUninitializedData - .long efi_entry - start @ AddressOfEntryPoint + .long efi_pe_entry - start @ AddressOfEntryPoint .long start_offset @ BaseOfCode .long __pecoff_data_start - start @ BaseOfData diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S index 1a03618df0df..5664af1e9260 100644 --- a/arch/arm64/kernel/efi-entry.S +++ b/arch/arm64/kernel/efi-entry.S @@ -14,7 +14,7 @@ SYM_CODE_START(efi_enter_kernel) /* - * efi_entry() will have copied the kernel image if necessary and we + * efi_pe_entry() will have copied the kernel image if necessary and we * end up here with device tree address in x1 and the kernel entry * point stored in x0. Save those values in registers which are * callee preserved. diff --git a/arch/arm64/kernel/efi-header.S b/arch/arm64/kernel/efi-header.S index 914999ccaf8a..f2457d4b76a4 100644 --- a/arch/arm64/kernel/efi-header.S +++ b/arch/arm64/kernel/efi-header.S @@ -27,7 +27,7 @@ optional_header: .long __initdata_begin - efi_header_end // SizeOfCode .long __pecoff_data_size // SizeOfInitializedData .long 0 // SizeOfUninitializedData - .long __efistub_efi_entry - _head // AddressOfEntryPoint + .long __efistub_efi_pe_entry - _head // AddressOfEntryPoint .long efi_header_end - _head // BaseOfCode extra_header_fields: diff --git a/drivers/firmware/efi/libstub/efi-stub.c b/drivers/firmware/efi/libstub/efi-stub.c index cc8d6f510a89..9b7634369158 100644 --- a/drivers/firmware/efi/libstub/efi-stub.c +++ b/drivers/firmware/efi/libstub/efi-stub.c @@ -140,7 +140,8 @@ asmlinkage void __noreturn efi_enter_kernel(unsigned long entrypoint, * for both archictectures, with the arch-specific code provided in the * handle_kernel_image() function. */ -efi_status_t efi_entry(efi_handle_t handle, efi_system_table_t *sys_table_arg) +efi_status_t __efiapi efi_pe_entry(efi_handle_t handle, + efi_system_table_t *sys_table_arg) { efi_loaded_image_t *image; efi_status_t status; diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index 1de8dc02529a..03f74608b963 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -40,6 +40,9 @@ extern bool efi_novamap; extern const efi_system_table_t *efi_system_table; +efi_status_t __efiapi efi_pe_entry(efi_handle_t handle, + efi_system_table_t *sys_table_arg); + #ifndef ARCH_HAS_EFISTUB_WRAPPERS #define efi_is_native() (true) -- cgit v1.2.3-70-g09d2 From a5c4c29d24c69b2d589f1bdfc0ad9ba8798b6e13 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 7 May 2020 17:56:51 +0200 Subject: ARM: dts: at91: Remove the USB EP child node The endpoint configuration used to be stored in the device tree, however the configuration depend on the "version" of the controller itself. Then the EP child node are useless and describe as deprecated in the documentation binding: remove all the nodes from the SoC device tree file. Remove also the #address-cells and #size-cells properties that are no longer needed. Signed-off-by: Gregory CLEMENT Signed-off-by: Felipe Balbi --- arch/arm/boot/dts/at91sam9g45.dtsi | 54 ----------------- arch/arm/boot/dts/at91sam9rl.dtsi | 54 ----------------- arch/arm/boot/dts/at91sam9x5.dtsi | 54 ----------------- arch/arm/boot/dts/sama5d2.dtsi | 120 ------------------------------------- arch/arm/boot/dts/sama5d3.dtsi | 107 --------------------------------- arch/arm/boot/dts/sama5d4.dtsi | 120 ------------------------------------- 6 files changed, 509 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index fd179097a4bf..342697f53cf7 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -1195,8 +1195,6 @@ }; usb2: gadget@fff78000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-udc"; reg = <0x00600000 0x80000 0xfff78000 0x400>; @@ -1204,58 +1202,6 @@ clocks = <&udphs_clk>, <&utmi>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; clk32k: sckc@fffffd50 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index ea024e4b6e09..4d70194fd808 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -299,8 +299,6 @@ }; usb0: gadget@fffd4000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9rl-udc"; reg = <0x00600000 0x100000>, <0xfffd4000 0x4000>; @@ -308,58 +306,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; dma0: dma-controller@ffffe600 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 7c2eb93f8cac..948fe99ab6c3 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -867,8 +867,6 @@ }; usb2: gadget@f803c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-udc"; reg = <0x00500000 0x80000 0xf803c000 0x400>; @@ -876,58 +874,6 @@ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "pclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; watchdog: watchdog@fffffe40 { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index ab550d69db91..1ae7a2ea696b 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -113,8 +113,6 @@ }; usb0: gadget@300000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00300000 0x100000 0xfc02c000 0x400>; @@ -122,124 +120,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; }; usb1: ohci@400000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index f11b018e9173..10e4492af234 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1420,8 +1420,6 @@ }; usb0: gadget@500000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00500000 0x100000 0xf8030000 0x4000>; @@ -1429,111 +1427,6 @@ clocks = <&udphs_clk>, <&utmi>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; }; usb1: ohci@600000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index c9c0316b5b0e..b0d79524277e 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -96,8 +96,6 @@ }; usb0: gadget@400000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00400000 0x100000 0xfc02c000 0x4000>; @@ -105,124 +103,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; }; usb1: ohci@500000 { -- cgit v1.2.3-70-g09d2 From 9d3239147d6d44dd6fd3c13338dcc3ce36c442ef Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Thu, 21 May 2020 20:51:37 +0200 Subject: ARM: pxa: remove Compulab pxa2xx boards As these boards have no more users nor testers, and patching them has become a burden, be that because of the PCI part or the MTD NAND support, let's remove them. The cm-x300 will for now remain and represent Compulab boards at its best in the PXA department. Link: https://lore.kernel.org/r/20200521185140.27276-1-robert.jarzmik@free.fr Signed-off-by: Robert Jarzmik Acked-by: Mike Rapoport Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm/configs/cm_x2xx_defconfig | 173 ----- arch/arm/configs/em_x270_defconfig | 178 ----- arch/arm/configs/pxa_defconfig | 2 - arch/arm/mach-pxa/Kconfig | 17 - arch/arm/mach-pxa/Makefile | 5 - arch/arm/mach-pxa/cm-x255.c | 240 ------- arch/arm/mach-pxa/cm-x270.c | 419 ------------ arch/arm/mach-pxa/cm-x2xx-pci.c | 196 ------ arch/arm/mach-pxa/cm-x2xx-pci.h | 14 - arch/arm/mach-pxa/cm-x2xx.c | 538 --------------- arch/arm/mach-pxa/em-x270.c | 1286 ----------------------------------- arch/arm/mach-pxa/include/mach/io.h | 18 - 12 files changed, 3086 deletions(-) delete mode 100644 arch/arm/configs/cm_x2xx_defconfig delete mode 100644 arch/arm/configs/em_x270_defconfig delete mode 100644 arch/arm/mach-pxa/cm-x255.c delete mode 100644 arch/arm/mach-pxa/cm-x270.c delete mode 100644 arch/arm/mach-pxa/cm-x2xx-pci.c delete mode 100644 arch/arm/mach-pxa/cm-x2xx-pci.h delete mode 100644 arch/arm/mach-pxa/cm-x2xx.c delete mode 100644 arch/arm/mach-pxa/em-x270.c delete mode 100644 arch/arm/mach-pxa/include/mach/io.h (limited to 'arch/arm') diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig deleted file mode 100644 index fa997ae2673e..000000000000 --- a/arch/arm/configs/cm_x2xx_defconfig +++ /dev/null @@ -1,173 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_ARMCORE=y -CONFIG_PCI=y -CONFIG_PCCARD=m -CONFIG_YENTA=m -# CONFIG_YENTA_O2 is not set -# CONFIG_YENTA_RICOH is not set -# CONFIG_YENTA_ENE_TUNE is not set -# CONFIG_YENTA_TOSHIBA is not set -CONFIG_PCMCIA_PXA2XX=m -CONFIG_NO_HZ=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=1f03 mem=32M" -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=m -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_BNEP=m -CONFIG_BT_HIDP=m -CONFIG_LIB80211=m -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PXA2XX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_GPIO=m -CONFIG_MTD_NAND_CM_X270=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_ATA=m -# CONFIG_SATA_PMP is not set -CONFIG_PATA_PCMCIA=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=1 -CONFIG_NET_PCI=y -CONFIG_8139TOO=m -# CONFIG_8139TOO_PIO is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_PXA27x=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_UCB1400=m -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_PXA2XX=m -# CONFIG_HWMON is not set -CONFIG_UCB1400_CORE=m -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_FB_PXA_PARAMETERS=y -CONFIG_FB_MBX=m -# CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_PCI is not set -CONFIG_SND_PXA2XX_AC97=m -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=m -CONFIG_MMC_PXA=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_V3020=y -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_VFAT_FS=m -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_CIFS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_FRAME_WARN=0 -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig deleted file mode 100644 index d08f02014755..000000000000 --- a/arch/arm/configs/em_x270_defconfig +++ /dev/null @@ -1,178 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_EM_X270=y -CONFIG_MACH_EXEDA=y -CONFIG_NO_HZ=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=1f03 mem=32M" -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_BNEP=m -CONFIG_BT_HIDP=m -CONFIG_BT_HCIBTUSB=m -CONFIG_LIB80211=m -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PXA2XX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=1 -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_APMPOWER=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_PXA27x=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_DA9034 is not set -CONFIG_TOUCHSCREEN_WM97XX=m -# CONFIG_TOUCHSCREEN_WM9705 is not set -# CONFIG_TOUCHSCREEN_WM9713 is not set -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_PXA2XX=y -CONFIG_POWER_SUPPLY=y -CONFIG_BATTERY_DA9030=y -# CONFIG_HWMON is not set -CONFIG_PMIC_DA903X=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DA903X=y -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_FB_PXA_PARAMETERS=y -CONFIG_FB_MBX=m -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_TDO24M=y -# CONFIG_BACKLIGHT_GENERIC is not set -CONFIG_BACKLIGHT_DA903X=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_SND_PXA2XX_SOC_EM_X270=m -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GYRATION=y -CONFIG_HID_LOGITECH=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=m -CONFIG_MMC_PXA=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_DA903X=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_V3020=y -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_VFAT_FS=m -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_CIFS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_UTF8=m -CONFIG_FRAME_WARN=0 -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index b817c57f05f1..e6559e3350e6 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -38,8 +38,6 @@ CONFIG_MACH_ARCOM_ZEUS=y CONFIG_MACH_BALLOON3=y CONFIG_MACH_CSB726=y CONFIG_CSB726_CSB701=y -CONFIG_MACH_ARMCORE=y -CONFIG_MACH_EM_X270=y CONFIG_MACH_EXEDA=y CONFIG_MACH_CM_X300=y CONFIG_MACH_CAPC7117=y diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index f60bc29aef68..f7520a6cc7d4 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -123,23 +123,6 @@ config CSB726_CSB701 bool "Enable support for CSB701 baseboard" depends on MACH_CSB726 -config MACH_ARMCORE - bool "CompuLab CM-X255/CM-X270 modules" - select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI - select IWMMXT - select HAVE_PCI - select NEED_MACH_IO_H if PCI - select PXA25x - select PXA27x - -config MACH_EM_X270 - bool "CompuLab EM-x270 platform" - select PXA27x - -config MACH_EXEDA - bool "CompuLab eXeda platform" - select PXA27x - config MACH_CM_X300 bool "CompuLab CM-X300 modules" select CPU_PXA300 diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f70728930c4f..177abe584dd5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -40,11 +40,6 @@ obj-$(CONFIG_MACH_ARCOM_ZEUS) += zeus.o obj-$(CONFIG_MACH_BALLOON3) += balloon3.o obj-$(CONFIG_MACH_CSB726) += csb726.o obj-$(CONFIG_CSB726_CSB701) += csb701.o -obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o -ifeq ($(CONFIG_PCI),y) -obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o -endif -obj-$(CONFIG_MACH_EM_X270) += em-x270.o obj-$(CONFIG_MACH_CM_X300) += cm-x300.o obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c deleted file mode 100644 index ea1e85775759..000000000000 --- a/arch/arm/mach-pxa/cm-x255.c +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-pxa/cm-x255.c - * - * Copyright (C) 2007, 2008 CompuLab, Ltd. - * Mike Rapoport - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "pxa25x.h" - -#include "generic.h" - -#define GPIO_NAND_CS (5) -#define GPIO_NAND_ALE (4) -#define GPIO_NAND_CLE (3) -#define GPIO_NAND_RB (10) - -static unsigned long cmx255_pin_config[] = { - /* AC'97 */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - - /* BTUART */ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - GPIO45_BTUART_RTS, - - /* STUART */ - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, - - /* LCD */ - GPIOxx_LCD_TFT_16BPP, - - /* SSP1 */ - GPIO23_SSP1_SCLK, - GPIO24_SSP1_SFRM, - GPIO25_SSP1_TXD, - GPIO26_SSP1_RXD, - - /* SSP2 */ - GPIO81_SSP2_CLK_OUT, - GPIO82_SSP2_FRM_OUT, - GPIO83_SSP2_TXD, - GPIO84_SSP2_RXD, - - /* PC Card */ - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO52_nPCE_1, - GPIO53_nPCE_2, - GPIO54_nPSKTSEL, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - - /* SDRAM and local bus */ - GPIO15_nCS_1, - GPIO78_nCS_2, - GPIO79_nCS_3, - GPIO80_nCS_4, - GPIO33_nCS_5, - GPIO18_RDY, - - /* GPIO */ - GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, - GPIO9_GPIO, /* PC card reset */ - - /* NAND controls */ - GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ - GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */ - GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */ - GPIO10_GPIO, /* NAND Ready/Busy */ - - /* interrupts */ - GPIO22_GPIO, /* DM9000 interrupt */ -}; - -#if defined(CONFIG_SPI_PXA2XX) -static struct pxa2xx_spi_controller pxa_ssp_master_info = { - .num_chipselect = 1, -}; - -static struct spi_board_info spi_board_info[] __initdata = { - [0] = { - .modalias = "rtc-max6902", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static void __init cmx255_init_rtc(void) -{ - pxa2xx_set_spi_info(1, &pxa_ssp_master_info); - spi_register_board_info(ARRAY_AND_SIZE(spi_board_info)); -} -#else -static inline void cmx255_init_rtc(void) {} -#endif - -#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) -static struct mtd_partition cmx255_nor_partitions[] = { - { - .name = "ARMmon", - .size = 0x00030000, - .offset = 0, - .mask_flags = MTD_WRITEABLE /* force read-only */ - } , { - .name = "ARMmon setup block", - .size = 0x00010000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE /* force read-only */ - } , { - .name = "kernel", - .size = 0x00160000, - .offset = MTDPART_OFS_APPEND, - } , { - .name = "ramdisk", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND - } -}; - -static struct physmap_flash_data cmx255_nor_flash_data[] = { - { - .width = 2, /* bankwidth in bytes */ - .parts = cmx255_nor_partitions, - .nr_parts = ARRAY_SIZE(cmx255_nor_partitions) - } -}; - -static struct resource cmx255_nor_resource = { - .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device cmx255_nor = { - .name = "physmap-flash", - .id = -1, - .dev = { - .platform_data = cmx255_nor_flash_data, - }, - .resource = &cmx255_nor_resource, - .num_resources = 1, -}; - -static void __init cmx255_init_nor(void) -{ - platform_device_register(&cmx255_nor); -} -#else -static inline void cmx255_init_nor(void) {} -#endif - -#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE) - -static struct gpiod_lookup_table cmx255_nand_gpiod_table = { - .dev_id = "gpio-nand", - .table = { - GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CS, "nce", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CLE, "cle", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_NAND_ALE, "ale", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_NAND_RB, "rdy", GPIO_ACTIVE_HIGH), - }, -}; - -static struct resource cmx255_nand_resource[] = { - [0] = { - .start = PXA_CS1_PHYS, - .end = PXA_CS1_PHYS + 11, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PXA_CS5_PHYS, - .end = PXA_CS5_PHYS + 3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct mtd_partition cmx255_nand_parts[] = { - [0] = { - .name = "cmx255-nand", - .size = MTDPART_SIZ_FULL, - .offset = 0, - }, -}; - -static struct gpio_nand_platdata cmx255_nand_platdata = { - .parts = cmx255_nand_parts, - .num_parts = ARRAY_SIZE(cmx255_nand_parts), - .chip_delay = 25, -}; - -static struct platform_device cmx255_nand = { - .name = "gpio-nand", - .num_resources = ARRAY_SIZE(cmx255_nand_resource), - .resource = cmx255_nand_resource, - .id = -1, - .dev = { - .platform_data = &cmx255_nand_platdata, - } -}; - -static void __init cmx255_init_nand(void) -{ - gpiod_add_lookup_table(&cmx255_nand_gpiod_table); - platform_device_register(&cmx255_nand); -} -#else -static inline void cmx255_init_nand(void) {} -#endif - -void __init cmx255_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config)); - - cmx255_init_rtc(); - cmx255_init_nor(); - cmx255_init_nand(); -} diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c deleted file mode 100644 index 9baad11314f2..000000000000 --- a/arch/arm/mach-pxa/cm-x270.c +++ /dev/null @@ -1,419 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-pxa/cm-x270.c - * - * Copyright (C) 2007, 2008 CompuLab, Ltd. - * Mike Rapoport - */ - -#include -#include -#include -#include -#include - -#include -#include