From f36c4720fca325579faddc880d4e178e4ccbda88 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Tue, 4 Mar 2014 13:34:43 +0000 Subject: MIPS: Add support for the M5150 processor The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a62b6379b6ae..3e53f1b065d6 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1173,6 +1173,7 @@ static void probe_pcache(void) case CPU_INTERAPTIV: case CPU_P5600: case CPU_PROAPTIV: + case CPU_M5150: if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) alias_74k_erratum(c); if (!(read_c0_config7() & MIPS_CONF7_IAR) && diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ccae9a46e222..be407d5ccc4e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -512,6 +512,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_1074K: case CPU_PROAPTIV: case CPU_P5600: + case CPU_M5150: break; default: -- cgit v1.2.3-70-g09d2