From 3a845b30bc43d7afc5824a0f15ee4a6caba3d86f Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Wed, 16 Dec 2020 21:08:51 +0800 Subject: mips: kernel: convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cevt-txx9.c | 2 +- arch/mips/kernel/vpe-mt.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 5709469c21ff..d761ead2e7fe 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -193,7 +193,7 @@ void __init txx9_clockevent_init(unsigned long baseaddr, int irq, cd->min_delta_ns = clockevent_delta2ns(0xf, cd); cd->min_delta_ticks = 0xf; cd->irq = irq; - cd->cpumask = cpumask_of(0), + cd->cpumask = cpumask_of(0); clockevents_register_device(cd); if (request_irq(irq, txx9tmr_interrupt, IRQF_PERCPU | IRQF_TIMER, "txx9tmr", &txx9_clock_event_device)) diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c index 2e003b11a098..bad6b0891b2b 100644 --- a/arch/mips/kernel/vpe-mt.c +++ b/arch/mips/kernel/vpe-mt.c @@ -365,8 +365,8 @@ int __init vpe_module_init(void) } device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, + vpe_device.class = &vpe_class; + vpe_device.parent = NULL; dev_set_name(&vpe_device, "vpe1"); vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); err = device_add(&vpe_device); -- cgit v1.2.3-70-g09d2 From a2d029b16cd8db2fd35d1c394889a38b3e73ca94 Mon Sep 17 00:00:00 2001 From: Zheng Yongjun Date: Wed, 16 Dec 2020 21:10:04 +0800 Subject: mips: pci: convert comma to semicolon Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vpe-cmp.c | 4 ++-- arch/mips/pci/pci-ar2315.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c index 9268ebc0f61e..e673603e11e5 100644 --- a/arch/mips/kernel/vpe-cmp.c +++ b/arch/mips/kernel/vpe-cmp.c @@ -117,8 +117,8 @@ int __init vpe_module_init(void) } device_initialize(&vpe_device); - vpe_device.class = &vpe_class, - vpe_device.parent = NULL, + vpe_device.class = &vpe_class; + vpe_device.parent = NULL; dev_set_name(&vpe_device, "vpe_sp"); vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); err = device_add(&vpe_device); diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c index 0b15730cef88..f741b8c528e4 100644 --- a/arch/mips/pci/pci-ar2315.c +++ b/arch/mips/pci/pci-ar2315.c @@ -483,11 +483,11 @@ static int ar2315_pci_probe(struct platform_device *pdev) apc->io_res.name = "AR2315 IO space"; apc->io_res.start = 0; apc->io_res.end = 0; - apc->io_res.flags = IORESOURCE_IO, + apc->io_res.flags = IORESOURCE_IO; apc->pci_ctrl.pci_ops = &ar2315_pci_ops; - apc->pci_ctrl.mem_resource = &apc->mem_res, - apc->pci_ctrl.io_resource = &apc->io_res, + apc->pci_ctrl.mem_resource = &apc->mem_res; + apc->pci_ctrl.io_resource = &apc->io_res; register_pci_controller(&apc->pci_ctrl); -- cgit v1.2.3-70-g09d2 From dbafd5105cfd9f44960bc6759a788f0290e8fba0 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 15 Dec 2020 13:07:26 +0800 Subject: MIPS: No need to check CPU 0 in cps_cpu_disable() After commit 9cce844abf07 ("MIPS: CPU#0 is not hotpluggable"), c->hotpluggable is 0 for CPU 0 and it will not generate a control file in sysfs for this CPU: [root@linux loongson]# cat /sys/devices/system/cpu/cpu0/online cat: /sys/devices/system/cpu/cpu0/online: No such file or directory [root@linux loongson]# echo 0 > /sys/devices/system/cpu/cpu0/online bash: /sys/devices/system/cpu/cpu0/online: Permission denied So no need to check CPU 0 in cps_cpu_disable(), just remove it. Reported-by: liwei (GF) Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/smp-cps.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 8b027c72b8ef..bcd6a944b839 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -451,9 +451,6 @@ static int cps_cpu_disable(void) unsigned cpu = smp_processor_id(); struct core_boot_config *core_cfg; - if (!cpu) - return -EBUSY; - if (!cps_pm_support_state(CPS_PM_POWER_GATED)) return -EINVAL; -- cgit v1.2.3-70-g09d2 From cf8194e46c1edd2368d19b71476bb77dc7bcb4c0 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 3 Dec 2020 20:32:52 +0800 Subject: MIPS: Loongson64: Give chance to build under !CONFIG_NUMA and !CONFIG_SMP In the current code, we can not build under !CONFIG_NUMA and !CONFIG_SMP on the Loongson64 platform, it seems bad for the users who just want to use pure single core (not nosmp) to debug, so do the following things to give them a chance: (1) Do not select NUMA and SMP for MACH_LOONGSON64 in Kconfig, make NUMA depends on SMP, and then just set them in the loongson3_defconfig. (2) Move szmem() from numa.c to init.c and add prom_init_memory() under !CONFIG_NUMA. (3) Clean up szmem() due to the statements of case SYSTEM_RAM_LOW and SYSTEM_RAM_HIGH are the same. (4) Remove the useless declaration of prom_init_memory() and add the declaration of szmem() in loongson.h to avoid build error. Signed-off-by: Youling Tang Signed-off-by: Jinyang He Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 3 +- arch/mips/configs/loongson3_defconfig | 2 + arch/mips/include/asm/mach-loongson64/loongson.h | 2 +- arch/mips/loongson64/init.c | 49 ++++++++++++++++++++++ arch/mips/loongson64/numa.c | 52 +----------------------- 5 files changed, 54 insertions(+), 54 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 0a17bedf4f0d..102236cb5e06 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -491,8 +491,6 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_RELOCATABLE select ZONE_DMA32 - select NUMA - select SMP select COMMON_CLK select USE_OF select BUILTIN_DTB @@ -2758,6 +2756,7 @@ config ARCH_SPARSEMEM_ENABLE config NUMA bool "NUMA Support" depends on SYS_SUPPORTS_NUMA + select SMP help Say Y to compile the kernel to support NUMA (Non-Uniform Memory Access). This option improves performance on systems with more diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index 9c5fadef38cb..0e79f81217bc 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -31,6 +31,8 @@ CONFIG_PERF_EVENTS=y CONFIG_MACH_LOONGSON64=y CONFIG_CPU_HAS_MSA=y CONFIG_NR_CPUS=16 +CONFIG_NUMA=y +CONFIG_SMP=y CONFIG_HZ_256=y CONFIG_KEXEC=y CONFIG_MIPS32_O32=y diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h index fde1b75c45ea..ac1c20e172a2 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson.h +++ b/arch/mips/include/asm/mach-loongson64/loongson.h @@ -23,8 +23,8 @@ extern u32 memsize, highmemsize; extern const struct plat_smp_ops loongson3_smp_ops; /* loongson-specific command line, env and memory initialization */ -extern void __init prom_init_memory(void); extern void __init prom_init_env(void); +extern void __init szmem(unsigned int node); extern void *loongson_fdt_blob; /* irq operation functions */ diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index ed75f7971261..e13f704bef80 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -47,6 +47,51 @@ void virtual_early_config(void) node_id_offset = 44; } +void __init szmem(unsigned int node) +{ + u32 i, mem_type; + static unsigned long num_physpages; + u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size; + + /* Parse memory information and activate */ + for (i = 0; i < loongson_memmap->nr_map; i++) { + node_id = loongson_memmap->map[i].node_id; + if (node_id != node) + continue; + + mem_type = loongson_memmap->map[i].mem_type; + mem_size = loongson_memmap->map[i].mem_size; + mem_start = loongson_memmap->map[i].mem_start; + + switch (mem_type) { + case SYSTEM_RAM_LOW: + case SYSTEM_RAM_HIGH: + start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT; + node_psize = (mem_size << 20) >> PAGE_SHIFT; + end_pfn = start_pfn + node_psize; + num_physpages += node_psize; + pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", + (u32)node_id, mem_type, mem_start, mem_size); + pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n", + start_pfn, end_pfn, num_physpages); + memblock_add_node(PFN_PHYS(start_pfn), PFN_PHYS(node_psize), node); + break; + case SYSTEM_RAM_RESERVED: + pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", + (u32)node_id, mem_type, mem_start, mem_size); + memblock_reserve(((node_id << 44) + mem_start), mem_size << 20); + break; + } + } +} + +#ifndef CONFIG_NUMA +static void __init prom_init_memory(void) +{ + szmem(0); +} +#endif + void __init prom_init(void) { fw_init_cmdline(); @@ -57,7 +102,11 @@ void __init prom_init(void) loongson_sysconf.early_config(); +#ifdef CONFIG_NUMA prom_init_numa_memory(); +#else + prom_init_memory(); +#endif /* Hardcode to CPU UART 0 */ setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE + 0x1e0), 0, 1024); diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c index c6f0c48384f8..a8f57bf01285 100644 --- a/arch/mips/loongson64/numa.c +++ b/arch/mips/loongson64/numa.c @@ -25,6 +25,7 @@ #include #include #include +#include static struct pglist_data prealloc__node_data[MAX_NUMNODES]; unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES]; @@ -81,57 +82,6 @@ static void __init init_topology_matrix(void) } } -static void __init szmem(unsigned int node) -{ - u32 i, mem_type; - static unsigned long num_physpages; - u64 node_id, node_psize, start_pfn, end_pfn, mem_start, mem_size; - - /* Parse memory information and activate */ - for (i = 0; i < loongson_memmap->nr_map; i++) { - node_id = loongson_memmap->map[i].node_id; - if (node_id != node) - continue; - - mem_type = loongson_memmap->map[i].mem_type; - mem_size = loongson_memmap->map[i].mem_size; - mem_start = loongson_memmap->map[i].mem_start; - - switch (mem_type) { - case SYSTEM_RAM_LOW: - start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT; - node_psize = (mem_size << 20) >> PAGE_SHIFT; - end_pfn = start_pfn + node_psize; - num_physpages += node_psize; - pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", - (u32)node_id, mem_type, mem_start, mem_size); - pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n", - start_pfn, end_pfn, num_physpages); - memblock_add_node(PFN_PHYS(start_pfn), - PFN_PHYS(node_psize), node); - break; - case SYSTEM_RAM_HIGH: - start_pfn = ((node_id << 44) + mem_start) >> PAGE_SHIFT; - node_psize = (mem_size << 20) >> PAGE_SHIFT; - end_pfn = start_pfn + node_psize; - num_physpages += node_psize; - pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", - (u32)node_id, mem_type, mem_start, mem_size); - pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n", - start_pfn, end_pfn, num_physpages); - memblock_add_node(PFN_PHYS(start_pfn), - PFN_PHYS(node_psize), node); - break; - case SYSTEM_RAM_RESERVED: - pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", - (u32)node_id, mem_type, mem_start, mem_size); - memblock_reserve(((node_id << 44) + mem_start), - mem_size << 20); - break; - } - } -} - static void __init node_mem_init(unsigned int node) { unsigned long node_addrspace_offset; -- cgit v1.2.3-70-g09d2 From 2ee1503e546f15ea8dbcdbaabf20c80175db46fe Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 30 Dec 2020 11:47:22 +0800 Subject: MIPS: zboot: head.S clean up .cprestore is removed as we don't expect Position Independent zboot ELF. .noreorder is also removed and rest instructions are massaged to improve readability. t9 register is used for indirect jump as MIPS ABI requirement. start label is removed as it already defined in LEAF. Reported-by: Paul Cercueil Signed-off-by: Jiaxun Yang Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/compressed/head.S | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 409cb483a9ff..070b2fbabae4 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -15,10 +15,7 @@ #include #include - .set noreorder - .cprestore LEAF(start) -start: /* Save boot rom start args */ move s0, a0 move s1, a1 @@ -35,21 +32,20 @@ start: PTR_LA a0, (.heap) /* heap address */ PTR_LA sp, (.stack + 8192) /* stack address */ - PTR_LA ra, 2f - PTR_LA k0, decompress_kernel - jr k0 - nop + PTR_LA t9, decompress_kernel + jalr t9 + 2: move a0, s0 move a1, s1 move a2, s2 move a3, s3 - PTR_LI k0, KERNEL_ENTRY - jr k0 - nop + PTR_LI t9, KERNEL_ENTRY + jalr t9 + 3: b 3b - nop + END(start) .comm .heap,BOOT_HEAP_SIZE,4 -- cgit v1.2.3-70-g09d2 From e8bb8f28233d88f4ad89fdf83d54bbc4a8ee40f2 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 30 Dec 2020 11:39:48 +0800 Subject: MIPS: cacheinfo: Add missing VCache Victim Cache is defined by Loongson as per-core unified private Cache. Add this into cacheinfo and make cache levels selfincrement instead of hardcode levels. Signed-off-by: Jiaxun Yang Reviewed-by: Tiezhu Yang Tested-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c index 47312c529410..5f9d0ebac558 100644 --- a/arch/mips/kernel/cacheinfo.c +++ b/arch/mips/kernel/cacheinfo.c @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu) leaves += (c->icache.waysize) ? 2 : 1; + if (c->vcache.waysize) { + levels++; + leaves++; + } + if (c->scache.waysize) { levels++; leaves++; @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu) struct cpuinfo_mips *c = ¤t_cpu_data; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); struct cacheinfo *this_leaf = this_cpu_ci->info_list; + int level = 1; if (c->icache.waysize) { - /* L1 caches are per core */ + /* I/D caches are per core */ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA); + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA); fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST); + level++; } else { - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED); + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; + } + + if (c->vcache.waysize) { + /* Vcache is per core as well */ + fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map); + populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; } if (c->scache.waysize) { - /* L2 cache is per cluster */ + /* Scache is per cluster */ fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map); - populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED); + populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; } - if (c->tcache.waysize) - populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); + if (c->tcache.waysize) { + populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED); + level++; + } this_cpu_ci->cpu_map_populated = true; -- cgit v1.2.3-70-g09d2 From 68324a68fbbe4fd2f2a1dc0ac26059245d0700ab Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 30 Dec 2020 11:39:49 +0800 Subject: MIPS: Loongson64: Set cluster for cores cluster is required for cacheinfo to set shared_cpu_map correctly. Signed-off-by: Jiaxun Yang Reviewed-by: Tiezhu Yang Tested-by: Tiezhu Yang Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index b8c1fc3158fd..aa6613be270f 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -492,6 +492,8 @@ static void __init loongson3_smp_setup(void) __cpu_number_map[i] = num; __cpu_logical_map[num] = i; set_cpu_possible(num, true); + /* Loongson processors are always grouped by 4 */ + cpu_set_cluster(&cpu_data[num], i / 4); num++; } i++; -- cgit v1.2.3-70-g09d2 From c2b49a3237869213ef154da05570365af23408ad Mon Sep 17 00:00:00 2001 From: Jia Qingtong Date: Fri, 1 Jan 2021 17:32:00 +0800 Subject: MIPS: perf: Add support for OCTEON III perf events. According to Hardware Reference Manual, OCTEON III are mostly same as previous OCTEON models. So just enable them and extend supported event code. 0x3e and 0x3f still reserved. Signed-off-by: Jia Qingtong Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/perf_event_mipsxx.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 011eb6bbf81a..22e22c2de1c9 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1919,19 +1919,22 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) { - unsigned int raw_id = config & 0xff; - unsigned int base_id = raw_id & 0x7f; + unsigned int base_id = config & 0x7f; + unsigned int event_max; raw_event.cntr_mask = CNTR_ALL; raw_event.event_id = base_id; - if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { - if (base_id > 0x42) - return ERR_PTR(-EOPNOTSUPP); - } else { - if (base_id > 0x3a) - return ERR_PTR(-EOPNOTSUPP); + if (current_cpu_type() == CPU_CAVIUM_OCTEON3) + event_max = 0x5f; + else if (current_cpu_type() == CPU_CAVIUM_OCTEON2) + event_max = 0x42; + else + event_max = 0x3a; + + if (base_id > event_max) { + return ERR_PTR(-EOPNOTSUPP); } switch (base_id) { @@ -1941,7 +1944,7 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) case 0x1f: case 0x2f: case 0x34: - case 0x3b ... 0x3f: + case 0x3e ... 0x3f: return ERR_PTR(-EOPNOTSUPP); default: break; @@ -2077,6 +2080,7 @@ init_hw_perf_events(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: mipspmu.name = "octeon"; mipspmu.general_event_map = &octeon_event_map; mipspmu.cache_event_map = &octeon_cache_map; -- cgit v1.2.3-70-g09d2 From 0ea33321ffaf20a54e87a9fe087628a1f72a36bc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Thu, 26 Mar 2020 14:17:00 +0800 Subject: MIPS: Kill RM7K & RM9K IRQ Code RM7000 IRQ driver never got really used by any of the platform, and rm9k_cpu_irq_init only exist in a header. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 3 --- arch/mips/include/asm/irq_cpu.h | 2 -- arch/mips/include/asm/mach-generic/irq.h | 6 ----- arch/mips/kernel/Makefile | 1 - arch/mips/kernel/irq-rm7000.c | 45 -------------------------------- 5 files changed, 57 deletions(-) delete mode 100644 arch/mips/kernel/irq-rm7000.c (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 102236cb5e06..d68df1febd25 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1256,9 +1256,6 @@ config SYS_SUPPORTS_HUGETLBFS config MIPS_HUGE_TLB_SUPPORT def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE -config IRQ_CPU_RM7K - bool - config IRQ_MSP_SLP bool diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h index 8d321180b5c2..83d7331ab215 100644 --- a/arch/mips/include/asm/irq_cpu.h +++ b/arch/mips/include/asm/irq_cpu.h @@ -10,8 +10,6 @@ #define _ASM_IRQ_CPU_H extern void mips_cpu_irq_init(void); -extern void rm7k_cpu_irq_init(void); -extern void rm9k_cpu_irq_init(void); #ifdef CONFIG_IRQ_DOMAIN struct device_node; diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h index 079889ced4f3..4249af4bef84 100644 --- a/arch/mips/include/asm/mach-generic/irq.h +++ b/arch/mips/include/asm/mach-generic/irq.h @@ -28,12 +28,6 @@ #endif /* CONFIG_I8259 */ #endif -#ifdef CONFIG_IRQ_CPU_RM7K -#ifndef RM7K_CPU_IRQ_BASE -#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8) -#endif -#endif - #endif /* CONFIG_IRQ_MIPS_CPU */ #endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 2a05b923f579..2303a5868c14 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -71,7 +71,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o -obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o obj-$(CONFIG_MIPS_MSC) += irq-msc01.o obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c deleted file mode 100644 index e1a497f639d7..000000000000 --- a/arch/mips/kernel/irq-rm7000.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2003 Ralf Baechle - * - * Handler for RM7000 extended interrupts. These are a non-standard - * feature so we handle them separately from standard interrupts. - */ -#include -#include -#include -#include - -#include -#include - -static inline void unmask_rm7k_irq(struct irq_data *d) -{ - set_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE)); -} - -static inline void mask_rm7k_irq(struct irq_data *d) -{ - clear_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE)); -} - -static struct irq_chip rm7k_irq_controller = { - .name = "RM7000", - .irq_ack = mask_rm7k_irq, - .irq_mask = mask_rm7k_irq, - .irq_mask_ack = mask_rm7k_irq, - .irq_unmask = unmask_rm7k_irq, - .irq_eoi = unmask_rm7k_irq -}; - -void __init rm7k_cpu_irq_init(void) -{ - int base = RM7K_CPU_IRQ_BASE; - int i; - - clear_c0_intcontrol(0x00000f00); /* Mask all */ - - for (i = base; i < base + 4; i++) - irq_set_chip_and_handler(i, &rm7k_irq_controller, - handle_percpu_irq); -} -- cgit v1.2.3-70-g09d2 From ecd3e709747b5f715de752d796b2f758534c10aa Mon Sep 17 00:00:00 2001 From: siyanteng Date: Tue, 22 Dec 2020 16:37:00 +0800 Subject: MIPS: loongson64: smp.c: Fix block comment coding style This patch fixes: "WARNING: Block comments use a trailing */ on a separate line" by checkpatch.pl Signed-off-by: siyanteng Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index aa6613be270f..6acde65f601b 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -483,7 +483,8 @@ static void __init loongson3_smp_setup(void) init_cpu_possible(cpu_none_mask); /* For unified kernel, NR_CPUS is the maximum possible value, - * loongson_sysconf.nr_cpus is the really present value */ + * loongson_sysconf.nr_cpus is the really present value + */ while (i < loongson_sysconf.nr_cpus) { if (loongson_sysconf.reserved_cpus_mask & (1< Date: Tue, 5 Jan 2021 13:18:27 -0700 Subject: MIPS: Use address-of operator on section symbols When building xway_defconfig with clang: arch/mips/lantiq/prom.c:82:23: error: array comparison always evaluates to true [-Werror,-Wtautological-compare] else if (__dtb_start != __dtb_end) ^ 1 error generated. These are not true arrays, they are linker defined symbols, which are just addresses. Using the address of operator silences the warning and does not change the resulting assembly with either clang/ld.lld or gcc/ld (tested with diff + objdump -Dr). Do the same thing across the entire MIPS subsystem to ensure there are no more warnings around this type of comparison. Link: https://github.com/ClangBuiltLinux/linux/issues/1232 Signed-off-by: Nathan Chancellor Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- arch/mips/bmips/setup.c | 2 +- arch/mips/lantiq/prom.c | 2 +- arch/mips/pic32/pic32mzda/init.c | 2 +- arch/mips/ralink/of.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 19308df5f577..1b06b25aea87 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -167,7 +167,7 @@ void __init plat_mem_setup(void) dtb = phys_to_virt(fw_arg2); else if (fw_passed_dtb) /* UHI interface or appended dtb */ dtb = (void *)fw_passed_dtb; - else if (__dtb_start != __dtb_end) + else if (&__dtb_start != &__dtb_end) dtb = (void *)__dtb_start; else panic("no dtb found"); diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 51a218f04fe0..3f568f5aae2d 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -79,7 +79,7 @@ void __init plat_mem_setup(void) if (fw_passed_dtb) /* UHI interface */ dtb = (void *)fw_passed_dtb; - else if (__dtb_start != __dtb_end) + else if (&__dtb_start != &__dtb_end) dtb = (void *)__dtb_start; else panic("no dtb found"); diff --git a/arch/mips/pic32/pic32mzda/init.c b/arch/mips/pic32/pic32mzda/init.c index 50f376f058f4..f232c77ff526 100644 --- a/arch/mips/pic32/pic32mzda/init.c +++ b/arch/mips/pic32/pic32mzda/init.c @@ -28,7 +28,7 @@ static ulong get_fdtaddr(void) if (fw_passed_dtb && !fw_arg2 && !fw_arg3) return (ulong)fw_passed_dtb; - if (__dtb_start < __dtb_end) + if (&__dtb_start < &__dtb_end) ftaddr = (ulong)__dtb_start; return ftaddr; diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index cbae9d23ab7f..2c9af61efc20 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -75,7 +75,7 @@ void __init plat_mem_setup(void) */ if (fw_passed_dtb) dtb = (void *)fw_passed_dtb; - else if (__dtb_start != __dtb_end) + else if (&__dtb_start != &__dtb_end) dtb = (void *)__dtb_start; __dt_setup_arch(dtb); -- cgit v1.2.3-70-g09d2 From c58734eee6a2151ba033c0dcb31902c89e310374 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 5 Jan 2021 13:34:56 -0700 Subject: MIPS: c-r4k: Fix section mismatch for loongson2_sc_init When building with clang, the following section mismatch warning occurs: WARNING: modpost: vmlinux.o(.text+0x24490): Section mismatch in reference from the function r4k_cache_init() to the function .init.text:loongson2_sc_init() This should have been fixed with commit ad4fddef5f23 ("mips: fix Section mismatch in reference") but it was missed. Remove the improper __init annotation like that commit did. Fixes: 078a55fc824c ("MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code") Link: https://github.com/ClangBuiltLinux/linux/issues/787 Signed-off-by: Nathan Chancellor Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-r4k.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4f976d687ab0..f67297b3175f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1593,7 +1593,7 @@ static int probe_scache(void) return 1; } -static void __init loongson2_sc_init(void) +static void loongson2_sc_init(void) { struct cpuinfo_mips *c = ¤t_cpu_data; -- cgit v1.2.3-70-g09d2 From a6e83acee2dd377959ec4bdeaa463da45ba0f811 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 5 Jan 2021 22:36:31 +0100 Subject: MIPS: Remove empty prom_free_prom_memory functions Most of the prom_free_prom_memory functions are empty. With a new weak prom_free_prom_memory() we can remove all of them. Signed-off-by: Thomas Bogendoerfer Acked-by: Florian Fainelli --- arch/mips/alchemy/common/prom.c | 4 ---- arch/mips/ar7/memory.c | 5 ----- arch/mips/ath25/prom.c | 4 ---- arch/mips/ath79/prom.c | 5 ----- arch/mips/bcm47xx/prom.c | 4 ---- arch/mips/bcm63xx/prom.c | 4 ---- arch/mips/bmips/setup.c | 4 ---- arch/mips/cobalt/setup.c | 5 ----- arch/mips/fw/arc/memory.c | 2 +- arch/mips/fw/sni/sniprom.c | 4 ---- arch/mips/generic/init.c | 4 ---- arch/mips/lantiq/prom.c | 4 ---- arch/mips/loongson2ef/common/init.c | 4 ---- arch/mips/loongson32/common/prom.c | 4 ---- arch/mips/loongson64/init.c | 4 ---- arch/mips/mm/init.c | 5 +++++ arch/mips/mti-malta/malta-memory.c | 4 ---- arch/mips/netlogic/xlp/setup.c | 5 ----- arch/mips/netlogic/xlr/setup.c | 5 ----- arch/mips/pic32/pic32mzda/init.c | 4 ---- arch/mips/pistachio/init.c | 4 ---- arch/mips/ralink/prom.c | 4 ---- arch/mips/rb532/prom.c | 5 ----- arch/mips/sgi-ip27/ip27-memory.c | 5 ----- arch/mips/sgi-ip32/ip32-memory.c | 5 ----- arch/mips/sibyte/common/cfe.c | 5 ----- arch/mips/txx9/generic/setup.c | 4 ---- arch/mips/vr41xx/common/init.c | 4 ---- 28 files changed, 6 insertions(+), 114 deletions(-) (limited to 'arch') diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index d910c0a64de9..b13d8adf3be4 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -143,7 +143,3 @@ int __init prom_get_ethernet_addr(char *ethernet_addr) return 0; } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c index 787716c5e946..ce8024c1a54e 100644 --- a/arch/mips/ar7/memory.c +++ b/arch/mips/ar7/memory.c @@ -49,8 +49,3 @@ void __init prom_meminit(void) pages = memsize() >> PAGE_SHIFT; memblock_add(PHYS_OFFSET, pages << PAGE_SHIFT); } - -void __init prom_free_prom_memory(void) -{ - /* Nothing to free */ -} diff --git a/arch/mips/ath25/prom.c b/arch/mips/ath25/prom.c index edf82be8870d..4466e14feaa4 100644 --- a/arch/mips/ath25/prom.c +++ b/arch/mips/ath25/prom.c @@ -20,7 +20,3 @@ void __init prom_init(void) { } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c index 25724b4e97fd..cc6dc5600677 100644 --- a/arch/mips/ath79/prom.c +++ b/arch/mips/ath79/prom.c @@ -32,8 +32,3 @@ void __init prom_init(void) } #endif } - -void __init prom_free_prom_memory(void) -{ - /* We do not have to prom memory to free */ -} diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 3e2a8166377f..0a63721d0fbf 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -113,10 +113,6 @@ void __init prom_init(void) setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); } -void __init prom_free_prom_memory(void) -{ -} - #if defined(CONFIG_BCM47XX_BCMA) && defined(CONFIG_HIGHMEM) #define EXTVBASE 0xc0000000 diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index df69eaa453a1..c3a2ea62c5c3 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -94,7 +94,3 @@ void __init prom_init(void) */ } } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 1b06b25aea87..10e31d91ca8f 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -129,10 +129,6 @@ void __init prom_init(void) register_bmips_smp_ops(); } -void __init prom_free_prom_memory(void) -{ -} - const char *get_system_type(void) { return "Generic BMIPS kernel"; diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 46581e686882..2e099d55a564 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -117,8 +117,3 @@ void __init prom_init(void) setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); } - -void __init prom_free_prom_memory(void) -{ - /* Nothing to do! */ -} diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c index 37625ae5e35d..ef5fc1ca1b5d 100644 --- a/arch/mips/fw/arc/memory.c +++ b/arch/mips/fw/arc/memory.c @@ -173,7 +173,7 @@ void __weak __init prom_cleanup(void) { } -void __weak __init prom_free_prom_memory(void) +void __init prom_free_prom_memory(void) { int i; diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c index 8f6730376a42..74975e115950 100644 --- a/arch/mips/fw/sni/sniprom.c +++ b/arch/mips/fw/sni/sniprom.c @@ -87,10 +87,6 @@ void *prom_get_hwconf(void) return (void *)CKSEG1ADDR(hwconf); } -void __init prom_free_prom_memory(void) -{ -} - /* * /proc/cpuinfo system type * diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 66a19337d2ab..68763fcde1d0 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -202,7 +202,3 @@ void __init arch_init_irq(void) irqchip_init(); } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 3f568f5aae2d..363937121617 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -44,10 +44,6 @@ int ltq_soc_type(void) return soc_info.type; } -void __init prom_free_prom_memory(void) -{ -} - static void __init prom_init_cmdline(void) { int argc = fw_arg0; diff --git a/arch/mips/loongson2ef/common/init.c b/arch/mips/loongson2ef/common/init.c index ce3f02f75e2a..088aa56d4ed1 100644 --- a/arch/mips/loongson2ef/common/init.c +++ b/arch/mips/loongson2ef/common/init.c @@ -46,7 +46,3 @@ void __init prom_init(void) prom_init_uart_base(); board_nmi_handler_setup = mips_nmi_setup; } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/loongson32/common/prom.c b/arch/mips/loongson32/common/prom.c index c133b5adf34e..fc580a22748e 100644 --- a/arch/mips/loongson32/common/prom.c +++ b/arch/mips/loongson32/common/prom.c @@ -36,10 +36,6 @@ void __init prom_init(void) setup_8250_early_printk_port((unsigned long)uart_base, 0, 0); } -void __init prom_free_prom_memory(void) -{ -} - void __init plat_mem_setup(void) { memblock_add(0x0, (memsize << 20)); diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index e13f704bef80..87a4569972ae 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -115,10 +115,6 @@ void __init prom_init(void) board_nmi_handler_setup = mips_nmi_setup; } -void __init prom_free_prom_memory(void) -{ -} - static int __init add_legacy_isa_io(struct fwnode_handle *fwnode, resource_size_t hw_start, resource_size_t size) { diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index bc80893e5c0f..5cb73bf74a8b 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -495,6 +495,11 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end) void (*free_init_pages_eva)(void *begin, void *end) = NULL; +void __weak __init prom_free_prom_memory(void) +{ + /* nothing to do */ +} + void __ref free_initmem(void) { prom_free_prom_memory(); diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 7c25a0a2345c..952018812885 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -37,10 +37,6 @@ void __init fw_meminit(void) free_init_pages_eva = eva ? free_init_pages_eva_malta : NULL; } -void __init prom_free_prom_memory(void) -{ -} - phys_addr_t mips_cdmm_phys_base(void) { /* This address is "typically unused" */ diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index 9adc0c1b4ffc..9fbaa1e5b340 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c @@ -130,11 +130,6 @@ const char *get_system_type(void) } } -void __init prom_free_prom_memory(void) -{ - /* Nothing yet */ -} - void xlp_mmu_init(void) { u32 conf4; diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c index 627e88101316..aa83d691df0f 100644 --- a/arch/mips/netlogic/xlr/setup.c +++ b/arch/mips/netlogic/xlr/setup.c @@ -89,11 +89,6 @@ unsigned int nlm_get_cpu_frequency(void) return (unsigned int)nlm_prom_info.cpu_frequency; } -void __init prom_free_prom_memory(void) -{ - /* Nothing yet */ -} - void nlm_percpu_init(int hwcpuid) { if (hwcpuid % 4 == 0) diff --git a/arch/mips/pic32/pic32mzda/init.c b/arch/mips/pic32/pic32mzda/init.c index f232c77ff526..1897aa863573 100644 --- a/arch/mips/pic32/pic32mzda/init.c +++ b/arch/mips/pic32/pic32mzda/init.c @@ -91,10 +91,6 @@ void __init prom_init(void) pic32_init_cmdline((int)fw_arg0, (char **)fw_arg1); } -void __init prom_free_prom_memory(void) -{ -} - void __init device_tree_init(void) { if (!initial_boot_params) diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index 558995ed6fe8..ddc0e84c13f5 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -118,10 +118,6 @@ void __init prom_init(void) pr_info("SoC Type: %s\n", get_system_type()); } -void __init prom_free_prom_memory(void) -{ -} - void __init device_tree_init(void) { if (!initial_boot_params) diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c index 02e7878dc427..25728def3503 100644 --- a/arch/mips/ralink/prom.c +++ b/arch/mips/ralink/prom.c @@ -66,7 +66,3 @@ void __init prom_init(void) prom_init_cmdline(); } - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index a9d1f2019dc3..23ad8dd9aa5e 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -34,11 +34,6 @@ static struct resource ddr_reg[] = { } }; -void __init prom_free_prom_memory(void) -{ - /* No prom memory to free */ -} - static inline int match_tag(char *arg, const char *tag) { return strncmp(arg, tag, strlen(tag)) == 0; diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index d411e0a90a5b..87bb6945ec25 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -404,11 +404,6 @@ void __init prom_meminit(void) } } -void __init prom_free_prom_memory(void) -{ - /* We got nothing to free here ... */ -} - extern void setup_zero_pages(void); void __init paging_init(void) diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c index 0f53fed39da6..3fc8d0a0bdfa 100644 --- a/arch/mips/sgi-ip32/ip32-memory.c +++ b/arch/mips/sgi-ip32/ip32-memory.c @@ -40,8 +40,3 @@ void __init prom_meminit(void) memblock_add(base, size); } } - - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c index 89f7fca45152..a3323f8dcc1b 100644 --- a/arch/mips/sibyte/common/cfe.c +++ b/arch/mips/sibyte/common/cfe.c @@ -316,11 +316,6 @@ void __init prom_init(void) #endif } -void __init prom_free_prom_memory(void) -{ - /* Not sure what I'm supposed to do here. Nothing, I think */ -} - void prom_putchar(char c) { int ret; diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index 6d0fd0e055b4..42ba1e97dff0 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -340,10 +340,6 @@ void __init prom_init(void) txx9_board_vec->prom_init(); } -void __init prom_free_prom_memory(void) -{ -} - const char *get_system_type(void) { return txx9_system_type; diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index ca53ac3060ef..628dddf79a05 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -58,7 +58,3 @@ void __init prom_init(void) strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); } } - -void __init prom_free_prom_memory(void) -{ -} -- cgit v1.2.3-70-g09d2 From fdd85e04df3fdd55bb7f32786890fdfb200c40f0 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Wed, 6 Jan 2021 08:47:39 +0800 Subject: MIPS: zboot: Avoid endless loop in clear BSS. Commit 2ee1503e546f ("MIPS: zboot: head.S clean up"). After .noreorder removed, clear BSS fall into endless loop. The bne instruction will add nop to the delay slot at compile time. So a0 register will not increment by 4. Fix it and clear BSS from _edata to (_end - 1). Signed-off-by: Jinyang He Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/compressed/head.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 070b2fbabae4..5795d0af1e1b 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -26,8 +26,8 @@ PTR_LA a0, _edata PTR_LA a2, _end 1: sw zero, 0(a0) + addiu a0, a0, 4 bne a2, a0, 1b - addiu a0, a0, 4 PTR_LA a0, (.heap) /* heap address */ PTR_LA sp, (.stack + 8192) /* stack address */ -- cgit v1.2.3-70-g09d2 From 3b31bb6bb5495f4f38e4d106f95df8be12463f48 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Thu, 7 Jan 2021 11:06:45 +0800 Subject: MIPS: init: move externs to header file This commit fixes the following checkpatch warnings: WARNING: externs should be avoided in .c files This is a warning for placing declarations in a ".c" file. This fix removes the declaration in ".c" and adds it to the common header file. Signed-off-by: Yanteng Si Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/traps.h | 1 + arch/mips/loongson2ef/common/init.c | 1 - arch/mips/loongson64/init.c | 1 - arch/mips/mti-malta/malta-init.c | 1 - arch/mips/pistachio/init.c | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 6a0864bb604d..6aa8f126a43d 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,6 +24,7 @@ extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); +extern char except_vec_nmi[]; #define nmi_notifier(fn, pri) \ ({ \ diff --git a/arch/mips/loongson2ef/common/init.c b/arch/mips/loongson2ef/common/init.c index 088aa56d4ed1..7797359359e4 100644 --- a/arch/mips/loongson2ef/common/init.c +++ b/arch/mips/loongson2ef/common/init.c @@ -19,7 +19,6 @@ unsigned long __maybe_unused _loongson_addrwincfg_base; static void __init mips_nmi_setup(void) { void *base; - extern char except_vec_nmi[]; base = (void *)(CAC_BASE + 0x380); memcpy(base, except_vec_nmi, 0x80); diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index 87a4569972ae..cfa788bca871 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -25,7 +25,6 @@ u32 node_id_offset; static void __init mips_nmi_setup(void) { void *base; - extern char except_vec_nmi[]; base = (void *)(CAC_BASE + 0x380); memcpy(base, except_vec_nmi, 0x80); diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 893af377aacc..b03cac5fdc02 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -90,7 +90,6 @@ static void __init console_config(void) static void __init mips_nmi_setup(void) { void *base; - extern char except_vec_nmi[]; base = cpu_has_veic ? (void *)(CAC_BASE + 0xa80) : diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index ddc0e84c13f5..8e83262e9da8 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -83,7 +83,6 @@ phys_addr_t mips_cdmm_phys_base(void) static void __init mips_nmi_setup(void) { void *base; - extern char except_vec_nmi[]; base = cpu_has_veic ? (void *)(CAC_BASE + 0xa80) : -- cgit v1.2.3-70-g09d2 From c6f2a9e17b9bef7677caddb1626c2402f3e9d2bd Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 5 Jan 2021 13:15:48 -0700 Subject: MIPS: lantiq: Explicitly compare LTQ_EBU_PCC_ISTAT against 0 When building xway_defconfig with clang: arch/mips/lantiq/irq.c:305:48: error: use of logical '&&' with constant operand [-Werror,-Wconstant-logical-operand] if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ^ ~~~~~~~~~~~~~~~~~ arch/mips/lantiq/irq.c:305:48: note: use '&' for a bitwise operation if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ^~ & arch/mips/lantiq/irq.c:305:48: note: remove constant to silence this warning if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) ~^~~~~~~~~~~~~~~~~~~~ 1 error generated. Explicitly compare the constant LTQ_EBU_PCC_ISTAT against 0 to fix the warning. Additionally, remove the unnecessary parentheses as this is a simple conditional statement and shorthand '== 0' to '!'. Fixes: 3645da0276ae ("OF: MIPS: lantiq: implement irq_domain support") Link: https://github.com/ClangBuiltLinux/linux/issues/807 Reported-by: Dmitry Golovin Signed-off-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index df8eed3875f6..43c2f271e6ab 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -302,7 +302,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc) generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq)); /* if this is a EBU irq, we need to ack it or get a deadlock */ - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) + if (irq == LTQ_ICU_EBU_IRQ && !module && LTQ_EBU_PCC_ISTAT != 0) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); } -- cgit v1.2.3-70-g09d2 From ccb21774863add648e709337919d2cfeefe4be49 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Mon, 4 Jan 2021 15:41:48 +0000 Subject: MIPS: UAPI: unexport unistd_nr_{n32,n64,o32}.h unistd_nr_{n32,n64,o32}.h are needed only by include/asm/unistd.h, which is a kernel-side header file, and their contents is generally not for userland use. Move their target destination from include/generated/uapi/asm/ to include/generated/asm/ to disable exporting them as UAPI headers. Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/Kbuild | 4 ++++ arch/mips/include/uapi/asm/Kbuild | 3 --- arch/mips/kernel/syscalls/Makefile | 16 ++++++++-------- 3 files changed, 12 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild index 198b3bafdac9..9040ff0b3a14 100644 --- a/arch/mips/include/asm/Kbuild +++ b/arch/mips/include/asm/Kbuild @@ -4,6 +4,10 @@ generated-y += syscall_table_32_o32.h generated-y += syscall_table_64_n32.h generated-y += syscall_table_64_n64.h generated-y += syscall_table_64_o32.h +generated-y += unistd_nr_n32.h +generated-y += unistd_nr_n64.h +generated-y += unistd_nr_o32.h + generic-y += export.h generic-y += kvm_para.h generic-y += local64.h diff --git a/arch/mips/include/uapi/asm/Kbuild b/arch/mips/include/uapi/asm/Kbuild index 6db08385d3d8..fdb9c5412cd9 100644 --- a/arch/mips/include/uapi/asm/Kbuild +++ b/arch/mips/include/uapi/asm/Kbuild @@ -2,8 +2,5 @@ generated-y += unistd_n32.h generated-y += unistd_n64.h generated-y += unistd_o32.h -generated-y += unistd_nr_n32.h -generated-y += unistd_nr_n64.h -generated-y += unistd_nr_o32.h generic-y += kvm_para.h diff --git a/arch/mips/kernel/syscalls/Makefile b/arch/mips/kernel/syscalls/Makefile index 6efb2f6889a7..a1ce8b7dbcfa 100644 --- a/arch/mips/kernel/syscalls/Makefile +++ b/arch/mips/kernel/syscalls/Makefile @@ -44,17 +44,17 @@ $(uapi)/unistd_o32.h: $(syscallo32) $(syshdr) sysnr_pfx_unistd_nr_n32 := N32 sysnr_offset_unistd_nr_n32 := 6000 -$(uapi)/unistd_nr_n32.h: $(syscalln32) $(sysnr) +$(kapi)/unistd_nr_n32.h: $(syscalln32) $(sysnr) $(call if_changed,sysnr) sysnr_pfx_unistd_nr_n64 := 64 sysnr_offset_unistd_nr_n64 := 5000 -$(uapi)/unistd_nr_n64.h: $(syscalln64) $(sysnr) +$(kapi)/unistd_nr_n64.h: $(syscalln64) $(sysnr) $(call if_changed,sysnr) sysnr_pfx_unistd_nr_o32 := O32 sysnr_offset_unistd_nr_o32 := 4000 -$(uapi)/unistd_nr_o32.h: $(syscallo32) $(sysnr) +$(kapi)/unistd_nr_o32.h: $(syscallo32) $(sysnr) $(call if_changed,sysnr) systbl_abi_syscall_table_32_o32 := 32_o32 @@ -79,14 +79,14 @@ $(kapi)/syscall_table_64_o32.h: $(syscallo32) $(systbl) uapisyshdr-y += unistd_n32.h \ unistd_n64.h \ - unistd_o32.h \ - unistd_nr_n32.h \ - unistd_nr_n64.h \ - unistd_nr_o32.h + unistd_o32.h kapisyshdr-y += syscall_table_32_o32.h \ syscall_table_64_n32.h \ syscall_table_64_n64.h \ - syscall_table_64_o32.h + syscall_table_64_o32.h \ + unistd_nr_n32.h \ + unistd_nr_n64.h \ + unistd_nr_o32.h targets += $(uapisyshdr-y) $(kapisyshdr-y) -- cgit v1.2.3-70-g09d2 From 99b40ced9ef63cef784905248735bd209ed6fe53 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 8 Jan 2021 11:55:26 +0100 Subject: MIPS: bitops: Fix reference to ffz location Unlike most other architectures, MIPS defines ffz() below ffs(). Signed-off-by: Geert Uytterhoeven Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/bitops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index a74769940fbd..1b08f9f38593 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -435,7 +435,7 @@ static inline int fls(unsigned int x) * * This is defined the same way as * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). + * differs in spirit from the below ffz (man ffs). */ static inline int ffs(int word) { -- cgit v1.2.3-70-g09d2 From e91fd6ddb72b2652177c0e015b415fbe2839cf6a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 9 Jan 2021 20:53:51 +0100 Subject: MIPS: lantiq: irq: register the interrupt controllers with irqchip_init Add support for more interrupt controllers by switching from of_irq_init() to irqchip_init() in Lantiq's arch_init_irq(). This requires switching the ICU interrupt controller to use IRQCHIP_DECLARE(), like a real irqchip driver would do. This is needed for future changes when new irqchip drivers are implemented: - a dedicated driver for the EIU interrupt controller - a driver for the MSI PIC (Programmable Interrupt Controller) found on VRX200 and newer SoCs - ..or any other driver which uses IRQCHIP_DECLARE Signed-off-by: Martin Blumenstingl Signed-off-by: Thomas Bogendoerfer --- arch/mips/lantiq/irq.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 43c2f271e6ab..acfbdc01b0ac 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -422,12 +423,9 @@ unsigned int get_c0_compare_int(void) return CP0_LEGACY_COMPARE_IRQ; } -static const struct of_device_id of_irq_ids[] __initconst = { - { .compatible = "lantiq,icu", .data = icu_of_init }, - {}, -}; +IRQCHIP_DECLARE(lantiq_icu, "lantiq,icu", icu_of_init); void __init arch_init_irq(void) { - of_irq_init(of_irq_ids); + irqchip_init(); } -- cgit v1.2.3-70-g09d2 From 8ac7c87acdcac156670f9920c8acbd84308ff4b1 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:08 +0000 Subject: MIPS: vmlinux.lds.S: add missing PAGE_ALIGNED_DATA() section MIPS uses its own declaration of rwdata, and thus it should be kept in sync with the asm-generic one. Currently PAGE_ALIGNED_DATA() is missing from the linker script, which emits the following ld warnings: mips-alpine-linux-musl-ld: warning: orphan section `.data..page_aligned' from `arch/mips/kernel/vdso.o' being placed in section `.data..page_aligned' mips-alpine-linux-musl-ld: warning: orphan section `.data..page_aligned' from `arch/mips/vdso/vdso-image.o' being placed in section `.data..page_aligned' Add the necessary declaration, so the mentioned structures will be placed in vmlinux as intended: ffffffff80630580 D __end_once ffffffff80630580 D __start___dyndbg ffffffff80630580 D __start_once ffffffff80630580 D __stop___dyndbg ffffffff80634000 d mips_vdso_data ffffffff80638000 d vdso_data ffffffff80638580 D _gp ffffffff8063c000 T __init_begin ffffffff8063c000 D _edata ffffffff8063c000 T _sinittext -> ffffffff805a4000 D __end_init_task ffffffff805a4000 D __nosave_begin ffffffff805a4000 D __nosave_end ffffffff805a4000 d mips_vdso_data ffffffff805a8000 d vdso_data ffffffff805ac000 D mmlist_lock ffffffff805ac080 D tasklist_lock Fixes: ebb5e78cc634 ("MIPS: Initial implementation of a VDSO") Signed-off-by: Alexander Lobakin Reviewed-by: Kees Cook Reviewed-by: Nathan Chancellor Cc: stable@vger.kernel.org # 4.4+ Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vmlinux.lds.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 5e97e9d02f98..83e27a181206 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -90,6 +90,7 @@ SECTIONS INIT_TASK_DATA(THREAD_SIZE) NOSAVE_DATA + PAGE_ALIGNED_DATA(PAGE_SIZE) CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) DATA_DATA -- cgit v1.2.3-70-g09d2 From ee90fef1891fd336943f9010330c3d6344f72b3a Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:14 +0000 Subject: MIPS: CPS: don't create redundant .text.cps-vec section A number of symbols from arch/mips/kernel/cps-vec.S is explicitly placed into '.text.cps-vec' section. There are no direct references to this section, so there's no need to form it. '.balign 0x1000' directive will work anyway. Moreover, this section was being placed in vmlinux differently depending on CONFIG_LD_DEAD_CODE_DATA_ELIMINATION: - with this option enabled, '.text.cps-vec' was being caught by '.text.[0-9a-zA-Z_]*' from include/asm-generic/vmlinux.lds.h; - without this option, '.text.cps-vec' was being caught by discouraging '.text.*' from arch/mips/kernel/vmlinux.lds.S. '.text.*' should not be used in vmlinux linker scripts at all as it silently catches any orphan text sections. So, remove both '.section .text.cps-vec' and '.text.*' from cps-vec.S and vmlinux.lds.S respectively. As said, this does not affect related functions alignment: 80116000 T mips_cps_core_entry 80116028 t not_nmi 80116200 T excep_tlbfill 80116280 T excep_xtlbfill 80116300 T excep_cache 80116380 T excep_genex 80116400 T excep_intex 80116480 T excep_ejtag 80116490 T mips_cps_core_init Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cps-vec.S | 1 - arch/mips/kernel/vmlinux.lds.S | 1 - 2 files changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 4db7ff055c9f..975343240148 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -91,7 +91,6 @@ .set pop .endm -.section .text.cps-vec .balign 0x1000 LEAF(mips_cps_core_entry) diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 83e27a181206..ae1d0b4bdd60 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -66,7 +66,6 @@ SECTIONS KPROBES_TEXT IRQENTRY_TEXT SOFTIRQENTRY_TEXT - *(.text.*) *(.fixup) *(.gnu.warning) } :text = 0 -- cgit v1.2.3-70-g09d2 From 5629d41838881335b7b00f13dab17073674793b8 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:22 +0000 Subject: MIPS: vmlinux.lds.S: add ".gnu.attributes" to DISCARDS Discard GNU attributes (MIPS FP type, GNU Hash etc.) at link time as kernel doesn't use it at all. Solves a dozen of the following ld warnings (one per every file): mips-alpine-linux-musl-ld: warning: orphan section `.gnu.attributes' from `arch/mips/kernel/head.o' being placed in section `.gnu.attributes' mips-alpine-linux-musl-ld: warning: orphan section `.gnu.attributes' from `init/main.o' being placed in section `.gnu.attributes' Signed-off-by: Alexander Lobakin Reviewed-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vmlinux.lds.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index ae1d0b4bdd60..09669a8fddec 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -220,6 +220,7 @@ SECTIONS /* ABI crap starts here */ *(.MIPS.abiflags) *(.MIPS.options) + *(.gnu.attributes) *(.options) *(.pdr) *(.reginfo) -- cgit v1.2.3-70-g09d2 From 894ef530012fb5078466efdfb2c15d8b2f1565cd Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:28 +0000 Subject: MIPS: properly stop .eh_frame generation Commit 866b6a89c6d1 ("MIPS: Add DWARF unwinding to assembly") added -fno-asynchronous-unwind-tables to KBUILD_CFLAGS to prevent compiler from emitting .eh_frame symbols. However, as MIPS heavily uses CFI, that's not enough. Use the approach taken for x86 (as it also uses CFI) and explicitly put CFI symbols into the .debug_frame section (except for VDSO). This allows us to drop .eh_frame from DISCARDS as it's no longer being generated. Fixes: 866b6a89c6d1 ("MIPS: Add DWARF unwinding to assembly") Suggested-by: Kees Cook Signed-off-by: Alexander Lobakin Reviewed-by: Kees Cook Reviewed-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/asm.h | 18 ++++++++++++++++++ arch/mips/kernel/vmlinux.lds.S | 1 - 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 3682d1a0bb80..ea4b62ece336 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -20,10 +20,27 @@ #include #include +#ifndef __VDSO__ +/* + * Emit CFI data in .debug_frame sections, not .eh_frame sections. + * We don't do DWARF unwinding at runtime, so only the offline DWARF + * information is useful to anyone. Note we should change this if we + * ever decide to enable DWARF unwinding at runtime. + */ +#define CFI_SECTIONS .cfi_sections .debug_frame +#else + /* + * For the vDSO, emit both runtime unwind information and debug + * symbols for the .dbg file. + */ +#define CFI_SECTIONS +#endif + /* * LEAF - declare leaf routine */ #define LEAF(symbol) \ + CFI_SECTIONS; \ .globl symbol; \ .align 2; \ .type symbol, @function; \ @@ -36,6 +53,7 @@ symbol: .frame sp, 0, ra; \ * NESTED - declare nested routine entry point */ #define NESTED(symbol, framesize, rpc) \ + CFI_SECTIONS; \ .globl symbol; \ .align 2; \ .type symbol, @function; \ diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 09669a8fddec..10d8f0dcb76b 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -224,6 +224,5 @@ SECTIONS *(.options) *(.pdr) *(.reginfo) - *(.eh_frame) } } -- cgit v1.2.3-70-g09d2 From 008c3cbd5eb8f5efc539cbec9abca9f7e32ea631 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:34 +0000 Subject: MIPS: vmlinux.lds.S: explicitly catch .rel.dyn symbols According to linker warnings, both GCC and LLVM generate '.rel.dyn' symbols: mips-alpine-linux-musl-ld: warning: orphan section `.rel.dyn' from `init/main.o' being placed in section `.rel.dyn' Link-time assertion shows that this section is sometimes empty, sometimes not, depending on machine bitness and the compiler [0]: LD .tmp_vmlinux.kallsyms1 mips64-linux-gnu-ld: Unexpected run-time relocations (.rel) detected! Just use the ARM64 approach and declare it in vmlinux.lds.S closer to __init_end. [0] https://lore.kernel.org/linux-mips/20210109111259.GA4213@alpha.franken.de Reported-by: Thomas Bogendoerfer Signed-off-by: Alexander Lobakin Reviewed-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vmlinux.lds.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 10d8f0dcb76b..70bba1ff08da 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -137,6 +137,11 @@ SECTIONS PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT) #endif + .rel.dyn : ALIGN(8) { + *(.rel) + *(.rel*) + } + #ifdef CONFIG_MIPS_ELF_APPENDED_DTB .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) { *(.appended_dtb) -- cgit v1.2.3-70-g09d2 From 795b3a363b76792058ef2b998bc15806f3451448 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:56:41 +0000 Subject: MIPS: vmlinux.lds.S: explicitly declare .got table LLVM stack generates GOT table when building the kernel: ld.lld: warning: :(.got) is being placed in '.got' According to the debug assertions, it's not zero-sized and thus can't be handled the way it's done for x86. Also use the ARM64 path here and place it at the end of .text section. Reported-by: Nathan Chancellor Signed-off-by: Alexander Lobakin Reviewed-by: Kees Cook Reviewed-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/vmlinux.lds.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 70bba1ff08da..c1c345be04ff 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -68,6 +68,8 @@ SECTIONS SOFTIRQENTRY_TEXT *(.fixup) *(.gnu.warning) + . = ALIGN(16); + *(.got) /* Global offset table */ } :text = 0 _etext = .; /* End of text section */ -- cgit v1.2.3-70-g09d2 From d3a4e0f1b440a3c9f665fff796a9532c686a014a Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sun, 10 Jan 2021 11:57:01 +0000 Subject: MIPS: select ARCH_WANT_LD_ORPHAN_WARN Now, after that all the sections are explicitly described and declared in vmlinux.lds.S, we can enable ld orphan warnings to prevent from missing any new sections in future. Signed-off-by: Alexander Lobakin Reviewed-by: Kees Cook Reviewed-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d68df1febd25..d3e64cc0932b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -18,6 +18,7 @@ config MIPS select ARCH_USE_QUEUED_SPINLOCKS select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_IPC_PARSE_VERSION + select ARCH_WANT_LD_ORPHAN_WARN select BUILDTIME_TABLE_SORT select CLONE_BACKWARDS select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1) -- cgit v1.2.3-70-g09d2 From 97c97c6ab173f9b784ef54d134cdb272a21d23bf Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Thu, 14 Jan 2021 18:30:15 +0000 Subject: MIPS: bitops: fix -Wshadow in asm/bitops.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Solves the following repetitive warning when building with -Wshadow: In file included from ./include/linux/bitops.h:32, from ./include/linux/kernel.h:11, from ./include/linux/skbuff.h:13, from ./include/linux/if_ether.h:19, from ./include/linux/etherdevice.h:20: ./arch/mips/include/asm/bitops.h: In function ‘test_and_set_bit_lock’: ./arch/mips/include/asm/bitops.h:46:16: warning: declaration of ‘orig’ shadows a previous local [-Wshadow] 46 | unsigned long orig, temp; \ | ^~~~ ./arch/mips/include/asm/bitops.h:190:10: note: in expansion of macro ‘__test_bit_op’ 190 | orig = __test_bit_op(*m, "%0", | ^~~~~~~~~~~~~ ./arch/mips/include/asm/bitops.h:185:21: note: shadowed declaration is here 185 | unsigned long res, orig; | ^~~~ ./arch/mips/include/asm/bitops.h: In function ‘test_and_clear_bit’: ./arch/mips/include/asm/bitops.h:46:16: warning: declaration of ‘orig’ shadows a previous local [-Wshadow] 46 | unsigned long orig, temp; \ | ^~~~ ./arch/mips/include/asm/bitops.h:236:9: note: in expansion of macro ‘__test_bit_op’ 236 | res = __test_bit_op(*m, "%1", | ^~~~~~~~~~~~~ ./arch/mips/include/asm/bitops.h:229:21: note: shadowed declaration is here 229 | unsigned long res, orig; | ^~~~ ./arch/mips/include/asm/bitops.h:46:16: warning: declaration of ‘orig’ shadows a previous local [-Wshadow] 46 | unsigned long orig, temp; \ | ^~~~ ./arch/mips/include/asm/bitops.h:241:10: note: in expansion of macro ‘__test_bit_op’ 241 | orig = __test_bit_op(*m, "%0", | ^~~~~~~~~~~~~ ./arch/mips/include/asm/bitops.h:229:21: note: shadowed declaration is here 229 | unsigned long res, orig; | ^~~~ ./arch/mips/include/asm/bitops.h: In function ‘test_and_change_bit’: ./arch/mips/include/asm/bitops.h:46:16: warning: declaration of ‘orig’ shadows a previous local [-Wshadow] 46 | unsigned long orig, temp; \ | ^~~~ ./arch/mips/include/asm/bitops.h:273:10: note: in expansion of macro ‘__test_bit_op’ 273 | orig = __test_bit_op(*m, "%0", | ^~~~~~~~~~~~~ ./arch/mips/include/asm/bitops.h:266:21: note: shadowed declaration is here 266 | unsigned long res, orig; | ^~~~ Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/bitops.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 1b08f9f38593..dc2a6234dd3c 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -26,7 +26,7 @@ #include #define __bit_op(mem, insn, inputs...) do { \ - unsigned long temp; \ + unsigned long __temp; \ \ asm volatile( \ " .set push \n" \ @@ -37,13 +37,13 @@ " " __SC "%0, %1 \n" \ " " __SC_BEQZ "%0, 1b \n" \ " .set pop \n" \ - : "=&r"(temp), "+" GCC_OFF_SMALL_ASM()(mem) \ + : "=&r"(__temp), "+" GCC_OFF_SMALL_ASM()(mem) \ : inputs \ : __LLSC_CLOBBER); \ } while (0) #define __test_bit_op(mem, ll_dst, insn, inputs...) ({ \ - unsigned long orig, temp; \ + unsigned long __orig, __temp; \ \ asm volatile( \ " .set push \n" \ @@ -54,12 +54,12 @@ " " __SC "%1, %2 \n" \ " " __SC_BEQZ "%1, 1b \n" \ " .set pop \n" \ - : "=&r"(orig), "=&r"(temp), \ + : "=&r"(__orig), "=&r"(__temp), \ "+" GCC_OFF_SMALL_ASM()(mem) \ : inputs \ : __LLSC_CLOBBER); \ \ - orig; \ + __orig; \ }) /* -- cgit v1.2.3-70-g09d2 From cabcff9be93b12135a8b123d2990dffb4f019618 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Thu, 14 Jan 2021 18:30:31 +0000 Subject: MIPS: pgtable: fix -Wshadow in asm/pgtable.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Solves the following repetitive warning when building with -Wshadow: In file included from ./include/linux/pgtable.h:6, from ./include/linux/mm.h:33, from ./include/linux/dax.h:6, from ./include/linux/mempolicy.h:11, from kernel/fork.c:34: ./arch/mips/include/asm/mmu_context.h: In function ‘switch_mm’: ./arch/mips/include/asm/pgtable.h:97:16: warning: declaration of ‘flags’ shadows a previous local [-Wshadow] 97 | unsigned long flags; \ | ^~~~~ ./arch/mips/include/asm/mmu_context.h:162:2: note: in expansion of macro ‘htw_stop’ 162 | htw_stop(); | ^~~~~~~~ In file included from kernel/fork.c:102: ./arch/mips/include/asm/mmu_context.h:159:16: note: shadowed declaration is here 159 | unsigned long flags; | ^~~~~ Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pgtable.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 4f9c37616d42..4d3ab682d093 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -94,31 +94,31 @@ extern void paging_init(void); #define htw_stop() \ do { \ - unsigned long flags; \ + unsigned long __flags; \ \ if (cpu_has_htw) { \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if(!raw_current_cpu_data.htw_seq++) { \ write_c0_pwctl(read_c0_pwctl() & \ ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \ back_to_back_c0_hazard(); \ } \ - local_irq_restore(flags); \ + local_irq_restore(__flags); \ } \ } while(0) #define htw_start() \ do { \ - unsigned long flags; \ + unsigned long __flags; \ \ if (cpu_has_htw) { \ - local_irq_save(flags); \ + local_irq_save(__flags); \ if (!--raw_current_cpu_data.htw_seq) { \ write_c0_pwctl(read_c0_pwctl() | \ (1 << MIPS_PWCTL_PWEN_SHIFT)); \ back_to_back_c0_hazard(); \ } \ - local_irq_restore(flags); \ + local_irq_restore(__flags); \ } \ } while(0) -- cgit v1.2.3-70-g09d2 From 8790ccf8daf1a8c53b6cb8ce0c9a109274bd3fa8 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 14 Jan 2021 10:34:16 -0700 Subject: MIPS: Compare __SYNC_loongson3_war against 0 When building with clang when CONFIG_CPU_LOONGSON3_WORKAROUNDS is enabled: In file included from lib/errseq.c:4: In file included from ./include/linux/atomic.h:7: ./arch/mips/include/asm/atomic.h:52:1: warning: converting the result of '<<' to a boolean always evaluates to true [-Wtautological-constant-compare] ATOMIC_OPS(atomic64, s64) ^ ./arch/mips/include/asm/atomic.h:40:9: note: expanded from macro 'ATOMIC_OPS' return cmpxchg(&v->counter, o, n); ^ ./arch/mips/include/asm/cmpxchg.h:194:7: note: expanded from macro 'cmpxchg' if (!__SYNC_loongson3_war) ^ ./arch/mips/include/asm/sync.h:147:34: note: expanded from macro '__SYNC_loongson3_war' # define __SYNC_loongson3_war (1 << 31) ^ While it is not wrong that the result of this shift is always true in a boolean context, it is not a problem here. Regardless, the warning is really noisy so rather than making the shift a boolean implicitly, use it in an equality comparison so the shift is used as an integer value. Fixes: 4d1dbfe6cbec ("MIPS: atomic: Emit Loongson3 sync workarounds within asm") Fixes: a91f2a1dba44 ("MIPS: cmpxchg: Omit redundant barriers for Loongson3") Reported-by: kernel test robot Signed-off-by: Nathan Chancellor Acked-by: Nick Desaulniers Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/atomic.h | 2 +- arch/mips/include/asm/cmpxchg.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index f904084fcb1f..27ad76791539 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -248,7 +248,7 @@ static __inline__ int pfx##_sub_if_positive(type i, pfx##_t * v) \ * bltz that can branch to code outside of the LL/SC loop. As \ * such, we don't need to emit another barrier here. \ */ \ - if (!__SYNC_loongson3_war) \ + if (__SYNC_loongson3_war == 0) \ smp_mb__after_atomic(); \ \ return result; \ diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 5b0b3a6777ea..ed8f3f3c4304 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -99,7 +99,7 @@ unsigned long __xchg(volatile void *ptr, unsigned long x, int size) * contains a completion barrier prior to the LL, so we don't \ * need to emit an extra one here. \ */ \ - if (!__SYNC_loongson3_war) \ + if (__SYNC_loongson3_war == 0) \ smp_mb__before_llsc(); \ \ __res = (__typeof__(*(ptr))) \ @@ -191,7 +191,7 @@ unsigned long __cmpxchg(volatile void *ptr, unsigned long old, * contains a completion barrier prior to the LL, so we don't \ * need to emit an extra one here. \ */ \ - if (!__SYNC_loongson3_war) \ + if (__SYNC_loongson3_war == 0) \ smp_mb__before_llsc(); \ \ __res = cmpxchg_local((ptr), (old), (new)); \ @@ -201,7 +201,7 @@ unsigned long __cmpxchg(volatile void *ptr, unsigned long old, * contains a completion barrier after the SC, so we don't \ * need to emit an extra one here. \ */ \ - if (!__SYNC_loongson3_war) \ + if (__SYNC_loongson3_war == 0) \ smp_llsc_mb(); \ \ __res; \ -- cgit v1.2.3-70-g09d2 From 5373ae67c3aad1ab306cc722b5a80b831eb4d4d1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sat, 9 Jan 2021 20:30:47 +0100 Subject: MIPS: Support binutils configured with --enable-mips-fix-loongson3-llsc=yes From version 2.35, binutils can be configured with --enable-mips-fix-loongson3-llsc=yes, which means it defaults to -mfix-loongson3-llsc. This breaks labels which might then point at the wrong instruction. The workaround to explicitly pass -mno-fix-loongson3-llsc has been added in Linux version 5.1, but is only enabled when building a Loongson 64 kernel. As vendors might use a common toolchain for building Loongson and non-Loongson kernels, just move that workaround to arch/mips/Makefile. At the same time update the comments to reflect the current status. Cc: stable@vger.kernel.org # 5.1+ Cc: YunQiang Su Signed-off-by: Aurelien Jarno Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 19 +++++++++++++++++++ arch/mips/loongson64/Platform | 22 ---------------------- 2 files changed, 19 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index cd4343edeb11..5ffdd67093bc 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -136,6 +136,25 @@ cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ # cflags-y += -fno-stack-check +# binutils from v2.35 when built with --enable-mips-fix-loongson3-llsc=yes, +# supports an -mfix-loongson3-llsc flag which emits a sync prior to each ll +# instruction to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h +# for a description). +# +# We disable this in order to prevent the assembler meddling with the +# instruction that labels refer to, ie. if we label an ll instruction: +# +# 1: ll v0, 0(a0) +# +# ...then with the assembler fix applied the label may actually point at a sync +# instruction inserted by the assembler, and if we were using the label in an +# exception table the table would no longer contain the address of the ll +# instruction. +# +# Avoid this by explicitly disabling that assembler behaviour. +# +cflags-y += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) + # # CPU-dependent compiler/assembler options for optimization. # diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform index ec42c5085905..e2354e128d9a 100644 --- a/arch/mips/loongson64/Platform +++ b/arch/mips/loongson64/Platform @@ -5,28 +5,6 @@ cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap -# -# Some versions of binutils, not currently mainline as of 2019/02/04, support -# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction -# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a -# description). -# -# We disable this in order to prevent the assembler meddling with the -# instruction that labels refer to, ie. if we label an ll instruction: -# -# 1: ll v0, 0(a0) -# -# ...then with the assembler fix applied the label may actually point at a sync -# instruction inserted by the assembler, and if we were using the label in an -# exception table the table would no longer contain the address of the ll -# instruction. -# -# Avoid this by explicitly disabling that assembler behaviour. If upstream -# binutils does not merge support for the flag then we can revisit & remove -# this later - for now it ensures vendor toolchains don't cause problems. -# -cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) - # # binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a # as MIPS64 R2; older versions as just R1. This leaves the possibility open -- cgit v1.2.3-70-g09d2 From a5360958a3cd1d876aae1f504ae014658513e1af Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 12 Dec 2020 00:03:54 +0000 Subject: MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The JZ4760 has the HPTLB as well, but has a XBurst CPU with a D0 CPUID. Disable the HPTLB for all XBurst CPUs with a D0 CPUID. In the case where there is no HPTLB (e.g. for older SoCs), this won't have any side effect. Fixes: b02efeb05699 ("MIPS: Ingenic: Disable abandoned HPTLB function.") Cc: # 5.4 Signed-off-by: Paul Cercueil Reviewed-by: 周琰杰 (Zhou Yanjie) Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cpu-probe.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e6853697a056..31cb9199197c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1830,16 +1830,17 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) */ case PRID_COMP_INGENIC_D0: c->isa_level &= ~MIPS_CPU_ISA_M32R2; - break; + fallthrough; /* * The config0 register in the XBurst CPUs with a processor ID of - * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this - * mode is not compatible with the MIPS standard, it will cause - * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S) - * when starting the init process. After chip reset, the default - * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to - * switch back to VTLB mode to prevent getting stuck. + * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned + * huge page tlb mode, this mode is not compatible with the MIPS + * standard, it will cause tlbmiss and into an infinite loop + * (line 21 in the tlb-funcs.S) when starting the init process. + * After chip reset, the default is HPTLB mode, Write 0xa9000000 + * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent + * getting stuck. */ case PRID_COMP_INGENIC_D1: write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); -- cgit v1.2.3-70-g09d2 From 76d7fff22be3e4185ee5f9da2eecbd8188e76b2c Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Fri, 15 Jan 2021 12:26:22 -0700 Subject: MIPS: VDSO: Use CLANG_FLAGS instead of filtering out '--target=' Commit ee67855ecd9d ("MIPS: vdso: Allow clang's --target flag in VDSO cflags") allowed the '--target=' flag from the main Makefile to filter through to the vDSO. However, it did not bring any of the other clang specific flags for controlling the integrated assembler and the GNU tools locations (--prefix=, --gcc-toolchain=, and -no-integrated-as). Without these, we will get a warning (visible with tinyconfig): arch/mips/vdso/elf.S:14:1: warning: DWARF2 only supports one section per compilation unit .pushsection .note.Linux, "a",@note ; .balign 4 ; .long 2f - 1f ; .long 4484f - 3f ; .long 0 ; 1:.asciz "Linux" ; 2:.balign 4 ; 3: ^ arch/mips/vdso/elf.S:34:2: warning: DWARF2 only supports one section per compilation unit .section .mips_abiflags, "a" ^ All of these flags are bundled up under CLANG_FLAGS in the main Makefile and exported so that they can be added to Makefiles that set their own CFLAGS. Use this value instead of filtering out '--target=' so there is no warning and all of the tools are properly used. Cc: stable@vger.kernel.org Fixes: ee67855ecd9d ("MIPS: vdso: Allow clang's --target flag in VDSO cflags") Link: https://github.com/ClangBuiltLinux/linux/issues/1256 Reported-by: Anders Roxell Signed-off-by: Nathan Chancellor Tested-by: Anders Roxell Signed-off-by: Thomas Bogendoerfer --- arch/mips/vdso/Makefile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/vdso/Makefile b/arch/mips/vdso/Makefile index 5810cc12bc1d..2131d3fd7333 100644 --- a/arch/mips/vdso/Makefile +++ b/arch/mips/vdso/Makefile @@ -16,16 +16,13 @@ ccflags-vdso := \ $(filter -march=%,$(KBUILD_CFLAGS)) \ $(filter -m%-float,$(KBUILD_CFLAGS)) \ $(filter -mno-loongson-%,$(KBUILD_CFLAGS)) \ + $(CLANG_FLAGS) \ -D__VDSO__ ifndef CONFIG_64BIT ccflags-vdso += -DBUILD_VDSO32 endif -ifdef CONFIG_CC_IS_CLANG -ccflags-vdso += $(filter --target=%,$(KBUILD_CFLAGS)) -endif - # # The -fno-jump-tables flag only prevents the compiler from generating # jump tables but does not prevent the compiler from emitting absolute -- cgit v1.2.3-70-g09d2 From 049a68efbf0bb29d012f2d73b91c674ca2d805fe Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sat, 16 Jan 2021 15:02:40 +0000 Subject: MIPS: module: optimize module relocations processing For now, module relocation functions are implemented as an array of handlers of type reloc_handler_t. Convert that array into a single switch-case function to: - remove unused arguments; - change the return type of simple handlers to void; - remove the array and don't use any data at all; - avoid using indirect calls; - allow the compiler to inline and greatly optimize the relocation function[s]. The result on MIPS32 R2 with GCC 10.2 -O2 is: scripts/bloat-o-meter -c arch/mips/kernel/__module.o arch/mips/kernel/module.o add/remove: 1/11 grow/shrink: 1/0 up/down: 876/-1436 (-560) Function old new delta apply_relocate 456 1148 +692 apply_r_mips_pc - 184 +184 apply_r_mips_none 8 - -8 apply_r_mips_32 16 - -16 apply_r_mips_64 76 - -76 apply_r_mips_highest 88 - -88 apply_r_mips_higher 108 - -108 apply_r_mips_26 132 - -132 apply_r_mips_pc26 160 - -160 apply_r_mips_pc21 160 - -160 apply_r_mips_pc16 160 - -160 apply_r_mips_hi16 172 - -172 apply_r_mips_lo16 356 - -356 Total: Before=2608, After=2048, chg -21.47% add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Data old new delta Total: Before=12, After=12, chg +0.00% add/remove: 0/1 grow/shrink: 0/0 up/down: 0/-248 (-248) RO Data old new delta reloc_handlers 248 - -248 Total: Before=248, After=0, chg -100.00% All functions were collapsed into a single one that is called directly by $(srctree)/kernel/module.c. Signed-off-by: Alexander Lobakin Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/module.c | 109 ++++++++++++++++++++++------------------------ 1 file changed, 52 insertions(+), 57 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c index 3c0c3d1260c1..14f46d17500a 100644 --- a/arch/mips/kernel/module.c +++ b/arch/mips/kernel/module.c @@ -40,22 +40,13 @@ void *module_alloc(unsigned long size) } #endif -static int apply_r_mips_none(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) -{ - return 0; -} - -static int apply_r_mips_32(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static void apply_r_mips_32(u32 *location, u32 base, Elf_Addr v) { *location = base + v; - - return 0; } -static int apply_r_mips_26(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_26(struct module *me, u32 *location, u32 base, + Elf_Addr v) { if (v % 4) { pr_err("module %s: dangerous R_MIPS_26 relocation\n", @@ -75,8 +66,8 @@ static int apply_r_mips_26(struct module *me, u32 *location, return 0; } -static int apply_r_mips_hi16(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_hi16(struct module *me, u32 *location, Elf_Addr v, + bool rela) { struct mips_hi16 *n; @@ -217,26 +208,25 @@ static int apply_r_mips_pc(struct module *me, u32 *location, u32 base, return 0; } -static int apply_r_mips_pc16(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_pc16(struct module *me, u32 *location, u32 base, + Elf_Addr v) { return apply_r_mips_pc(me, location, base, v, 16); } -static int apply_r_mips_pc21(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_pc21(struct module *me, u32 *location, u32 base, + Elf_Addr v) { return apply_r_mips_pc(me, location, base, v, 21); } -static int apply_r_mips_pc26(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_pc26(struct module *me, u32 *location, u32 base, + Elf_Addr v) { return apply_r_mips_pc(me, location, base, v, 26); } -static int apply_r_mips_64(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_64(u32 *location, Elf_Addr v, bool rela) { if (WARN_ON(!rela)) return -EINVAL; @@ -246,8 +236,7 @@ static int apply_r_mips_64(struct module *me, u32 *location, return 0; } -static int apply_r_mips_higher(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_higher(u32 *location, Elf_Addr v, bool rela) { if (WARN_ON(!rela)) return -EINVAL; @@ -258,8 +247,7 @@ static int apply_r_mips_higher(struct module *me, u32 *location, return 0; } -static int apply_r_mips_highest(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) +static int apply_r_mips_highest(u32 *location, Elf_Addr v, bool rela) { if (WARN_ON(!rela)) return -EINVAL; @@ -272,12 +260,14 @@ static int apply_r_mips_highest(struct module *me, u32 *location, /** * reloc_handler() - Apply a particular relocation to a module + * @type: type of the relocation to apply * @me: the module to apply the reloc to * @location: the address at which the reloc is to be applied * @base: the existing value at location for REL-style; 0 for RELA-style * @v: the value of the reloc, with addend for RELA-style + * @rela: indication of is this a RELA (true) or REL (false) relocation * - * Each implemented reloc_handler function applies a particular type of + * Each implemented relocation function applies a particular type of * relocation to the module @me. Relocs that may be found in either REL or RELA * variants can be handled by making use of the @base & @v parameters which are * set to values which abstract the difference away from the particular reloc @@ -285,23 +275,40 @@ static int apply_r_mips_highest(struct module *me, u32 *location, * * Return: 0 upon success, else -ERRNO */ -typedef int (*reloc_handler)(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela); - -/* The handlers for known reloc types */ -static reloc_handler reloc_handlers[] = { - [R_MIPS_NONE] = apply_r_mips_none, - [R_MIPS_32] = apply_r_mips_32, - [R_MIPS_26] = apply_r_mips_26, - [R_MIPS_HI16] = apply_r_mips_hi16, - [R_MIPS_LO16] = apply_r_mips_lo16, - [R_MIPS_PC16] = apply_r_mips_pc16, - [R_MIPS_64] = apply_r_mips_64, - [R_MIPS_HIGHER] = apply_r_mips_higher, - [R_MIPS_HIGHEST] = apply_r_mips_highest, - [R_MIPS_PC21_S2] = apply_r_mips_pc21, - [R_MIPS_PC26_S2] = apply_r_mips_pc26, -}; +static int reloc_handler(u32 type, struct module *me, u32 *location, u32 base, + Elf_Addr v, bool rela) +{ + switch (type) { + case R_MIPS_NONE: + break; + case R_MIPS_32: + apply_r_mips_32(location, base, v); + break; + case R_MIPS_26: + return apply_r_mips_26(me, location, base, v); + case R_MIPS_HI16: + return apply_r_mips_hi16(me, location, v, rela); + case R_MIPS_LO16: + return apply_r_mips_lo16(me, location, base, v, rela); + case R_MIPS_PC16: + return apply_r_mips_pc16(me, location, base, v); + case R_MIPS_PC21_S2: + return apply_r_mips_pc21(me, location, base, v); + case R_MIPS_PC26_S2: + return apply_r_mips_pc26(me, location, base, v); + case R_MIPS_64: + return apply_r_mips_64(location, v, rela); + case R_MIPS_HIGHER: + return apply_r_mips_higher(location, v, rela); + case R_MIPS_HIGHEST: + return apply_r_mips_highest(location, v, rela); + default: + pr_err("%s: Unknown relocation type %u\n", me->name, type); + return -EINVAL; + } + + return 0; +} static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relsec, @@ -311,7 +318,6 @@ static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab, Elf_Mips_Rel *rel; Elf_Mips_Rela *rela; } r; - reloc_handler handler; Elf_Sym *sym; u32 *location, base; unsigned int i, type; @@ -343,17 +349,6 @@ static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab, } type = ELF_MIPS_R_TYPE(*r.rel); - if (type < ARRAY_SIZE(reloc_handlers)) - handler = reloc_handlers[type]; - else - handler = NULL; - - if (!handler) { - pr_err("%s: Unknown relocation type %u\n", - me->name, type); - err = -EINVAL; - goto out; - } if (rela) { v = sym->st_value + r.rela->r_addend; @@ -365,7 +360,7 @@ static int __apply_relocate(Elf_Shdr *sechdrs, const char *strtab, r.rel = &r.rel[1]; } - err = handler(me, location, base, v, rela); + err = reloc_handler(type, me, location, base, v, rela); if (err) goto out; } -- cgit v1.2.3-70-g09d2 From d9e84fb1a34efd0ca3f68f481a051f26a952e383 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Sat, 16 Jan 2021 15:02:53 +0000 Subject: MIPS: relocatable: optimize the relocation process For now, vmlinux relocation functions for relocatable kernel are implemented as an array of handlers of a particular type. Convert that array into a single switch-case function to: - remove unused arguments; - change the return type of simple handlers to void; - remove the array and don't use any data at all; - avoid using indirect calls; - allow the compiler to inline and greatly optimize the relocation function[s]; and also mark do_relocations() and show_kernel_relocation() static as they aren't used anywhere else. The result on MIPS32 R2 with GCC 10.2 -O2 is: scripts/bloat-o-meter -c arch/mips/kernel/__relocate.o arch/mips/kernel/relocate.o add/remove: 0/6 grow/shrink: 1/0 up/down: 356/-640 (-284) Function old new delta relocate_kernel 852 1208 +356 apply_r_mips_32_rel 20 - -20 apply_r_mips_hi16_rel 40 - -40 apply_r_mips_64_rel 44 - -44 apply_r_mips_26_rel 144 - -144 show_kernel_relocation 164 - -164 do_relocations 228 - -228 Total: Before=1780, After=1496, chg -15.96% add/remove: 0/1 grow/shrink: 0/0 up/down: 0/-76 (-76) Data old new delta reloc_handlers_rel 76 - -76 Total: Before=92, After=16, chg -82.61% add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) RO Data old new delta Total: Before=0, After=0, chg +0.00% All functions were collapsed into the main one, relocate_kernel(). Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/relocate.c | 54 +++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 47aeb3350a76..c643c816cbe0 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -70,18 +70,14 @@ static void __init sync_icache(void *kbase, unsigned long kernel_length) __sync(); } -static int __init apply_r_mips_64_rel(u32 *loc_orig, u32 *loc_new, long offset) +static void __init apply_r_mips_64_rel(u32 *loc_new, long offset) { *(u64 *)loc_new += offset; - - return 0; } -static int __init apply_r_mips_32_rel(u32 *loc_orig, u32 *loc_new, long offset) +static void __init apply_r_mips_32_rel(u32 *loc_new, long offset) { *loc_new += offset; - - return 0; } static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset) @@ -114,7 +110,8 @@ static int __init apply_r_mips_26_rel(u32 *loc_orig, u32 *loc_new, long offset) } -static int __init apply_r_mips_hi16_rel(u32 *loc_orig, u32 *loc_new, long offset) +static void __init apply_r_mips_hi16_rel(u32 *loc_orig, u32 *loc_new, + long offset) { unsigned long insn = *loc_orig; unsigned long target = (insn & 0xffff) << 16; /* high 16bits of target */ @@ -122,17 +119,33 @@ static int __init apply_r_mips_hi16_rel(u32 *loc_orig, u32 *loc_new, long offset target += offset; *loc_new = (insn & ~0xffff) | ((target >> 16) & 0xffff); - return 0; } -static int (*reloc_handlers_rel[]) (u32 *, u32 *, long) __initdata = { - [R_MIPS_64] = apply_r_mips_64_rel, - [R_MIPS_32] = apply_r_mips_32_rel, - [R_MIPS_26] = apply_r_mips_26_rel, - [R_MIPS_HI16] = apply_r_mips_hi16_rel, -}; +static int __init reloc_handler(u32 type, u32 *loc_orig, u32 *loc_new, + long offset) +{ + switch (type) { + case R_MIPS_64: + apply_r_mips_64_rel(loc_new, offset); + break; + case R_MIPS_32: + apply_r_mips_32_rel(loc_new, offset); + break; + case R_MIPS_26: + return apply_r_mips_26_rel(loc_orig, loc_new, offset); + case R_MIPS_HI16: + apply_r_mips_hi16_rel(loc_orig, loc_new, offset); + break; + default: + pr_err("Unhandled relocation type %d at 0x%pK\n", type, + loc_orig); + return -ENOEXEC; + } -int __init do_relocations(void *kbase_old, void *kbase_new, long offset) + return 0; +} + +static int __init do_relocations(void *kbase_old, void *kbase_new, long offset) { u32 *r; u32 *loc_orig; @@ -149,14 +162,7 @@ int __init do_relocations(void *kbase_old, void *kbase_new, long offset) loc_orig = kbase_old + ((*r & 0x00ffffff) << 2); loc_new = RELOCATED(loc_orig); - if (reloc_handlers_rel[type] == NULL) { - /* Unsupported relocation */ - pr_err("Unhandled relocation type %d at 0x%pK\n", - type, loc_orig); - return -ENOEXEC; - } - - res = reloc_handlers_rel[type](loc_orig, loc_new, offset); + res = reloc_handler(type, loc_orig, loc_new, offset); if (res) return res; } @@ -412,7 +418,7 @@ out: /* * Show relocation information on panic. */ -void show_kernel_relocation(const char *level) +static void show_kernel_relocation(const char *level) { unsigned long offset; -- cgit v1.2.3-70-g09d2 From fe82de91af83a9212b6c704b1ce6cf6d129a108b Mon Sep 17 00:00:00 2001 From: Kevin Hao Date: Tue, 19 Jan 2021 19:15:31 +0800 Subject: Revert "MIPS: Octeon: Remove special handling of CONFIG_MIPS_ELF_APPENDED_DTB=y" This reverts commit d9df9fb901d25b941ab2cfb5b570d91fb2abf7a3. For the OCTEON boards, it need to patch the built-in DTB before using it. Previously it judges if it is a built-in DTB by checking fw_passed_dtb. But after commit 37e5c69ffd41 ("MIPS: head.S: Init fw_passed_dtb to builtin DTB", the fw_passed_dtb is initialized even when using built-in DTB. This causes the OCTEON boards boot broken due to an unpatched built-in DTB is used. Revert the commit d9df9fb901d2 to restore the codes before the fw_passed_dtb is used and then fix this issue. Fixed: 37e5c69ffd41 ("MIPS: head.S: Init fw_passed_dtb to builtin DTB") Cc: stable@vger.kernel.org Suggested-by: Thomas Bogendoerfer Signed-off-by: Kevin Hao Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/setup.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 982826ba0ef7..ce4e2806159b 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -1149,12 +1149,15 @@ void __init device_tree_init(void) bool do_prune; bool fill_mac; - if (fw_passed_dtb) { - fdt = (void *)fw_passed_dtb; +#ifdef CONFIG_MIPS_ELF_APPENDED_DTB + if (!fdt_check_header(&__appended_dtb)) { + fdt = &__appended_dtb; do_prune = false; fill_mac = true; pr_info("Using appended Device Tree.\n"); - } else if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { + } else +#endif + if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { fdt = phys_to_virt(octeon_bootinfo->fdt_addr); if (fdt_check_header(fdt)) panic("Corrupt Device Tree passed to kernel."); -- cgit v1.2.3-70-g09d2 From 01179ca040437d9db0232fc9eea69e6e195ae118 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Mon, 18 Jan 2021 21:20:09 +0800 Subject: MIPS: IRQ: Add prototype for function init_IRQ This commit adds a prototype to fix error at W=1: arch/mips/kernel/irq.c:52:13: error: no previous prototype for 'init_IRQ' [-Werror=missing-prototypes] Signed-off-by: Yanteng Si Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/irq.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index c5d351786416..f021de661c3a 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -20,6 +20,7 @@ #define IRQ_STACK_SIZE THREAD_SIZE #define IRQ_STACK_START (IRQ_STACK_SIZE - 16) +extern void __init init_IRQ(void); extern void *irq_stack[NR_CPUS]; /* -- cgit v1.2.3-70-g09d2 From fceb90bb43ca5c01eff73367f71a76c06f049b41 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Thu, 21 Jan 2021 17:04:16 +0100 Subject: MIPS: mm: abort uaccess retries upon fatal signal When there's a fatal signal pending, MIPS's do_page_fault() implementation returns. The intent is that we'll return to the faulting userspace instruction, delivering the signal on the way. However, if we take a fatal signal during fixing up a uaccess, this results in a return to the faulting kernel instruction, which will be instantly retried, resulting in the same fault being taken forever. As the task never reaches userspace, the signal is not delivered, and the task is left unkillable. While the task is stuck in this state, it can inhibit the forward progress of the system. To avoid this, we must ensure that when a fatal signal is pending, we apply any necessary fixup for a faulting kernel instruction. Thus we will return to an error path, and it is up to that code to make forward progress towards delivering the fatal signal. [ Description taken from commit 746a272e4414 ("ARM: 8692/1: mm: abort uaccess retries upon fatal signal") ] Signed-off-by: Thomas Bogendoerfer Acked-by: Mark Rutland --- arch/mips/mm/fault.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 7c871b14e74a..e7abda9c013f 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -156,8 +156,11 @@ good_area: */ fault = handle_mm_fault(vma, address, flags, regs); - if (fault_signal_pending(fault, regs)) + if (fault_signal_pending(fault, regs)) { + if (!user_mode(regs)) + goto no_context; return; + } if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) -- cgit v1.2.3-70-g09d2 From a2fa4cede9e3662e9e33fcf929b320fb1c73b0e9 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Thu, 21 Jan 2021 09:34:34 +0800 Subject: MIPS: mm: Add prototype for function __update_cache This commit adds a prototype to fix error at W=1: arch/mips/mm/cache.c:129:6: error: no previous prototype for '__update_cache' [-Werror=missing-prototypes] Signed-off-by: Yanteng Si Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pgtable.h | 2 +- arch/mips/mm/cache.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 4d3ab682d093..804889b70965 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -64,6 +64,7 @@ struct vm_area_struct; #define __S111 __pgprot(0) extern unsigned long _page_cachable_default; +extern void __update_cache(unsigned long address, pte_t pte); /* * ZERO_PAGE is a global shared page that is always zero; used @@ -224,7 +225,6 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) { - extern void __update_cache(unsigned long address, pte_t pte); if (!pte_present(pteval)) goto cache_sync_done; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 23b16bfd97b2..27f4228dd24e 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -21,6 +21,7 @@ #include #include #include +#include /* Cache operations. */ void (*flush_cache_all)(void); -- cgit v1.2.3-70-g09d2 From 65ce6197ed403b14f4efc70d509e07ac608a1ac5 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Wed, 13 Jan 2021 17:10:07 +0200 Subject: Revert "MIPS: Remove unused R4300 CPU support" This reverts commit f9065b54d437c4660e3d974ad9ce5188c068cd76. We're adding Nintendo 64 support, so the VR4300 is no longer unused. Signed-off-by: Lauri Kasanen Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 12 ++++++++++++ arch/mips/Makefile | 1 + arch/mips/include/asm/cpu-type.h | 5 +++++ arch/mips/include/asm/cpu.h | 2 +- arch/mips/include/asm/vermagic.h | 2 ++ arch/mips/kernel/cpu-probe.c | 9 +++++++++ arch/mips/kernel/idle.c | 1 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 9 files changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d3e64cc0932b..fc37ec02947e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1660,6 +1660,15 @@ config CPU_VR41XX kernel built with this option will not run on any other type of processor or vice versa. +config CPU_R4300 + bool "R4300" + depends on SYS_HAS_CPU_R4300 + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_HAS_LOAD_STORE_LR + help + MIPS Technologies R4300-series processors. + config CPU_R4X00 bool "R4x00" depends on SYS_HAS_CPU_R4X00 @@ -1994,6 +2003,9 @@ config SYS_HAS_CPU_TX39XX config SYS_HAS_CPU_VR41XX bool +config SYS_HAS_CPU_R4300 + bool + config SYS_HAS_CPU_R4X00 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5ffdd67093bc..18d6afe7c968 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -160,6 +160,7 @@ cflags-y += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # cflags-$(CONFIG_CPU_R3000) += -march=r3000 cflags-$(CONFIG_CPU_TX39XX) += -march=r3900 +cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 3288cef4b168..2be5d7b5de68 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -122,6 +122,11 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_VR4181A: #endif +#ifdef CONFIG_SYS_HAS_CPU_R4300 + case CPU_R4300: + case CPU_R4310: +#endif + #ifdef CONFIG_SYS_HAS_CPU_R4X00 case CPU_R4000PC: case CPU_R4000SC: diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c9222cc2244f..9e6211e6d76b 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -302,7 +302,7 @@ enum cpu_type_enum { /* * R4000 class processors */ - CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, + CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000, CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, diff --git a/arch/mips/include/asm/vermagic.h b/arch/mips/include/asm/vermagic.h index 4d2dae0c7c57..371c1873df0d 100644 --- a/arch/mips/include/asm/vermagic.h +++ b/arch/mips/include/asm/vermagic.h @@ -26,6 +26,8 @@ #define MODULE_PROC_FAMILY "TX39XX " #elif defined CONFIG_CPU_VR41XX #define MODULE_PROC_FAMILY "VR41XX " +#elif defined CONFIG_CPU_R4300 +#define MODULE_PROC_FAMILY "R4300 " #elif defined CONFIG_CPU_R4X00 #define MODULE_PROC_FAMILY "R4X00 " #elif defined CONFIG_CPU_TX49XX diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 31cb9199197c..9a89637b4ecf 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1154,6 +1154,15 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) break; } break; + case PRID_IMP_R4300: + c->cputype = CPU_R4300; + __cpu_name[cpu] = "R4300"; + set_isa(c, MIPS_CPU_ISA_III); + c->fpu_msk31 |= FPU_CSR_CONDX; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; case PRID_IMP_R4600: c->cputype = CPU_R4600; __cpu_name[cpu] = "R4600"; diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 18e69ebf5691..1aca3b4db904 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -151,6 +151,7 @@ void __init check_wait(void) cpu_wait = r39xx_wait; break; case CPU_R4200: +/* case CPU_R4300: */ case CPU_R4600: case CPU_R4640: case CPU_R4650: diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index f67297b3175f..7b2396249779 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1164,6 +1164,7 @@ static void probe_pcache(void) case CPU_R4400PC: case CPU_R4400SC: case CPU_R4400MC: + case CPU_R4300: icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); c->icache.linesz = 16 << ((config & CONF_IB) >> 5); c->icache.ways = 1; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index a7521b8f7658..0fb1db8a8ef7 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -549,6 +549,7 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, tlbw(p); break; + case CPU_R4300: case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: -- cgit v1.2.3-70-g09d2 From baec970aa5ba11099ad7a91773350c91fb2113f0 Mon Sep 17 00:00:00 2001 From: Lauri Kasanen Date: Wed, 13 Jan 2021 17:11:23 +0200 Subject: mips: Add N64 machine type Add support for the Nintendo 64. Signed-off-by: Lauri Kasanen Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 12 +++ arch/mips/include/asm/mach-n64/irq.h | 9 ++ arch/mips/include/asm/mach-n64/kmalloc.h | 8 ++ arch/mips/n64/Makefile | 6 ++ arch/mips/n64/Platform | 7 ++ arch/mips/n64/init.c | 164 +++++++++++++++++++++++++++++++ arch/mips/n64/irq.c | 16 +++ 8 files changed, 223 insertions(+) create mode 100644 arch/mips/include/asm/mach-n64/irq.h create mode 100644 arch/mips/include/asm/mach-n64/kmalloc.h create mode 100644 arch/mips/n64/Makefile create mode 100644 arch/mips/n64/Platform create mode 100644 arch/mips/n64/init.c create mode 100644 arch/mips/n64/irq.c (limited to 'arch') diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5483e38b5dc7..e4f6e49417a9 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -18,6 +18,7 @@ platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ +platform-$(CONFIG_MACH_NINTENDO64) += n64/ platform-$(CONFIG_NLM_COMMON) += netlogic/ platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_MACH_PISTACHIO) += pistachio/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fc37ec02947e..5d6840920c3e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -607,6 +607,18 @@ config MACH_VR41XX select SYS_SUPPORTS_MIPS16 select GPIOLIB +config MACH_NINTENDO64 + bool "Nintendo 64 console" + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_R4300 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_ZBOOT + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select DMA_NONCOHERENT + select IRQ_MIPS_CPU + config RALINK bool "Ralink based machines" select CEVT_R4K diff --git a/arch/mips/include/asm/mach-n64/irq.h b/arch/mips/include/asm/mach-n64/irq.h new file mode 100644 index 000000000000..7e260fcb2a51 --- /dev/null +++ b/arch/mips/include/asm/mach-n64/irq.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_N64_IRQ_H +#define __ASM_MACH_N64_IRQ_H + +#define NR_IRQS 8 + +#include + +#endif /* __ASM_MACH_N64_IRQ_H */ diff --git a/arch/mips/include/asm/mach-n64/kmalloc.h b/arch/mips/include/asm/mach-n64/kmalloc.h new file mode 100644 index 000000000000..e8b8d0b19571 --- /dev/null +++ b/arch/mips/include/asm/mach-n64/kmalloc.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_N64_KMALLOC_H +#define __ASM_MACH_N64_KMALLOC_H + +/* The default of 128 bytes wastes too much, use 32 (the largest cacheline, I) */ +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + +#endif /* __ASM_MACH_N64_KMALLOC_H */ diff --git a/arch/mips/n64/Makefile b/arch/mips/n64/Makefile new file mode 100644 index 000000000000..b64a05ae218e --- /dev/null +++ b/arch/mips/n64/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Nintendo 64 +# + +obj-y := init.o irq.o diff --git a/arch/mips/n64/Platform b/arch/mips/n64/Platform new file mode 100644 index 000000000000..24647831356c --- /dev/null +++ b/arch/mips/n64/Platform @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Nintendo 64 +# + +cflags-$(CONFIG_MACH_NINTENDO64) += -I$(srctree)/arch/mips/include/asm/mach-n64 +load-$(CONFIG_MACH_NINTENDO64) += 0xffffffff80101000 diff --git a/arch/mips/n64/init.c b/arch/mips/n64/init.c new file mode 100644 index 000000000000..dfbd864f4667 --- /dev/null +++ b/arch/mips/n64/init.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nintendo 64 init. + * + * Copyright (C) 2021 Lauri Kasanen + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define IO_MEM_RESOURCE_START 0UL +#define IO_MEM_RESOURCE_END 0x1fffffffUL + +/* + * System-specifc irq names for clarity + */ +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) +#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) +#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) +#define RCP_IRQ MIPS_CPU_IRQ(2) +#define CART_IRQ MIPS_CPU_IRQ(3) +#define PRENMI_IRQ MIPS_CPU_IRQ(4) +#define RDBR_IRQ MIPS_CPU_IRQ(5) +#define RDBW_IRQ MIPS_CPU_IRQ(6) +#define TIMER_IRQ MIPS_CPU_IRQ(7) + +static void __init iomem_resource_init(void) +{ + iomem_resource.start = IO_MEM_RESOURCE_START; + iomem_resource.end = IO_MEM_RESOURCE_END; +} + +const char *get_system_type(void) +{ + return "Nintendo 64"; +} + +void __init prom_init(void) +{ + fw_init_cmdline(); +} + +#define W 320 +#define H 240 +#define REG_BASE ((u32 *) CKSEG1ADDR(0x4400000)) + +static void __init n64rdp_write_reg(const u8 reg, const u32 value) +{ + __raw_writel(value, REG_BASE + reg); +} + +#undef REG_BASE + +static const u32 ntsc_320[] __initconst = { + 0x00013212, 0x00000000, 0x00000140, 0x00000200, + 0x00000000, 0x03e52239, 0x0000020d, 0x00000c15, + 0x0c150c15, 0x006c02ec, 0x002501ff, 0x000e0204, + 0x00000200, 0x00000400 +}; + +#define MI_REG_BASE 0x4300000 +#define NUM_MI_REGS 4 +#define AI_REG_BASE 0x4500000 +#define NUM_AI_REGS 6 +#define PI_REG_BASE 0x4600000 +#define NUM_PI_REGS 5 +#define SI_REG_BASE 0x4800000 +#define NUM_SI_REGS 7 + +static int __init n64_platform_init(void) +{ + static const char simplefb_resname[] = "FB"; + static const struct simplefb_platform_data mode = { + .width = W, + .height = H, + .stride = W * 2, + .format = "r5g5b5a1" + }; + struct resource res[3]; + void *orig; + unsigned long phys; + unsigned i; + + memset(res, 0, sizeof(struct resource) * 3); + res[0].flags = IORESOURCE_MEM; + res[0].start = MI_REG_BASE; + res[0].end = MI_REG_BASE + NUM_MI_REGS * 4 - 1; + + res[1].flags = IORESOURCE_MEM; + res[1].start = AI_REG_BASE; + res[1].end = AI_REG_BASE + NUM_AI_REGS * 4 - 1; + + res[2].flags = IORESOURCE_IRQ; + res[2].start = RCP_IRQ; + res[2].end = RCP_IRQ; + + platform_device_register_simple("n64audio", -1, res, 3); + + memset(&res[0], 0, sizeof(res[0])); + res[0].flags = IORESOURCE_MEM; + res[0].start = PI_REG_BASE; + res[0].end = PI_REG_BASE + NUM_PI_REGS * 4 - 1; + + platform_device_register_simple("n64cart", -1, res, 1); + + memset(&res[0], 0, sizeof(res[0])); + res[0].flags = IORESOURCE_MEM; + res[0].start = SI_REG_BASE; + res[0].end = SI_REG_BASE + NUM_SI_REGS * 4 - 1; + + platform_device_register_simple("n64joy", -1, res, 1); + + /* The framebuffer needs 64-byte alignment */ + orig = kzalloc(W * H * 2 + 63, GFP_DMA | GFP_KERNEL); + if (!orig) + return -ENOMEM; + phys = virt_to_phys(orig); + phys += 63; + phys &= ~63; + + for (i = 0; i < ARRAY_SIZE(ntsc_320); i++) { + if (i == 1) + n64rdp_write_reg(i, phys); + else + n64rdp_write_reg(i, ntsc_320[i]); + } + + /* setup IORESOURCE_MEM as framebuffer memory */ + memset(&res[0], 0, sizeof(res[0])); + res[0].flags = IORESOURCE_MEM; + res[0].name = simplefb_resname; + res[0].start = phys; + res[0].end = phys + W * H * 2 - 1; + + platform_device_register_resndata(NULL, "simple-framebuffer", 0, + &res[0], 1, &mode, sizeof(mode)); + + return 0; +} + +#undef W +#undef H + +arch_initcall(n64_platform_init); + +void __init plat_mem_setup(void) +{ + iomem_resource_init(); + memblock_add(0x0, 8 * 1024 * 1024); /* Bootloader blocks the 4mb config */ +} + +void __init plat_time_init(void) +{ + /* 93.75 MHz cpu, count register runs at half rate */ + mips_hpt_frequency = 93750000 / 2; +} diff --git a/arch/mips/n64/irq.c b/arch/mips/n64/irq.c new file mode 100644 index 000000000000..1861e962db42 --- /dev/null +++ b/arch/mips/n64/irq.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * N64 IRQ + * + * Copyright (C) 2021 Lauri Kasanen + */ +#include +#include +#include + +#include + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); +} -- cgit v1.2.3-70-g09d2 From 919af8b96c89898b83c32a83b34caff0b4e74335 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Fri, 22 Jan 2021 15:53:18 +0800 Subject: MIPS: Make definitions of MIPSInst_FMA_{FUNC,FMTM} consistent with MIPS64 manual The kernel definitions of MIPSInst_FMA_FUNC and MIPSInst_FMA_FFMT are not consistent with MADD.fmt, NMADD.fmt and NMSUB.fmt in the MIPS64 manual [1], the field func is bit 5..3 and fmt is bit 2..0, fix them. Otherwise there exists error when add new instruction simulation. [1] https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06 Reported-by: Ming Wang Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/inst.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 22912f78401c..2f98ced30263 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -65,11 +65,11 @@ #define I_FR_SFT 21 #define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) -#define I_FMA_FUNC_SFT 2 -#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT) +#define I_FMA_FUNC_SFT 3 +#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x00000038) >> I_FMA_FUNC_SFT) #define I_FMA_FFMT_SFT 0 -#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003) +#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007) typedef unsigned int mips_instruction; -- cgit v1.2.3-70-g09d2 From aadfe4b5f17c172e1329db23c7eb4657dd4f44b6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 22 Jan 2021 12:02:50 +0100 Subject: MIPS: jazz: always allow little-endian builds The kernel test robot keeps reporting the same bug when it shows up in new files after random unrelated patches: In file included from arch/mips/include/uapi/asm/byteorder.h:13, from arch/mips/include/asm/bitops.h:20, from include/linux/bitops.h:26, from include/linux/kernel.h:12, from include/linux/clk.h:13, from drivers/base/regmap/regmap-mmio.c:7: include/linux/byteorder/big_endian.h:8:2: warning: #warning inconsistent configuration, needs CONFIG_CPU_BIG_ENDIAN [-Wcpp] 8 | #warning inconsistent configuration, needs CONFIG_CPU_BIG_ENDIAN | ^~~~~~~ drivers/base/regmap/regmap-mmio.c: In function 'regmap_mmio_gen_context': >> drivers/base/regmap/regmap-mmio.c:274:2: error: duplicate case value 274 | case REGMAP_ENDIAN_NATIVE: | ^~~~ drivers/base/regmap/regmap-mmio.c:246:2: note: previously used here 246 | case REGMAP_ENDIAN_NATIVE: The problem is that some randconfig builds end up on the MIPS jazz platform with neither CONFIG_CPU_BIG_ENDIAN nor CONFIG_CPU_LITTLE_ENDIAN because no specific machine is selected. As it turns out, all jazz machines support little-endian kernels, so this can simply be allowed globally. Reported-by: kernel test robot Signed-off-by: Arnd Bergmann Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 + arch/mips/jazz/Kconfig | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5d6840920c3e..32df972feded 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -409,6 +409,7 @@ config MACH_JAZZ select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_100HZ + select SYS_SUPPORTS_LITTLE_ENDIAN help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. diff --git a/arch/mips/jazz/Kconfig b/arch/mips/jazz/Kconfig index 06838f80a5d7..42932ca98db9 100644 --- a/arch/mips/jazz/Kconfig +++ b/arch/mips/jazz/Kconfig @@ -3,7 +3,6 @@ config ACER_PICA_61 bool "Support for Acer PICA 1 chipset" depends on MACH_JAZZ select DMA_NONCOHERENT - select SYS_SUPPORTS_LITTLE_ENDIAN help This is a machine with a R4400 133/150 MHz CPU. To compile a Linux kernel that runs on these, say Y here. For details about Linux on @@ -15,7 +14,6 @@ config MIPS_MAGNUM_4000 depends on MACH_JAZZ select DMA_NONCOHERENT select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN help This is a machine with a R4000 100 MHz CPU. To compile a Linux kernel that runs on these, say Y here. For details about Linux on @@ -26,7 +24,6 @@ config OLIVETTI_M700 bool "Support for Olivetti M700-10" depends on MACH_JAZZ select DMA_NONCOHERENT - select SYS_SUPPORTS_LITTLE_ENDIAN help This is a machine with a R4000 100 MHz CPU. To compile a Linux kernel that runs on these, say Y here. For details about Linux on -- cgit v1.2.3-70-g09d2 From 42b20995fae6318fd2e85ddbbaf7b4f7c3724e68 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 22 Jan 2021 12:02:51 +0100 Subject: MIPS: make kgdb depend on FPU support kgdb fails to build when the FPU support is disabled: arch/mips/kernel/kgdb.c: In function 'dbg_set_reg': arch/mips/kernel/kgdb.c:147:35: error: 'struct thread_struct' has no member named 'fpu' 147 | memcpy((void *)¤t->thread.fpu.fcr31, mem, | ^ arch/mips/kernel/kgdb.c:155:34: error: 'struct thread_struct' has no member named 'fpu' 155 | memcpy((void *)¤t->thread.fpu.fpr[fp_reg], mem, This is only relevant for CONFIG_EXPERT=y, so disallowing it in Kconfig is an easier workaround than fixing it properly. Reported-by: kernel test robot Signed-off-by: Arnd Bergmann Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 32df972feded..62475fc95472 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -43,7 +43,7 @@ config MIPS select HANDLE_DOMAIN_IRQ select HAVE_ARCH_COMPILER_H select HAVE_ARCH_JUMP_LABEL - select HAVE_ARCH_KGDB + select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT select HAVE_ARCH_SECCOMP_FILTER -- cgit v1.2.3-70-g09d2 From fa85d6ac2c2511fa4afc671f0a8f307105ce7604 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Thu, 21 Jan 2021 13:31:35 +0800 Subject: MIPS: process: Remove unnecessary headers inclusion Some headers are not necessary, remove them and sort includes. Signed-off-by: Jinyang He Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 41 ++++++++++++----------------------------- 1 file changed, 12 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index d7e288f3a1e7..0c5bc06d0a6b 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -9,50 +9,33 @@ * Copyright (C) 2004 Thiemo Seufer * Copyright (C) 2013 Imagination Technologies Ltd. */ +#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include -#include #include -#include -#include +#include #include -#include +#include +#include +#include +#include +#include +#include #include #include -#include -#include #include #include #include +#include #include -#include +#include +#include #include +#include #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include #ifdef CONFIG_HOTPLUG_CPU void arch_cpu_idle_dead(void) -- cgit v1.2.3-70-g09d2 From 9308579fef3ddde19da9d45e23bf36d41932417f Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Thu, 21 Jan 2021 13:31:36 +0800 Subject: MIPS: microMIPS: Fix the judgment of mm_jr16_op and mm_jalr_op mm16_r5_format.rt is 5 bits, so directly judge the value if equal or not. mm_jalr_op requires 7th to 16th bits. These 10 which bits generated by shifting u_format.uimmediate by 6 may be affected by sign extension. Thus, take out the 10 bits for comparison. Without this patch, errors may occur, such as these bits are all ones. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 0c5bc06d0a6b..c2f9e182173d 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -294,8 +294,8 @@ static inline int is_jump_ins(union mips_instruction *ip) * microMIPS is kind of more fun... */ if (mm_insn_16bit(ip->word >> 16)) { - if ((ip->mm16_r5_format.opcode == mm_pool16c_op && - (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) + if (ip->mm16_r5_format.opcode == mm_pool16c_op && + ip->mm16_r5_format.rt == mm_jr16_op) return 1; return 0; } @@ -307,7 +307,7 @@ static inline int is_jump_ins(union mips_instruction *ip) if (ip->r_format.opcode != mm_pool32a_op || ip->r_format.func != mm_pool32axf_op) return 0; - return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; + return ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op; #else if (ip->j_format.opcode == j_op) return 1; -- cgit v1.2.3-70-g09d2 From 2d62f64bcc72ba45f73e58199f8e1b8cc5b67489 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Thu, 21 Jan 2021 13:31:37 +0800 Subject: MIPS: Fix get_frame_info() handing of function size [1]: Commit b6c7a324df37b ("MIPS: Fix get_frame_info() handling of microMIPS function size") [2]: Commit 2b424cfc69728 ("MIPS: Remove function size check in get_frame_info()") First patch added a constant to check the number of iterations against. Second patch fixed the situation that info->func_size is zero. However, func_size member became useless after the second commit. Without ip_end, the get frame_size operation may be out of range although KALLSYMS enabled. Thus, check func_size first. Then make ip_end be the sum of ip and a constant (512) if func_size is equal to 0. Otherwise make ip_end be the sum of ip and func_size. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index c2f9e182173d..9bf993f29603 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -373,10 +373,8 @@ static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size) static int get_frame_info(struct mips_frame_info *info) { bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); - union mips_instruction insn, *ip; - const unsigned int max_insns = 128; + union mips_instruction insn, *ip, *ip_end; unsigned int last_insn_size = 0; - unsigned int i; bool saw_jump = false; info->pc_offset = -1; @@ -386,7 +384,9 @@ static int get_frame_info(struct mips_frame_info *info) if (!ip) goto err; - for (i = 0; i < max_insns; i++) { + ip_end = (void *)ip + (info->func_size ? info->func_size : 512); + + while (ip < ip_end) { ip = (void *)ip + last_insn_size; if (is_mmips && mm_insn_16bit(ip->halfword[0])) { -- cgit v1.2.3-70-g09d2 From 50886234e846bbf2cbf14a86c727e5fc309fdf25 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Thu, 21 Jan 2021 13:31:38 +0800 Subject: MIPS: Add is_jr_ra_ins() to end the loop early For those leaf functions, they are likely to have no stack operations. Add is_jr_ra_ins() to determine whether jr ra has been touched before the frame_size is found. Without this patch, the get frame_size operation may be out of range and get the frame_size from the next nested function. There is no POOL32A format in uapi/asm/inst.h, so some bits here use the format of r_format instead. e.g. --------------------------------------------------------------------- | format | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 | -----------------+---------+-------+-------+------------+------------ | pool32a_format | pool32a | rt | rs | jalrc | pool32axf | -----------------+---------+-------+-------+------------+------------ | r_format | opcode | rs | rt | rd:5, re:5 | func | --------------------------------------------------------------------- Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 9bf993f29603..f94f291ee6c6 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -188,6 +188,36 @@ struct mips_frame_info { #define J_TARGET(pc,target) \ (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) +static inline int is_jr_ra_ins(union mips_instruction *ip) +{ +#ifdef CONFIG_CPU_MICROMIPS + /* + * jr16 ra + * jr ra + */ + if (mm_insn_16bit(ip->word >> 16)) { + if (ip->mm16_r5_format.opcode == mm_pool16c_op && + ip->mm16_r5_format.rt == mm_jr16_op && + ip->mm16_r5_format.imm == 31) + return 1; + return 0; + } + + if (ip->r_format.opcode == mm_pool32a_op && + ip->r_format.func == mm_pool32axf_op && + ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op && + ip->r_format.rt == 31) + return 1; + return 0; +#else + if (ip->r_format.opcode == spec_op && + ip->r_format.func == jr_op && + ip->r_format.rs == 31) + return 1; + return 0; +#endif +} + static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) { #ifdef CONFIG_CPU_MICROMIPS @@ -400,7 +430,9 @@ static int get_frame_info(struct mips_frame_info *info) last_insn_size = 4; } - if (!info->frame_size) { + if (is_jr_ra_ins(ip)) { + break; + } else if (!info->frame_size) { is_sp_move_ins(&insn, &info->frame_size); continue; } else if (!saw_jump && is_jump_ins(ip)) { -- cgit v1.2.3-70-g09d2 From 5b2d6d2d602068ae0568f990e850ad80e1f701d3 Mon Sep 17 00:00:00 2001 From: Souptick Joarder Date: Sat, 16 Jan 2021 14:10:00 +0530 Subject: mips: cacheinfo: Remove unnecessary increment of level kernel test robot throws below warning -> arch/mips/kernel/cacheinfo.c:112:3: warning: Variable 'level' is modified but its new value is never used. [unreadVariable] Remove unnecessary increment of level at the end. Reported-by: kernel test robot Signed-off-by: Souptick Joarder Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cacheinfo.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c index 5f9d0ebac558..53d8ea7d36e6 100644 --- a/arch/mips/kernel/cacheinfo.c +++ b/arch/mips/kernel/cacheinfo.c @@ -107,10 +107,8 @@ static int __populate_cache_leaves(unsigned int cpu) level++; } - if (c->tcache.waysize) { + if (c->tcache.waysize) populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED); - level++; - } this_cpu_ci->cpu_map_populated = true; -- cgit v1.2.3-70-g09d2 From 7cf52001ee7b5dbcf0bf81e26ac4dd261b128b70 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 22 Jan 2021 12:44:49 +0100 Subject: MIPS: vpe: Remove vpe_getcwd I couldn't find any user of the dubious vpe_getcwd so far. So remove it and get rid of another set_fs(KERNEL_DS). Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/vpe.h | 3 --- arch/mips/kernel/vpe.c | 33 --------------------------------- 2 files changed, 36 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index 80e70dbd1f64..baa949a744cb 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -26,7 +26,6 @@ #endif #define MAX_VPES 16 -#define VPE_PATH_MAX 256 static inline int aprp_cpu_index(void) { @@ -62,7 +61,6 @@ struct vpe { unsigned long len; char *pbuffer; unsigned long plen; - char cwd[VPE_PATH_MAX]; unsigned long __start; @@ -111,7 +109,6 @@ extern const struct file_operations vpe_fops; int vpe_notify(int index, struct vpe_notifications *notify); void *vpe_get_shared(int index); -char *vpe_getcwd(int index); struct vpe *get_vpe(int minor); struct tc *get_tc(int index); diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index d0d832ab3d3b..13294972707b 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -746,28 +746,12 @@ static int vpe_elfload(struct vpe *v) return 0; } -static int getcwd(char *buff, int size) -{ - mm_segment_t old_fs; - int ret; - - old_fs = get_fs(); - set_fs(KERNEL_DS); - - ret = sys_getcwd(buff, size); - - set_fs(old_fs); - - return ret; -} - /* checks VPE is unused and gets ready to load program */ static int vpe_open(struct inode *inode, struct file *filp) { enum vpe_state state; struct vpe_notifications *notifier; struct vpe *v; - int ret; if (VPE_MODULE_MINOR != iminor(inode)) { /* assume only 1 device at the moment. */ @@ -803,12 +787,6 @@ static int vpe_open(struct inode *inode, struct file *filp) v->plen = P_SIZE; v->load_addr = NULL; v->len = 0; - - v->cwd[0] = 0; - ret = getcwd(v->cwd, VPE_PATH_MAX); - if (ret < 0) - pr_warn("VPE loader: open, getcwd returned %d\n", ret); - v->shared_ptr = NULL; v->__start = 0; @@ -915,17 +893,6 @@ int vpe_notify(int index, struct vpe_notifications *notify) } EXPORT_SYMBOL(vpe_notify); -char *vpe_getcwd(int index) -{ - struct vpe *v = get_vpe(index); - - if (v == NULL) - return NULL; - - return v->cwd; -} -EXPORT_SYMBOL(vpe_getcwd); - module_init(vpe_module_init); module_exit(vpe_module_exit); MODULE_DESCRIPTION("MIPS VPE Loader"); -- cgit v1.2.3-70-g09d2 From 31205f0e0084dbbdc3a25f094e2f673e91619b14 Mon Sep 17 00:00:00 2001 From: Chengyang Fan Date: Mon, 25 Jan 2021 17:48:25 +0800 Subject: MIPS: asm: spram: remove unneeded semicolon Remove a superfluous semicolon after function definition. Signed-off-by: Chengyang Fan Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/spram.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h index 63cb90fd4148..373f2a5d495d 100644 --- a/arch/mips/include/asm/spram.h +++ b/arch/mips/include/asm/spram.h @@ -5,7 +5,7 @@ #if defined(CONFIG_MIPS_SPRAM) extern __init void spram_config(void); #else -static inline void spram_config(void) { }; +static inline void spram_config(void) { } #endif /* CONFIG_MIPS_SPRAM */ #endif /* _MIPS_SPRAM_H */ -- cgit v1.2.3-70-g09d2 From c4cbe3fb1c6f03d2295d15d089c3f6e9ddd94db6 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Wed, 27 Jan 2021 10:38:05 +0800 Subject: MIPS: loongson2ef: remove function __uncached_access() We no longer need the MESA workaround, so remove it. Signed-off-by: Yanteng Si Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson2ef/common/mem.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/mips/loongson2ef/common/mem.c b/arch/mips/loongson2ef/common/mem.c index 057d58bb470e..fceb3ee47eb0 100644 --- a/arch/mips/loongson2ef/common/mem.c +++ b/arch/mips/loongson2ef/common/mem.c @@ -41,14 +41,3 @@ void __init prom_init_memory(void) memblock_add(LOONGSON_HIGHMEM_START, highmemsize << 20); #endif /* !CONFIG_64BIT */ } - -/* override of arch/mips/mm/cache.c: __uncached_access */ -int __uncached_access(struct file *file, unsigned long addr) -{ - if (file->f_flags & O_DSYNC) - return 1; - - return addr >= __pa(high_memory) || - ((addr >= LOONGSON_MMIO_MEM_START) && - (addr < LOONGSON_MMIO_MEM_END)); -} -- cgit v1.2.3-70-g09d2 From e6a52b8f0f810781e031096442a532fdb179a3cc Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Wed, 27 Jan 2021 10:38:06 +0800 Subject: MIPS: mm:remove function __uncached_access() MIPS can now use the default uncached_access like other archs. Signed-off-by: Yanteng Si Acked-by: Greg Kroah-Hartman Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/cache.c | 8 -------- drivers/char/mem.c | 7 ------- 2 files changed, 15 deletions(-) (limited to 'arch') diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 27f4228dd24e..1754498b0717 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -208,11 +208,3 @@ void cpu_cache_init(void) setup_protection_map(); } - -int __weak __uncached_access(struct file *file, unsigned long addr) -{ - if (file->f_flags & O_DSYNC) - return 1; - - return addr >= __pa(high_memory); -} diff --git a/drivers/char/mem.c b/drivers/char/mem.c index 94c2b556cf97..887ffca3f47f 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -294,13 +294,6 @@ static int uncached_access(struct file *file, phys_addr_t addr) * attribute aliases. */ return !(efi_mem_attributes(addr) & EFI_MEMORY_WB); -#elif defined(CONFIG_MIPS) - { - extern int __uncached_access(struct file *file, - unsigned long addr); - - return __uncached_access(file, addr); - } #else /* * Accessing memory above the top the kernel knows about or through a -- cgit v1.2.3-70-g09d2 From 198688edbf77c6fc0e65f5d062f810d83d090166 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Wed, 27 Jan 2021 12:41:47 +0800 Subject: MIPS: Fix inline asm input/output type mismatch in checksum.h used with Clang Fix the following build error when make M=samples/bpf used with Clang: CLANG-bpf samples/bpf/sockex2_kern.o In file included from samples/bpf/sockex2_kern.c:7: In file included from ./include/uapi/linux/if_tunnel.h:7: In file included from ./include/linux/ip.h:16: In file included from ./include/linux/skbuff.h:28: In file included from ./include/net/checksum.h:22: ./arch/mips/include/asm/checksum.h:161:9: error: unsupported inline asm: input with type 'unsigned long' matching output with type '__wsum' (aka 'unsigned int') : "0" ((__force unsigned long)daddr), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. This is a known issue on MIPS [1], the changed code can be compiled successfully by both GCC and Clang. [1] https://lore.kernel.org/linux-mips/CAG_fn=W0JHf8QyUX==+rQMp8PoULHrsQCa9Htffws31ga8k-iw@mail.gmail.com/ Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/checksum.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h index 5f80c28f5253..1e6c1354f245 100644 --- a/arch/mips/include/asm/checksum.h +++ b/arch/mips/include/asm/checksum.h @@ -130,6 +130,8 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, __u8 proto, __wsum sum) { + unsigned long tmp = (__force unsigned long)sum; + __asm__( " .set push # csum_tcpudp_nofold\n" " .set noat \n" @@ -157,7 +159,7 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, " addu %0, $1 \n" #endif " .set pop" - : "=r" (sum) + : "=r" (tmp) : "0" ((__force unsigned long)daddr), "r" ((__force unsigned long)saddr), #ifdef __MIPSEL__ @@ -167,7 +169,7 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, #endif "r" ((__force unsigned long)sum)); - return sum; + return (__force __wsum)tmp; } #define csum_tcpudp_nofold csum_tcpudp_nofold -- cgit v1.2.3-70-g09d2 From a78ddac1bc22bd7a47fbec06c9c4ef4312ba71cf Mon Sep 17 00:00:00 2001 From: Huang Pei Date: Fri, 29 Jan 2021 12:35:07 +0800 Subject: MIPS: fix kernel_stack_pointer() MIPS always save kernel stack pointer in regs[29] Signed-off-by: Huang Pei Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/ptrace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index 1e76774b36dd..daf3cf244ea9 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -53,7 +53,7 @@ struct pt_regs { static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) { - return regs->regs[31]; + return regs->regs[29]; } static inline void instruction_pointer_set(struct pt_regs *regs, -- cgit v1.2.3-70-g09d2 From 6732a1fbab38695a5f4c0fd20ee4274f8433a0ec Mon Sep 17 00:00:00 2001 From: Yang Li Date: Tue, 2 Feb 2021 10:15:35 +0800 Subject: KVM: MIPS: remove unneeded semicolon Eliminate the following coccicheck warning: ./arch/mips/kvm/mips.c:151:2-3: Unneeded semicolon Reported-by: Abaci Robot Signed-off-by: Yang Li Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/kvm/mips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c index 3d6a7f5827b1..58a8812e2fa5 100644 --- a/arch/mips/kvm/mips.c +++ b/arch/mips/kvm/mips.c @@ -148,7 +148,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) default: /* Unsupported KVM type */ return -EINVAL; - }; + } /* Allocate page table to map GPA -> RPA */ kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); -- cgit v1.2.3-70-g09d2 From 3235c5f0bccd969c0f1396220154a1da0c2eaac4 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Tue, 2 Feb 2021 10:52:29 +0800 Subject: MIPS: malta-time: remove unneeded semicolon Eliminate the following coccicheck warning: ./arch/mips/mti-malta/malta-time.c:141:2-3: Unneeded semicolon Reported-by: Abaci Robot Signed-off-by: Yang Li Signed-off-by: Thomas Bogendoerfer --- arch/mips/mti-malta/malta-time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 7efcfe0c9cd4..567720374d57 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -138,7 +138,7 @@ int get_c0_fdc_int(void) case CPU_INTERAPTIV: case CPU_PROAPTIV: return -1; - }; + } if (cpu_has_veic) return -1; -- cgit v1.2.3-70-g09d2 From a056aacd2df2ec8134ed3baffd7fb6ba02874652 Mon Sep 17 00:00:00 2001 From: Bhaskar Chowdhury Date: Tue, 2 Feb 2021 14:48:11 +0530 Subject: arch: mips: kernel: Fix two spelling in smp.c s/logcal/logical/ s/intercpu/inter-CPU/ Signed-off-by: Bhaskar Chowdhury Acked-by: Randy Dunlap Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/smp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 74b9102fd06e..ef86fbad8546 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -59,7 +59,7 @@ static DECLARE_COMPLETION(cpu_starting); static DECLARE_COMPLETION(cpu_running); /* - * A logcal cpu mask containing only one VPE per core to + * A logical cpu mask containing only one VPE per core to * reduce the number of IPIs on large MT systems. */ cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly; @@ -510,8 +510,8 @@ static inline void smp_on_each_tlb(void (*func) (void *info), void *info) * address spaces, a new context is obtained on the current cpu, and tlb * context on other cpus are invalidated to force a new context allocation * at switch_mm time, should the mm ever be used on other cpus. For - * multithreaded address spaces, intercpu interrupts have to be sent. - * Another case where intercpu interrupts are required is when the target + * multithreaded address spaces, inter-CPU interrupts have to be sent. + * Another case where inter-CPU interrupts are required is when the target * mm might be active on another cpu (eg debuggers doing the flushes on * behalf of debugees, kswapd stealing pages from another process etc). * Kanoj 07/00. -- cgit v1.2.3-70-g09d2 From b83ba0b9df56f8404ccc6ebcc7050fb8294f0f20 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 27 Jan 2021 14:24:30 +0100 Subject: MIPS: of: Introduce helper function to get DTB Selection of the DTB to be used was burried in more or less readable code in head.S. Move this code into a inline helper function and use it. Signed-off-by: Thomas Bogendoerfer Acked-by: Florian Fainelli --- arch/mips/ath79/setup.c | 13 +++++++------ arch/mips/bmips/setup.c | 7 +++---- arch/mips/generic/init.c | 5 ++--- arch/mips/include/asm/bootinfo.h | 22 +++++++++++++++++++++- arch/mips/include/asm/octeon/octeon.h | 1 - arch/mips/kernel/head.S | 31 ------------------------------- arch/mips/kernel/setup.c | 4 ---- arch/mips/lantiq/prom.c | 7 ++----- arch/mips/pic32/pic32mzda/init.c | 15 +-------------- arch/mips/ralink/of.c | 11 +++-------- 10 files changed, 39 insertions(+), 77 deletions(-) (limited to 'arch') diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c index 7e7bf9c2ad26..891f495c4c3c 100644 --- a/arch/mips/ath79/setup.c +++ b/arch/mips/ath79/setup.c @@ -213,16 +213,17 @@ unsigned int get_c0_compare_int(void) void __init plat_mem_setup(void) { - unsigned long fdt_start; + void *dtb; set_io_port_base(KSEG1); /* Get the position of the FDT passed by the bootloader */ - fdt_start = fw_getenvl("fdt_start"); - if (fdt_start) - __dt_setup_arch((void *)KSEG0ADDR(fdt_start)); - else if (fw_passed_dtb) - __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); + dtb = (void *)fw_getenvl("fdt_start"); + if (dtb == NULL) + dtb = get_fdt(); + + if (dtb) + __dt_setup_arch((void *)KSEG0ADDR(dtb)); ath79_reset_base = ioremap(AR71XX_RESET_BASE, AR71XX_RESET_SIZE); diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 10e31d91ca8f..95f8f10d8697 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -161,11 +161,10 @@ void __init plat_mem_setup(void) /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */ if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) dtb = phys_to_virt(fw_arg2); - else if (fw_passed_dtb) /* UHI interface or appended dtb */ - dtb = (void *)fw_passed_dtb; - else if (&__dtb_start != &__dtb_end) - dtb = (void *)__dtb_start; else + dtb = get_fdt(); + + if (!dtb) panic("no dtb found"); __dt_setup_arch(dtb); diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 68763fcde1d0..1842cddd8356 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -39,14 +39,13 @@ void __init *plat_get_fdt(void) /* Already set up */ return (void *)fdt; - if (fw_passed_dtb && !fdt_check_header((void *)fw_passed_dtb)) { + fdt = (void *)get_fdt(); + if (fdt && !fdt_check_header(fdt)) { /* * We have been provided with the appropriate device tree for * the board. Make use of it & search for any machine struct * based upon the root compatible string. */ - fdt = (void *)fw_passed_dtb; - for_each_mips_machine(check_mach) { match = mips_machine_is_compatible(check_mach, fdt); if (match) { diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index aa03b1237155..5be10ece3ef0 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -112,7 +112,27 @@ extern char arcs_cmdline[COMMAND_LINE_SIZE]; extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; #ifdef CONFIG_USE_OF -extern unsigned long fw_passed_dtb; +#include +#include + +extern char __appended_dtb[]; + +static inline void *get_fdt(void) +{ + if (IS_ENABLED(CONFIG_MIPS_RAW_APPENDED_DTB) || + IS_ENABLED(CONFIG_MIPS_ELF_APPENDED_DTB)) + if (fdt_magic(&__appended_dtb) == FDT_MAGIC) + return &__appended_dtb; + + if (fw_arg0 == -2) /* UHI interface */ + return (void *)fw_arg1; + + if (IS_ENABLED(CONFIG_BUILTIN_DTB)) + if (&__dtb_start != &__dtb_end) + return &__dtb_start; + + return NULL; +} #endif /* diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 08d48f37c046..7e714aefc76d 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -282,7 +282,6 @@ union octeon_cvmemctl { extern void octeon_check_cpu_bist(void); int octeon_prune_device_tree(void); -extern const char __appended_dtb; extern const char __dtb_octeon_3xxx_begin; extern const char __dtb_octeon_68xx_begin; diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 61b73580b877..b825ed4476c7 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -93,33 +93,6 @@ NESTED(kernel_entry, 16, sp) # kernel entry point jr t0 0: -#ifdef CONFIG_USE_OF -#if defined(CONFIG_MIPS_RAW_APPENDED_DTB) || \ - defined(CONFIG_MIPS_ELF_APPENDED_DTB) - - PTR_LA t2, __appended_dtb - -#ifdef CONFIG_CPU_BIG_ENDIAN - li t1, 0xd00dfeed -#else /* !CONFIG_CPU_BIG_ENDIAN */ - li t1, 0xedfe0dd0 -#endif /* !CONFIG_CPU_BIG_ENDIAN */ - lw t0, (t2) - beq t0, t1, dtb_found -#endif /* CONFIG_MIPS_RAW_APPENDED_DTB || CONFIG_MIPS_ELF_APPENDED_DTB */ - li t1, -2 - move t2, a1 - beq a0, t1, dtb_found - -#ifdef CONFIG_BUILTIN_DTB - PTR_LA t2, __dtb_start - PTR_LA t1, __dtb_end - bne t1, t2, dtb_found -#endif /* CONFIG_BUILTIN_DTB */ - - li t2, 0 -dtb_found: -#endif /* CONFIG_USE_OF */ PTR_LA t0, __bss_start # clear .bss LONG_S zero, (t0) PTR_LA t1, __bss_stop - LONGSIZE @@ -133,10 +106,6 @@ dtb_found: LONG_S a2, fw_arg2 LONG_S a3, fw_arg3 -#ifdef CONFIG_USE_OF - LONG_S t2, fw_passed_dtb -#endif - MTC0 zero, CP0_CONTEXT # clear context register #ifdef CONFIG_64BIT MTC0 zero, CP0_XCONTEXT diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 7e1f8e277437..3785c72bc3bc 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -792,10 +792,6 @@ void __init setup_arch(char **cmdline_p) unsigned long kernelsp[NR_CPUS]; unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; -#ifdef CONFIG_USE_OF -unsigned long fw_passed_dtb; -#endif - #ifdef CONFIG_DEBUG_FS struct dentry *mips_debugfs_dir; static int __init debugfs_mips(void) diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 363937121617..bc9f58fcbdf9 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -73,11 +73,8 @@ void __init plat_mem_setup(void) set_io_port_base((unsigned long) KSEG1); - if (fw_passed_dtb) /* UHI interface */ - dtb = (void *)fw_passed_dtb; - else if (&__dtb_start != &__dtb_end) - dtb = (void *)__dtb_start; - else + dtb = get_fdt(); + if (dtb == NULL) panic("no dtb found"); /* diff --git a/arch/mips/pic32/pic32mzda/init.c b/arch/mips/pic32/pic32mzda/init.c index 1897aa863573..764f2d022fae 100644 --- a/arch/mips/pic32/pic32mzda/init.c +++ b/arch/mips/pic32/pic32mzda/init.c @@ -21,24 +21,11 @@ const char *get_system_type(void) return "PIC32MZDA"; } -static ulong get_fdtaddr(void) -{ - ulong ftaddr = 0; - - if (fw_passed_dtb && !fw_arg2 && !fw_arg3) - return (ulong)fw_passed_dtb; - - if (&__dtb_start < &__dtb_end) - ftaddr = (ulong)__dtb_start; - - return ftaddr; -} - void __init plat_mem_setup(void) { void *dtb; - dtb = (void *)get_fdtaddr(); + dtb = get_fdt(); if (!dtb) { pr_err("pic32: no DTB found.\n"); return; diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 2c9af61efc20..8286c3521476 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -64,20 +64,15 @@ static int __init early_init_dt_find_memory(unsigned long node, void __init plat_mem_setup(void) { - void *dtb = NULL; + void *dtb; set_io_port_base(KSEG1); /* * Load the builtin devicetree. This causes the chosen node to be - * parsed resulting in our memory appearing. fw_passed_dtb is used - * by CONFIG_MIPS_APPENDED_RAW_DTB as well. + * parsed resulting in our memory appearing. */ - if (fw_passed_dtb) - dtb = (void *)fw_passed_dtb; - else if (&__dtb_start != &__dtb_end) - dtb = (void *)__dtb_start; - + dtb = get_fdt(); __dt_setup_arch(dtb); of_scan_flat_dt(early_init_dt_find_memory, NULL); -- cgit v1.2.3-70-g09d2 From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001 From: Sander Vanheule Date: Wed, 3 Feb 2021 10:21:41 +0100 Subject: MIPS: ralink: manage low reset lines Reset lines with indices smaller than 8 are currently considered invalid by the rt2880-reset reset controller. The MT7621 SoC uses a number of these low reset lines. The DTS defines reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2. As a result of the above restriction, these resets cannot be asserted or de-asserted by the reset controller. In cases where the bootloader does not de-assert these lines, this results in e.g. the MT7621's internal switch staying in reset. Change the reset controller to only ignore the system reset, so all reset lines with index greater than 0 are considered valid. Signed-off-by: Sander Vanheule Acked-by: John Crispin Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/reset.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index 8126f1260407..274d33078c5e 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -27,7 +27,7 @@ static int ralink_assert_device(struct reset_controller_dev *rcdev, { u32 val; - if (id < 8) + if (id == 0) return -1; val = rt_sysc_r32(SYSC_REG_RESET_CTRL); @@ -42,7 +42,7 @@ static int ralink_deassert_device(struct reset_controller_dev *rcdev, { u32 val; - if (id < 8) + if (id == 0) return -1; val = rt_sysc_r32(SYSC_REG_RESET_CTRL); -- cgit v1.2.3-70-g09d2 From 671841d254b81939bde21e68ad16402ccca42901 Mon Sep 17 00:00:00 2001 From: Bert Vermeulen Date: Tue, 19 Jan 2021 10:21:06 +0100 Subject: Add support for Realtek RTL838x/RTL839x switch SoCs The RTL838x/839x family of SoCs are Realtek switches with an embedded MIPS core. * RTL838x - 500MHz 4kce single core - 1Gbit ports and L2 features * RTL839x - 700MHz 34Kc single core - 1Gbit ports and L2 features These switches, depending on the exact part number, will have anywhere between 8 and 52 ports. The MIPS core is wired to a switch cpu port which has a tagging feature allowing us to make use of the DSA subsystem. The SoCs are somewhat basic in certain areas, getting better with more advanced features on newer series. The switch functionality is MMIO-mapped via a large MFD region. The SoCs have the following peripherals * ethernet * switch * uart - ns16550a * spi-flash interface * gpio * wdt * led The code was derived from various vendor SDKs based on Linux v2.6 kernels. This patchset allows us to boot RTL838x/RTL839x units with basic support. Most of the other drivers are already written and functional, and work to get them upstream is already in progress. Signed-off-by: Birger Koblitz Signed-off-by: Bert Vermeulen Signed-off-by: John Crispin Signed-off-by: Sander Vanheule Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/realtek/rtl838x.dtsi | 21 ++++++++++++ arch/mips/boot/dts/realtek/rtl83xx.dtsi | 59 +++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 arch/mips/boot/dts/realtek/rtl838x.dtsi create mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi (limited to 'arch') diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 0259238d7a2e..60bd7d2a9ad8 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -14,6 +14,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 subdir-$(CONFIG_ATH79) += qca subdir-$(CONFIG_RALINK) += ralink +subdir-$(CONFIG_MACH_REALTEK_RTL) += realtek subdir-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += xilfpga obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi new file mode 100644 index 000000000000..6cc4ff5c0d19 --- /dev/null +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "mips,mips4KEc"; + reg = <0>; + clocks = <&baseclk 0>; + clock-names = "cpu"; + }; + }; + + baseclk: baseclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; +}; diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi new file mode 100644 index 000000000000..de65a111b626 --- /dev/null +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x10000>; + + uart0: uart@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + + uart1: uart@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <30>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 4042147a0cc6af5a400b5e12a7855e893dec01b4 Mon Sep 17 00:00:00 2001 From: Bert Vermeulen Date: Tue, 19 Jan 2021 10:21:07 +0100 Subject: MIPS: Add Realtek RTL838x/RTL839x support as generic MIPS system This is just enough system to boot the kernel with earlycon working. Signed-off-by: Bert Vermeulen Signed-off-by: Sander Vanheule Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 62475fc95472..71df230d9c54 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -639,6 +639,27 @@ config RALINK select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER +config MACH_REALTEK_RTL + bool "Realtek RTL838x/RTL839x based machines" + select MIPS_GENERIC + select DMA_NONCOHERENT + select IRQ_MIPS_CPU + select CSRC_R4K + select CEVT_R4K + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_MIPS16 + select SYS_SUPPORTS_MULTITHREADING + select SYS_SUPPORTS_VPE_LOADER + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_EARLY_PRINTK_8250 + select USE_GENERIC_EARLY_PRINTK_8250 + select BOOT_RAW + select PINCTRL + select USE_OF + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC_MEMORY -- cgit v1.2.3-70-g09d2 From 8991ae593ca25b8239472e68fd18504143b90465 Mon Sep 17 00:00:00 2001 From: Bert Vermeulen Date: Tue, 19 Jan 2021 10:21:09 +0100 Subject: mips: dts: Add support for Cisco SG220-26 switch Signed-off-by: Bert Vermeulen Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/realtek/Makefile | 2 ++ arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 25 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 arch/mips/boot/dts/realtek/Makefile create mode 100644 arch/mips/boot/dts/realtek/cisco_sg220-26.dts (limited to 'arch') diff --git a/arch/mips/boot/dts/realtek/Makefile b/arch/mips/boot/dts/realtek/Makefile new file mode 100644 index 000000000000..fba4e93187a6 --- /dev/null +++ b/arch/mips/boot/dts/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-y += cisco_sg220-26.dtb diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts new file mode 100644 index 000000000000..1cdbb09297ef --- /dev/null +++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +/dts-v1/; + +#include "rtl83xx.dtsi" +#include "rtl838x.dtsi" + +/ { + model = "Cisco SG220-26"; + compatible = "cisco,sg220-26", "realtek,rtl8382-soc"; + + chosen { + stdout-path = "serial0:9600n8"; + bootargs = "earlycon console=ttyS0,9600"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3-70-g09d2 From c87bc737220adc4627f191a5e4ed5068aabc24a1 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Thu, 4 Feb 2021 13:59:29 +0000 Subject: MIPS: pistachio: remove obsolete include/asm/mach-pistachio Since commit 02bd530f888c ("MIPS: generic: Increase NR_IRQS to 256") include/asm/mach-pistachio/irq.h just does nothing. Remove the file along with mach-pistachio folder and include compiler directive. Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- MAINTAINERS | 1 - arch/mips/include/asm/mach-pistachio/irq.h | 15 --------------- arch/mips/pistachio/Platform | 2 -- 3 files changed, 18 deletions(-) delete mode 100644 arch/mips/include/asm/mach-pistachio/irq.h (limited to 'arch') diff --git a/MAINTAINERS b/MAINTAINERS index 6add29cb2060..3e58787907d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14099,7 +14099,6 @@ L: linux-mips@vger.kernel.org S: Odd Fixes F: arch/mips/boot/dts/img/pistachio* F: arch/mips/configs/pistachio*_defconfig -F: arch/mips/include/asm/mach-pistachio/ F: arch/mips/pistachio/ PKTCDVD DRIVER diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h deleted file mode 100644 index 74ac016503ad..000000000000 --- a/arch/mips/include/asm/mach-pistachio/irq.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Pistachio IRQ setup - * - * Copyright (C) 2014 Google, Inc. - */ - -#ifndef __ASM_MACH_PISTACHIO_IRQ_H -#define __ASM_MACH_PISTACHIO_IRQ_H - -#define NR_IRQS 256 - -#include - -#endif /* __ASM_MACH_PISTACHIO_IRQ_H */ diff --git a/arch/mips/pistachio/Platform b/arch/mips/pistachio/Platform index f73a1a929965..c59de86dbddf 100644 --- a/arch/mips/pistachio/Platform +++ b/arch/mips/pistachio/Platform @@ -1,8 +1,6 @@ # # IMG Pistachio SoC # -cflags-$(CONFIG_MACH_PISTACHIO) += \ - -I$(srctree)/arch/mips/include/asm/mach-pistachio load-$(CONFIG_MACH_PISTACHIO) += 0xffffffff80400000 zload-$(CONFIG_MACH_PISTACHIO) += 0xffffffff81000000 all-$(CONFIG_MACH_PISTACHIO) := uImage.gz -- cgit v1.2.3-70-g09d2 From 1ddc96bd42daeeb58f66c9515e506f245ccb00c6 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 4 Feb 2021 11:35:22 +0800 Subject: MIPS: kernel: Support extracting off-line stack traces from user-space with perf Add perf_event_mips_regs/perf_reg_value/perf_reg_validate to support features HAVE_PERF_REGS/HAVE_PERF_USER_STACK_DUMP in kernel. [ayan@wavecomp.com: Repick this patch for unwinding userstack backtrace by perf and libunwind on MIPS based CPU.] [ralf@linux-mips.org: Add perf_get_regs_user() which is required after 'commit 88a7c26af8da ("perf: Move task_pt_regs sampling into arch code")'.] [yangtiezhu@loongson.cn: Fix build error about perf_get_regs_user() after commit 76a4efa80900 ("perf/arch: Remove perf_sample_data::regs_user_copy"), and also separate the original patches into two parts (MIPS kernel and perf tools) to merge easily.] The original patches: https://lore.kernel.org/patchwork/patch/1126521/ https://lore.kernel.org/patchwork/patch/1126520/ Signed-off-by: David Daney Signed-off-by: Ralf Baechle Signed-off-by: Archer Yan Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 + arch/mips/include/uapi/asm/perf_regs.h | 40 ++++++++++++++++++++ arch/mips/kernel/Makefile | 2 +- arch/mips/kernel/perf_regs.c | 68 ++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 arch/mips/include/uapi/asm/perf_regs.h create mode 100644 arch/mips/kernel/perf_regs.c (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 71df230d9c54..57b06798706c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -77,6 +77,8 @@ config MIPS select HAVE_NMI select HAVE_OPROFILE select HAVE_PERF_EVENTS + select HAVE_PERF_REGS + select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ select HAVE_SPARSE_SYSCALL_NR diff --git a/arch/mips/include/uapi/asm/perf_regs.h b/arch/mips/include/uapi/asm/perf_regs.h new file mode 100644 index 000000000000..d0f4ecd616cf --- /dev/null +++ b/arch/mips/include/uapi/asm/perf_regs.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _ASM_MIPS_PERF_REGS_H +#define _ASM_MIPS_PERF_REGS_H + +enum perf_event_mips_regs { + PERF_REG_MIPS_PC, + PERF_REG_MIPS_R1, + PERF_REG_MIPS_R2, + PERF_REG_MIPS_R3, + PERF_REG_MIPS_R4, + PERF_REG_MIPS_R5, + PERF_REG_MIPS_R6, + PERF_REG_MIPS_R7, + PERF_REG_MIPS_R8, + PERF_REG_MIPS_R9, + PERF_REG_MIPS_R10, + PERF_REG_MIPS_R11, + PERF_REG_MIPS_R12, + PERF_REG_MIPS_R13, + PERF_REG_MIPS_R14, + PERF_REG_MIPS_R15, + PERF_REG_MIPS_R16, + PERF_REG_MIPS_R17, + PERF_REG_MIPS_R18, + PERF_REG_MIPS_R19, + PERF_REG_MIPS_R20, + PERF_REG_MIPS_R21, + PERF_REG_MIPS_R22, + PERF_REG_MIPS_R23, + PERF_REG_MIPS_R24, + PERF_REG_MIPS_R25, + PERF_REG_MIPS_R26, + PERF_REG_MIPS_R27, + PERF_REG_MIPS_R28, + PERF_REG_MIPS_R29, + PERF_REG_MIPS_R30, + PERF_REG_MIPS_R31, + PERF_REG_MIPS_MAX = PERF_REG_MIPS_R31 + 1, +}; +#endif /* _ASM_MIPS_PERF_REGS_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 2303a5868c14..a893ea041ef5 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -103,7 +103,7 @@ obj-$(CONFIG_MIPSR2_TO_R6_EMULATOR) += mips-r2-to-r6-emul.o CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) -obj-$(CONFIG_PERF_EVENTS) += perf_event.o +obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o diff --git a/arch/mips/kernel/perf_regs.c b/arch/mips/kernel/perf_regs.c new file mode 100644 index 000000000000..e686780d1647 --- /dev/null +++ b/arch/mips/kernel/perf_regs.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Some parts derived from x86 version of this file. + * + * Copyright (C) 2013 Cavium, Inc. + */ + +#include + +#include + +#ifdef CONFIG_32BIT +u64 perf_reg_abi(struct task_struct *tsk) +{ + return PERF_SAMPLE_REGS_ABI_32; +} +#else /* Must be CONFIG_64BIT */ +u64 perf_reg_abi(struct task_struct *tsk) +{ + if (test_tsk_thread_flag(tsk, TIF_32BIT_REGS)) + return PERF_SAMPLE_REGS_ABI_32; + else + return PERF_SAMPLE_REGS_ABI_64; +} +#endif /* CONFIG_32BIT */ + +int perf_reg_validate(u64 mask) +{ + if (!mask) + return -EINVAL; + if (mask & ~((1ull << PERF_REG_MIPS_MAX) - 1)) + return -EINVAL; + return 0; +} + +u64 perf_reg_value(struct pt_regs *regs, int idx) +{ + long v; + + switch (idx) { + case PERF_REG_MIPS_PC: + v = regs->cp0_epc; + break; + case PERF_REG_MIPS_R1 ... PERF_REG_MIPS_R25: + v = regs->regs[idx - PERF_REG_MIPS_R1 + 1]; + break; + case PERF_REG_MIPS_R28 ... PERF_REG_MIPS_R31: + v = regs->regs[idx - PERF_REG_MIPS_R28 + 28]; + break; + + default: + WARN_ON_ONCE(1); + return 0; + } + + return (s64)v; /* Sign extend if 32-bit. */ +} + +void perf_get_regs_user(struct perf_regs *regs_user, + struct pt_regs *regs) +{ + regs_user->regs = task_pt_regs(current); + regs_user->abi = perf_reg_abi(current); +} -- cgit v1.2.3-70-g09d2 From d4d3ef8b347b73aa60f60f4be06acf1643e79f34 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Fri, 5 Feb 2021 18:11:21 +0800 Subject: MIPS: relocatable: Provide kaslr_offset() to get the kernel offset Provide kaslr_offset() to get the kernel offset when KASLR is enabled. Error may occur before update_kaslr_offset(), so put it at the end of the offset branch. Fixes: a307a4ce9ecd ("MIPS: Loongson64: Add KASLR support") Reported-by: kernel test robot Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/page.h | 6 ++++++ arch/mips/kernel/relocate.c | 10 ++++++++++ arch/mips/kernel/setup.c | 3 +++ 3 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 6a77bc4a6eec..74082e35d57c 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -255,6 +255,12 @@ extern bool __virt_addr_valid(const volatile void *kaddr); #define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_TSK_EXEC +extern unsigned long __kaslr_offset; +static inline unsigned long kaslr_offset(void) +{ + return __kaslr_offset; +} + #include #include diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index c643c816cbe0..95abb9c82f00 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -300,6 +300,13 @@ static inline int __init relocation_addr_valid(void *loc_new) return 1; } +static inline void __init update_kaslr_offset(unsigned long *addr, long offset) +{ + unsigned long *new_addr = (unsigned long *)RELOCATED(addr); + + *new_addr = (unsigned long)offset; +} + #if defined(CONFIG_USE_OF) void __weak *plat_get_fdt(void) { @@ -410,6 +417,9 @@ void *__init relocate_kernel(void) /* Return the new kernel's entry point */ kernel_entry = RELOCATED(start_kernel); + + /* Error may occur before, so keep it at last */ + update_kaslr_offset(&__kaslr_offset, offset); } out: return kernel_entry; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 3785c72bc3bc..f4e19125521a 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -84,6 +84,9 @@ static struct resource code_resource = { .name = "Kernel code", }; static struct resource data_resource = { .name = "Kernel data", }; static struct resource bss_resource = { .name = "Kernel bss", }; +unsigned long __kaslr_offset __ro_after_init; +EXPORT_SYMBOL(__kaslr_offset); + static void *detect_magic __initdata = detect_memory_region; #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET -- cgit v1.2.3-70-g09d2 From 457d2fc54f00b97367a67ef9dadebfd06772d9af Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Fri, 5 Feb 2021 18:11:22 +0800 Subject: MIPS: relocatable: Use __kaslr_offset in show_kernel_relocation The type of the VMLINUX_LOAD_ADDRESS macro is the (unsigned long long) in 32bits kernel but (unsigned long) in the 64-bit kernel. Although there is no error here, avoid using it to calculate kaslr_offset. Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/relocate.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c index 95abb9c82f00..e73c4fd74161 100644 --- a/arch/mips/kernel/relocate.c +++ b/arch/mips/kernel/relocate.c @@ -430,13 +430,9 @@ out: */ static void show_kernel_relocation(const char *level) { - unsigned long offset; - - offset = __pa_symbol(_text) - __pa_symbol(VMLINUX_LOAD_ADDRESS); - - if (IS_ENABLED(CONFIG_RELOCATABLE) && offset > 0) { + if (__kaslr_offset > 0) { printk(level); - pr_cont("Kernel relocated by 0x%pK\n", (void *)offset); + pr_cont("Kernel relocated by 0x%pK\n", (void *)__kaslr_offset); pr_cont(" .text @ 0x%pK\n", _text); pr_cont(" .data @ 0x%pK\n", _sdata); pr_cont(" .bss @ 0x%pK\n", __bss_start); -- cgit v1.2.3-70-g09d2 From fc4cac4cfc437659ce445c3c47b807e1cc625b66 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Mon, 8 Feb 2021 12:37:42 +0000 Subject: MIPS: compressed: fix build with enabled UBSAN Commit 1e35918ad9d1 ("MIPS: Enable Undefined Behavior Sanitizer UBSAN") added a possibility to build the entire kernel with UBSAN instrumentation for MIPS, with the exception for VDSO. However, self-extracting head wasn't been added to exceptions, so this occurs: mips-alpine-linux-musl-ld: arch/mips/boot/compressed/decompress.o: in function `FSE_buildDTable_wksp': decompress.c:(.text.FSE_buildDTable_wksp+0x278): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: decompress.c:(.text.FSE_buildDTable_wksp+0x2a8): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: decompress.c:(.text.FSE_buildDTable_wksp+0x2c4): undefined reference to `__ubsan_handle_shift_out_of_bounds' mips-alpine-linux-musl-ld: arch/mips/boot/compressed/decompress.o: decompress.c:(.text.FSE_buildDTable_raw+0x9c): more undefined references to `__ubsan_handle_shift_out_of_bounds' follow Add UBSAN_SANITIZE := n to mips/boot/compressed/Makefile to exclude it from instrumentation scope and fix this issue. Fixes: 1e35918ad9d1 ("MIPS: Enable Undefined Behavior Sanitizer UBSAN") Cc: stable@vger.kernel.org # 5.0+ Signed-off-by: Alexander Lobakin Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/compressed/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile index 47cd9dc7454a..f93f72bcba97 100644 --- a/arch/mips/boot/compressed/Makefile +++ b/arch/mips/boot/compressed/Makefile @@ -37,6 +37,7 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ # Prevents link failures: __sanitizer_cov_trace_pc() is not linked in. KCOV_INSTRUMENT := n GCOV_PROFILE := n +UBSAN_SANITIZE := n # decompressor objects (linked with vmlinuz) vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o -- cgit v1.2.3-70-g09d2 From 9f0781bac9f3d75d10d6a862e18ff172ce07c202 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Sun, 7 Feb 2021 16:52:36 +0800 Subject: MIPS: process: Fix no previous prototype warning unwind_stack_by_address and unwind_stack need . arch_align_stack needs link: https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/ZPL2RRA6RZKRQZI5IGOVLFXN2GVZBN3L/ Reported-by: kernel test robot Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index f94f291ee6c6..cdd2cd4df081 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include #ifdef CONFIG_HOTPLUG_CPU void arch_cpu_idle_dead(void) -- cgit v1.2.3-70-g09d2 From 4088024344672daccfd7fc97ff6e6cc241d4a39e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Mon, 8 Feb 2021 16:46:14 +0300 Subject: Revert "mips: Manually call fdt_init_reserved_mem() method" This reverts commit 3751cbda8f223549d7ea28803cbec8ac87e43ed2. Originally the patch was created to fix the reserved-memory DT-node parsing failure on the early stages of the platform memory initialization. That happened due to the two early memory allocators utilization that time: bootmem and memblock. At first the platform-specific memory mapping array was initialized. Then the early_init_fdt_scan_reserved_mem() was called, which couldn't fully parse the "reserved-memory" DT-node since neither memblock nor bootmem allocators hadn't been initialized at that stage, so the fdt_init_reserved_mem() method failed on the memory allocation calls. Only after that the platform-specific memory mapping were used to create proper bootmem and memblock structures and let the early memory allocations work. That's why we had to call the fdt_init_reserved_mem() method one more time to retry the initialization of the features like CMA. The necessity to have that fix was disappeared after the full memblock support had been added to the MIPS kernel and all plat_mem_setup() had been fixed to add the memory regions right into the memblock memory pool. Let's revert that patch then especially after having Paul reported that the second fdt_init_reserved_mem() call causes the reserved memory pool being created twice bigger than implied. Fixes: a94e4f24ec83 ("MIPS: init: Drop boot_mem_map") Reported-by: Paul Cercueil Signed-off-by: Serge Semin Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/setup.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index f4e19125521a..9a761ba36b6e 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -689,8 +688,6 @@ static void __init arch_mem_init(char **cmdline_p) memblock_reserve(__pa_symbol(&__nosave_begin), __pa_symbol(&__nosave_end) - __pa_symbol(&__nosave_begin)); - fdt_init_reserved_mem(); - early_memtest(PFN_PHYS(ARCH_PFN_OFFSET), PFN_PHYS(max_low_pfn)); } -- cgit v1.2.3-70-g09d2 From fe6c98a115affdb3ff9cfccc5b6207127223d4b8 Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sun, 7 Feb 2021 15:24:09 +0800 Subject: MIPS: crash_dump.c: Simplify copy_oldmem_page() Replace kmap_atomic_pfn() with kmap_local_pfn() which is preemptible and can take page faults. Remove the indirection of the dump page and the related cruft which is not longer required. Remove unused or redundant header files. Signed-off-by: Youling Tang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/crash_dump.c | 41 ++++++----------------------------------- 1 file changed, 6 insertions(+), 35 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/crash_dump.c b/arch/mips/kernel/crash_dump.c index 01b2bd95ba1f..2e50f55185a6 100644 --- a/arch/mips/kernel/crash_dump.c +++ b/arch/mips/kernel/crash_dump.c @@ -1,11 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include #include -#include -#include - -static void *kdump_buf_page; /** * copy_oldmem_page - copy one page from "oldmem" @@ -19,10 +14,6 @@ static void *kdump_buf_page; * * Copy a page from "oldmem". For this page, there is no pte mapped * in the current kernel. - * - * Calling copy_to_user() in atomic context is not desirable. Hence first - * copying the data to a pre-allocated kernel page and then copying to user - * space in non-atomic context. */ ssize_t copy_oldmem_page(unsigned long pfn, char *buf, size_t csize, unsigned long offset, int userbuf) @@ -32,36 +23,16 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf, if (!csize) return 0; - vaddr = kmap_atomic_pfn(pfn); + vaddr = kmap_local_pfn(pfn); if (!userbuf) { - memcpy(buf, (vaddr + offset), csize); - kunmap_atomic(vaddr); + memcpy(buf, vaddr + offset, csize); } else { - if (!kdump_buf_page) { - pr_warn("Kdump: Kdump buffer page not allocated\n"); - - return -EFAULT; - } - copy_page(kdump_buf_page, vaddr); - kunmap_atomic(vaddr); - if (copy_to_user(buf, (kdump_buf_page + offset), csize)) - return -EFAULT; + if (copy_to_user(buf, vaddr + offset, csize)) + csize = -EFAULT; } - return csize; -} - -static int __init kdump_buf_page_init(void) -{ - int ret = 0; + kunmap_local(vaddr); - kdump_buf_page = kmalloc(PAGE_SIZE, GFP_KERNEL); - if (!kdump_buf_page) { - pr_warn("Kdump: Failed to allocate kdump buffer page\n"); - ret = -ENOMEM; - } - - return ret; + return csize; } -arch_initcall(kdump_buf_page_init); -- cgit v1.2.3-70-g09d2 From ea4a1ea4c8f47b8dd0aa6e96d8cb806afe6726f8 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 9 Feb 2021 17:12:34 +0100 Subject: Revert "MIPS: microMIPS: Fix the judgment of mm_jr16_op and mm_jalr_op" This reverts commit 9308579fef3ddde19da9d45e23bf36d41932417f. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/process.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index cdd2cd4df081..af4c862ec5ff 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -326,8 +326,8 @@ static inline int is_jump_ins(union mips_instruction *ip) * microMIPS is kind of more fun... */ if (mm_insn_16bit(ip->word >> 16)) { - if (ip->mm16_r5_format.opcode == mm_pool16c_op && - ip->mm16_r5_format.rt == mm_jr16_op) + if ((ip->mm16_r5_format.opcode == mm_pool16c_op && + (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) return 1; return 0; } @@ -339,7 +339,7 @@ static inline int is_jump_ins(union mips_instruction *ip) if (ip->r_format.opcode != mm_pool32a_op || ip->r_format.func != mm_pool32axf_op) return 0; - return ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op; + return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; #else if (ip->j_format.opcode == j_op) return 1; -- cgit v1.2.3-70-g09d2 From e66ef72d269105cee2ae9c8fa0442d7a9857324f Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 10 Feb 2021 15:50:25 -0800 Subject: mips: Replace lkml.org links with lore As started by commit 05a5f51ca566 ("Documentation: Replace lkml.org links with lore"), replace lkml.org links with lore to better use a single source that's more likely to stay available long-term. Signed-off-by: Kees Cook Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/page.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 74082e35d57c..65acab9c41f9 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -202,14 +202,13 @@ static inline unsigned long ___pa(unsigned long x) /* * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org). The - * discussion can be found in lkml posting - * which is - * archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html + * discussion can be found in + * https://lore.kernel.org/lkml/a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com * * It is unclear if the misscompilations mentioned in - * http://lkml.org/lkml/2010/8/8/138 also affect MIPS so we keep this one - * until GCC 3.x has been retired before we can apply - * https://patchwork.linux-mips.org/patch/1541/ + * https://lore.kernel.org/lkml/1281303490-390-1-git-send-email-namhyung@gmail.com + * also affect MIPS so we keep this one until GCC 3.x has been retired + * before we can apply https://patchwork.linux-mips.org/patch/1541/ */ #ifndef __pa_symbol -- cgit v1.2.3-70-g09d2 From ee54d379fc9c490797aa71d25d0320b5af5924a1 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 9 Feb 2021 13:05:25 +0800 Subject: MIPS: Make check condition for SDBBP consistent with EJTAG spec According to MIPS EJTAG Specification [1], a Debug Breakpoint exception occurs when an SDBBP instruction is executed, the CP0_DEBUG bit DBp indicates that a Debug Breakpoint exception occurred. When I read the original code, it looks a little confusing at first glance, just check bit DBp for SDBBP to make the code more readable, it will be much easier to understand. [1] http://www.t-es-t.hu/download/mips/md00047f.pdf Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mipsregs.h | 4 ++++ arch/mips/kernel/genex.S | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a0e8ae5497b6..9c8099a6ffed 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1085,6 +1085,10 @@ #define CVMVMCONF_RMMUSIZEM1_S 0 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S) +/* Debug register field definitions */ +#define MIPS_DEBUG_DBP_SHIFT 1 +#define MIPS_DEBUG_DBP (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT) + /* * Coprocessor 1 (FPU) register names */ diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index bcce32a3de10..743d75927b71 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -349,8 +349,8 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp) MTC0 k0, CP0_DESAVE mfc0 k0, CP0_DEBUG - sll k0, k0, 30 # Check for SDBBP. - bgez k0, ejtag_return + andi k0, k0, MIPS_DEBUG_DBP # Check for SDBBP. + beqz k0, ejtag_return #ifdef CONFIG_SMP 1: PTR_LA k0, ejtag_debug_buffer_spinlock -- cgit v1.2.3-70-g09d2 From 7c86ff9925cbc83e8a21f164a8fdc2767e03531e Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Sat, 13 Feb 2021 02:20:46 +0800 Subject: MIPS: Add basic support for ptrace single step In the current code, arch_has_single_step() is not defined on MIPS, that means MIPS does not support instruction single-step for user mode. Delve is a debugger for the Go programming language, the ptrace syscall PtraceSingleStep() failed [1] on MIPS and then the single step function can not work well, we can see that PtraceSingleStep() definition returns ptrace(PTRACE_SINGLESTEP) [2]. So it is necessary to support ptrace single step on MIPS. At the beginning, we try to use the Debug Single Step exception on the Loongson 3A4000 platform, but it has no effect when set CP0_DEBUG SSt bit, this is because CP0_DEBUG NoSSt bit is 1 which indicates no single-step feature available [3], so this way which is dependent on the hardware is almost impossible. With further research, we find out there exists a common way used with break instruction in arch/alpha/kernel/ptrace.c, it is workable. For the above analysis, define arch_has_single_step(), add the common function user_enable_single_step() and user_disable_single_step(), set flag TIF_SINGLESTEP for child process, use break instruction to set breakpoint. We can use the following testcase to test it: tools/testing/selftests/breakpoints/step_after_suspend_test.c $ make -C tools/testing/selftests TARGETS=breakpoints $ cd tools/testing/selftests/breakpoints Without this patch: $ ./step_after_suspend_test -n TAP version 13 1..4 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 1 # SKIP CPU 0 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 2 # SKIP CPU 1 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 3 # SKIP CPU 2 # ptrace(PTRACE_SINGLESTEP) not supported on this architecture: Input/output error ok 4 # SKIP CPU 3 # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:4 error:0 With this patch: $ ./step_after_suspend_test -n TAP version 13 1..4 ok 1 CPU 0 ok 2 CPU 1 ok 3 CPU 2 ok 4 CPU 3 # Totals: pass:4 fail:0 xfail:0 xpass:0 skip:0 error:0 [1] https://github.com/go-delve/delve/blob/master/pkg/proc/native/threads_linux.go#L50 [2] https://github.com/go-delve/delve/blob/master/vendor/golang.org/x/sys/unix/syscall_linux.go#L1573 [3] http://www.t-es-t.hu/download/mips/md00047f.pdf Reported-by: Guoqi Chen Signed-off-by: Xingxing Su Signed-off-by: Tiezhu Yang Reported-by: kernel test robot Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/ptrace.h | 2 + arch/mips/include/asm/thread_info.h | 5 ++ arch/mips/kernel/ptrace.c | 108 ++++++++++++++++++++++++++++++++++++ arch/mips/kernel/signal.c | 2 +- 4 files changed, 116 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index daf3cf244ea9..c733daefd015 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -186,4 +186,6 @@ static inline void user_stack_pointer_set(struct pt_regs *regs, regs->regs[29] = val; } +#define arch_has_single_step() (1) + #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index e2c352da3877..bd4dbb5b2900 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -35,6 +35,10 @@ struct thread_info { */ struct pt_regs *regs; long syscall; /* syscall number */ + + int bpt_nsaved; + unsigned long bpt_addr[1]; /* breakpoint handling */ + unsigned int bpt_insn[1]; }; /* @@ -117,6 +121,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_UPROBE 6 /* breakpointed or singlestepping */ #define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ +#define TIF_SINGLESTEP 10 /* restore singlestep on return to user mode */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_NOHZ 19 /* in adaptive nohz mode */ diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index db7c5be1d4a3..f29141922001 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -45,10 +45,15 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include +#include "probes-common.h" + +#define BREAKINST 0x0000000d + /* * Called by kernel/ptrace.c when detaching.. * @@ -58,6 +63,7 @@ void ptrace_disable(struct task_struct *child) { /* Don't load the watchpoint registers for the ex-child. */ clear_tsk_thread_flag(child, TIF_LOAD_WATCH); + user_disable_single_step(child); } /* @@ -1072,6 +1078,108 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task) #endif } +static int read_insn(struct task_struct *task, unsigned long addr, unsigned int *insn) +{ + int copied = access_process_vm(task, addr, insn, + sizeof(unsigned int), FOLL_FORCE); + + if (copied != sizeof(unsigned int)) { + pr_err("failed to read instruction from 0x%lx\n", addr); + return -EIO; + } + + return 0; +} + +static int write_insn(struct task_struct *task, unsigned long addr, unsigned int insn) +{ + int copied = access_process_vm(task, addr, &insn, + sizeof(unsigned int), FOLL_FORCE | FOLL_WRITE); + + if (copied != sizeof(unsigned int)) { + pr_err("failed to write instruction to 0x%lx\n", addr); + return -EIO; + } + + return 0; +} + +static int insn_has_delayslot(union mips_instruction insn) +{ + return __insn_has_delay_slot(insn); +} + +static void ptrace_set_bpt(struct task_struct *child) +{ + union mips_instruction mips_insn = { 0 }; + struct pt_regs *regs; + unsigned long pc; + unsigned int insn; + int i, ret, nsaved = 0; + + regs = task_pt_regs(child); + pc = regs->cp0_epc; + + ret = read_insn(child, pc, &insn); + if (ret < 0) + return; + + if (insn_has_delayslot(mips_insn)) { + pr_info("executing branch insn\n"); + ret = __compute_return_epc(regs); + if (ret < 0) + return; + task_thread_info(child)->bpt_addr[nsaved++] = regs->cp0_epc; + } else { + pr_info("executing normal insn\n"); + task_thread_info(child)->bpt_addr[nsaved++] = pc + 4; + } + + /* install breakpoints */ + for (i = 0; i < nsaved; i++) { + ret = read_insn(child, task_thread_info(child)->bpt_addr[i], &insn); + if (ret < 0) + return; + + task_thread_info(child)->bpt_insn[i] = insn; + + ret = write_insn(child, task_thread_info(child)->bpt_addr[i], BREAKINST); + if (ret < 0) + return; + } + + task_thread_info(child)->bpt_nsaved = nsaved; +} + +static void ptrace_cancel_bpt(struct task_struct *child) +{ + int i, nsaved = task_thread_info(child)->bpt_nsaved; + + task_thread_info(child)->bpt_nsaved = 0; + + if (nsaved > 1) { + pr_info("%s: bogus nsaved: %d!\n", __func__, nsaved); + nsaved = 1; + } + + for (i = 0; i < nsaved; i++) { + write_insn(child, task_thread_info(child)->bpt_addr[i], + task_thread_info(child)->bpt_insn[i]); + } +} + +void user_enable_single_step(struct task_struct *child) +{ + set_tsk_thread_flag(child, TIF_SINGLESTEP); + ptrace_set_bpt(child); +} + +void user_disable_single_step(struct task_struct *child) +{ + clear_tsk_thread_flag(child, TIF_SINGLESTEP); + ptrace_cancel_bpt(child); +} + long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f1e985109da0..82d11d88d3a5 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -849,7 +849,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) ret = abi->setup_frame(vdso + abi->vdso->off_sigreturn, ksig, regs, oldset); - signal_setup_done(ret, ksig, 0); + signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); } static void do_signal(struct pt_regs *regs) -- cgit v1.2.3-70-g09d2 From 04e4783fccf4268249bff2c1be9f63013d12153a Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:36 +0100 Subject: MIPS/malta: simplify plat_setup_iocoherency Given that plat_mem_setup runs before earlyparams are handled and malta selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to IO_COHERENCE_DEFAULT at this point. So remove the checking for other options and merge plat_enable_iocoherency into plat_setup_iocoherency to simplify the code a bit. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer --- arch/mips/mti-malta/malta-setup.c | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index e1fb8b534944..4caff9e3b456 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -90,16 +90,15 @@ static void __init fd_activate(void) } #endif -static int __init plat_enable_iocoherency(void) +static void __init plat_setup_iocoherency(void) { - int supported = 0; u32 cfg; if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; pr_info("Enabled Bonito CPU coherency\n"); - supported = 1; + hw_coherentio = 1; } if (strstr(fw_getcmdline(), "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; @@ -118,29 +117,16 @@ static int __init plat_enable_iocoherency(void) /* Nothing special needs to be done to enable coherency */ pr_info("CMP IOCU detected\n"); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); - if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { + if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU) + hw_coherentio = 1; + else pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); - return 0; - } - supported = 1; } - hw_coherentio = supported; - return supported; -} -static void __init plat_setup_iocoherency(void) -{ - if (plat_enable_iocoherency()) { - if (coherentio == IO_COHERENCE_DISABLED) - pr_info("Hardware DMA cache coherency disabled\n"); - else - pr_info("Hardware DMA cache coherency enabled\n"); - } else { - if (coherentio == IO_COHERENCE_ENABLED) - pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); - else - pr_info("Software DMA cache coherency enabled\n"); - } + if (hw_coherentio) + pr_info("Hardware DMA cache coherency enabled\n"); + else + pr_info("Software DMA cache coherency enabled\n"); } static void __init pci_clock_check(void) -- cgit v1.2.3-70-g09d2 From 3440caf5f28c4e4a585dd5a7cead1b7c414973da Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:37 +0100 Subject: MIPS/alchemy: factor out the DMA coherent setup Factor out a alchemy_dma_coherent helper that determines if the platform is DMA coherent. Also stop initializing the hw_coherentio variable, given that is only ever set to a non-zero value by the malta setup code. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer --- arch/mips/alchemy/common/setup.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 0f60efe0481e..c2da68e79844 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -37,6 +37,23 @@ extern void __init board_setup(void); extern void __init alchemy_set_lpj(void); +static bool alchemy_dma_coherent(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + return false; + case ALCHEMY_CPU_AU1200: + /* Au1200 AB USB does not support coherent memory */ + if ((read_c0_prid() & PRID_REV_MASK) == 0) + return false; + return true; + default: + return true; + } +} + void __init plat_mem_setup(void) { alchemy_set_lpj(); @@ -48,20 +65,8 @@ void __init plat_mem_setup(void) /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ - hw_coherentio = 0; - coherentio = IO_COHERENCE_ENABLED; - switch (alchemy_get_cputype()) { - case ALCHEMY_CPU_AU1000: - case ALCHEMY_CPU_AU1500: - case ALCHEMY_CPU_AU1100: - coherentio = IO_COHERENCE_DISABLED; - break; - case ALCHEMY_CPU_AU1200: - /* Au1200 AB USB does not support coherent memory */ - if (0 == (read_c0_prid() & PRID_REV_MASK)) - coherentio = IO_COHERENCE_DISABLED; - break; - } + coherentio = alchemy_dma_coherent() ? + IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED; board_setup(); /* board specific setup */ -- cgit v1.2.3-70-g09d2 From 14ac09a65e19528ca05df56f8e36a4a8d4949795 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:38 +0100 Subject: MIPS: refactor the runtime coherent vs noncoherent DMA indicators Replace the global coherentio enum, and the hw_coherentio (fake) boolean variables with a single boolean dma_default_coherent flag. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer --- arch/mips/alchemy/common/setup.c | 3 +-- arch/mips/include/asm/dma-coherence.h | 24 ++++-------------------- arch/mips/kernel/setup.c | 10 ++++------ arch/mips/mm/c-r4k.c | 8 ++------ arch/mips/mti-malta/malta-setup.c | 6 +++--- arch/mips/pci/pci-alchemy.c | 5 ++--- 6 files changed, 16 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index c2da68e79844..39e5b9cd882b 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -65,8 +65,7 @@ void __init plat_mem_setup(void) /* Clear to obtain best system bus performance */ clear_c0_config(1 << 19); /* Clear Config[OD] */ - coherentio = alchemy_dma_coherent() ? - IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED; + dma_default_coherent = alchemy_dma_coherent(); board_setup(); /* board specific setup */ diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h index 5eaa1fcc878a..846c5ade30d1 100644 --- a/arch/mips/include/asm/dma-coherence.h +++ b/arch/mips/include/asm/dma-coherence.h @@ -9,30 +9,14 @@ #ifndef __ASM_DMA_COHERENCE_H #define __ASM_DMA_COHERENCE_H -enum coherent_io_user_state { - IO_COHERENCE_DEFAULT, - IO_COHERENCE_ENABLED, - IO_COHERENCE_DISABLED, -}; - -#if defined(CONFIG_DMA_PERDEV_COHERENT) -/* Don't provide (hw_)coherentio to avoid misuse */ -#elif defined(CONFIG_DMA_MAYBE_COHERENT) -extern enum coherent_io_user_state coherentio; -extern int hw_coherentio; - +#ifdef CONFIG_DMA_MAYBE_COHERENT +extern bool dma_default_coherent; static inline bool dev_is_dma_coherent(struct device *dev) { - return coherentio == IO_COHERENCE_ENABLED || - (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio); + return dma_default_coherent; } #else -#ifdef CONFIG_DMA_NONCOHERENT -#define coherentio IO_COHERENCE_DISABLED -#else -#define coherentio IO_COHERENCE_ENABLED +#define dma_default_coherent (!IS_ENABLED(CONFIG_DMA_NONCOHERENT)) #endif -#define hw_coherentio 0 -#endif /* CONFIG_DMA_MAYBE_COHERENT */ #endif diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 9a761ba36b6e..6008f45ad081 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -803,14 +803,12 @@ arch_initcall(debugfs_mips); #endif #ifdef CONFIG_DMA_MAYBE_COHERENT -/* User defined DMA coherency from command line. */ -enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; -EXPORT_SYMBOL_GPL(coherentio); -int hw_coherentio; /* Actual hardware supported DMA coherency setting. */ +bool dma_default_coherent; +EXPORT_SYMBOL_GPL(dma_default_coherent); static int __init setcoherentio(char *str) { - coherentio = IO_COHERENCE_ENABLED; + dma_default_coherent = true; pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } @@ -818,7 +816,7 @@ early_param("coherentio", setcoherentio); static int __init setnocoherentio(char *str) { - coherentio = IO_COHERENCE_DISABLED; + dma_default_coherent = true; pr_info("Software DMA cache coherency (command line)\n"); return 0; } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 7b2396249779..bbfab94194b9 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1914,15 +1914,11 @@ void r4k_cache_init(void) __local_flush_icache_user_range = local_r4k_flush_icache_user_range; #ifdef CONFIG_DMA_NONCOHERENT -#ifdef CONFIG_DMA_MAYBE_COHERENT - if (coherentio == IO_COHERENCE_ENABLED || - (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) { + if (dma_default_coherent) { _dma_cache_wback_inv = (void *)cache_noop; _dma_cache_wback = (void *)cache_noop; _dma_cache_inv = (void *)cache_noop; - } else -#endif /* CONFIG_DMA_MAYBE_COHERENT */ - { + } else { _dma_cache_wback_inv = r4k_dma_cache_wback_inv; _dma_cache_wback = r4k_dma_cache_wback_inv; _dma_cache_inv = r4k_dma_cache_inv; diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 4caff9e3b456..1cdcb76d393e 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void) if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; pr_info("Enabled Bonito CPU coherency\n"); - hw_coherentio = 1; + dma_default_coherent = true; } if (strstr(fw_getcmdline(), "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; @@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void) pr_info("CMP IOCU detected\n"); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU) - hw_coherentio = 1; + dma_default_coherent = true; else pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); } - if (hw_coherentio) + if (dma_default_coherent) pr_info("Hardware DMA cache coherency enabled\n"); else pr_info("Software DMA cache coherency enabled\n"); diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index 7285b5667568..54c86b40d304 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -429,9 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev) ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; /* Au1500 revisions older than AD have borked coherent PCI */ - if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && - (read_c0_prid() < 0x01030202) && - (coherentio == IO_COHERENCE_DISABLED)) { + if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 && + read_c0_prid() < 0x01030202 && !dma_default_coherent) { val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val |= PCI_CONFIG_NC; __raw_writel(val, ctx->regs + PCI_REG_CONFIG); -- cgit v1.2.3-70-g09d2 From 6d4e9a8efe3d59f31367d79e970c2f328da139a4 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:39 +0100 Subject: driver core: lift dma_default_coherent into common code Lift the dma_default_coherent variable from the mips architecture code to the driver core. This allows an architecture to sdefault all device to be DMA coherent at run time, even if the kernel is build with support for DMA noncoherent device. By allowing device_initialize to set the ->dma_coherent field to this default the amount of arch hooks required for this behavior can be greatly reduced. Signed-off-by: Christoph Hellwig Acked-by: Greg Kroah-Hartman Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 - arch/mips/alchemy/common/setup.c | 2 +- arch/mips/include/asm/dma-coherence.h | 22 ---------------------- arch/mips/kernel/setup.c | 4 ---- arch/mips/mm/c-r4k.c | 2 +- arch/mips/mm/dma-noncoherent.c | 1 - arch/mips/mti-malta/malta-setup.c | 2 +- arch/mips/pci/pci-alchemy.c | 2 +- arch/mips/pistachio/init.c | 1 - drivers/base/core.c | 6 ++++++ include/linux/dma-map-ops.h | 5 ++--- kernel/dma/Kconfig | 3 --- kernel/dma/mapping.c | 2 ++ 13 files changed, 14 insertions(+), 39 deletions(-) delete mode 100644 arch/mips/include/asm/dma-coherence.h (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 57b06798706c..a6d73c763be1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1163,7 +1163,6 @@ config ARCH_SUPPORTS_UPROBES bool config DMA_MAYBE_COHERENT - select ARCH_HAS_DMA_COHERENCE_H select DMA_NONCOHERENT bool diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 39e5b9cd882b..2388d68786f4 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -28,8 +28,8 @@ #include #include #include +#include /* for dma_default_coherent */ -#include #include #include diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h deleted file mode 100644 index 846c5ade30d1..000000000000 --- a/arch/mips/include/asm/dma-coherence.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006 Ralf Baechle - * - */ -#ifndef __ASM_DMA_COHERENCE_H -#define __ASM_DMA_COHERENCE_H - -#ifdef CONFIG_DMA_MAYBE_COHERENT -extern bool dma_default_coherent; -static inline bool dev_is_dma_coherent(struct device *dev) -{ - return dma_default_coherent; -} -#else -#define dma_default_coherent (!IS_ENABLED(CONFIG_DMA_NONCOHERENT)) -#endif - -#endif diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 6008f45ad081..f0f533294311 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include @@ -803,9 +802,6 @@ arch_initcall(debugfs_mips); #endif #ifdef CONFIG_DMA_MAYBE_COHERENT -bool dma_default_coherent; -EXPORT_SYMBOL_GPL(dma_default_coherent); - static int __init setcoherentio(char *str) { dma_default_coherent = true; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index bbfab94194b9..74b09e801c3a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -19,6 +19,7 @@ #include #include #include +#include /* for dma_default_coherent */ #include #include @@ -35,7 +36,6 @@ #include #include /* for run_uncached() */ #include -#include #include /* diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 38d3d9143b47..90b562753eb8 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -10,7 +10,6 @@ #include #include -#include #include /* diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 1cdcb76d393e..21cb3ac1237b 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -13,8 +13,8 @@ #include #include #include +#include /* for dma_default_coherent */ -#include #include #include #include diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index 54c86b40d304..1c722dd0c130 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -17,8 +17,8 @@ #include #include #include +#include /* for dma_default_coherent */ -#include #include #include diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index 8e83262e9da8..e0bacfc3c6b4 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include diff --git a/drivers/base/core.c b/drivers/base/core.c index 25e08e5f40bd..fb2988f955cb 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -28,6 +28,7 @@ #include #include #include +#include /* for dma_default_coherent */ #include "base.h" #include "power/power.h" @@ -2585,6 +2586,11 @@ void device_initialize(struct device *dev) INIT_LIST_HEAD(&dev->links.suppliers); INIT_LIST_HEAD(&dev->links.defer_sync); dev->links.status = DL_DEV_NO_DRIVER; +#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ + defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ + defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) + dev->dma_coherent = dma_default_coherent; +#endif } EXPORT_SYMBOL_GPL(device_initialize); diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index 70fcd0f610ea..1e98b8c1e055 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -229,11 +229,10 @@ bool dma_free_from_pool(struct device *dev, void *start, size_t size); int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, dma_addr_t dma_start, u64 size); -#ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H -#include -#elif defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ +#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) +extern bool dma_default_coherent; static inline bool dev_is_dma_coherent(struct device *dev) { return dev->dma_coherent; diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 479fc145acfc..77b405508743 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -33,9 +33,6 @@ config NEED_DMA_MAP_STATE config ARCH_DMA_ADDR_T_64BIT def_bool 64BIT || PHYS_ADDR_T_64BIT -config ARCH_HAS_DMA_COHERENCE_H - bool - config ARCH_HAS_DMA_SET_MASK bool diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index f87a89d08654..84de6b1c5fab 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -16,6 +16,8 @@ #include "debug.h" #include "direct.h" +bool dma_default_coherent; + /* * Managed DMA API */ -- cgit v1.2.3-70-g09d2 From a86497d66dd5891cef594744b8d56bc451aac418 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:40 +0100 Subject: MIPS: remove CONFIG_DMA_MAYBE_COHERENT CONFIG_DMA_MAYBE_COHERENT just guards two early init options now. Just enable them unconditionally for CONFIG_DMA_NONCOHERENT. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 8 ++------ arch/mips/kernel/setup.c | 2 +- 2 files changed, 3 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a6d73c763be1..206d34bd5e3f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -184,7 +184,7 @@ config MIPS_ALCHEMY select CEVT_R4K select CSRC_R4K select IRQ_MIPS_CPU - select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is + select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is select MIPS_FIXUP_BIGPHYS_ADDR if PCI select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL @@ -548,7 +548,7 @@ config MIPS_MALTA select CLKSRC_MIPS_GIC select COMMON_CLK select CSRC_R4K - select DMA_MAYBE_COHERENT + select DMA_NONCOHERENT select GENERIC_ISA_DMA select HAVE_PCSPKR_PLATFORM select HAVE_PCI @@ -1162,10 +1162,6 @@ config FW_CFE config ARCH_SUPPORTS_UPROBES bool -config DMA_MAYBE_COHERENT - select DMA_NONCOHERENT - bool - config DMA_PERDEV_COHERENT bool select ARCH_HAS_SETUP_DMA_OPS diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index f0f533294311..fb59188b623f 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -801,7 +801,7 @@ static int __init debugfs_mips(void) arch_initcall(debugfs_mips); #endif -#ifdef CONFIG_DMA_MAYBE_COHERENT +#ifdef CONFIG_DMA_NONCOHERENT static int __init setcoherentio(char *str) { dma_default_coherent = true; -- cgit v1.2.3-70-g09d2 From 4e0664416c70702731734ab8b3e4819a5a2c0486 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 10 Feb 2021 10:56:41 +0100 Subject: MIPS: remove CONFIG_DMA_PERDEV_COHERENT Just select DMA_NONCOHERENT and ARCH_HAS_SETUP_DMA_OPS from the MIPS_GENERIC platform instead. Signed-off-by: Christoph Hellwig Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 3 ++- arch/mips/mm/dma-noncoherent.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 206d34bd5e3f..47715cbaf810 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -126,6 +126,7 @@ choice config MIPS_GENERIC_KERNEL bool "Generic board-agnostic MIPS kernel" + select ARCH_HAS_SETUP_DMA_OPS select MIPS_GENERIC select BOOT_RAW select BUILTIN_DTB @@ -135,7 +136,7 @@ config MIPS_GENERIC_KERNEL select CPU_MIPSR2_IRQ_EI select CPU_MIPSR2_IRQ_VI select CSRC_R4K - select DMA_PERDEV_COHERENT + select DMA_NONCOHERENT select HAVE_PCI select IRQ_MIPS_CPU select MIPS_AUTO_PFN_OFFSET diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c index 90b562753eb8..212f3ce75a6b 100644 --- a/arch/mips/mm/dma-noncoherent.c +++ b/arch/mips/mm/dma-noncoherent.c @@ -135,7 +135,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, } #endif -#ifdef CONFIG_DMA_PERDEV_COHERENT +#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, const struct iommu_ops *iommu, bool coherent) { -- cgit v1.2.3-70-g09d2 From b1468f3071f7312bdc78c380dd01273b5e4459c1 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 10 Feb 2021 17:16:13 +0100 Subject: Revert "MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes" This reverts commit 6ebda44f366478d1eea180d93154e7d97b591f50. All icache flushes in this code paths are done via flush_icache_range(), which only uses normal cache instruction. And this is the correct thing for EVA mode, too. So no need to do set_fs(KERNEL_DS) here. Signed-off-by: Thomas Bogendoerfer Reviewed-by: Christoph Hellwig --- arch/mips/kernel/ftrace.c | 4 ---- arch/mips/kernel/kgdb.c | 18 +----------------- 2 files changed, 1 insertion(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index f57e68f40a34..666b9969c1bd 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -73,7 +73,6 @@ static inline void ftrace_dyn_arch_init_insns(void) static int ftrace_modify_code(unsigned long ip, unsigned int new_code) { int faulted; - mm_segment_t old_fs; /* *(unsigned int *)ip = new_code; */ safe_store_code(new_code, ip, faulted); @@ -81,10 +80,7 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code) if (unlikely(faulted)) return -EFAULT; - old_fs = get_fs(); - set_fs(KERNEL_DS); flush_icache_range(ip, ip + 8); - set_fs(old_fs); return 0; } diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index ea781b29f7f1..de779e23faf2 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -32,7 +32,6 @@ #include #include #include -#include #include static struct hard_trap_info { @@ -210,14 +209,7 @@ void arch_kgdb_breakpoint(void) void kgdb_call_nmi_hook(void *ignored) { - mm_segment_t old_fs; - - old_fs = get_fs(); - set_fs(KERNEL_DS); - kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); - - set_fs(old_fs); } static int compute_signal(int tt) @@ -302,7 +294,6 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, struct die_args *args = (struct die_args *)ptr; struct pt_regs *regs = args->regs; int trap = (regs->cp0_cause & 0x7c) >> 2; - mm_segment_t old_fs; #ifdef CONFIG_KPROBES /* @@ -317,17 +308,11 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, if (user_mode(regs)) return NOTIFY_DONE; - /* Kernel mode. Set correct address limit */ - old_fs = get_fs(); - set_fs(KERNEL_DS); - if (atomic_read(&kgdb_active) != -1) kgdb_nmicallback(smp_processor_id(), regs); - if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs)) { - set_fs(old_fs); + if (kgdb_handle_exception(trap, compute_signal(trap), cmd, regs)) return NOTIFY_DONE; - } if (atomic_read(&kgdb_setting_breakpoint)) if ((trap == 9) && (regs->cp0_epc == (unsigned long)breakinst)) @@ -337,7 +322,6 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, local_irq_enable(); __flush_cache_all(); - set_fs(old_fs); return NOTIFY_STOP; } -- cgit v1.2.3-70-g09d2 From f1b0bf577f46bf6339d63be229aa38e49fc7a611 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 10 Feb 2021 17:16:14 +0100 Subject: MIPS: Simplify EVA cache handling protected_cache_op is only used for flushing user addresses, so we only need to define protected_cache_op different in EVA mode and be done with it. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/r4kcache.h | 67 +++++++--------------------------------- 1 file changed, 11 insertions(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 15ab16f99f28..af3788589ee6 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -23,7 +23,6 @@ #include #include #include -#include /* for uaccess_kernel() */ extern void (*r4k_blast_dcache)(void); extern void (*r4k_blast_icache)(void); @@ -102,14 +101,17 @@ static inline void flush_scache_line(unsigned long addr) cache_op(Hit_Writeback_Inv_SD, addr); } -#define protected_cache_op(op,addr) \ +#ifdef CONFIG_EVA + +#define protected_cache_op(op, addr) \ ({ \ int __err = 0; \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set "MIPS_ISA_ARCH_LEVEL" \n" \ - "1: cache %1, (%2) \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + "1: cachee %1, (%2) \n" \ "2: .insn \n" \ " .set pop \n" \ " .section .fixup,\"ax\" \n" \ @@ -123,17 +125,16 @@ static inline void flush_scache_line(unsigned long addr) : "i" (op), "r" (addr), "i" (-EFAULT)); \ __err; \ }) +#else - -#define protected_cachee_op(op,addr) \ +#define protected_cache_op(op, addr) \ ({ \ int __err = 0; \ __asm__ __volatile__( \ " .set push \n" \ " .set noreorder \n" \ - " .set mips0 \n" \ - " .set eva \n" \ - "1: cachee %1, (%2) \n" \ + " .set "MIPS_ISA_ARCH_LEVEL" \n" \ + "1: cache %1, (%2) \n" \ "2: .insn \n" \ " .set pop \n" \ " .section .fixup,\"ax\" \n" \ @@ -147,6 +148,7 @@ static inline void flush_scache_line(unsigned long addr) : "i" (op), "r" (addr), "i" (-EFAULT)); \ __err; \ }) +#endif /* * The next two are for badland addresses like signal trampolines. @@ -158,11 +160,7 @@ static inline int protected_flush_icache_line(unsigned long addr) return protected_cache_op(Hit_Invalidate_I_Loongson2, addr); default: -#ifdef CONFIG_EVA - return protected_cachee_op(Hit_Invalidate_I, addr); -#else return protected_cache_op(Hit_Invalidate_I, addr); -#endif } } @@ -174,20 +172,12 @@ static inline int protected_flush_icache_line(unsigned long addr) */ static inline int protected_writeback_dcache_line(unsigned long addr) { -#ifdef CONFIG_EVA - return protected_cachee_op(Hit_Writeback_Inv_D, addr); -#else return protected_cache_op(Hit_Writeback_Inv_D, addr); -#endif } static inline int protected_writeback_scache_line(unsigned long addr) { -#ifdef CONFIG_EVA - return protected_cachee_op(Hit_Writeback_Inv_SD, addr); -#else return protected_cache_op(Hit_Writeback_Inv_SD, addr); -#endif } /* @@ -307,43 +297,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, } \ } -#ifndef CONFIG_EVA - __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) - -#else - -#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \ -static inline void protected_blast_##pfx##cache##_range(unsigned long start,\ - unsigned long end) \ -{ \ - unsigned long lsize = cpu_##desc##_line_size(); \ - unsigned long addr = start & ~(lsize - 1); \ - unsigned long aend = (end - 1) & ~(lsize - 1); \ - \ - if (!uaccess_kernel()) { \ - while (1) { \ - protected_cachee_op(hitop, addr); \ - if (addr == aend) \ - break; \ - addr += lsize; \ - } \ - } else { \ - while (1) { \ - protected_cache_op(hitop, addr); \ - if (addr == aend) \ - break; \ - addr += lsize; \ - } \ - \ - } \ -} - -__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) -__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) - -#endif __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ protected_, loongson2_) -- cgit v1.2.3-70-g09d2 From b306c5f560680fb9a4a25b9295d6c67b42d5f2b7 Mon Sep 17 00:00:00 2001 From: Jinyang He Date: Thu, 4 Feb 2021 11:07:13 +0800 Subject: MIPS: Use common way to parse elfcorehdr "elfcorehdr" can be parsed at kernel/crash_dump.c Signed-off-by: Jinyang He Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/setup.c | 49 +++++++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 28 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index fb59188b623f..279be0153f8b 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -405,34 +406,32 @@ static int __init early_parse_memmap(char *p) } early_param("memmap", early_parse_memmap); -#ifdef CONFIG_PROC_VMCORE -static unsigned long setup_elfcorehdr, setup_elfcorehdr_size; -static int __init early_parse_elfcorehdr(char *p) +static void __init mips_reserve_vmcore(void) { +#ifdef CONFIG_PROC_VMCORE phys_addr_t start, end; u64 i; - setup_elfcorehdr = memparse(p, &p); - - for_each_mem_range(i, &start, &end) { - if (setup_elfcorehdr >= start && setup_elfcorehdr < end) { - /* - * Reserve from the elf core header to the end of - * the memory segment, that should all be kdump - * reserved memory. - */ - setup_elfcorehdr_size = end - setup_elfcorehdr; - break; + if (!elfcorehdr_size) { + for_each_mem_range(i, &start, &end) { + if (elfcorehdr_addr >= start && elfcorehdr_addr < end) { + /* + * Reserve from the elf core header to the end of + * the memory segment, that should all be kdump + * reserved memory. + */ + elfcorehdr_size = end - elfcorehdr_addr; + break; + } } } - /* - * If we don't find it in the memory map, then we shouldn't - * have to worry about it, as the new kernel won't use it. - */ - return 0; -} -early_param("elfcorehdr", early_parse_elfcorehdr); + + pr_info("Reserving %ldKB of memory at %ldKB for kdump\n", + (unsigned long)elfcorehdr_size >> 10, (unsigned long)elfcorehdr_addr >> 10); + + memblock_reserve(elfcorehdr_addr, elfcorehdr_size); #endif +} #ifdef CONFIG_KEXEC @@ -654,13 +653,7 @@ static void __init arch_mem_init(char **cmdline_p) */ memblock_set_current_limit(PFN_PHYS(max_low_pfn)); -#ifdef CONFIG_PROC_VMCORE - if (setup_elfcorehdr && setup_elfcorehdr_size) { - printk(KERN_INFO "kdump reserved memory at %lx-%lx\n", - setup_elfcorehdr, setup_elfcorehdr_size); - memblock_reserve(setup_elfcorehdr, setup_elfcorehdr_size); - } -#endif + mips_reserve_vmcore(); mips_parse_crashkernel(); #ifdef CONFIG_KEXEC -- cgit v1.2.3-70-g09d2 From e6ce4a480c76b34cb015d5470a1b4cb6ec5cbc16 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 13 Feb 2021 15:02:31 +0100 Subject: MIPS: kernel: Drop kgdb_call_nmi_hook With the removal of set_fs() calls kgdb_call_nmi_hook() is now the same as the default implementation, so we can remove it. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/kgdb.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index de779e23faf2..09a2d7bb9eef 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -207,11 +207,6 @@ void arch_kgdb_breakpoint(void) ".set\treorder"); } -void kgdb_call_nmi_hook(void *ignored) -{ - kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); -} - static int compute_signal(int tt) { struct hard_trap_info *ht; -- cgit v1.2.3-70-g09d2 From b0c2793bad0b5f10be2fc5f56df827e0c1bbf4af Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Thu, 18 Feb 2021 11:57:44 +0100 Subject: Revert "MIPS: Add basic support for ptrace single step" This reverts commit 7c86ff9925cbc83e8a21f164a8fdc2767e03531e. There are too many special cases for MIPS not covered by this patch. In the end it might be better to implement single stepping in userland than emulating it in the kernel. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/ptrace.h | 2 - arch/mips/include/asm/thread_info.h | 5 -- arch/mips/kernel/ptrace.c | 108 ------------------------------------ arch/mips/kernel/signal.c | 2 +- 4 files changed, 1 insertion(+), 116 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h index c733daefd015..daf3cf244ea9 100644 --- a/arch/mips/include/asm/ptrace.h +++ b/arch/mips/include/asm/ptrace.h @@ -186,6 +186,4 @@ static inline void user_stack_pointer_set(struct pt_regs *regs, regs->regs[29] = val; } -#define arch_has_single_step() (1) - #endif /* _ASM_PTRACE_H */ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index bd4dbb5b2900..e2c352da3877 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -35,10 +35,6 @@ struct thread_info { */ struct pt_regs *regs; long syscall; /* syscall number */ - - int bpt_nsaved; - unsigned long bpt_addr[1]; /* breakpoint handling */ - unsigned int bpt_insn[1]; }; /* @@ -121,7 +117,6 @@ static inline struct thread_info *current_thread_info(void) #define TIF_UPROBE 6 /* breakpointed or singlestepping */ #define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ -#define TIF_SINGLESTEP 10 /* restore singlestep on return to user mode */ #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_NOHZ 19 /* in adaptive nohz mode */ diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index f29141922001..db7c5be1d4a3 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -45,15 +45,10 @@ #include #include #include -#include #define CREATE_TRACE_POINTS #include -#include "probes-common.h" - -#define BREAKINST 0x0000000d - /* * Called by kernel/ptrace.c when detaching.. * @@ -63,7 +58,6 @@ void ptrace_disable(struct task_struct *child) { /* Don't load the watchpoint registers for the ex-child. */ clear_tsk_thread_flag(child, TIF_LOAD_WATCH); - user_disable_single_step(child); } /* @@ -1078,108 +1072,6 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task) #endif } -static int read_insn(struct task_struct *task, unsigned long addr, unsigned int *insn) -{ - int copied = access_process_vm(task, addr, insn, - sizeof(unsigned int), FOLL_FORCE); - - if (copied != sizeof(unsigned int)) { - pr_err("failed to read instruction from 0x%lx\n", addr); - return -EIO; - } - - return 0; -} - -static int write_insn(struct task_struct *task, unsigned long addr, unsigned int insn) -{ - int copied = access_process_vm(task, addr, &insn, - sizeof(unsigned int), FOLL_FORCE | FOLL_WRITE); - - if (copied != sizeof(unsigned int)) { - pr_err("failed to write instruction to 0x%lx\n", addr); - return -EIO; - } - - return 0; -} - -static int insn_has_delayslot(union mips_instruction insn) -{ - return __insn_has_delay_slot(insn); -} - -static void ptrace_set_bpt(struct task_struct *child) -{ - union mips_instruction mips_insn = { 0 }; - struct pt_regs *regs; - unsigned long pc; - unsigned int insn; - int i, ret, nsaved = 0; - - regs = task_pt_regs(child); - pc = regs->cp0_epc; - - ret = read_insn(child, pc, &insn); - if (ret < 0) - return; - - if (insn_has_delayslot(mips_insn)) { - pr_info("executing branch insn\n"); - ret = __compute_return_epc(regs); - if (ret < 0) - return; - task_thread_info(child)->bpt_addr[nsaved++] = regs->cp0_epc; - } else { - pr_info("executing normal insn\n"); - task_thread_info(child)->bpt_addr[nsaved++] = pc + 4; - } - - /* install breakpoints */ - for (i = 0; i < nsaved; i++) { - ret = read_insn(child, task_thread_info(child)->bpt_addr[i], &insn); - if (ret < 0) - return; - - task_thread_info(child)->bpt_insn[i] = insn; - - ret = write_insn(child, task_thread_info(child)->bpt_addr[i], BREAKINST); - if (ret < 0) - return; - } - - task_thread_info(child)->bpt_nsaved = nsaved; -} - -static void ptrace_cancel_bpt(struct task_struct *child) -{ - int i, nsaved = task_thread_info(child)->bpt_nsaved; - - task_thread_info(child)->bpt_nsaved = 0; - - if (nsaved > 1) { - pr_info("%s: bogus nsaved: %d!\n", __func__, nsaved); - nsaved = 1; - } - - for (i = 0; i < nsaved; i++) { - write_insn(child, task_thread_info(child)->bpt_addr[i], - task_thread_info(child)->bpt_insn[i]); - } -} - -void user_enable_single_step(struct task_struct *child) -{ - set_tsk_thread_flag(child, TIF_SINGLESTEP); - ptrace_set_bpt(child); -} - -void user_disable_single_step(struct task_struct *child) -{ - clear_tsk_thread_flag(child, TIF_SINGLESTEP); - ptrace_cancel_bpt(child); -} - long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 82d11d88d3a5..f1e985109da0 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -849,7 +849,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) ret = abi->setup_frame(vdso + abi->vdso->off_sigreturn, ksig, regs, oldset); - signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP)); + signal_setup_done(ret, ksig, 0); } static void do_signal(struct pt_regs *regs) -- cgit v1.2.3-70-g09d2