From 19b85c086019e54c1976fdaf56e8923f7e568091 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 23 Oct 2012 08:17:20 +0200 Subject: arm: mvebu: support for the PlatHome OpenBlocks AX3-4 board This platform, available in Japan from PlatHome, has a dual-core Armada XP, the MV78260. For now, only the two serial ports and the three front LEDs are supported. Support for SMP, network, SATA, USB and other peripherals will be added as drivers for them become available for Armada XP in mainline. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Tested-by: Gregory CLEMENT --- This is 3.8 material. Changes since v2: * Renamed the .dts file to armada-xp-openblocks-ax3-4.dts * Removed the compatible string from armada-370-xp.c (which now only lists the common SoC compatible string) Changes since v1: * Renamed the board to OpenBlocks AX3-4, since there is a variant called AX3-2 which has less RAM, and no mini PCIe port. Requested by Andrew Lunn. * Fix the amount of memory to 3 GB. In fact, the board has 1 GB soldered, and 2 GB in a SODIMM slot (which is therefore removable). But as the board is delivered as is, we'll assume it has 3 GB of memory by default. --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 69 ++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f37cf9fa5fa0..718584df3398 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -44,7 +44,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ - armada-xp-db.dtb + armada-xp-db.dtb \ + armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ imx53-ard.dtb \ imx53-evk.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts new file mode 100644 index 000000000000..cb86853fef95 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -0,0 +1,69 @@ +/* + * Device Tree file for OpenBlocks AX3-4 board + * + * Copyright (C) 2012 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "armada-xp-mv78260.dtsi" + +/ { + model = "PlatHome OpenBlocks AX3-4 board"; + compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0xC0000000>; /* 3 GB */ + }; + + soc { + serial@d0012000 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@d0012100 { + clock-frequency = <250000000>; + status = "okay"; + }; + pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; + }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + red_led { + label = "red_led"; + gpios = <&gpio1 17 1>; + default-state = "off"; + }; + + yellow_led { + label = "yellow_led"; + gpios = <&gpio1 19 1>; + default-state = "off"; + }; + + green_led { + label = "green_led"; + gpios = <&gpio1 21 1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From e3e37bcab910a68616bc33145ed5c333825053ac Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Sat, 27 Oct 2012 18:22:45 +0200 Subject: arm: mvebu: support for the Globalscale Mirabox board This platform, available from Globalscale has an Armada 370. For now, only the serial port is supported. Support for network, USB and other peripherals will be added as drivers for them become available for Armada 370 in mainline. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni --- This is 3.8 material. Changes from original version posted by Gregory: * Renamed .dts file to armada-370-mirabox.dts * Change compatible string to 'globalscale,mirabox' * Remove compatible string from armada-370-xp.c * Removed references to MBX0001 --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-370-mirabox.dts | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm/boot/dts/armada-370-mirabox.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 718584df3398..32d1d404924a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \ msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ + armada-370-mirabox.dtb \ armada-xp-db.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts new file mode 100644 index 000000000000..9eef8dd61158 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -0,0 +1,37 @@ +/* + * Device Tree file for Globalscale Mirabox + * + * Gregory CLEMENT + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "armada-370.dtsi" + +/ { + model = "Globalscale Mirabox"; + compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + serial@d0012000 { + clock-frequency = <200000000>; + status = "okay"; + }; + timer@d0020300 { + clock-frequency = <600000000>; + status = "okay"; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 92ece1cdd27eee32c53630dc6af6d031b55be199 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 9 Nov 2012 16:29:17 +0100 Subject: arm: mvebu: fix compatible string in armada-370-xp.dtsi All the Device Tree files for Armada 370 and XP SoCs and boards use the "armada-370-xp" common compatible string, except armada-370-xp.dtsi which was specifying "armada_370_xp". Fix this inconsistency by making armada-370-xp.dtsi declare a compatible string of "armada-370-xp" like everyone else. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Tested-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 16cc82cdaa81..b113e0b87783 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -20,7 +20,7 @@ / { model = "Marvell Armada 370 and XP SoC"; - compatible = "marvell,armada_370_xp"; + compatible = "marvell,armada-370-xp"; cpus { cpu@0 { -- cgit v1.2.3-70-g09d2 From 61505e117bb5d626ed7db2e9daa791e184d81bd3 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 9 Nov 2012 16:26:26 +0100 Subject: arm: mvebu: don't list all boards in dt compat field for Armada 370/XP Instead of listing explicitly all boards in the .dt_compat field of the DT_MACHINE_START structure for Armada 370/XP, use instead a compatible string that is common to all boards using the Armada 370/XP. This allows to add new boards by just using a different Device Tree, without having to modify the source code of the kernel. Note that the name of the array containing the compatible string is also renamed, to reflect the fact that it no longer contains the list of all boards. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Tested-by: Gregory CLEMENT --- arch/arm/mach-mvebu/armada-370-xp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 49d791548ad6..29c27cd71018 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -46,9 +46,8 @@ static void __init armada_370_xp_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char * const armada_370_xp_dt_board_dt_compat[] = { - "marvell,a370-db", - "marvell,axp-db", +static const char * const armada_370_xp_dt_compat[] = { + "marvell,armada-370-xp", NULL, }; @@ -59,5 +58,5 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)") .handle_irq = armada_370_xp_handle_irq, .timer = &armada_370_xp_timer, .restart = mvebu_restart, - .dt_compat = armada_370_xp_dt_board_dt_compat, + .dt_compat = armada_370_xp_dt_compat, MACHINE_END -- cgit v1.2.3-70-g09d2 From 8c4340fcfb3e40372101a608ccd906e456ed3fcd Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 12 Nov 2012 12:03:38 +0100 Subject: arm: mvebu: fix typo in machine name for Armada 370/XP Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Tested-by: Gregory CLEMENT --- arch/arm/mach-mvebu/armada-370-xp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 29c27cd71018..a2f5bbc0d2e5 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -51,7 +51,7 @@ static const char * const armada_370_xp_dt_compat[] = { NULL, }; -DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)") +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, .init_irq = armada_370_xp_init_irq, -- cgit v1.2.3-70-g09d2 From 323c10101f584f9efccecaa723047b87262fc1a7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 4 Sep 2012 15:06:43 +0200 Subject: arm: mvebu: add Ethernet controllers using mvneta driver for Armada 370/XP The Armada 370 SoC has two network units, while the Armada XP has four network units. The first two network units are common to both the Armada XP and Armada 370, so they are added to armada-370-xp.dtsi, while the other two network units are specific to the Armada XP and therefore added to armada-xp.dtsi. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-xp.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/armada-xp.dtsi | 14 ++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 16cc82cdaa81..643101b73306 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -68,6 +68,27 @@ compatible = "marvell,armada-addr-decoding-controller"; reg = <0xd0020000 0x258>; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0xd0072004 0x4>; + }; + + ethernet@d0070000 { + compatible = "marvell,armada-370-neta"; + reg = <0xd0070000 0x2500>; + interrupts = <8>; + status = "disabled"; + }; + + ethernet@d0074000 { + compatible = "marvell,armada-370-neta"; + reg = <0xd0074000 0x2500>; + interrupts = <10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 71d6b5d0daf1..3bbbccfa2c8f 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -51,5 +51,19 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x500>; }; + + ethernet@d0030000 { + compatible = "marvell,armada-370-neta"; + reg = <0xd0030000 0x2500>; + interrupts = <12>; + status = "disabled"; + }; + + ethernet@d0034000 { + compatible = "marvell,armada-370-neta"; + reg = <0xd0034000 0x2500>; + interrupts = <14>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-70-g09d2 From f01959a96f23d3e005cfb0ab154695a3e014cc13 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 4 Sep 2012 15:06:44 +0200 Subject: arm: mvebu: enable Ethernet controllers on Armada 370/XP eval boards This patch enables the two network interfaces of the Armada 370 official Marvell evaluation platform, and the four network interfaces of the Armada XP official Marvell evaluation platform. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-db.dts | 23 ++++++++++++++++++++ arch/arm/boot/dts/armada-xp-db.dts | 43 +++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index fffd5c2a3041..76362f733d7b 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -38,5 +38,28 @@ clock-frequency = <600000000>; status = "okay"; }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + ethernet@d0070000 { + clock-frequency = <200000000>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@d0074000 { + clock-frequency = <200000000>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index b1fc728515e9..b614bd054822 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -46,5 +46,48 @@ clock-frequency = <250000000>; status = "okay"; }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <25>; + }; + + phy3: ethernet-phy@3 { + reg = <27>; + }; + }; + + ethernet@d0070000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@d0074000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + ethernet@d0030000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@d0034000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; }; }; -- cgit v1.2.3-70-g09d2 From f69c92f4fe4a6c9730554b3a7bb3253e7360ca32 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 9 Nov 2012 15:12:47 +0100 Subject: arm: mvebu: enable Ethernet controllers on OpenBlocks AX3-4 platform The PlatHome OpenBlocks AX3-4 platform has 4 Ethernet ports, connected to a single quad-port PHY through SGMII. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index cb86853fef95..bb8d83cfbb50 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -65,5 +65,48 @@ linux,default-trigger = "heartbeat"; }; }; + + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + }; + }; + + ethernet@d0070000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@d0074000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@d0030000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@d0034000 { + clock-frequency = <250000000>; + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; }; }; -- cgit v1.2.3-70-g09d2 From 9f32cccc67590ccda30529bcbcea5c22d95c00a6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 12 Nov 2012 15:22:54 +0100 Subject: arm: mvebu: enable Ethernet controllers on Mirabox platform The Globalscale Mirabox platform has two Ethernet interfaces, connected to the SoC with a RGMII interface. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-mirabox.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 9eef8dd61158..8554dbee2640 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -33,5 +33,26 @@ clock-frequency = <600000000>; status = "okay"; }; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + ethernet@d0070000 { + clock-frequency = <200000000>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@d0074000 { + clock-frequency = <200000000>; + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; }; }; -- cgit v1.2.3-70-g09d2 From 9d2027830c6306b079d5e888d40ec1f2efebd6ad Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Sat, 17 Nov 2012 15:22:24 +0100 Subject: clk: armada-370-xp: add support for clock framework Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Tested-by Gregory CLEMENT --- arch/arm/boot/dts/armada-370.dtsi | 15 ++++++++++++++ arch/arm/boot/dts/armada-xp-mv78230.dtsi | 12 +++++++++++ arch/arm/boot/dts/armada-xp-mv78260.dtsi | 19 ++++++++++++++++++ arch/arm/boot/dts/armada-xp-mv78460.dtsi | 34 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/armada-xp.dtsi | 20 +++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 4 ++++ arch/arm/mach-mvebu/armada-370-xp.c | 9 ++++++++- 7 files changed, 112 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 2069151afe01..175df2887076 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -75,5 +75,20 @@ #interrupts-cells = <2>; interrupts = <91>; }; + + coreclk: mvebu-sar@d0018230 { + compatible = "marvell,armada-370-core-clock"; + reg = <0xd0018230 0x08>; + #clock-cells = <1>; + }; + + gateclk: clock-gating-control@d0018220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0xd0018220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + }; }; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index ea355192be6f..c45c7b4dc352 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -24,6 +24,18 @@ gpio1 = &gpio1; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; + } + soc { pinctrl { compatible = "marvell,mv78230-pinctrl"; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 2057863f3dfa..a2aee5707377 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -25,6 +25,25 @@ gpio2 = &gpio2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + }; + }; + soc { pinctrl { compatible = "marvell,mv78260-pinctrl"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index ffac98373792..da03a129243a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -25,6 +25,40 @@ gpio2 = &gpio2; }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <2>; + clocks = <&cpuclk 2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <3>; + clocks = <&cpuclk 3>; + }; + }; + soc { pinctrl { compatible = "marvell,mv78460-pinctrl"; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 71d6b5d0daf1..f51554e80009 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -47,6 +47,26 @@ marvell,timer-25Mhz; }; + coreclk: mvebu-sar@d0018230 { + compatible = "marvell,armada-xp-core-clock"; + reg = <0xd0018230 0x08>; + #clock-cells = <1>; + }; + + cpuclk: clock-complex@d0018700 { + #clock-cells = <1>; + compatible = "marvell,armada-xp-cpu-clock"; + reg = <0xd0018700 0xA0>; + clocks = <&coreclk 1>; + }; + + gateclk: clock-gating-control@d0018220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0xd0018220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + system-controller@d0018200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x500>; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 416d46ef7ebd..79299cd94f0f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -9,6 +9,10 @@ config ARCH_MVEBU select PINCTRL select PLAT_ORION select SPARSE_IRQ + select CLKDEV_LOOKUP + select MVEBU_CLK_CORE + select MVEBU_CLK_CPU + select MVEBU_CLK_GATING if ARCH_MVEBU diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 49d791548ad6..3292d6da5dc7 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -37,8 +38,14 @@ void __init armada_370_xp_map_io(void) iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); } +void __init armada_370_xp_timer_and_clk_init(void) +{ + mvebu_clocks_init(); + armada_370_xp_timer_init(); +} + struct sys_timer armada_370_xp_timer = { - .init = armada_370_xp_timer_init, + .init = armada_370_xp_timer_and_clk_init, }; static void __init armada_370_xp_dt_init(void) -- cgit v1.2.3-70-g09d2 From 307c2bf467e3682c6df1b8186365224fd2d581d3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Sat, 17 Nov 2012 15:22:25 +0100 Subject: clocksource: convert time-armada-370-xp to clk framework Signed-off-by: Gregory CLEMENT Tested-by Gregory CLEMENT --- Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt | 1 + arch/arm/boot/dts/armada-370-db.dts | 4 ---- arch/arm/boot/dts/armada-370-xp.dtsi | 1 + drivers/clocksource/time-armada-370-xp.c | 11 ++++++----- 4 files changed, 8 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt index 8b6ea2267c94..64830118b013 100644 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Should be "marvell,armada-370-xp-timer" - interrupts: Should contain the list of Global Timer interrupts - reg: Should contain the base address of the Global Timer registers +- clocks: clock driving the timer hardware Optional properties: - marvell,timer-25Mhz: Tells whether the Global timer supports the 25 diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index fffd5c2a3041..4a31b0396623 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -34,9 +34,5 @@ clock-frequency = <200000000>; status = "okay"; }; - timer@d0020300 { - clock-frequency = <600000000>; - status = "okay"; - }; }; }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 16cc82cdaa81..94b4b9e03571 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -62,6 +62,7 @@ compatible = "marvell,armada-370-xp-timer"; reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; + clocks = <&coreclk 2>; }; addr-decoding@d0020000 { diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c index 4674f94957cd..a4605fd7e303 100644 --- a/drivers/clocksource/time-armada-370-xp.c +++ b/drivers/clocksource/time-armada-370-xp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void) u32 u; struct device_node *np; unsigned int timer_clk; - int ret; np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer"); timer_base = of_iomap(np, 0); WARN_ON(!timer_base); @@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void) timer_base + TIMER_CTRL_OFF); timer_clk = 25000000; } else { - u32 clk = 0; - ret = of_property_read_u32(np, "clock-frequency", &clk); - WARN_ON(!clk || ret < 0); + unsigned long rate = 0; + struct clk *clk = of_clk_get(np, 0); + WARN_ON(IS_ERR(clk)); + rate = clk_get_rate(clk); u = readl(timer_base + TIMER_CTRL_OFF); writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ), timer_base + TIMER_CTRL_OFF); - timer_clk = clk / TIMER_DIVIDER; + timer_clk = rate / TIMER_DIVIDER; } /* We use timer 0 as clocksource, and timer 1 for -- cgit v1.2.3-70-g09d2 From 5b03df9ace680d7cdd34a69dfd85ca5f74159d18 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Sat, 17 Nov 2012 15:22:27 +0100 Subject: ARM: dove: switch to DT clock providers With true DT clock providers available switch Dove clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT at all. Therefore, some clock aliases are created until the devices also move to DT. Signed-off-by: Sebastian Hesselbarth --- arch/arm/Kconfig | 1 + arch/arm/boot/dts/dove.dtsi | 20 ++++++++++++++ arch/arm/mach-dove/Kconfig | 2 ++ arch/arm/mach-dove/common.c | 63 ++++++++++++++++++++++++++++++++++----------- 4 files changed, 71 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ade7e924bef5..05900997af90 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -533,6 +533,7 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select ARCH_REQUIRE_GPIOLIB + select COMMON_CLK_DOVE select CPU_V7 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 5a00022383e7..b524ee377f83 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -31,6 +31,19 @@ reg = <0x20204 0x04>, <0x20214 0x04>; }; + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; + }; + + gate_clk: clock-gating-control@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; @@ -100,6 +113,7 @@ cell-index = <0>; interrupts = <6>; reg = <0x10600 0x28>; + clocks = <&core_clk 0>; status = "disabled"; }; @@ -110,6 +124,7 @@ cell-index = <1>; interrupts = <5>; reg = <0x14600 0x28>; + clocks = <&core_clk 0>; status = "disabled"; }; @@ -121,6 +136,7 @@ interrupts = <11>; clock-frequency = <400000>; timeout-ms = <1000>; + clocks = <&core_clk 0>; status = "disabled"; }; @@ -128,6 +144,7 @@ compatible = "marvell,dove-sdhci"; reg = <0x92000 0x100>; interrupts = <35>, <37>; + clocks = <&gate_clk 8>; status = "disabled"; }; @@ -135,6 +152,7 @@ compatible = "marvell,dove-sdhci"; reg = <0x90000 0x100>; interrupts = <36>, <38>; + clocks = <&gate_clk 9>; status = "disabled"; }; @@ -142,6 +160,7 @@ compatible = "marvell,orion-sata"; reg = <0xa0000 0x2400>; interrupts = <62>; + clocks = <&gate_clk 3>; nr-ports = <1>; status = "disabled"; }; @@ -152,6 +171,7 @@ <0xc8000000 0x800>; reg-names = "regs", "sram"; interrupts = <31>; + clocks = <&gate_clk 15>; status = "okay"; }; }; diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 00154e74ce6b..603c5fd99e8a 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -17,6 +17,8 @@ config MACH_CM_A510 config MACH_DOVE_DT bool "Marvell Dove Flattened Device Tree" + select MVEBU_CLK_CORE + select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index f723fe13d0f0..6a2c4dc413a8 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -376,19 +377,52 @@ void dove_restart(char mode, const char *cmd) #if defined(CONFIG_MACH_DOVE_DT) /* - * Auxdata required until real OF clock provider + * There are still devices that doesn't even know about DT, + * get clock gates here and add a clock lookup. */ -struct of_dev_auxdata dove_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), - OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL), - OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), - OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", - NULL), - OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL), - OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL), - OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL), - {}, -}; +static void __init dove_legacy_clk_init(void) +{ + struct device_node *np = of_find_compatible_node(NULL, NULL, + "marvell,dove-gating-clock"); + struct of_phandle_args clkspec; + + clkspec.np = np; + clkspec.args_count = 1; + + clkspec.args[0] = CLOCK_GATING_BIT_USB0; + orion_clkdev_add(NULL, "orion-ehci.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_USB1; + orion_clkdev_add(NULL, "orion-ehci.1", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_GBE; + orion_clkdev_add(NULL, "mv643xx_eth_port.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; + orion_clkdev_add("0", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_PCIE1; + orion_clkdev_add("1", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_XOR0; + orion_clkdev_add(NULL, "mv_xor_shared.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CLOCK_GATING_BIT_XOR1; + orion_clkdev_add(NULL, "mv_xor_shared.1", + of_clk_get_from_provider(&clkspec)); +} + +static void __init dove_of_clk_init(void) +{ + mvebu_clocks_init(); + dove_legacy_clk_init(); +} static struct mv643xx_eth_platform_data dove_dt_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, @@ -405,7 +439,7 @@ static void __init dove_dt_init(void) dove_setup_cpu_mbus(); /* Setup root of clk tree */ - dove_clk_init(); + dove_of_clk_init(); /* Internal devices not ported to DT yet */ dove_rtc_init(); @@ -417,8 +451,7 @@ static void __init dove_dt_init(void) dove_ehci1_init(); dove_pcie_init(1, 1); - of_platform_populate(NULL, of_default_bus_match_table, - dove_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const dove_dt_board_compat[] = { -- cgit v1.2.3-70-g09d2 From 1611f872513735ac7105535689c0dd668fbf1c04 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 17 Nov 2012 15:22:28 +0100 Subject: ARM: Kirkwood: switch to DT clock providers With true DT clock providers available switch Kirkwood clock setup in DT- enabled boards. While AUXDATA can be removed completely from bus probing, some devices still don't know about DT. Therefore, some clkdev aliases are created until these devices also move to DT. Signed-off-by: Andrew Lunn --- arch/arm/boot/dts/kirkwood.dtsi | 22 ++++++++++ arch/arm/mach-kirkwood/Kconfig | 2 + arch/arm/mach-kirkwood/board-dt.c | 71 +++++++++++++++++++++++++------ arch/arm/plat-orion/include/plat/common.h | 1 + 4 files changed, 83 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 4e5b8154a5be..7a9fac0d4251 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -19,6 +19,12 @@ #address-cells = <1>; #size-cells = <1>; + core_clk: core-clocks@10030 { + compatible = "marvell,kirkwood-core-clock"; + reg = <0x10030 0x4>; + #clock-cells = <1>; + }; + gpio0: gpio@10100 { compatible = "marvell,orion-gpio"; #gpio-cells = <2>; @@ -42,6 +48,7 @@ reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <33>; + clocks = <&gate_clk 7>; /* set clock-frequency in board dts */ status = "disabled"; }; @@ -51,6 +58,7 @@ reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <34>; + clocks = <&gate_clk 7>; /* set clock-frequency in board dts */ status = "disabled"; }; @@ -68,12 +76,21 @@ cell-index = <0>; interrupts = <23>; reg = <0x10600 0x28>; + clocks = <&gate_clk 7>; status = "disabled"; }; + gate_clk: clock-gating-control@2011c { + compatible = "marvell,kirkwood-gating-clock"; + reg = <0x2011c 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; + clocks = <&gate_clk 7>; status = "okay"; }; @@ -81,6 +98,8 @@ compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; status = "disabled"; }; @@ -94,6 +113,7 @@ reg = <0x3000000 0x400>; chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ + clocks = <&gate_clk 7>; status = "disabled"; }; @@ -104,6 +124,7 @@ #size-cells = <0>; interrupts = <29>; clock-frequency = <100000>; + clocks = <&gate_clk 7>; status = "disabled"; }; @@ -113,6 +134,7 @@ <0xf5000000 0x800>; reg-names = "regs", "sram"; interrupts = <22>; + clocks = <&gate_clk 17>; status = "okay"; }; }; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 50bca5032b7e..2833492eb273 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -46,6 +46,8 @@ config MACH_GURUPLUG config ARCH_KIRKWOOD_DT bool "Marvell Kirkwood Flattened Device Tree" + select MVEBU_CLK_CORE + select MVEBU_CLK_GATING select USE_OF help Say 'Y' here if you want your kernel to support the diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index d94872fed8c0..8bdfaa4db091 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -14,11 +14,15 @@ #include #include #include +#include +#include #include #include #include #include +#include #include +#include #include "common.h" static struct of_device_id kirkwood_dt_match_table[] __initdata = { @@ -26,16 +30,58 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = { { } }; -struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), - OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", - NULL), - OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL), - OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL), - OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL), - OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL), - {}, -}; +/* + * There are still devices that doesn't know about DT yet. Get clock + * gates here and add a clock lookup alias, so that old platform + * devices still work. +*/ + +static void __init kirkwood_legacy_clk_init(void) +{ + + struct device_node *np = of_find_compatible_node( + NULL, NULL, "marvell,kirkwood-gating-clock"); + + struct of_phandle_args clkspec; + + clkspec.np = np; + clkspec.args_count = 1; + + clkspec.args[0] = CGC_BIT_GE0; + orion_clkdev_add(NULL, "mv643xx_eth_port.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_PEX0; + orion_clkdev_add("0", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_USB0; + orion_clkdev_add(NULL, "orion-ehci.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_XOR0; + orion_clkdev_add(NULL, "mv_xor_shared.0", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_XOR1; + orion_clkdev_add(NULL, "mv_xor_shared.1", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_PEX1; + orion_clkdev_add("1", "pcie", + of_clk_get_from_provider(&clkspec)); + + clkspec.args[0] = CGC_BIT_GE1; + orion_clkdev_add(NULL, "mv643xx_eth_port.1", + of_clk_get_from_provider(&clkspec)); + +} + +static void __init kirkwood_of_clk_init(void) +{ + mvebu_clocks_init(); + kirkwood_legacy_clk_init(); +} static void __init kirkwood_dt_init(void) { @@ -54,7 +100,7 @@ static void __init kirkwood_dt_init(void) kirkwood_l2_init(); /* Setup root of clk tree */ - kirkwood_clk_init(); + kirkwood_of_clk_init(); /* internal devices that every board has */ kirkwood_xor0_init(); @@ -94,8 +140,7 @@ static void __init kirkwood_dt_init(void) if (of_machine_is_compatible("keymile,km_kirkwood")) km_kirkwood_init(); - of_platform_populate(NULL, kirkwood_dt_match_table, - kirkwood_auxdata_lookup, NULL); + of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL); } static const char *kirkwood_dt_board_compat[] = { diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 6bbc3fe5f58e..e06fc5fefa14 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -12,6 +12,7 @@ #include struct dsa_platform_data; +struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, -- cgit v1.2.3-70-g09d2 From 53d2f8899f71a1b2ca4788cd74845daa683efb2e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 26 Oct 2012 14:30:46 +0200 Subject: arm: mvebu: increase atomic coherent pool size for armada 370/XP For Armada 370/XP we have the same problem that for the commit cb01b63, so we applied the same solution: "The default 256 KiB coherent pool may be too small for some of the Kirkwood devices, so increase it to make sure that devices will be able to allocate their buffers with GFP_ATOMIC flag" Signed-off-by: Gregory CLEMENT Acked-by: Marek Szyprowski --- arch/arm/mach-mvebu/armada-370-xp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 3292d6da5dc7..cd6eac17fb67 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,16 @@ void __init armada_370_xp_timer_and_clk_init(void) armada_370_xp_timer_init(); } +void __init armada_370_xp_init_early(void) +{ + /* + * Some Armada 370/XP devices allocate their coherent buffers + * from atomic context. Increase size of atomic coherent pool + * to make sure such the allocations won't fail. + */ + init_dma_coherent_pool_size(SZ_1M); +} + struct sys_timer armada_370_xp_timer = { .init = armada_370_xp_timer_and_clk_init, }; @@ -62,6 +73,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = { DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)") .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, + .init_early = armada_370_xp_init_early, .init_irq = armada_370_xp_init_irq, .handle_irq = armada_370_xp_handle_irq, .timer = &armada_370_xp_timer, -- cgit v1.2.3-70-g09d2 From a6a6de1a0a8479ad5c31392a9896dfd735e3c5f5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 26 Oct 2012 14:30:47 +0200 Subject: arm: mvebu: SATA support: SoC-level DT data for Armada 370/XP Signed-off-by: Gregory CLEMENT Signed-off-by: Lior Amsalem Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-xp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 94b4b9e03571..0abc8a16fc25 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -69,6 +69,16 @@ compatible = "marvell,armada-addr-decoding-controller"; reg = <0xd0020000 0x258>; }; + + sata@d00a0000 { + compatible = "marvell,orion-sata"; + reg = <0xd00a0000 0x2400>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; + status = "disabled"; + }; + }; }; -- cgit v1.2.3-70-g09d2 From 5872c6fe65626f7375249befe928e3e042192861 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 26 Oct 2012 14:30:48 +0200 Subject: arm: mvebu: SATA support: mvebu_defconfig update Signed-off-by: Gregory CLEMENT Signed-off-by: Lior Amsalem Signed-off-by: Thomas Petazzoni --- arch/arm/configs/multi_v7_defconfig | 2 ++ arch/arm/configs/mvebu_defconfig | 3 +++ 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 159f75fc4377..dbea6f4efe9f 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -17,8 +17,10 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_NET=y +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_HIGHBANK=y +CONFIG_SATA_MV=y CONFIG_NETDEVICES=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 3458752c4bb2..cdec70600994 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -20,6 +20,9 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_VFP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_MV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y -- cgit v1.2.3-70-g09d2 From 3d82daaaa6c7b91a534a54c7d123fe419155bf98 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 26 Oct 2012 14:30:49 +0200 Subject: arm: mvebu: SATA support: board-level DT data for Armada 370/XP boards Add the SATA device tree bindings for - Armada XP evaluation board (DB-78460-BP) - Armada 370 evaluation board (DB-88F6710-BP-DDR3) Signed-off-by: Gregory CLEMENT Signed-off-by: Lior Amsalem Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-db.dts | 4 ++++ arch/arm/boot/dts/armada-xp-db.dts | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 4a31b0396623..cfc080777da1 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -34,5 +34,9 @@ clock-frequency = <200000000>; status = "okay"; }; + sata@d00a0000 { + nr-ports = <2>; + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index b1fc728515e9..e59f14f14dd0 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -46,5 +46,9 @@ clock-frequency = <250000000>; status = "okay"; }; + sata@d00a0000 { + nr-ports = <2>; + status = "okay"; + }; }; }; -- cgit v1.2.3-70-g09d2 From af19e148be5e2d7acf2d6322cce74e85be87d603 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 29 Oct 2012 17:45:21 +0100 Subject: arm: plat-orion: convert the registration of the xor0 engine to the single driver Instead of registering one 'mv_xor_shared' device for the XOR engine, and then two 'mv_xor' devices for the XOR channels, pass the channels properties as platform_data for the main 'mv_xor_shared' device. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 94 ++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 52 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index b8a688cad4c2..800af19c51c5 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -636,61 +636,43 @@ static struct resource orion_xor0_shared_resources[] = { }, { .name = "xor 0 high", .flags = IORESOURCE_MEM, + }, { + .name = "irq channel 0", + .flags = IORESOURCE_IRQ, + }, { + .name = "irq channel 1", + .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_xor0_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), - .resource = orion_xor0_shared_resources, -}; - -static struct resource orion_xor00_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion_xor00_data = { - .shared = &orion_xor0_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; +static struct platform_device orion_xor0_shared; -static struct platform_device orion_xor00_channel = { - .name = MV_XOR_NAME, - .id = 0, - .num_resources = ARRAY_SIZE(orion_xor00_resources), - .resource = orion_xor00_resources, - .dev = { - .dma_mask = &orion_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion_xor00_data, +static struct mv_xor_platform_data orion_xor0_channels_pdata[2] = { + { + .shared = &orion_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, }, -}; - -static struct resource orion_xor01_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, + { + .shared = &orion_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, }, }; -static struct mv_xor_platform_data orion_xor01_data = { - .shared = &orion_xor0_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, +static struct mv_xor_shared_platform_data orion_xor0_pdata = { + .channels = orion_xor0_channels_pdata, }; -static struct platform_device orion_xor01_channel = { - .name = MV_XOR_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(orion_xor01_resources), - .resource = orion_xor01_resources, - .dev = { - .dma_mask = &orion_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion_xor01_data, +static struct platform_device orion_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), + .resource = orion_xor0_shared_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor0_pdata, }, }; @@ -704,15 +686,23 @@ void __init orion_xor0_init(unsigned long mapbase_low, orion_xor0_shared_resources[1].start = mapbase_high; orion_xor0_shared_resources[1].end = mapbase_high + 0xff; - orion_xor00_resources[0].start = irq_0; - orion_xor00_resources[0].end = irq_0; - orion_xor01_resources[0].start = irq_1; - orion_xor01_resources[0].end = irq_1; + orion_xor0_shared_resources[2].start = irq_0; + orion_xor0_shared_resources[2].end = irq_0; + orion_xor0_shared_resources[3].start = irq_1; + orion_xor0_shared_resources[3].end = irq_1; - platform_device_register(&orion_xor0_shared); + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, orion_xor0_channels_pdata[0].cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_channels_pdata[0].cap_mask); - orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel, - &orion_xor01_data, &orion_xor01_channel); + dma_cap_set(DMA_MEMSET, orion_xor0_channels_pdata[1].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor0_channels_pdata[1].cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_channels_pdata[1].cap_mask); + + platform_device_register(&orion_xor0_shared); } /***************************************************************************** -- cgit v1.2.3-70-g09d2 From dd2c57b822bc0fc999f95c57933e4c597e765b0a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Oct 2012 11:11:36 +0100 Subject: arm: plat-orion: convert the registration of the xor1 engine to the single driver Instead of registering one 'mv_xor_shared' device for the XOR engine, and then two 'mv_xor' devices for the XOR channels, pass the channels properties as platform_data for the main 'mv_xor_shared' device. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 94 ++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 52 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 800af19c51c5..afbbb97937ea 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -715,61 +715,43 @@ static struct resource orion_xor1_shared_resources[] = { }, { .name = "xor 1 high", .flags = IORESOURCE_MEM, + }, { + .name = "irq channel 0", + .flags = IORESOURCE_IRQ, + }, { + .name = "irq channel 1", + .flags = IORESOURCE_IRQ, }, }; -static struct platform_device orion_xor1_shared = { - .name = MV_XOR_SHARED_NAME, - .id = 1, - .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), - .resource = orion_xor1_shared_resources, -}; - -static struct resource orion_xor10_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct mv_xor_platform_data orion_xor10_data = { - .shared = &orion_xor1_shared, - .hw_id = 0, - .pool_size = PAGE_SIZE, -}; +static struct platform_device orion_xor1_shared; -static struct platform_device orion_xor10_channel = { - .name = MV_XOR_NAME, - .id = 2, - .num_resources = ARRAY_SIZE(orion_xor10_resources), - .resource = orion_xor10_resources, - .dev = { - .dma_mask = &orion_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion_xor10_data, +static struct mv_xor_platform_data orion_xor1_channels_pdata[2] = { + { + .shared = &orion_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, }, -}; - -static struct resource orion_xor11_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, + { + .shared = &orion_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, }, }; -static struct mv_xor_platform_data orion_xor11_data = { - .shared = &orion_xor1_shared, - .hw_id = 1, - .pool_size = PAGE_SIZE, +static struct mv_xor_shared_platform_data orion_xor1_pdata = { + .channels = orion_xor1_channels_pdata, }; -static struct platform_device orion_xor11_channel = { - .name = MV_XOR_NAME, - .id = 3, - .num_resources = ARRAY_SIZE(orion_xor11_resources), - .resource = orion_xor11_resources, - .dev = { - .dma_mask = &orion_xor_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = &orion_xor11_data, +static struct platform_device orion_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), + .resource = orion_xor1_shared_resources, + .dev = { + .dma_mask = &orion_xor_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = &orion_xor1_pdata, }, }; @@ -783,15 +765,23 @@ void __init orion_xor1_init(unsigned long mapbase_low, orion_xor1_shared_resources[1].start = mapbase_high; orion_xor1_shared_resources[1].end = mapbase_high + 0xff; - orion_xor10_resources[0].start = irq_0; - orion_xor10_resources[0].end = irq_0; - orion_xor11_resources[0].start = irq_1; - orion_xor11_resources[0].end = irq_1; + orion_xor1_shared_resources[2].start = irq_0; + orion_xor1_shared_resources[2].end = irq_0; + orion_xor1_shared_resources[3].start = irq_1; + orion_xor1_shared_resources[3].end = irq_1; - platform_device_register(&orion_xor1_shared); + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, orion_xor1_channels_pdata[0].cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_channels_pdata[0].cap_mask); - orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel, - &orion_xor11_data, &orion_xor11_channel); + dma_cap_set(DMA_MEMSET, orion_xor1_channels_pdata[1].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor1_channels_pdata[1].cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_channels_pdata[1].cap_mask); + + platform_device_register(&orion_xor1_shared); } /***************************************************************************** -- cgit v1.2.3-70-g09d2 From c08f1495c886f70f99af7fdcbabe612b31b97d4a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Oct 2012 11:12:46 +0100 Subject: arm: plat-orion: remove unused orion_xor_init_channels() Now that xor0 and xor1 are registered in a single driver manner, the orion_xor_init_channels() function has become useless. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index afbbb97937ea..c6e6666986ff 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -606,26 +606,6 @@ void __init orion_wdt_init(void) ****************************************************************************/ static u64 orion_xor_dmamask = DMA_BIT_MASK(32); -void __init orion_xor_init_channels( - struct mv_xor_platform_data *orion_xor0_data, - struct platform_device *orion_xor0_channel, - struct mv_xor_platform_data *orion_xor1_data, - struct platform_device *orion_xor1_channel) -{ - /* - * two engines can't do memset simultaneously, this limitation - * satisfied by removing memset support from one of the engines. - */ - dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask); - dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask); - platform_device_register(orion_xor0_channel); - - dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask); - dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask); - dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask); - platform_device_register(orion_xor1_channel); -} - /***************************************************************************** * XOR0 ****************************************************************************/ -- cgit v1.2.3-70-g09d2 From 2ccc469cfecee291707dd50e5842cbf206bc17d7 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 31 Oct 2012 13:24:41 +0100 Subject: dma: mv_xor: remove 'shared' from mv_xor_platform_data This member of the platform_data structure is no longer used, so get rid of it. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 8 -------- include/linux/platform_data/dma-mv_xor.h | 1 - 2 files changed, 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index c6e6666986ff..5a66211d523c 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -625,16 +625,12 @@ static struct resource orion_xor0_shared_resources[] = { }, }; -static struct platform_device orion_xor0_shared; - static struct mv_xor_platform_data orion_xor0_channels_pdata[2] = { { - .shared = &orion_xor0_shared, .hw_id = 0, .pool_size = PAGE_SIZE, }, { - .shared = &orion_xor0_shared, .hw_id = 1, .pool_size = PAGE_SIZE, }, @@ -704,16 +700,12 @@ static struct resource orion_xor1_shared_resources[] = { }, }; -static struct platform_device orion_xor1_shared; - static struct mv_xor_platform_data orion_xor1_channels_pdata[2] = { { - .shared = &orion_xor1_shared, .hw_id = 0, .pool_size = PAGE_SIZE, }, { - .shared = &orion_xor1_shared, .hw_id = 1, .pool_size = PAGE_SIZE, }, diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index 6abe5f9326b6..4a0980b14c9b 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -13,7 +13,6 @@ #define MV_XOR_SHARED_NAME "mv_xor_shared" struct mv_xor_platform_data { - struct platform_device *shared; int hw_id; dma_cap_mask_t cap_mask; size_t pool_size; -- cgit v1.2.3-70-g09d2 From e39f6ec1f9c1d6a7011adf6d95d8d80bad0586b1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Oct 2012 11:56:26 +0100 Subject: dma: mv_xor: rename mv_xor_platform_data to mv_xor_channel_data mv_xor_platform_data used to be the platform_data structure associated to the 'mv_xor' driver. This driver no longer exists, and this data structure really contains the properties of each XOR channel part of a given XOR engine. Therefore 'struct mv_xor_channel_data' is a more appropriate name. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 28 ++++++++++++++-------------- drivers/dma/mv_xor.c | 2 +- include/linux/platform_data/dma-mv_xor.h | 4 ++-- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 5a66211d523c..7ffbe77c52cb 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -625,7 +625,7 @@ static struct resource orion_xor0_shared_resources[] = { }, }; -static struct mv_xor_platform_data orion_xor0_channels_pdata[2] = { +static struct mv_xor_channel_data orion_xor0_channels_data[2] = { { .hw_id = 0, .pool_size = PAGE_SIZE, @@ -637,7 +637,7 @@ static struct mv_xor_platform_data orion_xor0_channels_pdata[2] = { }; static struct mv_xor_shared_platform_data orion_xor0_pdata = { - .channels = orion_xor0_channels_pdata, + .channels = orion_xor0_channels_data, }; static struct platform_device orion_xor0_shared = { @@ -671,12 +671,12 @@ void __init orion_xor0_init(unsigned long mapbase_low, * two engines can't do memset simultaneously, this limitation * satisfied by removing memset support from one of the engines. */ - dma_cap_set(DMA_MEMCPY, orion_xor0_channels_pdata[0].cap_mask); - dma_cap_set(DMA_XOR, orion_xor0_channels_pdata[0].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask); - dma_cap_set(DMA_MEMSET, orion_xor0_channels_pdata[1].cap_mask); - dma_cap_set(DMA_MEMCPY, orion_xor0_channels_pdata[1].cap_mask); - dma_cap_set(DMA_XOR, orion_xor0_channels_pdata[1].cap_mask); + dma_cap_set(DMA_MEMSET, orion_xor0_channels_data[1].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask); + dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask); platform_device_register(&orion_xor0_shared); } @@ -700,7 +700,7 @@ static struct resource orion_xor1_shared_resources[] = { }, }; -static struct mv_xor_platform_data orion_xor1_channels_pdata[2] = { +static struct mv_xor_channel_data orion_xor1_channels_data[2] = { { .hw_id = 0, .pool_size = PAGE_SIZE, @@ -712,7 +712,7 @@ static struct mv_xor_platform_data orion_xor1_channels_pdata[2] = { }; static struct mv_xor_shared_platform_data orion_xor1_pdata = { - .channels = orion_xor1_channels_pdata, + .channels = orion_xor1_channels_data, }; static struct platform_device orion_xor1_shared = { @@ -746,12 +746,12 @@ void __init orion_xor1_init(unsigned long mapbase_low, * two engines can't do memset simultaneously, this limitation * satisfied by removing memset support from one of the engines. */ - dma_cap_set(DMA_MEMCPY, orion_xor1_channels_pdata[0].cap_mask); - dma_cap_set(DMA_XOR, orion_xor1_channels_pdata[0].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask); - dma_cap_set(DMA_MEMSET, orion_xor1_channels_pdata[1].cap_mask); - dma_cap_set(DMA_MEMCPY, orion_xor1_channels_pdata[1].cap_mask); - dma_cap_set(DMA_XOR, orion_xor1_channels_pdata[1].cap_mask); + dma_cap_set(DMA_MEMSET, orion_xor1_channels_data[1].cap_mask); + dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask); + dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask); platform_device_register(&orion_xor1_shared); } diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index be3907bdef14..c7926e417281 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1300,7 +1300,7 @@ static int mv_xor_shared_probe(struct platform_device *pdev) if (pdata && pdata->channels) { for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { - struct mv_xor_platform_data *cd; + struct mv_xor_channel_data *cd; int irq; cd = &pdata->channels[i]; diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index 4a0980b14c9b..40ea3d5f5b9f 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -12,14 +12,14 @@ #define MV_XOR_SHARED_NAME "mv_xor_shared" -struct mv_xor_platform_data { +struct mv_xor_channel_data { int hw_id; dma_cap_mask_t cap_mask; size_t pool_size; }; struct mv_xor_shared_platform_data { - struct mv_xor_platform_data *channels; + struct mv_xor_channel_data *channels; }; #endif -- cgit v1.2.3-70-g09d2 From 7dde453d628687c0e991cfc55c9fd299a804aee6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Oct 2012 11:58:14 +0100 Subject: dma: mv_xor: rename mv_xor_shared_platform_data to mv_xor_platform_data 'struct mv_xor_shared_platform_data' used to be the platform_data structure for the 'mv_xor_shared', but this driver is going to be renamed simply 'mv_xor', so also rename its platform_data structure accordingly. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 4 ++-- drivers/dma/mv_xor.c | 2 +- include/linux/platform_data/dma-mv_xor.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 7ffbe77c52cb..edd57a68fa8c 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -636,7 +636,7 @@ static struct mv_xor_channel_data orion_xor0_channels_data[2] = { }, }; -static struct mv_xor_shared_platform_data orion_xor0_pdata = { +static struct mv_xor_platform_data orion_xor0_pdata = { .channels = orion_xor0_channels_data, }; @@ -711,7 +711,7 @@ static struct mv_xor_channel_data orion_xor1_channels_data[2] = { }, }; -static struct mv_xor_shared_platform_data orion_xor1_pdata = { +static struct mv_xor_platform_data orion_xor1_pdata = { .channels = orion_xor1_channels_data, }; diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index c7926e417281..ac598168b21f 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1254,7 +1254,7 @@ static int mv_xor_shared_probe(struct platform_device *pdev) { const struct mbus_dram_target_info *dram; struct mv_xor_shared_private *msp; - struct mv_xor_shared_platform_data *pdata = pdev->dev.platform_data; + struct mv_xor_platform_data *pdata = pdev->dev.platform_data; struct resource *res; int i, ret; diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index 40ea3d5f5b9f..82a5f4b84afe 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -18,7 +18,7 @@ struct mv_xor_channel_data { size_t pool_size; }; -struct mv_xor_shared_platform_data { +struct mv_xor_platform_data { struct mv_xor_channel_data *channels; }; -- cgit v1.2.3-70-g09d2 From 0dddee7a7d42192267ebef0fe15be8b296b665c8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Oct 2012 11:59:42 +0100 Subject: dma: mv_xor: change the driver name to 'mv_xor' Since we got rid of the per-XOR channel 'mv_xor' driver, now the per-XOR engine driver that used to be called 'mv_xor_shared' can simply be named 'mv_xor'. Signed-off-by: Thomas Petazzoni --- arch/arm/mach-dove/common.c | 9 +++++---- arch/arm/mach-kirkwood/board-dt.c | 5 +++-- arch/arm/mach-kirkwood/common.c | 4 ++-- arch/arm/plat-orion/common.c | 4 ++-- drivers/dma/mv_xor.c | 2 +- include/linux/platform_data/dma-mv_xor.h | 2 +- 6 files changed, 14 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 6a2c4dc413a8..f4ac5b06014b 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -124,8 +125,8 @@ static void __init dove_clk_init(void) orion_clkdev_add(NULL, "mv_crypto", crypto); orion_clkdev_add(NULL, "dove-ac97", ac97); orion_clkdev_add(NULL, "dove-pdma", pdma); - orion_clkdev_add(NULL, "mv_xor_shared.0", xor0); - orion_clkdev_add(NULL, "mv_xor_shared.1", xor1); + orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); + orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); } /***************************************************************************** @@ -410,11 +411,11 @@ static void __init dove_legacy_clk_init(void) of_clk_get_from_provider(&clkspec)); clkspec.args[0] = CLOCK_GATING_BIT_XOR0; - orion_clkdev_add(NULL, "mv_xor_shared.0", + orion_clkdev_add(NULL, MV_XOR_NAME ".0", of_clk_get_from_provider(&clkspec)); clkspec.args[0] = CLOCK_GATING_BIT_XOR1; - orion_clkdev_add(NULL, "mv_xor_shared.1", + orion_clkdev_add(NULL, MV_XOR_NAME ".1", of_clk_get_from_provider(&clkspec)); } diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 8bdfaa4db091..294ad5a4fd98 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include "common.h" @@ -60,11 +61,11 @@ static void __init kirkwood_legacy_clk_init(void) of_clk_get_from_provider(&clkspec)); clkspec.args[0] = CGC_BIT_XOR0; - orion_clkdev_add(NULL, "mv_xor_shared.0", + orion_clkdev_add(NULL, MV_XOR_NAME ".0", of_clk_get_from_provider(&clkspec)); clkspec.args[0] = CGC_BIT_XOR1; - orion_clkdev_add(NULL, "mv_xor_shared.1", + orion_clkdev_add(NULL, MV_XOR_NAME ".1", of_clk_get_from_provider(&clkspec)); clkspec.args[0] = CGC_BIT_PEX1; diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 2c6c218fb79e..401dac1a8d80 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -260,8 +260,8 @@ void __init kirkwood_clk_init(void) orion_clkdev_add(NULL, "orion_nand", runit); orion_clkdev_add(NULL, "mvsdio", sdio); orion_clkdev_add(NULL, "mv_crypto", crypto); - orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0); - orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1); + orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); + orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); orion_clkdev_add("0", "pcie", pex0); orion_clkdev_add("1", "pcie", pex1); orion_clkdev_add(NULL, "kirkwood-i2s", audio); diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index edd57a68fa8c..31517cef8c4d 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -641,7 +641,7 @@ static struct mv_xor_platform_data orion_xor0_pdata = { }; static struct platform_device orion_xor0_shared = { - .name = MV_XOR_SHARED_NAME, + .name = MV_XOR_NAME, .id = 0, .num_resources = ARRAY_SIZE(orion_xor0_shared_resources), .resource = orion_xor0_shared_resources, @@ -716,7 +716,7 @@ static struct mv_xor_platform_data orion_xor1_pdata = { }; static struct platform_device orion_xor1_shared = { - .name = MV_XOR_SHARED_NAME, + .name = MV_XOR_NAME, .id = 1, .num_resources = ARRAY_SIZE(orion_xor1_shared_resources), .resource = orion_xor1_shared_resources, diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index ac598168b21f..0ed5183eb5a3 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1361,7 +1361,7 @@ static struct platform_driver mv_xor_shared_driver = { .remove = mv_xor_shared_remove, .driver = { .owner = THIS_MODULE, - .name = MV_XOR_SHARED_NAME, + .name = MV_XOR_NAME, }, }; diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index 82a5f4b84afe..367bb216c4a7 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -10,7 +10,7 @@ #include #include -#define MV_XOR_SHARED_NAME "mv_xor_shared" +#define MV_XOR_NAME "mv_xor" struct mv_xor_channel_data { int hw_id; -- cgit v1.2.3-70-g09d2 From 9aedbdbab39c8aa58c0b2a0791fb10df6eebc123 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 15 Nov 2012 15:36:37 +0100 Subject: dma: mv_xor: remove hw_id field from platform_data There is no need for the platform_data to give this ID, it is simply the channel number, so we can compute it inside the driver when registering the channels. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 4 ---- drivers/dma/mv_xor.c | 6 +++--- include/linux/platform_data/dma-mv_xor.h | 1 - 3 files changed, 3 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 31517cef8c4d..09d836060bf4 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -627,11 +627,9 @@ static struct resource orion_xor0_shared_resources[] = { static struct mv_xor_channel_data orion_xor0_channels_data[2] = { { - .hw_id = 0, .pool_size = PAGE_SIZE, }, { - .hw_id = 1, .pool_size = PAGE_SIZE, }, }; @@ -702,11 +700,9 @@ static struct resource orion_xor1_shared_resources[] = { static struct mv_xor_channel_data orion_xor1_channels_data[2] = { { - .hw_id = 0, .pool_size = PAGE_SIZE, }, { - .hw_id = 1, .pool_size = PAGE_SIZE, }, }; diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index a6a5a28574c4..fc983bf38438 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1088,7 +1088,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) static struct mv_xor_chan * mv_xor_channel_add(struct mv_xor_device *xordev, struct platform_device *pdev, - int hw_id, dma_cap_mask_t cap_mask, + int idx, dma_cap_mask_t cap_mask, size_t pool_size, int irq) { int ret = 0; @@ -1101,7 +1101,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, goto err_free_dma; } - mv_chan->idx = hw_id; + mv_chan->idx = idx; dma_dev = &mv_chan->dmadev; @@ -1295,7 +1295,7 @@ static int mv_xor_probe(struct platform_device *pdev) } xordev->channels[i] = - mv_xor_channel_add(xordev, pdev, cd->hw_id, + mv_xor_channel_add(xordev, pdev, i, cd->cap_mask, cd->pool_size, irq); if (IS_ERR(xordev->channels[i])) { diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index 367bb216c4a7..b18dc2496186 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -13,7 +13,6 @@ #define MV_XOR_NAME "mv_xor" struct mv_xor_channel_data { - int hw_id; dma_cap_mask_t cap_mask; size_t pool_size; }; -- cgit v1.2.3-70-g09d2 From b503fa01990f6875640339d8f4ba98dbc068f821 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 15 Nov 2012 15:55:30 +0100 Subject: dma: mv_xor: remove the pool_size from platform_data The pool_size is always PAGE_SIZE, and since it is a software configuration paramter (and not a hardware description parameter), we cannot make it part of the Device Tree binding, so we'd better remove it from the platform_data as well. Signed-off-by: Thomas Petazzoni --- arch/arm/plat-orion/common.c | 18 ++---------------- drivers/dma/mv_xor.c | 15 ++++++--------- drivers/dma/mv_xor.h | 1 + include/linux/platform_data/dma-mv_xor.h | 1 - 4 files changed, 9 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 09d836060bf4..2d4b6414609f 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -625,14 +625,7 @@ static struct resource orion_xor0_shared_resources[] = { }, }; -static struct mv_xor_channel_data orion_xor0_channels_data[2] = { - { - .pool_size = PAGE_SIZE, - }, - { - .pool_size = PAGE_SIZE, - }, -}; +static struct mv_xor_channel_data orion_xor0_channels_data[2]; static struct mv_xor_platform_data orion_xor0_pdata = { .channels = orion_xor0_channels_data, @@ -698,14 +691,7 @@ static struct resource orion_xor1_shared_resources[] = { }, }; -static struct mv_xor_channel_data orion_xor1_channels_data[2] = { - { - .pool_size = PAGE_SIZE, - }, - { - .pool_size = PAGE_SIZE, - }, -}; +static struct mv_xor_channel_data orion_xor1_channels_data[2]; static struct mv_xor_platform_data orion_xor1_pdata = { .channels = orion_xor1_channels_data, diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index fc983bf38438..ec741b4607e2 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -603,7 +603,7 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan) int idx; struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); struct mv_xor_desc_slot *slot = NULL; - int num_descs_in_pool = mv_chan->pool_size/MV_XOR_SLOT_SIZE; + int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; /* Allocate descriptor slots */ idx = mv_chan->slots_allocated; @@ -1074,7 +1074,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) dma_async_device_unregister(&mv_chan->dmadev); - dma_free_coherent(dev, mv_chan->pool_size, + dma_free_coherent(dev, MV_XOR_POOL_SIZE, mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, @@ -1088,8 +1088,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) static struct mv_xor_chan * mv_xor_channel_add(struct mv_xor_device *xordev, struct platform_device *pdev, - int idx, dma_cap_mask_t cap_mask, - size_t pool_size, int irq) + int idx, dma_cap_mask_t cap_mask, int irq) { int ret = 0; struct mv_xor_chan *mv_chan; @@ -1109,9 +1108,8 @@ mv_xor_channel_add(struct mv_xor_device *xordev, * note: writecombine gives slightly better performance, but * requires that we explicitly flush the writes */ - mv_chan->pool_size = pool_size; mv_chan->dma_desc_pool_virt = - dma_alloc_writecombine(&pdev->dev, mv_chan->pool_size, + dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool, GFP_KERNEL); if (!mv_chan->dma_desc_pool_virt) return ERR_PTR(-ENOMEM); @@ -1193,7 +1191,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, return mv_chan; err_free_dma: - dma_free_coherent(&pdev->dev, pool_size, + dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); return ERR_PTR(ret); } @@ -1296,8 +1294,7 @@ static int mv_xor_probe(struct platform_device *pdev) xordev->channels[i] = mv_xor_channel_add(xordev, pdev, i, - cd->cap_mask, - cd->pool_size, irq); + cd->cap_mask, irq); if (IS_ERR(xordev->channels[i])) { ret = PTR_ERR(xordev->channels[i]); goto err_channel_add; diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index dab9f30e564a..698b4487b348 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h @@ -24,6 +24,7 @@ #include #define USE_TIMER +#define MV_XOR_POOL_SIZE PAGE_SIZE #define MV_XOR_SLOT_SIZE 64 #define MV_XOR_THRESHOLD 1 #define MV_XOR_MAX_CHANNELS 2 diff --git a/include/linux/platform_data/dma-mv_xor.h b/include/linux/platform_data/dma-mv_xor.h index b18dc2496186..8ec18f64e396 100644 --- a/include/linux/platform_data/dma-mv_xor.h +++ b/include/linux/platform_data/dma-mv_xor.h @@ -14,7 +14,6 @@ struct mv_xor_channel_data { dma_cap_mask_t cap_mask; - size_t pool_size; }; struct mv_xor_platform_data { -- cgit v1.2.3-70-g09d2 From c896ed0fd72505104db3e78fffe3d8c604d25277 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sun, 18 Nov 2012 11:44:57 +0100 Subject: arm: kirkwood: Convert XOR instantiation to DT. Use DT to describe the two XOR DMA engines on Kirkwood. Remove the C code initialization. Signed-off-by: Andrew Lunn Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/kirkwood.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-kirkwood/board-dt.c | 13 ------------- 2 files changed, 40 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 7a9fac0d4251..2388f9936ebf 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -94,6 +94,46 @@ status = "okay"; }; + xor@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60A00 0x100>; + status = "okay"; + clocks = <&gate_clk 8>; + + xor00 { + interrupts = <5>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <6>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0xd0B00 0x100>; + status = "okay"; + clocks = <&gate_clk 16>; + + xor00 { + interrupts = <7>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <8>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 294ad5a4fd98..9826904277b8 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "common.h" @@ -60,14 +59,6 @@ static void __init kirkwood_legacy_clk_init(void) orion_clkdev_add(NULL, "orion-ehci.0", of_clk_get_from_provider(&clkspec)); - clkspec.args[0] = CGC_BIT_XOR0; - orion_clkdev_add(NULL, MV_XOR_NAME ".0", - of_clk_get_from_provider(&clkspec)); - - clkspec.args[0] = CGC_BIT_XOR1; - orion_clkdev_add(NULL, MV_XOR_NAME ".1", - of_clk_get_from_provider(&clkspec)); - clkspec.args[0] = CGC_BIT_PEX1; orion_clkdev_add("1", "pcie", of_clk_get_from_provider(&clkspec)); @@ -103,10 +94,6 @@ static void __init kirkwood_dt_init(void) /* Setup root of clk tree */ kirkwood_of_clk_init(); - /* internal devices that every board has */ - kirkwood_xor0_init(); - kirkwood_xor1_init(); - #ifdef CONFIG_KEXEC kexec_reinit = kirkwood_enable_pcie; #endif -- cgit v1.2.3-70-g09d2 From 49f175b9fed5dbfc370057ae0a2a57d1be750c0a Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Mon, 19 Nov 2012 09:37:24 +0100 Subject: arm: dove: Convert Dove to DT XOR DMA engine With DT support for Marvell XOR DMA engine, make use of it on Dove. Also remove the now redundant code in DT board init for xor engines. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/dove.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-dove/common.c | 10 ---------- 2 files changed, 42 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index b524ee377f83..b1cfa52ae223 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -174,5 +174,47 @@ clocks = <&gate_clk 15>; status = "okay"; }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memset; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memset; + dmacap,memcpy; + dmacap,xor; + }; + }; }; }; diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index f4ac5b06014b..89f4f993cd03 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -409,14 +409,6 @@ static void __init dove_legacy_clk_init(void) clkspec.args[0] = CLOCK_GATING_BIT_PCIE1; orion_clkdev_add("1", "pcie", of_clk_get_from_provider(&clkspec)); - - clkspec.args[0] = CLOCK_GATING_BIT_XOR0; - orion_clkdev_add(NULL, MV_XOR_NAME ".0", - of_clk_get_from_provider(&clkspec)); - - clkspec.args[0] = CLOCK_GATING_BIT_XOR1; - orion_clkdev_add(NULL, MV_XOR_NAME ".1", - of_clk_get_from_provider(&clkspec)); } static void __init dove_of_clk_init(void) @@ -444,8 +436,6 @@ static void __init dove_dt_init(void) /* Internal devices not ported to DT yet */ dove_rtc_init(); - dove_xor0_init(); - dove_xor1_init(); dove_ge00_init(&dove_dt_ge00_data); dove_ehci0_init(); -- cgit v1.2.3-70-g09d2 From 0122eee890e28e466d682cdc4e1d125cc0ad9fdf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 20 Nov 2012 16:03:12 +0100 Subject: arm: mvebu: add XOR engines to Armada 370 .dtsi Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 175df2887076..7fbac28b01f3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -89,6 +89,42 @@ #clock-cells = <1>; }; + xor@d0060800 { + compatible = "marvell,orion-xor"; + reg = <0xd0060800 0x100 + 0xd0060A00 0x100>; + status = "okay"; + xor00 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@d0060900 { + compatible = "marvell,orion-xor"; + reg = <0xd0060900 0x100 + 0xd0060b00 0x100>; + status = "okay"; + + xor10 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; }; }; -- cgit v1.2.3-70-g09d2 From a1d53dab4f5b37c800d7a20c56e84a96180a8ea6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 20 Nov 2012 16:03:19 +0100 Subject: arm: mvebu: add XOR engines to Armada XP .dtsi Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index f51554e80009..a09998523d40 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -71,5 +71,45 @@ compatible = "marvell,armada-370-xp-system-controller"; reg = <0xd0018200 0x500>; }; + + xor@d0060900 { + compatible = "marvell,orion-xor"; + reg = <0xd0060900 0x100 + 0xd0060b00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + xor@d00f0900 { + compatible = "marvell,orion-xor"; + reg = <0xd00F0900 0x100 + 0xd00F0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; }; }; -- cgit v1.2.3-70-g09d2 From 4aa935a2cfd164362680eb4a7919c89a4b8ddb48 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 19 Nov 2012 14:18:09 +0100 Subject: arm: mvebu: add 'clocks' property to Ethernet nodes for Armada 370/XP SoCs The mvneta driver now understands a standard 'clocks' clock pointer property in the Device Tree nodes for the Ethernet devices, so we add the right clock reference for the different Ethernet ports of the Armada 370/XP SoCs. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-xp.dtsi | 2 ++ arch/arm/boot/dts/armada-xp.dtsi | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 4c248e30fcb3..4ff108151278 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -90,6 +90,7 @@ compatible = "marvell,armada-370-neta"; reg = <0xd0070000 0x2500>; interrupts = <8>; + clocks = <&gateclk 4>; status = "disabled"; }; @@ -97,6 +98,7 @@ compatible = "marvell,armada-370-neta"; reg = <0xd0074000 0x2500>; interrupts = <10>; + clocks = <&gateclk 3>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index fbe30f5e98a8..3744ea18be72 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -76,6 +76,7 @@ compatible = "marvell,armada-370-neta"; reg = <0xd0030000 0x2500>; interrupts = <12>; + clocks = <&gateclk 2>; status = "disabled"; }; @@ -83,6 +84,7 @@ compatible = "marvell,armada-370-neta"; reg = <0xd0034000 0x2500>; interrupts = <14>; + clocks = <&gateclk 1>; status = "disabled"; }; }; -- cgit v1.2.3-70-g09d2 From 42db1215eeb1dc591ef5120bc2dbbeeee5ee41e1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 19 Nov 2012 14:19:29 +0100 Subject: arm: mvebu: remove 'clock-frequency' properties from Armada 370/XP Ethernet nodes The mvneta driver for the Marvell Armada 370/XP Ethernet devices has gained proper clock framework integration, and the corresponding Device Tree nodes now have a correct 'clocks' pointer. The 'clock-frequency' properties in the various .dts files for Armada 370/XP boards have therefore become useless. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-db.dts | 2 -- arch/arm/boot/dts/armada-370-mirabox.dts | 2 -- arch/arm/boot/dts/armada-xp-db.dts | 4 ---- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 4 ---- 4 files changed, 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 63120569878a..00044026ef1f 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -50,13 +50,11 @@ }; ethernet@d0070000 { - clock-frequency = <200000000>; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@d0074000 { - clock-frequency = <200000000>; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 8554dbee2640..3b4071336599 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -43,13 +43,11 @@ }; }; ethernet@d0070000 { - clock-frequency = <200000000>; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@d0074000 { - clock-frequency = <200000000>; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index ca1e03135567..c06c93ceba22 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -70,25 +70,21 @@ }; ethernet@d0070000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@d0074000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; }; ethernet@d0030000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy2>; phy-mode = "sgmii"; }; ethernet@d0034000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy3>; phy-mode = "sgmii"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index bb8d83cfbb50..638fb68d47b2 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -85,25 +85,21 @@ }; ethernet@d0070000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy0>; phy-mode = "sgmii"; }; ethernet@d0074000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy1>; phy-mode = "sgmii"; }; ethernet@d0030000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy2>; phy-mode = "sgmii"; }; ethernet@d0034000 { - clock-frequency = <250000000>; status = "okay"; phy = <&phy3>; phy-mode = "sgmii"; -- cgit v1.2.3-70-g09d2 From ef804d049d7fba5e7395184ea0b3ee24fd20d5f5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 19 Nov 2012 12:10:25 +0100 Subject: arm: mvebu: update defconfig to include network driver Signed-off-by: Thomas Petazzoni --- arch/arm/configs/mvebu_defconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 3458752c4bb2..6c36d91ddc8a 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -19,7 +19,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_VFP=y +CONFIG_NET=y +CONFIG_INET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NETDEVICES=y +CONFIG_MVNETA=y +CONFIG_MARVELL_PHY=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y -- cgit v1.2.3-70-g09d2 From 8dc40c19efad15f5bdb77b8d1ccf902902c00c58 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 19 Nov 2012 12:10:54 +0100 Subject: arm: mvebu: update defconfig to include XOR driver Signed-off-by: Thomas Petazzoni --- arch/arm/configs/mvebu_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 6c36d91ddc8a..58f3537466fc 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -31,6 +31,8 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # CONFIG_USB_SUPPORT is not set +CONFIG_DMADEVICES=y +CONFIG_MV_XOR=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y -- cgit v1.2.3-70-g09d2 From 009f13159bfdccd6e06fe3b62a39fee6dce26c39 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 2 Aug 2012 11:16:29 +0300 Subject: arm: mvebu: Add support for coherency fabric in mach-mvebu The Armada 370 and Armada XP SOCs have a coherency fabric unit which is responsible for ensuring hardware coherency between all CPUs and between CPUs and I/O masters. This patch provides the basic support needed for SMP. Signed-off-by: Yehuda Yitschak Signed-off-by: Gregory CLEMENT Reviewed-by: Will Deacon --- .../devicetree/bindings/arm/coherency-fabric.txt | 16 +++++ arch/arm/boot/dts/armada-370-xp.dtsi | 5 ++ arch/arm/mach-mvebu/Makefile | 2 +- arch/arm/mach-mvebu/coherency.c | 82 ++++++++++++++++++++++ arch/arm/mach-mvebu/coherency.h | 24 +++++++ arch/arm/mach-mvebu/coherency_ll.S | 49 +++++++++++++ arch/arm/mach-mvebu/common.h | 1 + 7 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/coherency-fabric.txt create mode 100644 arch/arm/mach-mvebu/coherency.c create mode 100644 arch/arm/mach-mvebu/coherency.h create mode 100644 arch/arm/mach-mvebu/coherency_ll.S (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt new file mode 100644 index 000000000000..2bfbf67dd77e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt @@ -0,0 +1,16 @@ +Coherency fabric +---------------- +Available on Marvell SOCs: Armada 370 and Armada XP + +Required properties: + +- compatible: "marvell,coherency-fabric" +- reg: Should contain,coherency fabric registers location and length. + +Example: + +coherency-fabric@d0020200 { + compatible = "marvell,coherency-fabric"; + reg = <0xd0020200 0xb0>; +}; + diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 94b4b9e03571..b0d075b50f29 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -36,6 +36,11 @@ interrupt-controller; }; + coherency-fabric@d0020200 { + compatible = "marvell,coherency-fabric"; + reg = <0xd0020200 0xb0>; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 57f996b6aa0e..5ce4b42c2697 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-orion/include obj-y += system-controller.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c new file mode 100644 index 000000000000..596ee66a9cc4 --- /dev/null +++ b/arch/arm/mach-mvebu/coherency.c @@ -0,0 +1,82 @@ +/* + * Coherency fabric (Aurora) support for Armada 370 and XP platforms. + * + * Copyright (C) 2012 Marvell + * + * Yehuda Yitschak + * Gregory Clement + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The Armada 370 and Armada XP SOCs have a coherency fabric which is + * responsible for ensuring hardware coherency between all CPUs and between + * CPUs and I/O masters. This file initializes the coherency fabric and + * supplies basic routines for configuring and controlling hardware coherency + */ + +#include +#include +#include +#include +#include +#include +#include "armada-370-xp.h" + +/* + * Some functions in this file are called very early during SMP + * initialization. At that time the device tree framework is not yet + * ready, and it is not possible to get the register address to + * ioremap it. That's why the pointer below is given with an initial + * value matching its virtual mapping + */ +static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200; + +/* Coherency fabric registers */ +#define COHERENCY_FABRIC_CFG_OFFSET 0x4 + +static struct of_device_id of_coherency_table[] = { + {.compatible = "marvell,coherency-fabric"}, + { /* end of list */ }, +}; + +#ifdef CONFIG_SMP +int coherency_get_cpu_count(void) +{ + int reg, cnt; + + reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET); + cnt = (reg & 0xF) + 1; + + return cnt; +} +#endif + +/* Function defined in coherency_ll.S */ +int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id); + +int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) +{ + if (!coherency_base) { + pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id); + pr_warn("Coherency fabric is not initialized\n"); + return 1; + } + + return ll_set_cpu_coherent(coherency_base, hw_cpu_id); +} + +int __init coherency_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, of_coherency_table); + if (np) { + pr_info("Initializing Coherency fabric\n"); + coherency_base = of_iomap(np, 0); + } + + return 0; +} diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h new file mode 100644 index 000000000000..2f428137f6fe --- /dev/null +++ b/arch/arm/mach-mvebu/coherency.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-mvebu/include/mach/coherency.h + * + * + * Coherency fabric (Aurora) support for Armada 370 and XP platforms. + * + * Copyright (C) 2012 Marvell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_370_XP_COHERENCY_H +#define __MACH_370_XP_COHERENCY_H + +#ifdef CONFIG_SMP +int coherency_get_cpu_count(void); +#endif + +int set_cpu_coherent(int cpu_id, int smp_group_id); +int coherency_init(void); + +#endif /* __MACH_370_XP_COHERENCY_H */ diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S new file mode 100644 index 000000000000..53e8391192cd --- /dev/null +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -0,0 +1,49 @@ +/* + * Coherency fabric: low level functions + * + * Copyright (C) 2012 Marvell + * + * Gregory CLEMENT + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file implements the assembly function to add a CPU to the + * coherency fabric. This function is called by each of the secondary + * CPUs during their early boot in an SMP kernel, this why this + * function have to callable from assembly. It can also be called by a + * primary CPU from C code during its boot. + */ + +#include +#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0 +#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4 + + .text +/* + * r0: Coherency fabric base register address + * r1: HW CPU id + */ +ENTRY(ll_set_cpu_coherent) + /* Create bit by cpu index */ + mov r3, #(1 << 24) + lsl r1, r3, r1 + + /* Add CPU to SMP group - Atomic */ + add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET + ldr r2, [r3] + orr r2, r2, r1 + str r2, [r3] + + /* Enable coherency on CPU - Atomic */ + add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET + ldr r2, [r3] + orr r2, r2, r1 + str r2, [r3] + + dsb + + mov r0, #0 + mov pc, lr +ENDPROC(ll_set_cpu_coherent) diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 02f89eaa25fe..ba6b62a42f52 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -20,4 +20,5 @@ void mvebu_restart(char mode, const char *cmd); void armada_370_xp_init_irq(void); void armada_370_xp_handle_irq(struct pt_regs *regs); +int armada_370_xp_coherency_init(void); #endif -- cgit v1.2.3-70-g09d2 From 7444dad2409afd94c08875e961ca61c5999cd606 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 2 Aug 2012 11:17:51 +0300 Subject: arm: mvebu: Add initial support for power managmement service unit The Armada 370 and Armada XP SOCs have a power management service unit which is responsible for powering down and waking up CPUs and other SOC units. This patch adds support for this unit. Signed-off-by: Yehuda Yitschak Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/arm/armada-370-xp-pmsu.txt | 20 ++++++ arch/arm/boot/dts/armada-xp.dtsi | 6 ++ arch/arm/mach-mvebu/Makefile | 2 +- arch/arm/mach-mvebu/common.h | 1 + arch/arm/mach-mvebu/pmsu.c | 75 ++++++++++++++++++++++ arch/arm/mach-mvebu/pmsu.h | 16 +++++ 6 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt create mode 100644 arch/arm/mach-mvebu/pmsu.c create mode 100644 arch/arm/mach-mvebu/pmsu.h (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt new file mode 100644 index 000000000000..926b4d6aae7e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt @@ -0,0 +1,20 @@ +Power Management Service Unit(PMSU) +----------------------------------- +Available on Marvell SOCs: Armada 370 and Armada XP + +Required properties: + +- compatible: "marvell,armada-370-xp-pmsu" + +- reg: Should contain PMSU registers location and length. First pair + for the per-CPU SW Reset Control registers, second pair for the + Power Management Service Unit. + +Example: + +armada-370-xp-pmsu@d0022000 { + compatible = "marvell,armada-370-xp-pmsu"; + reg = <0xd0022100 0x430>, + <0xd0020800 0x20>; +}; + diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index f51554e80009..1f95e227053b 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -27,6 +27,12 @@ <0xd0021870 0x58>; }; + armada-370-xp-pmsu@d0022000 { + compatible = "marvell,armada-370-xp-pmsu"; + reg = <0xd0022100 0x430>, + <0xd0020800 0x20>; + }; + soc { serial@d0012200 { compatible = "ns16550"; diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 5ce4b42c2697..2e3ec11c51e6 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -2,4 +2,4 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-orion/include obj-y += system-controller.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index ba6b62a42f52..9285d0496651 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -21,4 +21,5 @@ void armada_370_xp_init_irq(void); void armada_370_xp_handle_irq(struct pt_regs *regs); int armada_370_xp_coherency_init(void); +int armada_370_xp_pmsu_init(void); #endif diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c new file mode 100644 index 000000000000..3cc4bef6401c --- /dev/null +++ b/arch/arm/mach-mvebu/pmsu.c @@ -0,0 +1,75 @@ +/* + * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. + * + * Copyright (C) 2012 Marvell + * + * Yehuda Yitschak + * Gregory Clement + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The Armada 370 and Armada XP SOCs have a power management service + * unit which is responsible for powering down and waking up CPUs and + * other SOC units + */ + +#include +#include +#include +#include +#include +#include + +static void __iomem *pmsu_mp_base; +static void __iomem *pmsu_reset_base; + +#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x24) +#define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8) + +static struct of_device_id of_pmsu_table[] = { + {.compatible = "marvell,armada-370-xp-pmsu"}, + { /* end of list */ }, +}; + +#ifdef CONFIG_SMP +int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) +{ + int reg, hw_cpu; + + if (!pmsu_mp_base || !pmsu_reset_base) { + pr_warn("Can't boot CPU. PMSU is uninitialized\n"); + return 1; + } + + hw_cpu = cpu_logical_map(cpu_id); + + writel(virt_to_phys(boot_addr), pmsu_mp_base + + PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); + + /* Release CPU from reset by clearing reset bit*/ + reg = readl(pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu)); + reg &= (~0x1); + writel(reg, pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu)); + + return 0; +} +#endif + +int __init armada_370_xp_pmsu_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, of_pmsu_table); + if (np) { + pr_info("Initializing Power Management Service Unit\n"); + pmsu_mp_base = of_iomap(np, 0); + pmsu_reset_base = of_iomap(np, 1); + } + + return 0; +} + +early_initcall(armada_370_xp_pmsu_init); diff --git a/arch/arm/mach-mvebu/pmsu.h b/arch/arm/mach-mvebu/pmsu.h new file mode 100644 index 000000000000..07a737c6b95d --- /dev/null +++ b/arch/arm/mach-mvebu/pmsu.h @@ -0,0 +1,16 @@ +/* + * Power Management Service Unit (PMSU) support for Armada 370/XP platforms. + * + * Copyright (C) 2012 Marvell + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_MVEBU_PMSU_H +#define __MACH_MVEBU_PMSU_H + +int armada_xp_boot_cpu(unsigned int cpu_id, void *phys_addr); + +#endif /* __MACH_370_XP_PMSU_H */ -- cgit v1.2.3-70-g09d2 From 344e873e5657e8dc0631e4d1d42b69f7d625b02c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 2 Aug 2012 11:19:12 +0300 Subject: arm: mvebu: Add IPI support via doorbells This patch enhances the IRQ controller driver to add support for Inter-Processor-Interrupts that are needed to enable SMP support. Signed-off-by: Yehuda Yitschak Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 12 ++- arch/arm/boot/dts/armada-xp.dtsi | 2 +- arch/arm/mach-mvebu/armada-370-xp.h | 7 ++ arch/arm/mach-mvebu/irq-armada-370-xp.c | 92 ++++++++++++++++++++-- 4 files changed, 103 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt index 70c0dc5f00ed..61df564c0d23 100644 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt @@ -6,9 +6,15 @@ Required properties: - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. Should be 1. The cell is the IRQ number + - reg: Should contain PMIC registers location and length. First pair for the main interrupt registers, second pair for the per-CPU - interrupt registers + interrupt registers. For this last pair, to be compliant with SMP + support, the "virtual" must be use (For the record, these registers + automatically map to the interrupt controller registers of the + current CPU) + + Example: @@ -18,6 +24,6 @@ Example: #address-cells = <1>; #size-cells = <1>; interrupt-controller; - reg = <0xd0020000 0x1000>, - <0xd0021000 0x1000>; + reg = <0xd0020a00 0x1d0>, + <0xd0021070 0x58>; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 1f95e227053b..e6db2b7e2925 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -24,7 +24,7 @@ mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, - <0xd0021870 0x58>; + <0xd0021070 0x58>; }; armada-370-xp-pmsu@d0022000 { diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index aac9bebc6b03..c6a7d74fddfe 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -19,4 +19,11 @@ #define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000) #define ARMADA_370_XP_REGS_SIZE SZ_1M +#ifdef CONFIG_SMP +#include + +void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq); +void armada_xp_mpic_smp_cpu_init(void); +#endif + #endif /* __MACH_ARMADA_370_XP_H */ diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 5f5f9394b6b2..549b6846f940 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Interrupt Controller Registers Map */ #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) @@ -35,6 +36,12 @@ #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) +#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) +#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) +#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) + +#define ACTIVE_DOORBELLS (8) + static void __iomem *per_cpu_int_base; static void __iomem *main_int_base; static struct irq_domain *armada_370_xp_mpic_domain; @@ -51,11 +58,22 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); } +#ifdef CONFIG_SMP +static int armada_xp_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + return 0; +} +#endif + static struct irq_chip armada_370_xp_irq_chip = { .name = "armada_370_xp_irq", .irq_mask = armada_370_xp_irq_mask, .irq_mask_ack = armada_370_xp_irq_mask, .irq_unmask = armada_370_xp_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = armada_xp_set_affinity, +#endif }; static int armada_370_xp_mpic_irq_map(struct irq_domain *h, @@ -72,6 +90,41 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, return 0; } +#ifdef CONFIG_SMP +void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq) +{ + int cpu; + unsigned long map = 0; + + /* Convert our logical CPU mask into a physical one. */ + for_each_cpu(cpu, mask) + map |= 1 << cpu_logical_map(cpu); + + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before issuing the IPI. + */ + dsb(); + + /* submit softirq */ + writel((map << 8) | irq, main_int_base + + ARMADA_370_XP_SW_TRIG_INT_OFFS); +} + +void armada_xp_mpic_smp_cpu_init(void) +{ + /* Clear pending IPIs */ + writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + + /* Enable first 8 IPIs */ + writel((1 << ACTIVE_DOORBELLS) - 1, per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + + /* Unmask IPI interrupt */ + writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); +} +#endif /* CONFIG_SMP */ + static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { .map = armada_370_xp_mpic_irq_map, .xlate = irq_domain_xlate_onecell, @@ -91,13 +144,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); armada_370_xp_mpic_domain = - irq_domain_add_linear(node, (control >> 2) & 0x3ff, - &armada_370_xp_mpic_irq_ops, NULL); + irq_domain_add_linear(node, (control >> 2) & 0x3ff, + &armada_370_xp_mpic_irq_ops, NULL); if (!armada_370_xp_mpic_domain) panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n"); irq_set_default_host(armada_370_xp_mpic_domain); + +#ifdef CONFIG_SMP + armada_xp_mpic_smp_cpu_init(); +#endif + return 0; } @@ -111,14 +169,36 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs ARMADA_370_XP_CPU_INTACK_OFFS); irqnr = irqstat & 0x3FF; - if (irqnr < 1023) { - irqnr = - irq_find_mapping(armada_370_xp_mpic_domain, irqnr); + if (irqnr > 1022) + break; + + if (irqnr >= 8) { + irqnr = irq_find_mapping(armada_370_xp_mpic_domain, + irqnr); handle_IRQ(irqnr, regs); continue; } +#ifdef CONFIG_SMP + /* IPI Handling */ + if (irqnr == 0) { + u32 ipimask, ipinr; + + ipimask = readl_relaxed(per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) + & 0xFF; + + writel(0x0, per_cpu_int_base + + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + + /* Handle all pending doorbells */ + for (ipinr = 0; ipinr < ACTIVE_DOORBELLS; ipinr++) { + if (ipimask & (0x1 << ipinr)) + handle_IPI(ipinr, regs); + } + continue; + } +#endif - break; } while (1); } -- cgit v1.2.3-70-g09d2 From de4901933f6dfc0180f761790d3f47fc64e6270f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 3 Oct 2012 11:58:07 +0200 Subject: arm: mm: Add support for PJ4B cpu and init routines PJ4B is an implementation of the ARMv7 (such as the Cortex A9 for example) released by Marvell. This CPU is currently found in Armada 370 and Armada XP SoCs. This patch provides a support for the specific initialization of this CPU. Signed-off-by: Yehuda Yitschak Signed-off-by: Gregory CLEMENT Reviewed-by: Will Deacon Acked-by: Catalin Marinas --- arch/arm/mach-mvebu/Kconfig | 2 +- arch/arm/mm/Kconfig | 4 +++ arch/arm/mm/proc-v7.S | 67 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 79299cd94f0f..f4c3bf88f178 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -21,7 +21,7 @@ menu "Marvell SOC with device tree" config MACH_ARMADA_370_XP bool select ARMADA_370_XP_TIMER - select CPU_V7 + select CPU_PJ4B config MACH_ARMADA_370 bool "Marvell Armada 370 boards" diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 94186b6c685f..3fd629d5a513 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -352,6 +352,10 @@ config CPU_PJ4 select ARM_THUMBEE select CPU_V7 +config CPU_PJ4B + bool + select CPU_V7 + # ARMv6 config CPU_V6 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 846d279f3176..7cd0028cab8e 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -169,6 +169,63 @@ __v7_ca15mp_setup: orreq r0, r0, r10 @ Enable CPU-specific SMP bits mcreq p15, 0, r0, c1, c0, 1 #endif + +__v7_pj4b_setup: +#ifdef CONFIG_CPU_PJ4B + +/* Auxiliary Debug Modes Control 1 Register */ +#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ +#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ +#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ +#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ + +/* Auxiliary Debug Modes Control 2 Register */ +#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ +#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ +#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ +#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ +#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ +#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ + PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) + +/* Auxiliary Functional Modes Control Register 0 */ +#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ +#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ +#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ + +/* Auxiliary Debug Modes Control 0 Register */ +#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ + + /* Auxiliary Debug Modes Control 1 Register */ + mrc p15, 1, r0, c15, c1, 1 + orr r0, r0, #PJ4B_CLEAN_LINE + orr r0, r0, #PJ4B_BCK_OFF_STREX + orr r0, r0, #PJ4B_INTER_PARITY + bic r0, r0, #PJ4B_STATIC_BP + mcr p15, 1, r0, c15, c1, 1 + + /* Auxiliary Debug Modes Control 2 Register */ + mrc p15, 1, r0, c15, c1, 2 + bic r0, r0, #PJ4B_FAST_LDR + orr r0, r0, #PJ4B_AUX_DBG_CTRL2 + mcr p15, 1, r0, c15, c1, 2 + + /* Auxiliary Functional Modes Control Register 0 */ + mrc p15, 1, r0, c15, c2, 0 +#ifdef CONFIG_SMP + orr r0, r0, #PJ4B_SMP_CFB +#endif + orr r0, r0, #PJ4B_L1_PAR_CHK + orr r0, r0, #PJ4B_BROADCAST_CACHE + mcr p15, 1, r0, c15, c2, 0 + + /* Auxiliary Debug Modes Control 0 Register */ + mrc p15, 1, r0, c15, c1, 0 + orr r0, r0, #PJ4B_WFI_WFE + mcr p15, 1, r0, c15, c1, 0 + +#endif /* CONFIG_CPU_PJ4B */ + __v7_setup: adr r12, __v7_setup_stack @ the local stack stmia r12, {r0-r5, r7, r9, r11, lr} @@ -342,6 +399,16 @@ __v7_ca9mp_proc_info: .long 0xff0ffff0 __v7_proc __v7_ca9mp_setup .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info + + /* + * Marvell PJ4B processor. + */ + .type __v7_pj4b_proc_info, #object +__v7_pj4b_proc_info: + .long 0x562f5840 + .long 0xfffffff0 + __v7_proc __v7_pj4b_setup + .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info #endif /* CONFIG_ARM_LPAE */ /* -- cgit v1.2.3-70-g09d2 From 45f5984a8a528f7507f3ec860d297934d4449ad1 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Nov 2012 22:51:08 +0100 Subject: arm: mvebu: Add SMP support for Armada XP This enables SMP support on the Armada XP processor. It adds the mandatory functions to support SMP such as: the SMP initialization functions in platsmp.c, the secondary CPU entry point in headsmp.S and the CPU hotplug initial support in hotplug.c. Signed-off-by: Yehuda Yitschak Signed-off-by: Gregory CLEMENT Reviewed-by: Will Deacon --- arch/arm/configs/mvebu_defconfig | 3 + arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/Makefile | 2 + arch/arm/mach-mvebu/armada-370-xp.c | 3 + arch/arm/mach-mvebu/common.h | 3 + arch/arm/mach-mvebu/headsmp.S | 49 +++++++++++++++ arch/arm/mach-mvebu/hotplug.c | 30 +++++++++ arch/arm/mach-mvebu/platsmp.c | 122 ++++++++++++++++++++++++++++++++++++ 8 files changed, 213 insertions(+) create mode 100644 arch/arm/mach-mvebu/headsmp.S create mode 100644 arch/arm/mach-mvebu/hotplug.c create mode 100644 arch/arm/mach-mvebu/platsmp.c (limited to 'arch') diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 3458752c4bb2..da598d37a65f 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -12,6 +12,9 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y # CONFIG_CACHE_L2X0 is not set +# CONFIG_SWP_EMULATE is not set +CONFIG_SMP=y +# CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_HIGHMEM=y # CONFIG_COMPACTION is not set diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f4c3bf88f178..c934e1d4933d 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -21,6 +21,7 @@ menu "Marvell SOC with device tree" config MACH_ARMADA_370_XP bool select ARMADA_370_XP_TIMER + select HAVE_SMP select CPU_PJ4B config MACH_ARMADA_370 diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 2e3ec11c51e6..5dcb369b58aa 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,3 +3,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o coherency.o coherency_ll.o pmsu.o +obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 3292d6da5dc7..472e70ffce8d 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -23,6 +23,7 @@ #include #include "armada-370-xp.h" #include "common.h" +#include "coherency.h" static struct map_desc armada_370_xp_io_desc[] __initdata = { { @@ -51,6 +52,7 @@ struct sys_timer armada_370_xp_timer = { static void __init armada_370_xp_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + coherency_init(); } static const char * const armada_370_xp_dt_board_dt_compat[] = { @@ -60,6 +62,7 @@ static const char * const armada_370_xp_dt_board_dt_compat[] = { }; DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)") + .smp = smp_ops(armada_xp_smp_ops), .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, .init_irq = armada_370_xp_init_irq, diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 9285d0496651..aa27bc2ffb60 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -20,6 +20,9 @@ void mvebu_restart(char mode, const char *cmd); void armada_370_xp_init_irq(void); void armada_370_xp_handle_irq(struct pt_regs *regs); +void armada_xp_cpu_die(unsigned int cpu); int armada_370_xp_coherency_init(void); int armada_370_xp_pmsu_init(void); +void armada_xp_secondary_startup(void); +extern struct smp_operations armada_xp_smp_ops; #endif diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S new file mode 100644 index 000000000000..a06e0ede8c08 --- /dev/null +++ b/arch/arm/mach-mvebu/headsmp.S @@ -0,0 +1,49 @@ +/* + * SMP support: Entry point for secondary CPUs + * + * Copyright (C) 2012 Marvell + * + * Yehuda Yitschak + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file implements the assembly entry point for secondary CPUs in + * an SMP kernel. The only thing we need to do is to add the CPU to + * the coherency fabric by writing to 2 registers. Currently the base + * register addresses are hard coded due to the early initialisation + * problems. + */ + +#include +#include + +/* + * At this stage the secondary CPUs don't have acces yet to the MMU, so + * we have to provide physical addresses + */ +#define ARMADA_XP_CFB_BASE 0xD0020200 + + __CPUINIT + +/* + * Armada XP specific entry point for secondary CPUs. + * We add the CPU to the coherency fabric and then jump to secondary + * startup + */ +ENTRY(armada_xp_secondary_startup) + + /* Read CPU id */ + mrc p15, 0, r1, c0, c0, 5 + and r1, r1, #0xF + + /* Add CPU to coherency fabric */ + ldr r0, =ARMADA_XP_CFB_BASE + + bl ll_set_cpu_coherent + b secondary_startup + +ENDPROC(armada_xp_secondary_startup) diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c new file mode 100644 index 000000000000..b228b6a80c85 --- /dev/null +++ b/arch/arm/mach-mvebu/hotplug.c @@ -0,0 +1,30 @@ +/* + * Symmetric Multi Processing (SMP) support for Armada XP + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void __ref armada_xp_cpu_die(unsigned int cpu) +{ + cpu_do_idle(); + + /* We should never return from idle */ + panic("mvebu: cpu %d unexpectedly exit from shutdown\n", cpu); +} diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c new file mode 100644 index 000000000000..fe16aaf7c19c --- /dev/null +++ b/arch/arm/mach-mvebu/platsmp.c @@ -0,0 +1,122 @@ +/* + * Symmetric Multi Processing (SMP) support for Armada XP + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Yehuda Yitschak + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency + * This file implements the routines for preparing the SMP infrastructure + * and waking up the secondary CPUs + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "armada-370-xp.h" +#include "pmsu.h" +#include "coherency.h" + +void __init set_secondary_cpus_clock(void) +{ + int thiscpu; + unsigned long rate; + struct clk *cpu_clk = NULL; + struct device_node *np = NULL; + + thiscpu = smp_processor_id(); + for_each_node_by_type(np, "cpu") { + int err; + int cpu; + + err = of_property_read_u32(np, "reg", &cpu); + if (WARN_ON(err)) + return; + + if (cpu == thiscpu) { + cpu_clk = of_clk_get(np, 0); + break; + } + } + if (WARN_ON(IS_ERR(cpu_clk))) + return; + clk_prepare_enable(cpu_clk); + rate = clk_get_rate(cpu_clk); + + /* set all the other CPU clk to the same rate than the boot CPU */ + for_each_node_by_type(np, "cpu") { + int err; + int cpu; + + err = of_property_read_u32(np, "reg", &cpu); + if (WARN_ON(err)) + return; + + if (cpu != thiscpu) { + cpu_clk = of_clk_get(np, 0); + clk_set_rate(cpu_clk, rate); + } + } +} + +static void __cpuinit armada_xp_secondary_init(unsigned int cpu) +{ + armada_xp_mpic_smp_cpu_init(); +} + +static int __cpuinit armada_xp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + pr_info("Booting CPU %d\n", cpu); + + armada_xp_boot_cpu(cpu, armada_xp_secondary_startup); + + return 0; +} + +static void __init armada_xp_smp_init_cpus(void) +{ + unsigned int i, ncores; + ncores = coherency_get_cpu_count(); + + /* Limit possible CPUs to defconfig */ + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %d CPUs physically present. Only %d configured.", + ncores, nr_cpu_ids); + pr_warn("Clipping CPU count to %d\n", nr_cpu_ids); + ncores = nr_cpu_ids; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + + set_smp_cross_call(armada_mpic_send_doorbell); +} + +void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) +{ + set_secondary_cpus_clock(); + flush_cache_all(); + set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); +} + +struct smp_operations armada_xp_smp_ops __initdata = { + .smp_init_cpus = armada_xp_smp_init_cpus, + .smp_prepare_cpus = armada_xp_smp_prepare_cpus, + .smp_secondary_init = armada_xp_secondary_init, + .smp_boot_secondary = armada_xp_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = armada_xp_cpu_die, +#endif +}; -- cgit v1.2.3-70-g09d2 From 87b54e786afda828984645a8364a228ae8ac71f4 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 21 Nov 2012 09:39:19 +0100 Subject: arm: dma mapping: Export a dma ops function arm_dma_set_mask Expose another DMA operations function: arm_dma_set_mask. This function will be added to a custom DMA ops for Armada 370/XP. Depending of its configuration Armada 370/XP can be set as a "nearly" coherent architecture. In this case the DMA ops is made of: - specific functions for this architecture - already exposed arm DMA related functions - the arm_dma_set_mask which was not exposed yet. Signed-off-by: Gregory CLEMENT Acked-by: Marek Szyprowski --- arch/arm/include/asm/dma-mapping.h | 2 ++ arch/arm/mm/dma-mapping.c | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 23004847bb05..98d4dabb2c10 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -111,6 +111,8 @@ static inline void dma_free_noncoherent(struct device *dev, size_t size, extern int dma_supported(struct device *dev, u64 mask); +extern int arm_dma_set_mask(struct device *dev, u64 dma_mask); + /** * arm_dma_alloc - allocate consistent memory for DMA * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 58bc3e4d3bd0..5383bc018571 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -124,8 +124,6 @@ static void arm_dma_sync_single_for_device(struct device *dev, __dma_page_cpu_to_dev(page, offset, size, dir); } -static int arm_dma_set_mask(struct device *dev, u64 dma_mask); - struct dma_map_ops arm_dma_ops = { .alloc = arm_dma_alloc, .free = arm_dma_free, @@ -971,7 +969,7 @@ int dma_supported(struct device *dev, u64 mask) } EXPORT_SYMBOL(dma_supported); -static int arm_dma_set_mask(struct device *dev, u64 dma_mask) +int arm_dma_set_mask(struct device *dev, u64 dma_mask) { if (!dev->dma_mask || !dma_supported(dev, dma_mask)) return -EIO; -- cgit v1.2.3-70-g09d2 From 722202e10b488c14e93c428743a0e476093949e3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 12 Oct 2012 17:59:48 +0200 Subject: arm: plat-orion: Add coherency attribute when setup mbus target Recent SoC such as Armada 370/XP came with the possibility to deal with the I/O coherency by hardware. In this case the transaction attribute of the window must be flagged as "Shared transaction". Once this flag is set, then the transactions will be forced to be sent through the coherency block, in other case transaction is driven directly to DRAM. Signed-off-by: Gregory CLEMENT Reviewed-by: Yehuda Yitschak Acked-by: Thomas Petazzoni --- arch/arm/plat-orion/addr-map.c | 4 ++++ arch/arm/plat-orion/include/plat/addr-map.h | 1 + 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index a7b8060c293a..febe3862873c 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -42,6 +42,8 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info); #define WIN_REMAP_LO_OFF 0x0008 #define WIN_REMAP_HI_OFF 0x000c +#define ATTR_HW_COHERENCY (0x1 << 4) + /* * Default implementation */ @@ -163,6 +165,8 @@ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, w = &orion_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); + if (cfg->hw_io_coherency) + w->mbus_attr |= ATTR_HW_COHERENCY; w->base = base & 0xffff0000; w->size = (size | 0x0000ffff) + 1; } diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index ec63e4a627d0..b76c06569fe5 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -17,6 +17,7 @@ struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; void __iomem *bridge_virt_base; + int hw_io_coherency; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ -- cgit v1.2.3-70-g09d2 From e60304f8cb7bb545e79fe62d9b9762460c254ec2 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 12 Oct 2012 19:20:36 +0200 Subject: arm: mvebu: Add hardware I/O Coherency support Armada 370 and XP come with an unit called coherency fabric. This unit allows to use the Armada 370/XP as a nearly coherent architecture. The coherency mechanism uses snoop filters to ensure the coherency between caches, DRAM and devices. This mechanism needs a synchronization barrier which guarantees that all the memory writes initiated by the devices have reached their target and do not reside in intermediate write buffers. That's why the architecture is not totally coherent and we need to provide our own functions for some DMA operations. Beside the use of the coherency fabric, the device units will have to set the attribute flag of the decoding address window to select the accurate coherency process for the memory transaction. This is done each device driver programs the DRAM address windows. The value of the attribute set by the driver is retrieved through the orion_addr_map_cfg struct filled during the early initialization of the platform. Signed-off-by: Gregory CLEMENT Reviewed-by: Yehuda Yitschak Acked-by: Marek Szyprowski --- .../devicetree/bindings/arm/coherency-fabric.txt | 9 ++- arch/arm/boot/dts/armada-370-xp.dtsi | 3 +- arch/arm/mach-mvebu/addr-map.c | 3 + arch/arm/mach-mvebu/coherency.c | 73 ++++++++++++++++++++++ 4 files changed, 85 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt index 2bfbf67dd77e..17d8cd107559 100644 --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt @@ -5,12 +5,17 @@ Available on Marvell SOCs: Armada 370 and Armada XP Required properties: - compatible: "marvell,coherency-fabric" -- reg: Should contain,coherency fabric registers location and length. + +- reg: Should contain coherency fabric registers location and + length. First pair for the coherency fabric registers, second pair + for the per-CPU fabric registers registers. Example: coherency-fabric@d0020200 { compatible = "marvell,coherency-fabric"; - reg = <0xd0020200 0xb0>; + reg = <0xd0020200 0xb0>, + <0xd0021810 0x1c>; + }; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index b0d075b50f29..98a6b26a7dc8 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -38,7 +38,8 @@ coherency-fabric@d0020200 { compatible = "marvell,coherency-fabric"; - reg = <0xd0020200 0xb0>; + reg = <0xd0020200 0xb0>, + <0xd0021810 0x1c>; }; soc { diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c index fe454a4430be..595f6b722a8f 100644 --- a/arch/arm/mach-mvebu/addr-map.c +++ b/arch/arm/mach-mvebu/addr-map.c @@ -108,6 +108,9 @@ static int __init armada_setup_cpu_mbus(void) addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base; + if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric")) + addr_map_cfg.hw_io_coherency = 1; + /* * Disable, clear and configure windows. */ diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 596ee66a9cc4..8278960066c3 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include "armada-370-xp.h" @@ -33,10 +35,13 @@ * value matching its virtual mapping */ static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200; +static void __iomem *coherency_cpu_base; /* Coherency fabric registers */ #define COHERENCY_FABRIC_CFG_OFFSET 0x4 +#define IO_SYNC_BARRIER_CTL_OFFSET 0x0 + static struct of_device_id of_coherency_table[] = { {.compatible = "marvell,coherency-fabric"}, { /* end of list */ }, @@ -68,6 +73,70 @@ int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) return ll_set_cpu_coherent(coherency_base, hw_cpu_id); } +static inline void mvebu_hwcc_sync_io_barrier(void) +{ + writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET); + while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1); +} + +static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + if (dir != DMA_TO_DEVICE) + mvebu_hwcc_sync_io_barrier(); + return pfn_to_dma(dev, page_to_pfn(page)) + offset; +} + + +static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + if (dir != DMA_TO_DEVICE) + mvebu_hwcc_sync_io_barrier(); +} + +static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir) +{ + if (dir != DMA_TO_DEVICE) + mvebu_hwcc_sync_io_barrier(); +} + +static struct dma_map_ops mvebu_hwcc_dma_ops = { + .alloc = arm_dma_alloc, + .free = arm_dma_free, + .mmap = arm_dma_mmap, + .map_page = mvebu_hwcc_dma_map_page, + .unmap_page = mvebu_hwcc_dma_unmap_page, + .get_sgtable = arm_dma_get_sgtable, + .map_sg = arm_dma_map_sg, + .unmap_sg = arm_dma_unmap_sg, + .sync_single_for_cpu = mvebu_hwcc_dma_sync, + .sync_single_for_device = mvebu_hwcc_dma_sync, + .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, + .sync_sg_for_device = arm_dma_sync_sg_for_device, + .set_dma_mask = arm_dma_set_mask, +}; + +static int mvebu_hwcc_platform_notifier(struct notifier_block *nb, + unsigned long event, void *__dev) +{ + struct device *dev = __dev; + + if (event != BUS_NOTIFY_ADD_DEVICE) + return NOTIFY_DONE; + set_dma_ops(dev, &mvebu_hwcc_dma_ops); + + return NOTIFY_OK; +} + +static struct notifier_block mvebu_hwcc_platform_nb = { + .notifier_call = mvebu_hwcc_platform_notifier, +}; + int __init coherency_init(void) { struct device_node *np; @@ -76,6 +145,10 @@ int __init coherency_init(void) if (np) { pr_info("Initializing Coherency fabric\n"); coherency_base = of_iomap(np, 0); + coherency_cpu_base = of_iomap(np, 1); + set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + bus_register_notifier(&platform_bus_type, + &mvebu_hwcc_platform_nb); } return 0; -- cgit v1.2.3-70-g09d2 From 539eb5bca02ff0b93e17f110ffec18c5b5e744ee Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 30 Oct 2012 19:41:23 +0900 Subject: ARM: mvebu: Add support for I2C controllers in Armada 370/XP The Armada 370 and Armada XP have the same I2C controllers as previous Marvell SoCs, so the existing mv64xxx-i2c driver works fine. [Thomas Petazzoni: updated on top of other Armada 370/XP changes, rephrased the commit log]. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-370-xp.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 4ff108151278..70c35f8ccf90 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -101,6 +101,28 @@ clocks = <&gateclk 3>; status = "disabled"; }; + + i2c0: i2c@d0011000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0xd0011000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@d0011100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0xd0011100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-70-g09d2 From 9eab21cffcdfc7869e2342651b276141b335fb89 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 30 Oct 2012 19:41:24 +0900 Subject: ARM: mvebu: Add support for I2C on OpenBlocks AX3-4 The OpenBlocks AX3-4 board, based on the Armada XP SoC, has an I2C bus. This patch enables this bus and sets the clock frequency of the bus. [Thomas Petazzoni: updated with other changes on OpenBlocks, rephrased commit log.] Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 638fb68d47b2..cb7f0d972c6f 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -104,5 +104,13 @@ phy = <&phy3>; phy-mode = "sgmii"; }; + i2c@d0011000 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@d0011100 { + status = "okay"; + clock-frequency = <400000>; + }; }; }; -- cgit v1.2.3-70-g09d2 From 14bedd4afbd10a89b50f439f88cdd01c999ecd16 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 30 Oct 2012 19:41:25 +0900 Subject: ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4 The OpenBlocks AX3-4 has a Seiko Instruments S-35390A as the RTC controller. This patch enables this RTC device in the OpenBlocks AX3-4 Device Tree. [Thomas Petazzoni: updated with other OpenBlocks changes, rephrased commit log.] Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index cb7f0d972c6f..13ce6ae364cc 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -111,6 +111,11 @@ i2c@d0011100 { status = "okay"; clock-frequency = <400000>; + + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; }; }; }; -- cgit v1.2.3-70-g09d2 From 6435389dde897644b5e0f3202d0d2ce9e47ddf45 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Nov 2012 22:37:01 +0100 Subject: ARM: mvebu: Add SATA support for OpenBlocks AX3-4 This patch enables SATA support on the OpenBlocks AX3-4. It has one internal SATA port, and an external eSATA port. Signed-off-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 13ce6ae364cc..b42652fd3d8c 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -117,5 +117,9 @@ reg = <0x30>; }; }; + sata@d00a0000 { + nr-ports = <2>; + status = "okay"; + }; }; }; -- cgit v1.2.3-70-g09d2 From 9bfd143ed247fc7a9e0573dc1fbaf6d124b5cac9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Nov 2012 23:12:54 +0100 Subject: ARM: mvebu: update defconfig with I2C and RTC support Now that we have support for the I2C busses on Armada 370/XP, and support for the RTC on the OpenBlocks AX3-4 platform, include the necessary options in mvebu_defconfig. Signed-off-by: Thomas Petazzoni --- arch/arm/configs/mvebu_defconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index cc2c3b2e9641..73b53fc06638 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -31,9 +31,13 @@ CONFIG_MARVELL_PHY=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_I2C=y +CONFIG_I2C_MV64XXX=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # CONFIG_USB_SUPPORT is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S35390A=y CONFIG_DMADEVICES=y CONFIG_MV_XOR=y # CONFIG_IOMMU_SUPPORT is not set -- cgit v1.2.3-70-g09d2 From 9f3410ff217f55c2a30bd1b2eb1032806d17c80e Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 22 Nov 2012 18:09:53 +0100 Subject: arm: mvebu: fix address decoding armada_cfg_base() function The armada_cfg_base() function returns the base address of the registers that allow to configure the decoding for a particular address window. On Armada 370/XP, the lower windows have more configuration registers (4 registers) than the higher windows (2 registers). This armada_cfg_base() takes this into account by doing a different offset calculation depending on the window number, but this offset calculation was wrong for the higher windows. Even though we were not using high window numbers until now (only window 0 is used to map the BootROM, needed for SMP), we use this function at boot time to disable all windows to ensure that nothing remains intialized from what the bootloader has done. Unfortunately, the U-Boot on the OpenBlocks AX3-4 uses a window with a high number (above 8) to remap the BootROM. And then when the kernel boots, it remaps the BootROM in window 0. Normally, this is not a problem, because all windows have previously been disabled. Except that due to our wrong offset calculation, the windows with high numbers were not properly disabled, leading to the BootROM being mapped twice. The visible result of this bug was that the kernel was unable to get the second CPU started on the OpenBlocks AX3-4 platform. With this fix, all windows are properly cleared at boot time, the BootROM is remapped only once in window 0, and the second CPU boots fine. Thanks a lot to Lior Amsamlen for his help in debugging this problem. Signed-off-by: Thomas Petazzoni --- Strictly speaking, this bug was introduced in 3.7, but since the only platforms supported in 3.7 were Armada 370 and Armada XP, and there was anyway no SMP support at this time, it isn't really worth the effort to push this patch in 3.7. --- arch/arm/mach-mvebu/addr-map.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c index fe454a4430be..b20fc751b1e5 100644 --- a/arch/arm/mach-mvebu/addr-map.c +++ b/arch/arm/mach-mvebu/addr-map.c @@ -78,7 +78,7 @@ armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win) if (win < 8) offset = (win << 4); else - offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3); + offset = ARMADA_WINDOW_8_PLUS_OFFSET + ((win - 8) << 3); return cfg->bridge_virt_base + offset; } -- cgit v1.2.3-70-g09d2 From d792b1e94dfad4bce0acd4ac03d361b0038dc8d7 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 26 Sep 2012 18:02:48 +0200 Subject: arm: mvebu: add L2 cache support Signed-off-by: Gregory CLEMENT Tested-and-reviewed-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Jason Cooper Cc: Andrew Lunn Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/irq-armada-370-xp.c | 4 ++++ 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index c934e1d4933d..440b13ef1fed 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -22,6 +22,7 @@ config MACH_ARMADA_370_XP bool select ARMADA_370_XP_TIMER select HAVE_SMP + select CACHE_L2X0 select CPU_PJ4B config MACH_ARMADA_370 diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 549b6846f940..8e3fb082c3c6 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -25,6 +25,7 @@ #include #include #include +#include /* Interrupt Controller Registers Map */ #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) @@ -210,4 +211,7 @@ static const struct of_device_id mpic_of_match[] __initconst = { void __init armada_370_xp_init_irq(void) { of_irq_init(mpic_of_match); +#ifdef CONFIG_CACHE_L2X0 + l2x0_of_init(0, ~0UL); +#endif } -- cgit v1.2.3-70-g09d2 From 2f96fbb7d851740d0594a6b74142083d51483ab5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 26 Sep 2012 18:02:49 +0200 Subject: arm: mvebu: add Aurora L2 Cache Controller to the DT Signed-off-by: Gregory CLEMENT Signed-off-by: Yehuda Yitschak Tested-and-reviewed-by: Yehuda Yitschak Tested-and-reviewed-by: Lior Amsalem Acked-by: Arnd Bergmann Cc: Jason Cooper Cc: Andrew Lunn Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370.dtsi | 6 ++++++ arch/arm/boot/dts/armada-xp.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7fbac28b01f3..636cf7d4009e 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -20,6 +20,12 @@ / { model = "Marvell Armada 370 family SoC"; compatible = "marvell,armada370", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-outer-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; aliases { gpio0 = &gpio0; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 45a567c2e9ba..367aa3f94912 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -22,6 +22,13 @@ model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + L2: l2-cache { + compatible = "marvell,aurora-system-cache"; + reg = <0xd0008000 0x1000>; + cache-id-part = <0x100>; + wt-override; + }; + mpic: interrupt-controller@d0020000 { reg = <0xd0020a00 0x1d0>, <0xd0021070 0x58>; -- cgit v1.2.3-70-g09d2