From f5ff9a115ec633852312a8e43df4bbd36b4dad3d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 18 Oct 2013 10:56:14 +0200 Subject: clk: ux500: fix erroneous bit assignment Due to a typo or similar, the peripheral group 2 clock 11 gate was set to bit 1 instead of bit 11. We need to fix this to be able to set the correct enable bit in the device tree: when trying to correct the bit assignment in the device tree, the system would hang. Cc: Mike Turquette Acked-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/clk/ux500/u8500_of_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index b768b507c95c..cdeff299de26 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -339,7 +339,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, BIT(11), 0); - PRCC_PCLK_STORE(clk, 2, 1); + PRCC_PCLK_STORE(clk, 2, 11); clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, BIT(12), 0); -- cgit v1.2.3-70-g09d2