From 35ba8850b673050b71b17c1421079031f4fda319 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 7 Jul 2022 20:57:34 +0800 Subject: drm/amdgpu/mes: fix mes submission in atomic context For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index ca44aa123a1e..db2138b7a858 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -150,6 +150,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev) idr_init(&adev->mes.queue_id_idr); ida_init(&adev->mes.doorbell_ida); spin_lock_init(&adev->mes.queue_id_lock); + spin_lock_init(&adev->mes.ring_lock); mutex_init(&adev->mes.mutex_hidden); adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; @@ -794,8 +795,6 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, struct mes_unmap_legacy_queue_input queue_input; int r; - amdgpu_mes_lock(&adev->mes); - queue_input.action = action; queue_input.queue_type = ring->funcs->type; queue_input.doorbell_offset = ring->doorbell_index; @@ -808,7 +807,6 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, if (r) DRM_ERROR("failed to unmap legacy queue\n"); - amdgpu_mes_unlock(&adev->mes); return r; } @@ -817,8 +815,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) struct mes_misc_op_input op_input; int r, val = 0; - amdgpu_mes_lock(&adev->mes); - op_input.op = MES_MISC_OP_READ_REG; op_input.read_reg.reg_offset = reg; op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr; @@ -835,7 +831,6 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) val = *(adev->mes.read_val_ptr); error: - amdgpu_mes_unlock(&adev->mes); return val; } @@ -845,8 +840,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev, struct mes_misc_op_input op_input; int r; - amdgpu_mes_lock(&adev->mes); - op_input.op = MES_MISC_OP_WRITE_REG; op_input.write_reg.reg_offset = reg; op_input.write_reg.reg_value = val; @@ -862,7 +855,6 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev, DRM_ERROR("failed to write reg (0x%x)\n", reg); error: - amdgpu_mes_unlock(&adev->mes); return r; } @@ -873,8 +865,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, struct mes_misc_op_input op_input; int r; - amdgpu_mes_lock(&adev->mes); - op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; op_input.wrm_reg.reg0 = reg0; op_input.wrm_reg.reg1 = reg1; @@ -892,7 +882,6 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, DRM_ERROR("failed to reg_write_reg_wait\n"); error: - amdgpu_mes_unlock(&adev->mes); return r; } @@ -902,8 +891,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, struct mes_misc_op_input op_input; int r; - amdgpu_mes_lock(&adev->mes); - op_input.op = MES_MISC_OP_WRM_REG_WAIT; op_input.wrm_reg.reg0 = reg; op_input.wrm_reg.ref = val; @@ -920,7 +907,6 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, DRM_ERROR("failed to reg_write_reg_wait\n"); error: - amdgpu_mes_unlock(&adev->mes); return r; } -- cgit v1.2.3-70-g09d2