From adcf949e664a8b04df2fb8aa916892e58561653c Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 25 May 2021 14:36:29 +0800 Subject: drm/amdgpu: fix the hang caused by PCIe link width switch SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/amdgpu/nv.c') diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 63c96ca8d2a2..5231b3402990 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1414,6 +1414,9 @@ static int nv_common_hw_init(void *handle) if (adev->nbio.funcs->apply_lc_spc_mode_wa) adev->nbio.funcs->apply_lc_spc_mode_wa(adev); + if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) + adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); + /* enable pcie gen2/3 link */ nv_pcie_gen3_enable(adev); /* enable aspm */ -- cgit v1.2.3-70-g09d2