From 118a331516581c3acf1279857b0f663a54b7f31b Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 19 May 2021 10:47:22 -0400 Subject: drm/amd/display: Add DCN3.1 clock manager support Adds support for clock requests for the various parts of the DCN3.1 IP and the interfaces and definitions for sending messages to SMU/PMFW. Includes new support for z9/10, detecting SMU timeout and p-state support enablement. Acked-by: Huang Rui Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 5dc8d02b40c3..90dbe26bf954 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -91,6 +91,9 @@ struct clk_limit_table_entry { unsigned int dispclk_mhz; unsigned int dppclk_mhz; unsigned int phyclk_mhz; +#ifdef CONFIG_DRM_AMD_DC_DCN3_1 + unsigned int wck_ratio; +#endif }; /* This table is contiguous */ -- cgit v1.2.3-70-g09d2