From 2b80ffc2d86cce8444d5fc0237afd77f7d18cd1d Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 27 Feb 2023 17:36:19 +0800 Subject: drm/amdgpu: Add gc v9_4_3 ras error status registers GC v9_4_3 introduces UE|CE_ERR_STATUS_LO|HI to log hardware errors Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- .../drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h | 192 ++++ .../drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h | 1112 ++++++++++++++++++++ 2 files changed, 1304 insertions(+) (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc') diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h index 3100de8b3881..393963502b7a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h @@ -705,6 +705,46 @@ #define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 #define regSQC_DCACHE_UTCL1_STATUS 0x03d8 #define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 +#define regSQC_UE_EDC_LO 0x03d9 +#define regSQC_UE_EDC_LO_BASE_IDX 0 +#define regSQC_UE_EDC_HI 0x03da +#define regSQC_UE_EDC_HI_BASE_IDX 0 +#define regSQC_CE_EDC_LO 0x03db +#define regSQC_CE_EDC_LO_BASE_IDX 0 +#define regSQC_CE_EDC_HI 0x03dc +#define regSQC_CE_EDC_HI_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_LO 0x03dd +#define regSQ_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_HI 0x03de +#define regSQ_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_LO 0x03df +#define regSQ_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_HI 0x03e0 +#define regSQ_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_LO 0x03e1 +#define regLDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_HI 0x03e2 +#define regLDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_LO 0x03e3 +#define regLDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_HI 0x03e4 +#define regLDS_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_LO 0x03e5 +#define regSP0_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_HI 0x03e6 +#define regSP0_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_LO 0x03e7 +#define regSP0_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_HI 0x03e8 +#define regSP0_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_LO 0x03e9 +#define regSP1_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_HI 0x03ea +#define regSP1_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_LO 0x03eb +#define regSP1_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_HI 0x03ec +#define regSP1_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_shsdec @@ -727,6 +767,14 @@ #define regSPI_DSM_CNTL2_BASE_IDX 0 #define regSPI_EDC_CNT 0x0445 #define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_LO 0x0446 +#define regSPI_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_HI 0x0447 +#define regSPI_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_LO 0x0448 +#define regSPI_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_HI 0x0449 +#define regSPI_CE_ERR_STATUS_HI_BASE_IDX 0 #define regSPI_DEBUG_BUSY 0x0450 #define regSPI_DEBUG_BUSY_BASE_IDX 0 #define regSPI_CONFIG_PS_CU_EN 0x0452 @@ -871,6 +919,14 @@ #define regTD_STATUS_BASE_IDX 0 #define regTD_POWER_CNTL 0x052a #define regTD_POWER_CNTL_BASE_IDX 0 +#define regTD_UE_EDC_LO 0x052b +#define regTD_UE_EDC_LO_BASE_IDX 0 +#define regTD_UE_EDC_HI 0x052c +#define regTD_UE_EDC_HI_BASE_IDX 0 +#define regTD_CE_EDC_LO 0x052d +#define regTD_CE_EDC_LO_BASE_IDX 0 +#define regTD_CE_EDC_HI 0x052e +#define regTD_CE_EDC_HI_BASE_IDX 0 #define regTD_DSM_CNTL 0x052f #define regTD_DSM_CNTL_BASE_IDX 0 #define regTD_DSM_CNTL2 0x0530 @@ -893,6 +949,14 @@ #define regTA_DSM_CNTL_BASE_IDX 0 #define regTA_DSM_CNTL2 0x0585 #define regTA_DSM_CNTL2_BASE_IDX 0 +#define regTA_UE_EDC_LO 0x0587 +#define regTA_UE_EDC_LO_BASE_IDX 0 +#define regTA_UE_EDC_HI 0x0588 +#define regTA_UE_EDC_HI_BASE_IDX 0 +#define regTA_CE_EDC_LO 0x0589 +#define regTA_CE_EDC_LO_BASE_IDX 0 +#define regTA_CE_EDC_HI 0x058a +#define regTA_CE_EDC_HI_BASE_IDX 0 // addressBlock: xcd0_gc_gdsdec @@ -923,6 +987,14 @@ #define regGDS_DSM_CNTL2_BASE_IDX 0 #define regGDS_WD_GDS_CSB 0x05ce #define regGDS_WD_GDS_CSB_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_LO 0x05cf +#define regGDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_HI 0x05d0 +#define regGDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_LO 0x05d1 +#define regGDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_HI 0x05d2 +#define regGDS_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_rbdec @@ -1243,6 +1315,10 @@ #define regGCEA_MAM_CTRL_BASE_IDX 0 #define regGCEA_MAM_CTRL2 0x0702 #define regGCEA_MAM_CTRL2_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_LO 0x0706 +#define regGCEA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_HI 0x0707 +#define regGCEA_UE_ERR_STATUS_HI_BASE_IDX 0 #define regGCEA_DSM_CNTL 0x0708 #define regGCEA_DSM_CNTL_BASE_IDX 0 #define regGCEA_DSM_CNTLA 0x0709 @@ -1277,6 +1353,10 @@ #define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 #define regGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 #define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_LO 0x071b +#define regGCEA_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_HI 0x071d +#define regGCEA_CE_ERR_STATUS_HI_BASE_IDX 0 #define regGCEA_SDP_ENABLE 0x071f #define regGCEA_SDP_ENABLE_BASE_IDX 0 @@ -1389,6 +1469,14 @@ #define regATC_L2_CNTL4_BASE_IDX 0 #define regATC_L2_MM_GROUP_RT_CLASSES 0x0816 #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_LO 0x081a +#define regATC_L2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_HI 0x081b +#define regATC_L2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_LO 0x081c +#define regATC_L2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_HI 0x081d +#define regATC_L2_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_utcl2_vml2pfdec @@ -1475,6 +1563,30 @@ #define regUTCL2_EDC_MODE_BASE_IDX 0 #define regUTCL2_EDC_CONFIG 0x084c #define regUTCL2_EDC_CONFIG_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_LO 0x084d +#define regVML2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_LO 0x084e +#define regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_LO 0x084f +#define regUTCL2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_HI 0x0850 +#define regVML2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_HI 0x0851 +#define regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_HI 0x0852 +#define regUTCL2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_LO 0x0853 +#define regVML2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_LO 0x0854 +#define regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_LO 0x0855 +#define regUTCL2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_HI 0x0856 +#define regVML2_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_HI 0x0857 +#define regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_HI 0x0858 +#define regUTCL2_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_utcl2_vml2vcdec @@ -2011,6 +2123,22 @@ #define regTC_CFG_L1_VOLATILE_BASE_IDX 0 #define regTC_CFG_L2_VOLATILE 0x0b23 #define regTC_CFG_L2_VOLATILE_BASE_IDX 0 +#define regTCP_UE_EDC_HI_REG 0x0b54 +#define regTCP_UE_EDC_HI_REG_BASE_IDX 0 +#define regTCP_UE_EDC_LO_REG 0x0b55 +#define regTCP_UE_EDC_LO_REG_BASE_IDX 0 +#define regTCP_CE_EDC_HI_REG 0x0b56 +#define regTCP_CE_EDC_HI_REG_BASE_IDX 0 +#define regTCP_CE_EDC_LO_REG 0x0b57 +#define regTCP_CE_EDC_LO_REG_BASE_IDX 0 +#define regTCI_UE_EDC_HI_REG 0x0b58 +#define regTCI_UE_EDC_HI_REG_BASE_IDX 0 +#define regTCI_UE_EDC_LO_REG 0x0b59 +#define regTCI_UE_EDC_LO_REG_BASE_IDX 0 +#define regTCI_CE_EDC_HI_REG 0x0b5a +#define regTCI_CE_EDC_HI_REG_BASE_IDX 0 +#define regTCI_CE_EDC_LO_REG 0x0b5b +#define regTCI_CE_EDC_LO_REG_BASE_IDX 0 #define regTCI_MISC 0x0b5c #define regTCI_MISC_BASE_IDX 0 #define regTCI_CNTL_3 0x0b5d @@ -2061,6 +2189,26 @@ #define regTCX_DSM_CNTL_BASE_IDX 0 #define regTCX_DSM_CNTL2 0x0bc8 #define regTCX_DSM_CNTL2_BASE_IDX 0 +#define regTCA_UE_ERR_STATUS_LO 0x0bc9 +#define regTCA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCA_UE_ERR_STATUS_HI 0x0bca +#define regTCA_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCX_UE_ERR_STATUS_LO 0x0bcb +#define regTCX_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCX_UE_ERR_STATUS_HI 0x0bcc +#define regTCX_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCX_CE_ERR_STATUS_LO 0x0bcd +#define regTCX_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCX_CE_ERR_STATUS_HI 0x0bce +#define regTCX_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCC_UE_ERR_STATUS_LO 0x0bcf +#define regTCC_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCC_UE_ERR_STATUS_HI 0x0bd0 +#define regTCC_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regTCC_CE_ERR_STATUS_LO 0x0bd1 +#define regTCC_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regTCC_CE_ERR_STATUS_HI 0x0bd2 +#define regTCC_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_shdec @@ -2905,6 +3053,30 @@ #define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 #define regCP_VMID_STATUS 0x10bf #define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_UE_ERR_STATUS_LO 0x10e0 +#define regCPC_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPC_UE_ERR_STATUS_HI 0x10e1 +#define regCPC_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPC_CE_ERR_STATUS_LO 0x10e2 +#define regCPC_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPC_CE_ERR_STATUS_HI 0x10e3 +#define regCPC_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPF_UE_ERR_STATUS_LO 0x10e4 +#define regCPF_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPF_UE_ERR_STATUS_HI 0x10e5 +#define regCPF_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPF_CE_ERR_STATUS_LO 0x10e6 +#define regCPF_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPF_CE_ERR_STATUS_HI 0x10e7 +#define regCPF_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPG_UE_ERR_STATUS_LO 0x10e8 +#define regCPG_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPG_UE_ERR_STATUS_HI 0x10e9 +#define regCPG_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regCPG_CE_ERR_STATUS_LO 0x10ea +#define regCPG_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regCPG_CE_ERR_STATUS_HI 0x10eb +#define regCPG_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_cppdec2 @@ -5364,6 +5536,18 @@ #define regSPI_WAVE_LIMIT_CNTL 0x2443 #define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 +// addressBlock: xcd0_gc_gccanedec +// base address: 0x33d00 +#define regGC_CANE_ERR_STATUS 0x2f4d +#define regGC_CANE_ERR_STATUS_BASE_IDX 1 +#define regGC_CANE_UE_ERR_STATUS_LO 0x2f4e +#define regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX 1 +#define regGC_CANE_UE_ERR_STATUS_HI 0x2f4f +#define regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX 1 +#define regGC_CANE_CE_ERR_STATUS_LO 0x2f50 +#define regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX 1 +#define regGC_CANE_CE_ERR_STATUS_HI 0x2f51 +#define regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX 1 // addressBlock: xcd0_gc_perfddec // base address: 0x34000 @@ -6583,6 +6767,10 @@ #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 #define regRLC_CPG_STAT_INVAL 0x4d09 #define regRLC_CPG_STAT_INVAL_BASE_IDX 1 +#define regRLC_UE_ERR_STATUS_LOW 0x4d40 +#define regRLC_UE_ERR_STATUS_LOW_BASE_IDX 1 +#define regRLC_UE_ERR_STATUS_HIGH 0x4d41 +#define regRLC_UE_ERR_STATUS_HIGH_BASE_IDX 1 #define regRLC_DSM_CNTL 0x4d42 #define regRLC_DSM_CNTL_BASE_IDX 1 #define regRLC_DSM_CNTLA 0x4d43 @@ -6591,6 +6779,10 @@ #define regRLC_DSM_CNTL2_BASE_IDX 1 #define regRLC_DSM_CNTL2A 0x4d45 #define regRLC_DSM_CNTL2A_BASE_IDX 1 +#define regRLC_CE_ERR_STATUS_LOW 0x4d49 +#define regRLC_CE_ERR_STATUS_LOW_BASE_IDX 1 +#define regRLC_CE_ERR_STATUS_HIGH 0x4d4a +#define regRLC_CE_ERR_STATUS_HIGH_BASE_IDX 1 #define regRLC_RLCV_SPARE_INT 0x4f30 #define regRLC_RLCV_SPARE_INT_BASE_IDX 1 #define regRLC_SMU_CLK_REQ 0x4f97 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h index 84a75b58347f..2bd9f3f1026f 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h @@ -4129,6 +4129,240 @@ #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//SQC_UE_EDC_LO +#define SQC_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define SQC_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define SQC_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define SQC_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define SQC_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define SQC_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQC_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//SQC_UE_EDC_HI +#define SQC_UE_EDC_HI__ECC__SHIFT 0x0 +#define SQC_UE_EDC_HI__PARITY__SHIFT 0x1 +#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQC_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define SQC_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define SQC_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define SQC_UE_EDC_HI__ECC_MASK 0x00000001L +#define SQC_UE_EDC_HI__PARITY_MASK 0x00000002L +#define SQC_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQC_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQC_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define SQC_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//SQC_CE_EDC_LO +#define SQC_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define SQC_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define SQC_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define SQC_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define SQC_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define SQC_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQC_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//SQC_CE_EDC_HI +#define SQC_CE_EDC_HI__ECC__SHIFT 0x0 +#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQC_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define SQC_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define SQC_CE_EDC_HI__POSION__SHIFT 0x1a +#define SQC_CE_EDC_HI__ECC_MASK 0x00000001L +#define SQC_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQC_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQC_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define SQC_CE_EDC_HI__POSION_MASK 0x04000000L +//SQ_UE_ERR_STATUS_LO +#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SQ_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SQ_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SQ_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SQ_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SQ_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQ_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SQ_UE_ERR_STATUS_HI +#define SQ_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SQ_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQ_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SQ_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SQ_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SQ_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SQ_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SQ_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQ_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQ_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SQ_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SQ_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SQ_CE_ERR_STATUS_LO +#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SQ_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SQ_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SQ_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SQ_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SQ_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SQ_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SQ_CE_ERR_STATUS_HI +#define SQ_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SQ_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SQ_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SQ_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SQ_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SQ_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SQ_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SQ_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SQ_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SQ_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SQ_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SQ_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//LDS_UE_ERR_STATUS_LO +#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define LDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define LDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define LDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define LDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define LDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define LDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//LDS_UE_ERR_STATUS_HI +#define LDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define LDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define LDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define LDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define LDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define LDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define LDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define LDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define LDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define LDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define LDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define LDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//LDS_CE_ERR_STATUS_LO +#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define LDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define LDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define LDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define LDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define LDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define LDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//LDS_CE_ERR_STATUS_HI +#define LDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define LDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define LDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define LDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define LDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define LDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define LDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define LDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define LDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define LDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define LDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define LDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//SP0_UE_ERR_STATUS_LO +#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP0_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP0_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP0_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP0_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP0_UE_ERR_STATUS_HI +#define SP0_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP0_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP0_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SP0_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SP0_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SP0_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP0_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP0_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP0_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SP0_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SP0_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SP0_CE_ERR_STATUS_LO +#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP0_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP0_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP0_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP0_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP0_CE_ERR_STATUS_HI +#define SP0_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP0_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP0_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SP0_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SP0_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SP0_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP0_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP0_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP0_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SP0_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SP0_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//SP1_UE_ERR_STATUS_LO +#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP1_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP1_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP1_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP1_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP1_UE_ERR_STATUS_HI +#define SP1_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP1_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP1_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SP1_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SP1_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SP1_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP1_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP1_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP1_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SP1_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SP1_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SP1_CE_ERR_STATUS_LO +#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SP1_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SP1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SP1_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SP1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SP1_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SP1_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SP1_CE_ERR_STATUS_HI +#define SP1_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SP1_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SP1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SP1_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SP1_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SP1_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SP1_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SP1_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SP1_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SP1_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SP1_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SP1_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L // addressBlock: xcd0_gc_shsdec @@ -4235,6 +4469,54 @@ #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L #define SPI_EDC_CNT__UNUSED_MASK 0xFFF00000L +//SPI_UE_ERR_STATUS_LO +#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SPI_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SPI_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SPI_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SPI_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SPI_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SPI_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SPI_UE_ERR_STATUS_HI +#define SPI_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SPI_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SPI_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SPI_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SPI_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SPI_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SPI_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SPI_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SPI_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SPI_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SPI_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SPI_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//SPI_CE_ERR_STATUS_LO +#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SPI_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SPI_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SPI_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SPI_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SPI_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SPI_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SPI_CE_ERR_STATUS_HI +#define SPI_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SPI_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SPI_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SPI_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define SPI_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define SPI_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define SPI_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SPI_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SPI_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SPI_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define SPI_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define SPI_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L //SPI_DEBUG_BUSY #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 @@ -4622,6 +4904,48 @@ #define TD_POWER_CNTL__MGCG_OUTPUTSTAGE_MASK 0x00000002L #define TD_POWER_CNTL__MID0_THREAD_DATA_MASK 0x00000004L #define TD_POWER_CNTL__MID2_ACCUM_DATA_MASK 0x00000008L +//TD_UE_EDC_LO +#define TD_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TD_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TD_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TD_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TD_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TD_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TD_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TD_UE_EDC_HI +#define TD_UE_EDC_HI__ECC__SHIFT 0x0 +#define TD_UE_EDC_HI__PARITY__SHIFT 0x1 +#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TD_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TD_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define TD_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define TD_UE_EDC_HI__ECC_MASK 0x00000001L +#define TD_UE_EDC_HI__PARITY_MASK 0x00000002L +#define TD_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TD_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TD_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define TD_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//TD_CE_EDC_LO +#define TD_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TD_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TD_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TD_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TD_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TD_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TD_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TD_CE_EDC_HI +#define TD_CE_EDC_HI__ECC__SHIFT 0x0 +#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TD_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TD_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define TD_CE_EDC_HI__POISON__SHIFT 0x1a +#define TD_CE_EDC_HI__ECC_MASK 0x00000001L +#define TD_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TD_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TD_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define TD_CE_EDC_HI__POISON_MASK 0x04000000L //TD_DSM_CNTL #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -4771,6 +5095,48 @@ #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L #define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L +//TA_UE_EDC_LO +#define TA_UE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TA_UE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TA_UE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TA_UE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TA_UE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TA_UE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TA_UE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TA_UE_EDC_HI +#define TA_UE_EDC_HI__ECC__SHIFT 0x0 +#define TA_UE_EDC_HI__PARITY__SHIFT 0x1 +#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TA_UE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TA_UE_EDC_HI__UE_CNT__SHIFT 0x17 +#define TA_UE_EDC_HI__FED_CNT__SHIFT 0x1a +#define TA_UE_EDC_HI__ECC_MASK 0x00000001L +#define TA_UE_EDC_HI__PARITY_MASK 0x00000002L +#define TA_UE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TA_UE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TA_UE_EDC_HI__UE_CNT_MASK 0x03800000L +#define TA_UE_EDC_HI__FED_CNT_MASK 0x1C000000L +//TA_CE_EDC_LO +#define TA_CE_EDC_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TA_CE_EDC_LO__ADDRESS__SHIFT 0x2 +#define TA_CE_EDC_LO__MEM_ID__SHIFT 0x18 +#define TA_CE_EDC_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define TA_CE_EDC_LO__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TA_CE_EDC_LO__ADDRESS_MASK 0x00FFFFFCL +#define TA_CE_EDC_LO__MEM_ID_MASK 0xFF000000L +//TA_CE_EDC_HI +#define TA_CE_EDC_HI__ECC__SHIFT 0x0 +#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TA_CE_EDC_HI__ERR_INFO__SHIFT 0x3 +#define TA_CE_EDC_HI__CE_CNT__SHIFT 0x17 +#define TA_CE_EDC_HI__POISON__SHIFT 0x1a +#define TA_CE_EDC_HI__ECC_MASK 0x00000001L +#define TA_CE_EDC_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TA_CE_EDC_HI__ERR_INFO_MASK 0x007FFFF8L +#define TA_CE_EDC_HI__CE_CNT_MASK 0x03800000L +#define TA_CE_EDC_HI__POISON_MASK 0x04000000L // addressBlock: xcd0_gc_gdsdec @@ -5015,6 +5381,54 @@ #define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd #define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL #define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L +//GDS_UE_ERR_STATUS_LO +#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GDS_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GDS_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GDS_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GDS_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GDS_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GDS_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GDS_UE_ERR_STATUS_HI +#define GDS_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GDS_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GDS_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GDS_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GDS_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GDS_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define GDS_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GDS_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GDS_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GDS_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GDS_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define GDS_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//GDS_CE_ERR_STATUS_LO +#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GDS_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GDS_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GDS_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GDS_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GDS_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GDS_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GDS_CE_ERR_STATUS_HI +#define GDS_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GDS_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GDS_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GDS_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GDS_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GDS_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define GDS_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GDS_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GDS_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GDS_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GDS_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define GDS_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L // addressBlock: xcd0_gc_rbdec @@ -7370,6 +7784,30 @@ #define GCEA_MAM_CTRL2__ARAM_FLUSH_NOALLOC_MASK 0x00000040L #define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0x00FFFF80L #define GCEA_MAM_CTRL2__ADDR_HI_MASK 0xFF000000L +//GCEA_UE_ERR_STATUS_LO +#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GCEA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GCEA_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GCEA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GCEA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GCEA_UE_ERR_STATUS_HI +#define GCEA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GCEA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GCEA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GCEA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define GCEA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GCEA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GCEA_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GCEA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GCEA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define GCEA_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //GCEA_DSM_CNTL #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -7745,6 +8183,30 @@ #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L +//GCEA_CE_ERR_STATUS_LO +#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GCEA_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GCEA_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GCEA_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GCEA_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GCEA_CE_ERR_STATUS_HI +#define GCEA_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GCEA_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GCEA_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define GCEA_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GCEA_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GCEA_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GCEA_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define GCEA_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L //GCEA_SDP_ENABLE #define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 #define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L @@ -8440,6 +8902,54 @@ //ATC_L2_MM_GROUP_RT_CLASSES #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//ATC_L2_UE_ERR_STATUS_LO +#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define ATC_L2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define ATC_L2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define ATC_L2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//ATC_L2_UE_ERR_STATUS_HI +#define ATC_L2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define ATC_L2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define ATC_L2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define ATC_L2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define ATC_L2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define ATC_L2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define ATC_L2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define ATC_L2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define ATC_L2_UE_ERR_STATUS_HI__RESERVED_MASK 0x60000000L +//ATC_L2_CE_ERR_STATUS_LO +#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define ATC_L2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define ATC_L2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define ATC_L2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//ATC_L2_CE_ERR_STATUS_HI +#define ATC_L2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define ATC_L2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define ATC_L2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define ATC_L2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define ATC_L2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define ATC_L2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define ATC_L2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define ATC_L2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define ATC_L2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define ATC_L2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L // addressBlock: xcd0_gc_utcl2_vml2pfdec @@ -8888,6 +9398,150 @@ #define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 #define UTCL2_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L #define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//VML2_UE_ERR_STATUS_LO +#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_WALKER_UE_ERR_STATUS_LO +#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_WALKER_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_WALKER_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_WALKER_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//UTCL2_UE_ERR_STATUS_LO +#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define UTCL2_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define UTCL2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define UTCL2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_UE_ERR_STATUS_HI +#define VML2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define VML2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define VML2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define VML2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define VML2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define VML2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//VML2_WALKER_UE_ERR_STATUS_HI +#define VML2_WALKER_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define VML2_WALKER_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_WALKER_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_WALKER_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_WALKER_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define VML2_WALKER_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define VML2_WALKER_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//UTCL2_UE_ERR_STATUS_HI +#define UTCL2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define UTCL2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define UTCL2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define UTCL2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define UTCL2_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define UTCL2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define UTCL2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define UTCL2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define UTCL2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define UTCL2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define UTCL2_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//VML2_CE_ERR_STATUS_LO +#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_WALKER_CE_ERR_STATUS_LO +#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define VML2_WALKER_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define VML2_WALKER_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define VML2_WALKER_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//UTCL2_CE_ERR_STATUS_LO +#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define UTCL2_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define UTCL2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define UTCL2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//VML2_CE_ERR_STATUS_HI +#define VML2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define VML2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define VML2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define VML2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define VML2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define VML2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//VML2_WALKER_CE_ERR_STATUS_HI +#define VML2_WALKER_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define VML2_WALKER_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define VML2_WALKER_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define VML2_WALKER_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define VML2_WALKER_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define VML2_WALKER_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define VML2_WALKER_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define VML2_WALKER_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//UTCL2_CE_ERR_STATUS_HI +#define UTCL2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define UTCL2_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define UTCL2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define UTCL2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define UTCL2_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define UTCL2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define UTCL2_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define UTCL2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define UTCL2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define UTCL2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define UTCL2_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L // addressBlock: xcd0_gc_utcl2_vml2vcdec @@ -11139,6 +11793,98 @@ //TC_CFG_L2_VOLATILE #define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 #define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL +//TCP_UE_EDC_HI_REG +#define TCP_UE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCP_UE_EDC_HI_REG__PARITY__SHIFT 0x1 +#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCP_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCP_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17 +#define TCP_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a +#define TCP_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d +#define TCP_UE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCP_UE_EDC_HI_REG__PARITY_MASK 0x00000002L +#define TCP_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCP_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCP_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L +#define TCP_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L +#define TCP_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L +//TCP_UE_EDC_LO_REG +#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCP_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCP_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCP_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCP_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCP_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCP_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCP_CE_EDC_HI_REG +#define TCP_CE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCP_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCP_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17 +#define TCP_CE_EDC_HI_REG__POISON__SHIFT 0x1a +#define TCP_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b +#define TCP_CE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCP_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCP_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCP_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L +#define TCP_CE_EDC_HI_REG__POISON_MASK 0x04000000L +#define TCP_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L +//TCP_CE_EDC_LO_REG +#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCP_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCP_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCP_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCP_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCP_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCP_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCI_UE_EDC_HI_REG +#define TCI_UE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCI_UE_EDC_HI_REG__PARITY__SHIFT 0x1 +#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCI_UE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCI_UE_EDC_HI_REG__UE_CNT__SHIFT 0x17 +#define TCI_UE_EDC_HI_REG__FED_CNT__SHIFT 0x1a +#define TCI_UE_EDC_HI_REG__RESERVED__SHIFT 0x1d +#define TCI_UE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCI_UE_EDC_HI_REG__PARITY_MASK 0x00000002L +#define TCI_UE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCI_UE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCI_UE_EDC_HI_REG__UE_CNT_MASK 0x03800000L +#define TCI_UE_EDC_HI_REG__FED_CNT_MASK 0x1C000000L +#define TCI_UE_EDC_HI_REG__RESERVED_MASK 0xE0000000L +//TCI_UE_EDC_LO_REG +#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCI_UE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCI_UE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCI_UE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCI_UE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCI_UE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCI_UE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L +//TCI_CE_EDC_HI_REG +#define TCI_CE_EDC_HI_REG__ECC__SHIFT 0x0 +#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCI_CE_EDC_HI_REG__ERR_INFO__SHIFT 0x3 +#define TCI_CE_EDC_HI_REG__CE_CNT__SHIFT 0x17 +#define TCI_CE_EDC_HI_REG__POISON__SHIFT 0x1a +#define TCI_CE_EDC_HI_REG__RESERVED__SHIFT 0x1b +#define TCI_CE_EDC_HI_REG__ECC_MASK 0x00000001L +#define TCI_CE_EDC_HI_REG__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCI_CE_EDC_HI_REG__ERR_INFO_MASK 0x007FFFF8L +#define TCI_CE_EDC_HI_REG__CE_CNT_MASK 0x03800000L +#define TCI_CE_EDC_HI_REG__POISON_MASK 0x04000000L +#define TCI_CE_EDC_HI_REG__RESERVED_MASK 0xF8000000L +//TCI_CE_EDC_LO_REG +#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG__SHIFT 0x0 +#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG__SHIFT 0x1 +#define TCI_CE_EDC_LO_REG__ADDRESS__SHIFT 0x2 +#define TCI_CE_EDC_LO_REG__MEM_ID__SHIFT 0x18 +#define TCI_CE_EDC_LO_REG__STATUS_VALID_FLAG_MASK 0x00000001L +#define TCI_CE_EDC_LO_REG__ADDRESS_INFO_VALID_FLAG_MASK 0x00000002L +#define TCI_CE_EDC_LO_REG__ADDRESS_MASK 0x00FFFFFCL +#define TCI_CE_EDC_LO_REG__MEM_ID_MASK 0xFF000000L //TCI_MISC #define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0 #define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1 @@ -11560,6 +12306,112 @@ #define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L #define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L #define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//TCA_UE_ERR_STATUS_LO +#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCA_UE_ERR_STATUS_HI +#define TCA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCA_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCX_UE_ERR_STATUS_LO +#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCX_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCX_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCX_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCX_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCX_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCX_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCX_UE_ERR_STATUS_HI +#define TCX_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCX_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCX_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCX_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCX_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCX_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCX_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCX_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCX_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCX_CE_ERR_STATUS_LO +#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCX_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCX_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCX_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCX_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCX_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCX_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCX_CE_ERR_STATUS_HI +#define TCX_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCX_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define TCX_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define TCX_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCX_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCX_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define TCX_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +//TCC_UE_ERR_STATUS_LO +#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCC_UE_ERR_STATUS_HI +#define TCC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define TCC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define TCC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCC_UE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define TCC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//TCC_CE_ERR_STATUS_LO +#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define TCC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define TCC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define TCC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define TCC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define TCC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define TCC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//TCC_CE_ERR_STATUS_HI +#define TCC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG__SHIFT 0x2 +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO__SHIFT 0x3 +#define TCC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define TCC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define TCC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_VALID_FLAG_MASK 0x00000004L +#define TCC_CE_ERR_STATUS_HI__ERROR_INFO_MASK 0x007FFFF8L +#define TCC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define TCC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L // addressBlock: xcd0_gc_shdec @@ -14384,6 +15236,150 @@ #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L +//CPC_UE_ERR_STATUS_LO +#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPC_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPC_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPC_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPC_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPC_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPC_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPC_UE_ERR_STATUS_HI +#define CPC_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPC_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPC_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPC_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPC_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPC_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPC_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPC_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPC_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPC_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPC_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPC_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPC_CE_ERR_STATUS_LO +#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPC_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPC_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPC_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPC_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPC_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPC_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPC_CE_ERR_STATUS_HI +#define CPC_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPC_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPC_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPC_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPC_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPC_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPC_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPC_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPC_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPC_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPC_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPC_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//CPF_UE_ERR_STATUS_LO +#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPF_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPF_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPF_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPF_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPF_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPF_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPF_UE_ERR_STATUS_HI +#define CPF_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPF_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPF_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPF_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPF_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPF_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPF_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPF_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPF_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPF_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPF_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPF_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPF_CE_ERR_STATUS_LO +#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPF_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPF_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPF_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPF_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPF_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPF_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPF_CE_ERR_STATUS_HI +#define CPF_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPF_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPF_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPF_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPF_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPF_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPF_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPF_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPF_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPF_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPF_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPF_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L +//CPG_UE_ERR_STATUS_LO +#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPG_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPG_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPG_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPG_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPG_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPG_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPG_UE_ERR_STATUS_HI +#define CPG_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPG_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPG_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPG_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define CPG_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define CPG_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define CPG_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPG_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPG_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPG_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define CPG_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define CPG_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L +//CPG_CE_ERR_STATUS_LO +#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define CPG_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define CPG_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define CPG_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define CPG_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define CPG_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define CPG_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//CPG_CE_ERR_STATUS_HI +#define CPG_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define CPG_CE_ERR_STATUS_HI__OTHER__SHIFT 0x1 +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define CPG_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define CPG_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define CPG_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define CPG_CE_ERR_STATUS_HI__RESERVED__SHIFT 0x1b +#define CPG_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define CPG_CE_ERR_STATUS_HI__OTHER_MASK 0x00000002L +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define CPG_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define CPG_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define CPG_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define CPG_CE_ERR_STATUS_HI__RESERVED_MASK 0xF8000000L // addressBlock: xcd0_gc_cppdec2 @@ -22764,6 +23760,74 @@ #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L +// addressBlock: xcd0_gc_gccanedec +//GC_CANE_ERR_STATUS +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT 0x0 +#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT 0x4 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT 0x8 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT 0xb +#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT 0xc +#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd +#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe +#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT 0xf +#define GC_CANE_ERR_STATUS__FUE_FLAG__SHIFT 0x10 +#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0x11 +#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x12 +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK 0x0000000FL +#define GC_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK 0x000000F0L +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK 0x00000300L +#define GC_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GC_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK 0x00000800L +#define GC_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK 0x00001000L +#define GC_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L +#define GC_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L +#define GC_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK 0x00008000L +#define GC_CANE_ERR_STATUS__FUE_FLAG_MASK 0x00010000L +#define GC_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00020000L +#define GC_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00040000L +//GC_CANE_UE_ERR_STATUS_LO +#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GC_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GC_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GC_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GC_CANE_UE_ERR_STATUS_HI +#define GC_CANE_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GC_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define GC_CANE_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GC_CANE_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GC_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GC_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define GC_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//GC_CANE_CE_ERR_STATUS_LO +#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define GC_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define GC_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define GC_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//GC_CANE_CE_ERR_STATUS_HI +#define GC_CANE_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define GC_CANE_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define GC_CANE_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define GC_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define GC_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define GC_CANE_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L // addressBlock: xcd0_gc_perfddec //CPG_PERFCOUNTER1_LO @@ -26471,6 +27535,30 @@ //RLC_CPG_STAT_INVAL #define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0 #define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L +//RLC_UE_ERR_STATUS_LOW +#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define RLC_UE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2 +#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18 +#define RLC_UE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define RLC_UE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL +#define RLC_UE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L +//RLC_UE_ERR_STATUS_HIGH +#define RLC_UE_ERR_STATUS_HIGH__ECC__SHIFT 0x0 +#define RLC_UE_ERR_STATUS_HIGH__PARITY__SHIFT 0x1 +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3 +#define RLC_UE_ERR_STATUS_HIGH__UE_CNT__SHIFT 0x17 +#define RLC_UE_ERR_STATUS_HIGH__FED_CNT__SHIFT 0x1a +#define RLC_UE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1d +#define RLC_UE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L +#define RLC_UE_ERR_STATUS_HIGH__PARITY_MASK 0x00000002L +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define RLC_UE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L +#define RLC_UE_ERR_STATUS_HIGH__UE_CNT_MASK 0x03800000L +#define RLC_UE_ERR_STATUS_HIGH__FED_CNT_MASK 0x1C000000L +#define RLC_UE_ERR_STATUS_HIGH__RESERVED_MASK 0xE0000000L //RLC_DSM_CNTL #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 @@ -26573,6 +27661,30 @@ #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L +//RLC_CE_ERR_STATUS_LOW +#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define RLC_CE_ERR_STATUS_LOW__ADDRESS__SHIFT 0x2 +#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID__SHIFT 0x18 +#define RLC_CE_ERR_STATUS_LOW__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define RLC_CE_ERR_STATUS_LOW__ADDRESS_MASK 0x00FFFFFCL +#define RLC_CE_ERR_STATUS_LOW__MEMORY_ID_MASK 0xFF000000L +//RLC_CE_ERR_STATUS_HIGH +#define RLC_CE_ERR_STATUS_HIGH__ECC__SHIFT 0x0 +#define RLC_CE_ERR_STATUS_HIGH__OTHER__SHIFT 0x1 +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO__SHIFT 0x3 +#define RLC_CE_ERR_STATUS_HIGH__CE_CNT__SHIFT 0x17 +#define RLC_CE_ERR_STATUS_HIGH__POISON__SHIFT 0x1a +#define RLC_CE_ERR_STATUS_HIGH__RESERVED__SHIFT 0x1b +#define RLC_CE_ERR_STATUS_HIGH__ECC_MASK 0x00000001L +#define RLC_CE_ERR_STATUS_HIGH__OTHER_MASK 0x00000002L +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define RLC_CE_ERR_STATUS_HIGH__ERR_INFO_MASK 0x007FFFF8L +#define RLC_CE_ERR_STATUS_HIGH__CE_CNT_MASK 0x03800000L +#define RLC_CE_ERR_STATUS_HIGH__POISON_MASK 0x04000000L +#define RLC_CE_ERR_STATUS_HIGH__RESERVED_MASK 0xF8000000L //RLC_RLCV_SPARE_INT #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 -- cgit v1.2.3-70-g09d2 From 4504f14338cdc43586189558113faafa8acb9ffe Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 31 Mar 2022 12:05:00 -0400 Subject: drm/amdgpu: setup hw debug registers on driver initialization Add missing debug trap registers references and initialize all debug registers on boot by clearing the hardware exception overrides and the wave allocation ID index. The debugger requires that TTMPs 6 & 7 save the dispatch ID to map waves onto dispatch during compute context inspection. In order to correctly set this up, set the special reserved CP bit by default whenever the MQD is initailized. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 ++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 5 ++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 5 ++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 ++ .../drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 14 +++++ .../amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h | 69 ++++++++++++++++++++++ .../drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 10 ++++ .../amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h | 4 ++ .../amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h | 4 ++ 12 files changed, 176 insertions(+) (limited to 'drivers/gpu/drm/amd/include/asic_reg/gc') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f7ad883a70fa..be984f8c71c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4825,6 +4825,29 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade #define DEFAULT_SH_MEM_BASES (0x6000) +static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, + uint32_t first_vmid, + uint32_t last_vmid) +{ + uint32_t data; + uint32_t trap_config_vmid_mask = 0; + int i; + + /* Calculate trap config vmid mask */ + for (i = first_vmid; i < last_vmid; i++) + trap_config_vmid_mask |= (1 << i); + + data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, + VMID_SEL, trap_config_vmid_mask); + data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, + TRAP_EN, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); +} + static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) { int i; @@ -4856,6 +4879,9 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); } + + gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid, + AMDGPU_NUM_VMID); } static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index da21bf868080..690e121d9dda 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1638,6 +1638,7 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) /* Enable trap for each kfd vmid. */ data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); } soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 0189e50bd89f..7f17e0061027 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2303,6 +2303,29 @@ static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) adev->gfx.config.num_rbs = hweight32(active_rbs); } +static void gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev, + uint32_t first_vmid, + uint32_t last_vmid) +{ + uint32_t data; + uint32_t trap_config_vmid_mask = 0; + int i; + + /* Calculate trap config vmid mask */ + for (i = first_vmid; i < last_vmid; i++) + trap_config_vmid_mask |= (1 << i); + + data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG, + VMID_SEL, trap_config_vmid_mask); + data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG, + TRAP_EN, 1); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); + + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); +} + #define DEFAULT_SH_MEM_BASES (0x6000) static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) { @@ -4602,6 +4625,13 @@ static int gfx_v9_0_late_init(void *handle) if (r) return r; + if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) + gfx_v9_4_2_debug_trap_config_init(adev, + adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); + else + gfx_v9_0_debug_trap_config_init(adev, + adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index 2cc3a7cb1f54..63f6843a069e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -771,6 +771,9 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, soc15_grbm_select(adev, 0, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); + + WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA0), 0); + WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_TRAP_DATA1), 0); } void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 772c09b5821b..eaaa4f4ddaaa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -117,6 +117,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; + /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the + * DISPATCH_PTR. This is required for the kfd debugger + */ + m->cp_hqd_hq_scheduler0 = 1 << 14; + if (q->format == KFD_QUEUE_FORMAT_AQL) { m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 632344b95d90..3a48bbc589fe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -143,6 +143,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; + /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the + * DISPATCH_PTR. This is required for the kfd debugger + */ + m->cp_hqd_hq_status0 = 1 << 14; + /* * GFX11 RS64 CPFW version >= 509 supports PCIe atomics support * acknowledgment. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 226132ec3714..b7c95158d4a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -182,6 +182,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; + /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the + * DISPATCH_PTR. This is required for the kfd debugger + */ + m->cp_hqd_hq_status0 = 1 << 14; + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h index 79c41004c0b6..4908044f7409 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h @@ -5194,6 +5194,20 @@ #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 #define mmSPI_WCL_PIPE_PERCENT_CS7 0x1f70 #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL 0x1f71 +#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 +#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_MASK 0x1f73 +#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL2 0x1f74 +#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 +#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA0 0x1f78 +#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA1 0x1f79 +#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h index 52043e143067..9b7d219e7954 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h @@ -19700,6 +19700,75 @@ //SPI_WCL_PIPE_PERCENT_CS7 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L +//SPI_GDBG_TRAP_MASK +#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 +#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL +#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L +//SPI_GDBG_WAVE_CNTL2 +#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10 +#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL +#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_GDBG_TRAP_DATA0 +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL +//SPI_GDBG_TRAP_DATA1 +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL //SPI_COMPUTE_QUEUE_RESET #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index a734abaa91a5..5e15ac14b63c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -26,6 +26,8 @@ #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 #define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 +#define mmSQ_DEBUG 0x10B1 +#define mmSQ_DEBUG_BASE_IDX 0 // addressBlock: gc_sdma0_sdma0dec // base address: 0x4980 @@ -4853,10 +4855,18 @@ #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL 0x1f71 #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 +#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 #define mmSPI_GDBG_TRAP_MASK 0x1f73 #define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL2 0x1f74 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 +#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA0 0x1f78 +#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA1 0x1f79 +#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h index d7a17bae2584..e4ecd6c2d20e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h @@ -47907,6 +47907,10 @@ // addressBlock: sqind +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x00000000 + //SQ_DEBUG_STS_GLOBAL #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h index 4f08f90856fc..3088a4a13cb5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h @@ -17216,11 +17216,15 @@ #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x00004000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x00008000L //SPI_COMPUTE_QUEUE_RESET #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L -- cgit v1.2.3-70-g09d2