From e997ae5f45caf7df08a421b1d1edac7a47d06890 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 25 Sep 2023 16:50:36 +0200 Subject: drm/msm/a6xx: Mostly implement A7xx gpu_state Provide the necessary alternations to mostly support state dumping on A7xx. Newer GPUs will probably require more changes here. Crashdumper and debugbus remain untested. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/559289/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 61 ++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h') diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index e788ed72eb0d..8d7e6f26480a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -338,6 +338,28 @@ static const struct a6xx_registers a6xx_vbif_reglist = static const struct a6xx_registers a6xx_gbif_reglist = REGS(a6xx_gbif_registers, 0, 0); +static const u32 a7xx_ahb_registers[] = { + /* RBBM_STATUS */ + 0x210, 0x210, + /* RBBM_STATUS2-3 */ + 0x212, 0x213, +}; + +static const u32 a7xx_gbif_registers[] = { + 0x3c00, 0x3c0b, + 0x3c40, 0x3c42, + 0x3c45, 0x3c47, + 0x3c49, 0x3c4a, + 0x3cc0, 0x3cd1, +}; + +static const struct a6xx_registers a7xx_ahb_reglist[] = { + REGS(a7xx_ahb_registers, 0, 0), +}; + +static const struct a6xx_registers a7xx_gbif_reglist = + REGS(a7xx_gbif_registers, 0, 0); + static const u32 a6xx_gmu_gx_registers[] = { /* GMU GX */ 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b, @@ -384,14 +406,17 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = { }; static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu); +static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu); -static struct a6xx_indexed_registers { +struct a6xx_indexed_registers { const char *name; u32 addr; u32 data; u32 count; u32 (*count_fn)(struct msm_gpu *gpu); -} a6xx_indexed_reglist[] = { +}; + +static struct a6xx_indexed_registers a6xx_indexed_reglist[] = { { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, @@ -402,11 +427,43 @@ static struct a6xx_indexed_registers { REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size}, }; +static struct a6xx_indexed_registers a7xx_indexed_reglist[] = { + { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, + REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL }, + { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, + REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, + REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR, + REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL }, + { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR, + REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR, + REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR, + REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL }, + { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR, + REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL }, + { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR, + REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL }, + { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR, + REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL }, + { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR, + REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size }, +}; + static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = { "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL, }; +static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = { + { "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR, + REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL }, + { "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR, + REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL }, +}; + #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count } static const struct a6xx_debugbus_block { -- cgit v1.2.3-70-g09d2 From b08d26dac1a1075c874f40ee02ec8ddc39e20146 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 12 Oct 2023 04:20:13 +0300 Subject: drm/msm/a7xx: actually use a7xx state registers Make a6xx_get_registers() use a7xx registers instead of a6xx ones if the detected Adreno is from the A7xx family. Fixes: e997ae5f45ca ("drm/msm/a6xx: Mostly implement A7xx gpu_state") Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/562233/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 17 +++++++++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 10 ++++------ 2 files changed, 17 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h') diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 18be2d3bde09..91a564a24dbe 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -882,12 +882,13 @@ static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu, } } +#define A6XX_REGLIST_SIZE 1 #define A6XX_GBIF_REGLIST_SIZE 1 static void a6xx_get_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) { - int i, count = ARRAY_SIZE(a6xx_ahb_reglist) + + int i, count = A6XX_REGLIST_SIZE + ARRAY_SIZE(a6xx_reglist) + ARRAY_SIZE(a6xx_hlsq_reglist) + A6XX_GBIF_REGLIST_SIZE; int index = 0; @@ -901,12 +902,20 @@ static void a6xx_get_registers(struct msm_gpu *gpu, a6xx_state->nr_registers = count; - for (i = 0; i < ARRAY_SIZE(a6xx_ahb_reglist); i++) + if (adreno_is_a7xx(adreno_gpu)) a6xx_get_ahb_gpu_registers(gpu, - a6xx_state, &a6xx_ahb_reglist[i], + a6xx_state, &a7xx_ahb_reglist, + &a6xx_state->registers[index++]); + else + a6xx_get_ahb_gpu_registers(gpu, + a6xx_state, &a6xx_ahb_reglist, &a6xx_state->registers[index++]); - if (a6xx_has_gbif(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu)) + a6xx_get_ahb_gpu_registers(gpu, + a6xx_state, &a7xx_gbif_reglist, + &a6xx_state->registers[index++]); + else if (a6xx_has_gbif(adreno_gpu)) a6xx_get_ahb_gpu_registers(gpu, a6xx_state, &a6xx_gbif_reglist, &a6xx_state->registers[index++]); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 8d7e6f26480a..9560fc1b858a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -328,9 +328,8 @@ static const u32 a6xx_gbif_registers[] = { 0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A, }; -static const struct a6xx_registers a6xx_ahb_reglist[] = { - REGS(a6xx_ahb_registers, 0, 0), -}; +static const struct a6xx_registers a6xx_ahb_reglist = + REGS(a6xx_ahb_registers, 0, 0); static const struct a6xx_registers a6xx_vbif_reglist = REGS(a6xx_vbif_registers, 0, 0); @@ -353,9 +352,8 @@ static const u32 a7xx_gbif_registers[] = { 0x3cc0, 0x3cd1, }; -static const struct a6xx_registers a7xx_ahb_reglist[] = { - REGS(a7xx_ahb_registers, 0, 0), -}; +static const struct a6xx_registers a7xx_ahb_reglist= + REGS(a7xx_ahb_registers, 0, 0); static const struct a6xx_registers a7xx_gbif_reglist = REGS(a7xx_gbif_registers, 0, 0); -- cgit v1.2.3-70-g09d2