From 281f1f99cf3a761b45f611943721dfb1895c68a3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 5 Nov 2020 15:11:59 -0600 Subject: PCI: dwc: Detect number of iATU windows Currently the number of inbound and outbound iATU windows are determined from DT properties. Unfortunately, there's 'num-viewport' for RC mode and 'num-ib-windows' and 'num-ob-windows' for EP mode, yet the number of windows is not mode dependent. Also, 'num-viewport' is not clear whether that's inbound, outbound or both. We can probably assume it's outbound windows as that's all RC mode uses. However, using DT properties isn't really needed as the number of regions can be detected at runtime by poking the iATU registers. The basic algorithm is just writing a target address and reading back what we wrote. In the unrolled ATU case, we have to take care not to go past the mapped region. With this, we can drop num_viewport in favor of num_ob_windows instead. Link: https://lore.kernel.org/r/20201105211159.1814485-17-robh@kernel.org Tested-by: Marek Szyprowski Signed-off-by: Rob Herring Signed-off-by: Lorenzo Pieralisi Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org --- drivers/pci/controller/dwc/pcie-designware.c | 93 +++++++++++++++++++++++++--- 1 file changed, 86 insertions(+), 7 deletions(-) (limited to 'drivers/pci/controller/dwc/pcie-designware.c') diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index b5e438b70cd5..645fa1892375 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -546,6 +546,70 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) return 0; } +static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci) +{ + int max_region, i, ob = 0, ib = 0; + u32 val; + + max_region = min((int)pci->atu_size / 512, 256); + + for (i = 0; i < max_region; i++) { + dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, + 0x11110000); + + val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); + if (val == 0x11110000) + ob++; + else + break; + } + + for (i = 0; i < max_region; i++) { + dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, + 0x11110000); + + val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); + if (val == 0x11110000) + ib++; + else + break; + } + pci->num_ib_windows = ib; + pci->num_ob_windows = ob; +} + +static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci) +{ + int max_region, i, ob = 0, ib = 0; + u32 val; + + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); + max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; + + for (i = 0; i < max_region; i++) { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | i); + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); + val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); + if (val == 0x11110000) + ob++; + else + break; + } + + for (i = 0; i < max_region; i++) { + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | i); + dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); + val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); + if (val == 0x11110000) + ib++; + else + break; + } + + pci->num_ib_windows = ib; + pci->num_ob_windows = ob; +} + void dw_pcie_setup(struct dw_pcie *pci) { u32 val; @@ -556,15 +620,30 @@ void dw_pcie_setup(struct dw_pcie *pci) if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; - if (!pci->atu_base) - pci->atu_base = - devm_platform_ioremap_resource_byname(pdev, "atu"); - if (IS_ERR(pci->atu_base)) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; - } - dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + if (!pci->atu_base) { + struct resource *res = + platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + if (res) + pci->atu_size = resource_size(res); + pci->atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->atu_base)) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + + if (!pci->atu_size) + /* Pick a minimal default, enough for 8 in and 8 out windows */ + pci->atu_size = SZ_4K; + + dw_pcie_iatu_detect_regions_unroll(pci); + } else + dw_pcie_iatu_detect_regions(pci); + + dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? "enabled" : "disabled"); + dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound", + pci->num_ob_windows, pci->num_ib_windows); + if (pci->link_gen > 0) dw_pcie_link_set_max_speed(pci, pci->link_gen); -- cgit v1.2.3-70-g09d2