From bccaa3f917c90917a758020dfbdd9027290a7c4e Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Mon, 4 Dec 2017 14:00:17 +0800 Subject: pwm: meson: Add clock source configuration for Meson-AXG For PWM controller in the Meson-AXG SoC, the EE domain and AO domain have different clock sources. This patch tries to describe them in the DT compatible data. Signed-off-by: Jian Hu Signed-off-by: Yixun Lan Signed-off-by: Thierry Reding --- drivers/pwm/pwm-meson.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index d589331d1884..0767deba8e62 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -411,6 +411,24 @@ static const struct meson_pwm_data pwm_gxbb_ao_data = { .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; +static const char * const pwm_axg_ee_parent_names[] = { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data = { + .parent_names = pwm_axg_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names), +}; + +static const char * const pwm_axg_ao_parent_names[] = { + "aoclk81", "xtal", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data = { + .parent_names = pwm_axg_ao_parent_names, + .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -424,6 +442,14 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-gxbb-ao-pwm", .data = &pwm_gxbb_ao_data }, + { + .compatible = "amlogic,meson-axg-ee-pwm", + .data = &pwm_axg_ee_data + }, + { + .compatible = "amlogic,meson-axg-ao-pwm", + .data = &pwm_axg_ao_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- cgit v1.2.3-70-g09d2