1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
|
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ingenic,jz4725b";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-mxu1.0";
reg = <0>;
clocks = <&cgu JZ4725B_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
intc: interrupt-controller@10001000 {
compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
reg = <0x10001000 0x14>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};
ext: ext {
compatible = "fixed-clock";
#clock-cells = <0>;
};
osc32k: osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
cgu: clock-controller@10000000 {
compatible = "ingenic,jz4725b-cgu";
reg = <0x10000000 0x100>;
clocks = <&ext>, <&osc32k>;
clock-names = "ext", "osc32k";
#clock-cells = <1>;
};
tcu: timer@10002000 {
compatible = "ingenic,jz4725b-tcu", "simple-mfd";
reg = <0x10002000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10002000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu JZ4725B_CLK_RTC>,
<&cgu JZ4725B_CLK_EXT>,
<&cgu JZ4725B_CLK_PCLK>,
<&cgu JZ4725B_CLK_TCU>;
clock-names = "rtc", "ext", "pclk", "tcu";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <23>, <22>, <21>;
watchdog: watchdog@0 {
compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
reg = <0x0 0xc>;
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
pwm: pwm@60 {
compatible = "ingenic,jz4725b-pwm";
reg = <0x60 0x40>;
#pwm-cells = <3>;
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
clock-names = "timer0", "timer1", "timer2",
"timer3", "timer4", "timer5";
};
ost: timer@e0 {
compatible = "ingenic,jz4725b-ost";
reg = <0xe0 0x20>;
clocks = <&tcu TCU_CLK_OST>;
clock-names = "ost";
interrupts = <15>;
};
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
reg = <0x10003000 0x40>;
interrupt-parent = <&intc>;
interrupts = <6>;
clocks = <&cgu JZ4725B_CLK_RTC>;
clock-names = "rtc";
};
pinctrl: pinctrl@10010000 {
compatible = "ingenic,jz4725b-pinctrl";
reg = <0x10010000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
gpa: gpio@0 {
compatible = "ingenic,jz4725b-gpio";
reg = <0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <16>;
};
gpb: gpio@1 {
compatible = "ingenic,jz4725b-gpio";
reg = <1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <15>;
};
gpc: gpio@2 {
compatible = "ingenic,jz4725b-gpio";
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <14>;
};
gpd: gpio@3 {
compatible = "ingenic,jz4725b-gpio";
reg = <3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
};
aic: audio-controller@10020000 {
compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
reg = <0x10020000 0x38>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
clock-names = "aic", "i2s";
interrupt-parent = <&intc>;
interrupts = <10>;
dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
dma-names = "rx", "tx";
};
codec: audio-codec@100200a4 {
compatible = "ingenic,jz4725b-codec";
reg = <0x100200a4 0x8>;
#sound-dai-cells = <0>;
clocks = <&cgu JZ4725B_CLK_AIC>;
clock-names = "aic";
};
mmc0: mmc@10021000 {
compatible = "ingenic,jz4725b-mmc";
reg = <0x10021000 0x1000>;
clocks = <&cgu JZ4725B_CLK_MMC0>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <25>;
dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
};
mmc1: mmc@10022000 {
compatible = "ingenic,jz4725b-mmc";
reg = <0x10022000 0x1000>;
clocks = <&cgu JZ4725B_CLK_MMC1>;
clock-names = "mmc";
interrupt-parent = <&intc>;
interrupts = <24>;
dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
dma-names = "rx", "tx";
cap-sd-highspeed;
cap-mmc-highspeed;
cap-sdio-irq;
};
uart: serial@10030000 {
compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
reg = <0x10030000 0x100>;
interrupt-parent = <&intc>;
interrupts = <9>;
clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
clock-names = "baud", "module";
};
adc: adc@10070000 {
compatible = "ingenic,jz4725b-adc";
#io-channel-cells = <1>;
reg = <0x10070000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10070000 0x30>;
clocks = <&cgu JZ4725B_CLK_ADC>;
clock-names = "adc";
interrupt-parent = <&intc>;
interrupts = <18>;
};
nemc: memory-controller@13010000 {
compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
reg = <0x13010000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
<3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
clocks = <&cgu JZ4725B_CLK_MCLK>;
};
dmac: dma-controller@13020000 {
compatible = "ingenic,jz4725b-dma";
reg = <0x13020000 0xd8>, <0x13020300 0x14>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <29>;
clocks = <&cgu JZ4725B_CLK_DMA>;
};
udc: usb@13040000 {
compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
reg = <0x13040000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <27>;
interrupt-names = "mc";
clocks = <&cgu JZ4725B_CLK_UDC>;
clock-names = "udc";
};
lcd: lcd-controller@13050000 {
compatible = "ingenic,jz4725b-lcd";
reg = <0x13050000 0x130>; /* tbc */
interrupt-parent = <&intc>;
interrupts = <31>;
clocks = <&cgu JZ4725B_CLK_LCD>;
clock-names = "lcd_pclk";
lcd_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
port@8 {
reg = <8>;
ipu_output: endpoint {
remote-endpoint = <&ipu_input>;
};
};
};
};
ipu: ipu@13080000 {
compatible = "ingenic,jz4725b-ipu";
reg = <0x13080000 0x64>;
interrupt-parent = <&intc>;
interrupts = <30>;
clocks = <&cgu JZ4725B_CLK_IPU>;
clock-names = "ipu";
port {
ipu_input: endpoint {
remote-endpoint = <&ipu_output>;
};
};
};
bch: ecc-controller@130d0000 {
compatible = "ingenic,jz4725b-bch";
reg = <0x130d0000 0x44>;
clocks = <&cgu JZ4725B_CLK_BCH>;
};
rom: memory@1fc00000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;
device-width = <1>;
};
};
|
